GS1528 Multi-Rate SDI Dual Slew-Rate Cable Driver ™ DATA SHEET DESCRIPTION • SMPTE 292M, SMPTE 344M and SMPTE 259M compliant The GS1528 is a second generation high-speed bipolar integrated circuit designed to drive one or two 75Ω co-axial cables at data rates up to 1.485Gb/s. The GS1528 provides two selectable slew rates in order to achieve compliance to SMPTE 259M, SMPTE 344M and SMPTE 292M. • dual coaxial cable driving outputs with selectable slew rate • 50Ω Ω differential PECL input • seamless interface to other HD-LINX™ II family products • single 3.3V power supply operation • operating temperature range: 0°C to 70°C The GS1528 accepts a LVPECL level differential input that may be AC coupled. External biasing resistors at the inputs are not required. Power consumption is typically 160mW using a 3.3V power supply. APPLICATIONS • SMPTE 292M, SMPTE 344M and SMPTE 259M Coaxial Cable Serial Digital Interfaces. ORDERING INFORMATION PART NUMBER PACKAGE TEMPERATURE GS1528-CKA 8 pin SOIC 0°C to 70°C BANDGAP REFERENCE AND BIASING CIRCUIT SDI INPUT DIFFERENTIAL PAIR RSET SDO OUTPUT STAGE & CONTROL SDI SDO SD/HD FUNCTIONAL BLOCK DIAGRAM Revision Date: July 2002 Document No. 16632 - 2 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: [email protected] www.gennum.com GS1528 FEATURES ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise indicated PARAMETER VALUE Supply Voltage CAUTION -0.5V to 3.6 VDC Input ESD Voltage Storage Temperature Range -50°C < Ts < 125°C Input Voltage Range (any input) -0.3 to (VCC +0.3)V Operating Temperature Range 0°C to 70°C Power Dissipation 300mW Lead Temperature (soldering, 10 sec) 260°C DC ELECTRICAL CHARACTERISTICS VDD = 3.3V, TA = 0°C to 70°C, unless otherwise shown PARAMETER CONDITIONS SYMBOL MIN Supply Voltage TYP MAX UNITS NOTES TEST LEVELS ±5% 3 VCC 3.135 3.3 3.465 V Power Consumption TA = 25°C PD - 160 - mW 5 Supply Current TA = 25°C Ιs - 48 - mA 1 Output Voltage Common mode VCMOUT - VCC - VOUT - - 6 Input Voltage Common mode VCMIN 1.6 + ∆VSDI/2 - VCC - ∆VSDI/2 V 5 VIH 2.4 - - V 7 VIL - - 0.8 V SD/HD Input AC ELECTRICAL CHARACTERISTICS VDD = 3.3V, TA = 0°C to 70°C, unless otherwise shown PARAMETER CONDITIONS Serial input data rate Additive jitter Rise/Fall time SYMBOL MIN TYP MAX UNITS NOTES TEST LEVELS DRSDO - - 1.485 Gb/s 2 1 1.485Gb/s - 15 - psp-p 270Mb/s - 25 - psp-p tr, tf - - 220 ps 20% to 80% 1 tr, tf 400 - 800 ps 20% to 80% 1 !tr, !tf - - 30 ps SD/HD=0 SD/HD=1 Mismatch in rise/fall time 1 1 1 Duty cycle distortion - - 30 ps 1 Overshoot - - 8 % 1 ORL 15 - - dB VOUT 750 800 850 mVp-p 1 !VSDI 300 - 2000 mVp-p 1 Output Return Loss Output Voltage Swing Single Ended into 75Ω external load RSET = 750Ω Input Voltage Swing Differential 1 7 TEST LEVELS 1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1, 2, or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product. 9. Indirect test. NOTES: 1. Tested on CB1528 board from 5MHz to 1.435GHz 2. The input coupling capacitor must be set accordingly for lower data rates. 2 GENNUM CORPORATION 16632 - 2 GS1528 The GS1528 is sensitive to electrostatic discharge. Use extreme caution, observing all ESD-prevention practices, during handling and assembly. The SDI inputs of the GS1528 must be protected from electrostatic discharge and electrical overstress during the handling and operation of circuit assemblies containing the device. 500V PIN CONNECTIONS 1 SDI 2 VEE 3 RSET 4 GS1528 8 PIN SOIC TOP VIEW 8 SDO 7 SDO 6 SD/HD 5 VCC GS1528 SDI 8 PIN SOIC PIN DESCRIPTION PIN NUMBER 1,2 NAME TYPE DESCRIPTION SDI, SDI PECL INPUT Serial digital differential input. 4 RSET INPUT External output amplitude control resistor. 6 SD/HD LOGIC INPUT Output slew rate control. When HIGH, the output will meet SMPTE259M rise/fall time specifications. When LOW, the serial outputs will meet SMPTE292M rise/fall time specifications. SDO, SDO OUTPUT Serial digital differential output. 3 VEE POWER Most negative power supply connection. Connect to GND. 5 VCC POWER Most positive power supply connection. Connect to +3.3V. 7, 8 INPUT/OUTPUT CIRCUITS VCC SDO SDO Vcc ΙREF SDI SDI Fig. 2 Differential Output Stage (SDO/SDO) ΙREF derived using RSET VCC VCC 10k 5k 10k SD/HD On Chip Reference 10k Fig. 3 Slew Rate Select Input Stage (SD/HD) Fig. 1 Differential Input Stage (SDI/SDI) 3 GENNUM CORPORATION 16632 - 2 DETAILED DESCRIPTION Tek Stopped: INPUT INTERFACING 8110 Acquisitions SDI/SDI are high impedance differential inputs. (See Figure 1 for equivalent input circuit). Several conditions must be observed when interfacing to these inputs: GS1528 1. The differential input signal amplitude must be between 300 and 2000mVpp. 2. The common mode voltage range must be as specified in the DC Characteristics Table. 3. For input trace lengths longer than approximately 1cm, the inputs should be terminated as shown in the Typical Application Circuit. The GS1528 inputs are self-biased, allowing for simple AC coupling to the device. For serial digital video, a minimum capacitor value of 4.7µF should be used to allow coupling of pathological test signals. A tantalum capacitor is recommended. Fig. 4 Output signal for 270Mb/s input Tek Running: Normal SD/HD The GS1528 SDO rise and fall times can be set to comply with both SMPTE 259M/344M and SMPTE 292M. For all SMPTE 259M standards, or any data rate that requires longer rise and fall time characteristics, the SD/HD pin must be set to a HIGH INPUT. For SMPTE 292M standards and signals which require faster rise and fall times, this pin should be set to a LOW INPUT. OUTPUT INTERFACING The GS1528 outputs are current mode, and will drive 800mV into a 75Ω load. These outputs are protected from accidental static damage with internal static protection diodes. The SMPTE 292M, SMPTE 344M and SMPTE 259M standards requires that the output of a cable driver have a source impedance of 75Ω and a return loss of at least 15dB between 5MHz and 1.485GHz. Fig. 5 Output signal for 1.485Gb/s input In order for an SDI output circuit using the GS1528 to meet this specification, the output circuit shown in the Typical Application Circuit is recommended. When measuring return loss at the GS1528 output, it is necessary to take the measurement for both a logic high and a logic low output condition. This is because the output protection diodes act as a varactor (voltage controlled capacitor) as shown in Figure 6. The value of LCOMP will vary depending on the PCB layout, with a typical value of 5.6nH (see the Application Information section in this data sheet for further details). A 4.7µF capacitor is used for AC coupling the output of the GS1528. This value is chosen to ensure that pathological signals can be coupled without a significant DC component occurring. Consequently, the output capacitance of the GS1528 is dependent on the logic state of the output. 4 GENNUM CORPORATION 16632 - 2 GS1528 SDO 1000 900 GS1528 OUTPUT SWING (mV) 1100 800 700 SDO 600 500 600 700 800 900 1000 RSET R (Ω) Fig. 6 Static Protection Diodes Fig. 7 Output Amplitude Adjustment OUTPUT RETURN LOSS MEASUREMENT To perform a practical return loss measurement, it is necessary to force the GS1528 output to a DC high or low condition. The actual measured return loss will be based on the outputs being static at VCC or VCC-1.6V. Under normal operating conditions the outputs of the GS1528 swing between VCC-0.4V and VCC-1.2V, so the measured value of return loss will not represent the actual operating return loss. The RSET resistor is part of the high speed output circuit of the GS1528. The resistor should be placed as close as possible to the RSET pin. In addition, the PCB capacitance should be minimized at this node by removing the PCB groundplane beneath the RSET resistor and the RSET pin. TABLE 1: RSET vs VOD A simple method of calculating the values of actual operating return loss is to interpolate the two return loss measurements. In this way, the values of return loss are estimated at VCC-0.4V and VCC-1.2V based on the measurements at VCC and VCC-1.6V. The two values of return loss (high and low) will typically differ by several decibels. If the measured return loss is RH for logic high and RL for logic low, then the two values can be interpolated as follows: RSET R (Ω) OUTPUT SWING 995 608 824 734 750 800 600 884 573 1040 NOTE: For reliable operation of the GS1528 over the full temperature range, do not use an RSET value below 573Ω. RIH = RH- (RH-RL)/4 and RIL = RL+(RH-RL)/4 where RIH is the interpolated logic high value and RIL is the interpolated logic low value. For example, if RH = -18dB and RL = -14dB, then the interpolated values are RIH = -17dB and RIL = -15dB. OUTPUT AMPLITUDE ADJUSTMENT The output amplitude of the GS1528 can be adjusted by changing the value of the RSET resistor as shown in Figure 7 and Table 1. For an 800mVp-p output with a nominal ±7% tolerance, a value of 750Ω is required. A ±1% SMT resistor should be used. 5 GENNUM CORPORATION 16632 - 2 APPLICATION INFORMATION PCB LAYOUT GS1528 Special attention must be paid to component layout when designing serial digital interfaces for HDTV. An FR-4 dielectric can be used, however, controlled impedance transmission lines are required for PCB traces longer than approximately 1cm. Note the following PCB artwork features used to optimize performance: The PCB trace width for HD rate signals is closely matched to SMT component width to minimize reflections due to changes in trace impedance. The PCB groundplane is removed under the GS1528 output components to minimize parasitic capacitance. The PCB ground plane is removed under the GS1528 RSET pin and resistor to minimize parasitic capacitance. Input and output BNC connectors are surface mounted in-line to eliminate a transmission line stub caused by a BNC mounting via high speed traces which are curved to minimize impedance variations due to change of PCB trace width. TYPICAL APPLICATION CIRCUIT 5.6n 75 * BNC 4u7 4u7 GS1528 49.9 10n 1 2 3 49.9 4 4u7 8 7 6 75 10n 75 75 5.6n * VCC RSET DIFFERENTIAL DATA INPUT VCC SDO SDO SD/HD SDI SDI VEE 5 BNC 4u7 VCC * TYPICAL VALUE VARIES WITH LAYOUT VCC 750 10n SD/HD NOTE: All resistors in Ohms, capacitors in Farads, and inductors in Henrys, unless otherwise noted. 6 GENNUM CORPORATION 16632 - 2 PACKAGE DIMENSIONS 1.91 5.00 MAX. MAX 1.27 MAX GS1528 0.49 MAX 5 8 0.25 4.0 6.20 MAX MAX MAX 4 1 0.25 MAX = = = 0.60 MAX 3.81 ±0.05 8-pin SOIC All dimensions are in millimetres 3 spaces @ 1.27 ±0.05 8 PIN SOIC CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION REVISION NOTES: Add ESD warning. DOCUMENT IDENTIFICATION DATA SHEET The product is in production. Gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible. GENNUM CORPORATION GENNUM JAPAN CORPORATION C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku Tokyo 168-0081, Japan Tel. +81 (03) 3334-7700 Fax. +81 (03) 3247-8839 MAILING ADDRESS: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 GENNUM UK LIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523 SHIPPING ADDRESS: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. © Copyright March 2002 Gennum Corporation. All rights reserved. Printed in Canada. 7 16632 - 2