AGILENT HFCT

Agilent HFCT-5905E MT-RJ Duplex
Single Mode Transceiver
Data Sheet
Description
The HFCT-5905E transceiver is a
high performance, cost effective
module for serial optical data
communications applications
specified for a signal rate of
155 MBd. It is designed to provide
a SONET/SDH compliant link for
155 Mb/s intermediate reach links.
The HFCT-5905 does not include a
nose shield and is not
recommended due to the potential
degradation of EMI performance in
a complete system. The HFCT-5905
is available on the rare occasion
that a system mechanical design
may not allow for a nose shield.
This module is designed for single
mode fiber and operates at a
nominal wavelength of 1300 nm.
It incorporates Agilent’s high
performance, reliable, long
wavelength optical devices and
proven circuit technology to give
long life and consistent service.
The transmitter section uses an
advanced SMQW Fabry Perot
laser with full IEC 825 and CDRH
Class I eye safety.
The receiver section uses a
MOVPE grown planar PIN
photodetector for low dark
current and excellent
responsivity.
A pseudo-ECL logic interface
simplifies interface to external
circuitry.
Features
• MT-RJ duplex single mode
transceiver
• Intermediate SONET OC3 SDH
STM1 (S1.1) compliant
• Single +3.3 V power supply
• Multisourced 2 x 5 pin
configuration
• Interchangeable with LED
multisourced 2 x 5 transceivers
• Unconditionally eye safe
laser IEC 825/CDRH Class 1
compliant
• Temperature range:
0°C to +70°C
Applications
• SONET/SDH equipment
interconnect
• ATM 155 Mb/s links
Connection Diagram
RX
TX
Mounting Studs/
Solder Posts
Package
Grounding Tabs
Top
View
RECEIVER SIGNAL GROUND
RECEIVER POWER SUPPLY
SIGNAL DETECT
RECEIVER DATA OUT BAR
RECEIVER DATA OUT
f
f
f
f
f
1
2
3
4
5
10
9
8
7
6
f
f
f
f
f
TRANSMITTER DATA IN BAR
TRANSMITTER DATA IN
TRANSMITTER DISABLE
TRANSMITTER SIGNAL GROUND
TRANSMITTER POWER SUPPLY
Pin Descriptions:
Pin 1 Receiver Signal Ground
VEE RX:1
Directly connect this pin to the
receiver ground plane.
Pin 4 Receiver Data Out Bar RD-:
No internal terminations are
provided. See recommended
circuit schematic.
Pin 2 Receiver Power Supply
VCC RX:
Provide +3.3 V dc via the
recommended receiver power
supply filter circuit. Locate the
power supply filter circuit as
close as possible to the VCC RX
pin.
Pin 5 Receiver Data Out RD+:
No internal terminations are
provided. See recommended
circuit schematic.
Pin 3 Signal Detect SD:
Normal optical input levels to the
receiver result in a logic “1”
output.
Low optical input levels to the
receiver result in a fault condition
indicated by a logic “0” output.
This Signal Detect output can be
used to drive a PECL input on an
upstream circuit, such as Signal
Detect input or Loss of Signal-bar.
Pin 6 Transmitter Power Supply
VCC TX:
Provide +3.3 V dc via the
recommended transmitter power
supply filter circuit. Locate the
power supply filter circuit as
close as possible to the VCC TX
pin.
Pin 7 Transmitter Signal Ground
VEE TX:
Directly connect this pin to the
transmitter ground plane.
Note: 1. The Transmitter and Receiver VEE connections are commoned within the module.
2
Pin 8 Transmitter Disable TDIS:
Optional feature for laser based
products only. For laser based
products connect this pin to
+3.3 V TTL logic high “1” to
disable module. To enable module
connect to TTL logic low “0”.
Pin 9 Transmitter Data In TD+:
No internal terminations are
provided. See recommended
circuit schematic.
Pin 10 Transmitter Data In Bar TD-:
No internal terminations are
provided. See recommended
circuit schematic.
Mounting Studs/Solder Posts
The two mounting studs are
provided for transceiver
mechanical attachment to the
circuit board. It is recommended
that the holes in the circuit board
be connected to chassis ground.
Package Grounding Tabs
Connect four package grounding
tabs to signal ground.
Functional Description
Receiver Section
Design
The receiver section contains an
InGaAs/InP photo detector and a
preamplifier mounted in an
optical subassembly. This optical
subassembly is coupled to a
postamp/decision circuit on a
separate circuit board.
The postamplifier is ac coupled to
the preamplifier as illustrated in
Figure 1. The coupling capacitors
are large enough to pass the
SONET/SDH test pattern at
155 MBd without significant
distortion or performance penalty.
If a lower signal rate, or a code
which has significantly more low
frequency content is used,
sensitivity, jitter and pulse
distortion could be degraded.
Figure 1 also shows a filter
network which limits the
bandwidth of the preamp output
signal. The filter is designed to
bandlimit the preamp output
noise and thus improve the
receiver sensitivity.
These components will also
reduce the sensitivity of the
receiver as the signal bit rate is
increased above 155 MBd.
Noise Immunity
The receiver includes internal
circuit components to filter
power supply noise. Under some
conditions of EMI and power
supply noise, external power
supply filtering may be necessary.
If receiver sensitivity is found to
be degraded by power supply
noise, the filter network
illustrated in Figure 3 may be
used to improve performance.
The values of the filter
components are general
recommendations and may be
changed to suit a particular
system environment. Shielded
inductors are recommended.
Terminating the Outputs
The PECL Data outputs of the
receiver may be terminated with
the standard Thevenin-equivalent
50 ohm to VCC - 2 V termination.
Other standard PECL terminating
techniques may be used.
The Signal Detect Circuit
The signal detect circuit works by
sensing the peak level of the
received signal and comparing
this level to a reference.
DATA OUT
FILTER
TRANSIMPEDANCE
PREAMPLIFIER
PECL
OUTPUT
BUFFER
AMPLIFIER
GND
SIGNAL
DETECT
CIRCUIT
Figure 1. Receiver Block Diagram
3
The two outputs of the receiver
should be terminated with
identical load circuits to avoid
unnecessarily large ac current in
VCC. If the outputs are loaded
identically the ac current is
largely nulled. The SD output of
the receiver is PECL logic and
must be loaded if it is to be used.
The signal detect circuit is much
slower that the data path, so the
ac noise generated by an
asymmetrical load is negligible.
Power consumption may be
reduced by using a higher than
normal load impedance for the SD
output. Transmission line effects
are not generally a problem as the
switching rate is slow.
PECL
OUTPUT
BUFFER
DATA OUT
SD
Functional Description
Transmitter Section
Design
The transmitter section uses a
buried heterostructure Fabry
Perot laser as its optical source.
The package of this laser is
designed to allow repeatable
coupling into single mode fiber.
In addition, this package has been
designed to be compliant with
IEC 825 Class 1 and CDRH Class I
eye safety requirements. The
optical output is controlled by a
custom IC which detects the laser
output via the monitor photodiode.
This IC provides both dc and ac
current drive to the laser to
ensure correct modulation, eye
diagram and extinction ratio over
temperature, supply voltage and
life.
Solder and Wash Process
Compatibility
The transceivers are delivered
with protective process plugs
inserted into the MT-RJ connector
receptacle. This process plug
protects the optical subassemblies
during wave solder and aqueous
wash processing and acts as a
dust cover during shipping.
These transceivers are compatible
with either industry standard
wave or hand solder processes.
Each process plug can only be
used once during processing,
although with subsequent use, it
can be used as a dust cover.
LASER
DATA
LASER
MODULATOR
DATA
PECL
INPUT
LASER BIAS
DRIVER
LASER BIAS
CONTROL
Figure 2. Simplified Transmitter Schematic
4
PHOTODIODE
(rear facet monitor)
Interface and Termination
Recommendations
Figure 3 shows a +3.3 V coupling
scheme. Also present are power
supply filtering arrangements
which comply with the
recommendations of the small
form factor multisource
agreement. Such a compliance
ensures noise rejection
compatibility between
transceivers from various
vendors.
PHY DEVICE
VCC (+3.3 V)
TERMINATE AT
TRANSCEIVER INPUTS
100
f
1
2
3
TD-
Z = 50
W
TD+
LVPECL
130
f
VCC TX
f
SD
VCC RX
RX
VEE RX
TX
W
6
f
RD+
7
f
N/C
TD+
TD-
8
f
VEE TX
9
f
RD-
10
W
Z = 50
f
f
4
5
1 µH
C2
C3
W
130
10 µF
VCC (+3.3 V)
RD+
C1
130
W
W
Z = 50
W
Z = 50
W
100
Note: C1 = C2 = C3 = 10 nF or 100 nF
Figure 3. +3.3 V Transceiver Interface with +3.3 V LVPECL Device
W
LVPECL
RD-
VCC (+3.3 V)
130
W
SD
82
5
W
1 µH
f
Z = 50
130
W
VCC (+3.3 V)
W
TERMINATE AT
DEVICE INPUTS
Regulatory Compliance
Feature
Test Method
Targeted Performance
Electrostatic Discharge
(ESD) to the Electrical Pins
MIL-STD-883C
Method 3015.4
Meets Class 1 (2000 Volts).
Electrostatic Discharge
(ESD) to the Duplex MT-RJ
Receptacle
Variation of IEC 801-2
Products of this type, typically, withstand at least
25 kV without damage when the Duplex MT-RJ
Connector Receptacle is contacted by a Human
Body Model probe.
Electromagnetic
Interference (EMI)
FCC Class B
CENELEC EN55022 Class B
(CISPR 22A)
VCCI Class 1
Transceivers typically provide 12 dB margin to the
noted standard limits when tested at a certified test
range with the transceiver mounted to a circuit card
without a chassis enclosure.
Three transceivers typically provide 20 dB of margin
in a ’perfect’ closed box with the recommended port
openings.
Immunity
Variation of IEC 801-3
Typically show no measurable effect from a 10 V/m
field swept from 10 to 450 MHz applied to the
transceiver when mounted to a circuit card without a
chassis enclosure.
Eye Safety
FDA CDRH 21-CFR 1040
Class 1
Compliant per Agilent testing under normal operating
conditions.
Accession Number: 9521220-20.
IEC 825 Issue 1 1993:11
Class 1
CENELEC EN60825 Class 1
Compliant per Agilent testing under single fault
conditions.
TUV Certification: 933/510817/05.
6
Performance Specifications
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause catastrophic damage to the device. Limits apply to each parameter
in isolation, all other parameters having values within the recommended operating conditions. It should not be assumed that
limiting values of more than one parameter can be applied to the product at the same time. Exposure to the absolute maximum
ratings for extended periods can adversely affect device reliability.
Parameter
Storage Temperature
Lead Soldering Temperature/Time
Output Current
Data Input Voltage
Power Supply Voltage
Symbol
TS
TSOLD /tSOLD
IO
VI
VCC
Minimum
-40
Symbol
TA
VCC
VIL - VCC
VIH - VCC
RL
Minimum
0
3.1
-1.810
-1.165
Typical
Maximum
+85
+260/10
30
VCC
3.6
Units
°C
°C/s
mA
V
V
Notes
Typical
Maximum
+70
3.5
-1.475
-0.880
Units
°C
V
V
V
Notes
1
0
GND
0
Operating Environment
Parameter
Ambient Operating Temperature
Power Supply Voltage
Data Input Voltage - Low
Data Input Voltage - High
Data and Signal Detect Output Load
50
W
2
Transmitter Section
(Ambient Operating Temperature VCC = 3.1 V to 3.5 V)
Parameter
Supply Current
Power Dissipation
Optical Output Power
Center Wavelength
Spectral Width
Extinction Ratio
Output Optical Eye
Optical Rise Time
Optical Fall Time
Data Input Current - Low
Data Input Current - High
Data Input Voltage - Low
Data Input Voltage - High
Symbol
ICC
PDISS
PO
Minimum
Typical
50
0.175
Maximum
120
0.42
-8
1360
7.7
Units
mA
W
-15
dBm avg.
lC
1261
nm
Dl
nm
8.2
dB
ER
Compliant with Eye Mask Bellcore TR-NWT-000253 and
ITU recommendation G.957
tR
2
ns
2
ns
tF
-200
µA
IIL
200
µA
IIH
-1.810
-1.475
V
VIL - VCC
-1.165
-0.880
V
VIH - VCC
Notes
3
4
5
5
6
6
Notes:
1. 2 ms-1 air flow required.
2. Outputs terminated with 50 W to VCC – 2V are the Thevenin equivalent.
3. The power supply current varies with temperature. Maximum current is specified at V CC = Maximum @ maximum temperature (not including
terminations) and end of life.
4. Output power is power coupled into a single mode fiber.
5. 10% - 90% Values
6. These inputs are compatible with 10 K, 10 KH, and 100 K ECL and LVPECL inputs.
7
Receiver Section
(Ambient Operating Temperature VCC = 3.1 V to 3.5 V)
Parameter
Supply Current
Power Dissipation
Receiver Sensitivity at Eye Center
Receiver Sensitivity at Window Edge
Maximum Input Optical Power
Operating Wavelength
Data Output Voltage - Low
Data Output Voltage - High
Signal Detect Output Voltage - Low
Signal Detect Output Voltage - High
Signal Detect - Asserted
Signal Detect - Deasserted
Signal Detect - Hysteresis
Signal Detect Assert time
(off to on)
Signal Detect Deassert time
(on to off)
Power Supply Noise Rejection
Symbol
Minimum
Typical
75
ICC
0.263
PDISS
PIN Min. (C)
PIN Min. (W)
-8.0
PIN Max.
1261
l
VOL - VCC
-1.840
VOH - VCC -1.045
-1.840
VOL - VCC
VOH - VCC -1.045
PD + 1.5 dB
PA
-45
PD
0.5
PA - PD
AS_Max
0
4.0
100
Units
mA
W
dBm avg.
dBm avg.
dBm avg.
nm
V
V
V
V
dBm avg.
dBm avg.
dB
µs
ANS_Max
350
µs
50
mV p-p
PSNR
0
Maximum
100
0.35
-31.8
-31
1360
-1.620
-0.880
-1.620
-0.880
-34
Notes
7
8
9
9
9
10
10
10
10
11
Notes:
7. This does not include the output load current.
8. This does not include the output load power.
9. Minimum sensitivity and saturation levels for a 223 -1 PRBS with 72 ones and 72 zeros inserted. (CCITT recommendation G.958)
10. These outputs are compatible with 10 K, 10 KH and 100 K ECL and PECL outputs.
11. Between 20 Hz and 2000 KHz with the recommended power supply filter. No degradation above the maximum ‘receiver sensitivity at eye
center’specification of –31.8 dBm.
8
13.97
(0.55)
MIN.
5.15
(0.20)
(PCB to OVERALL
RECEPTACLE
CENTER LINE)
4.5 ±0.2
(0.177 ±0.008)
(PCB to OPTICS
CENTER LINE)
FRONT VIEW
7.11
(0.28)
13.59 10.0
(0.535) (0.394)
MAX. MAX.
10.16
(0.4)
TOP VIEW
4.57
(0.18)
Pin 1
1.778
(0.07)
7.59
(0.299)
17.778
(0.7)
12.4
(0.488)
7.112
(0.28)
+0
Ø 0.61 –0.2
(+000)
(0.024) (–008)
49.56 (1.951)
37.56 (1.479) MAX.
9.3
9.8
(0.386) (0.366)
MAX. MAX.
SIDE VIEW
0.25
(0.01)
Ø 1.07
(0.042)
3.3
(0.13)
Full Radius
1
(0.039)
DIMENSIONS IN MILLIMETERS (INCHES)
NOTES:
1. THIS PAGE DESCRIBES THE MAXIMUM PACKAGE OUTLINE, MOUNTING STUDS, PINS AND THEIR RELATIONSHIPS TO EACH OTHER.
2. TOLERANCED TO ACCOMMODATE ROUND OR RECTANGULAR LEADS.
3. THE 10 I/O PINS, 2 SOLDER POSTS AND 4 PACKAGE GROUNDING TABS ARE TO BE TREATED AS A SINGLE PATTERN.
(SEE FIGURE 6 PCB LAYOUT).
4. THE MT-RJ HAS A 750 µm FIBER SPACING.
5. THE MT-RJ ALIGNMENT PINS ARE IN THE MODULE.
6. SEE MT-RJ TRANSCEIVER PIN OUT DIAGRAM FOR DETAILS.
Figure 4. HFCT-5905E Package Outline Drawing
9
13.97
(0.55)
MIN.
5.15
(0.20)
(PCB to OVERALL
RECEPTACLE
CENTER LINE)
4.5 ±0.2
(0.177 ±0.008)
(PCB to OPTICS
CENTER LINE)
FRONT VIEW
7.11
(0.28)
13.59
9.6
(0.535) (0.378)
MAX. MAX.
10.16
(0.4)
TOP VIEW
4.57
(0.18)
Pin 1
1.778
(0.07)
7.59
(0.299)
17.778
(0.7)
12
(0.472)
+0
–0.2
(+000)
(0.024) (–008)
Ø 0.61
7.112
(0.28)
49.56 (1.951)
37.56 (1.479) MAX.
9.3
9.8
(0.386) (0.366)
MAX. MAX.
SIDE VIEW
0.25
(0.01)
Ø 1.07
(0.042)
3.3
(0.13)
Full Radius
1
(0.039)
DIMENSIONS IN MILLIMETERS (INCHES)
NOTES:
1. THIS PAGE DESCRIBES THE MAXIMUM PACKAGE OUTLINE, MOUNTING STUDS, PINS AND THEIR RELATIONSHIPS TO EACH OTHER.
2. TOLERANCED TO ACCOMMODATE ROUND OR RECTANGULAR LEADS.
3. THE 10 I/O PINS, 2 SOLDER POSTS AND 4 PACKAGE GROUNDING TABS ARE TO BE TREATED AS A SINGLE PATTERN.
(SEE FIGURE 6 PCB LAYOUT).
4. THE MT-RJ HAS A 750 µm FIBER SPACING.
5. THE MT-RJ ALIGNMENT PINS ARE IN THE MODULE.
6. SEE MT-RJ TRANSCEIVER PIN OUT DIAGRAM FOR DETAILS.
Figure 5. HFCT-5905 Package Outline Drawing
10
Board Layout - Decoupling Circuit
and Ground Planes
It is important to take care in the
layout of your circuit board to
achieve optimum performance
from these transceivers. Figure 3
provides a good example of a
schematic for a power supply
decoupling circuit that works well
with these parts. It is further
recommended that a continuous
ground plane be provided in the
circuit board directly under the
transceiver to provide a low
inductance ground for signal
return current. This recommendation is in keeping with good high
frequency board layout practices.
Spacing Of Front
Housing Leads Holes
KEEP OUT AREA
FOR PORT PLUG
7
(0.276)
Ø 1.4 ±0.1
(0.055 ±0.004)
Board Layout - Hole Pattern
The Agilent transceiver complies
with the circuit board “Common
Transceiver Footprint” hole
pattern defined in the original
multisource announcement which
defined the 2 x 5 package style.
This drawing is reproduced in
Figure 6 with the addition of ANSI
Y14.5M compliant dimensioning
to be used as a guide in the
mechanical layout of your circuit
board. Figure 7 shows the front
panel dimensions associated with
such a layout.
7.11
(0.28)
Ø 1.4 ±0.1
(0.055 ±0.004)
3.56
(0.14)
Holes For
Housing
Leads
Ø 1.4 ±0.1
(0.055 ±0.004)
10.16
(0.4)
10.8
(0.425)
3.08
(0.121)
13.34 7.59
(0.525) (0.299)
3
(0.118)
3
(0.118)
27
(1.063)
6
(0.236)
4.57
(0.18)
17.78
(0.7)
9.59
(0.378)
1.778
(0.07)
13.97
(0.55)
MIN.
2
(0.079)
Ø 2.29
(0.09)
7.112
(0.28)
3.08
(0.121)
Ø 0.81 ±0.1
(0.032 ±0.004)
DIMENSIONS IN MILLIMETERS (INCHES)
NOTES:
1. THIS FIGURE DESCRIBES THE RECOMMENDED CIRCUIT BOARD LAYOUT FOR THE MT-RJ TRANSCEIVER PLACED
AT .550 SPACING.
2. THE HATCHED AREAS ARE KEEP-OUT AREAS RESERVED FOR HOUSING STANDOFFS. NO METAL TRACES OR
GROUND CONNECTION IN KEEP-OUT AREAS.
3. 2 x 5 TRANSCEIVER MODULE REQUIRES 16 PCB HOLES (10 I/O PINS, 2 SOLDER POSTS AND 4 PACKAGE
GROUNDING TABS).
PACKAGE GROUNDING TABS SHOULD BE CONNECTED TO SIGNAL GROUND.
4. THE SOLDER POSTS SHOULD BE SOLDERED TO CHASSIS GROUND FOR MECHANICAL INTEGRITY AND TO
ENSURE FOOTPRINT COMPATIBILITY WITH OTHER SFF TRANSCEIVERS.
Figure 6. Recommended Board Layout Hole Pattern
11
Design Support Materials
Further technical details and
supporting information regarding
small form factor transceivers are
contained in an application note
aimed at providing useful
information to the fiber-optic
system designer. This document
describes PC board layout
techniques, power supply filtering,
EMI considerations and
interfacing options. Agilent has
created a number of reference
designs with major PHY IC
vendors in order to establish full
functionality and interoperability.
Such design information and
results can be made available to
the designer as a technical aid.
Please contact your Agilent
representative for further
information if required.
3.8
(0.15)
10.8 ±0.1
(0.425 ±0.004)
1
(0.039)
9.8 ±0.1
(0.386 ±0.004)
0.25 ±0.1
(0.01 ±0.004)
(TOP OF PCB TO
BOTTOM OF
OPENING)
13.97
(0.55)
MIN.
14.79
(0.589)
DIMENSIONS IN MILLIMETERS (INCHES)
NOTE: NOSE SHIELD SHOULD BE CONNECTED TO CHASSIS GROUND.
Figure 7. Recommended Panel Mounting
Ordering Information
HFCT-5905E
Model Name:
HFCT-5905E - Preferred option with nose shield fitted
HFCT-5905E - Non-preferred option without nose shield
Class 1 Laser Product: This product conforms to the
applicable requirements of 21 CFR 1040 at the date of
manufacture
Date of Manufacture:
Agilent Technologies Ltd., Depot Road, Singapore
Handling Precautions
1. The HFCT-5905E can be damaged by current surges or overvoltage.
Power supply transient precautions should be taken.
2. Normal handling precautions for electrostatic sensitive devices
should be taken.
www.semiconductor.agilent.com
Data subject to change.
Copyright © 2000 Agilent Technologies, Inc.
Obsoletes: 5968-5829E
5988-0697EN (10/00)