HANBIT HMD2M64B2-F10

HANBit
HSD2M64B2
Synchronous DRAM Module 16Mbyte (2Mx64-Bit), SO-DIMM,
4Banks, 4K Ref., 3.3V
Part No. HSD2M64B2
GENERAL DESCRIPTION
The HSD2M64B2 is a 2M x 64 bit Synchronous Dynamic RAM high density memory module. The module consists of
two CMOS 512K x 32 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages on a 144-pin glass-epoxy
substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The
HSD2M64B2 is a SO-DIMM(Small Outline Dual in line Memory Module) and is intended for mounting into 144-pin edge
connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are
possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be
useful for a variety of high bandwidth, high performance memory system applications All module components may be
powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.
FEATURES
• Part Identification
HSD2M64B2-F/10 :100MHz
HSD2M64B2-F/8 :125MHz
* F : Auto Self-Refresh with Low Power
• Burst mode operation
• Auto & self refresh capability (4096 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ±0.3V power supply
• MRS cycle with address key programs
- Latency (Access from column address)
- Burst length (1, 2, 4, 8 & Full page)
- Data scramble (Sequential & Interleave)
• JEDEC standard 144-Pin SO-DIMM
• All inputs are sampled at the positive going edge of the system clock
• The used device is 512Kx32Bitx4Banks SDRAM
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REV.1.0 (August.2002)
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HANBit Electronics Co.,Ltd.
HANBit
HSD2M64B2
PIN ASSIGN
PIN
Symbol
PIN
Symbol
PIN
Symbol
PIN
Symbol
PIN
Symbol
1
Vss
3
DQ0
5
7
PIN
Symbol
2
Vss
49
DQ13
50
DQ45
97
4
DQ32
51
DQ14
52
DQ46
99
DQ22
98
DQ54
DQ23
100
DQ55
DQ1
6
DQ33
53
DQ15
54
DQ47
DQ2
8
DQ34
55
Vss
56
Vss
101
VDD
102
VDD
103
A6
104
A7
9
DQ3
10
DQ35
57
NC
58
NC
105
A8
106
BA0
11
VDD
12
VDD
59
NC
60
NC
107
Vss
108
Vss
13
DQ4
14
DQ36
61
CLK0
62
CKE0
109
A9
110
BA1
15
DQ5
16
DQ37
63
VDD
64
VDD
111
A10_AP
112
A11
17
DQ6
18
DQ38
65
/RAS
66
/CAS
113
VDD
114
VDD
19
DQ7
20
DQ39
67
/WE
68
NC
115
DQM2
116
DQM6
21
Vss
22
Vss
69
/CS0
70
NC
117
DQM3
118
DQM7
23
DQM0
24
DQM4
71
NC
72
NC
119
Vss
120
Vss
25
DQM1
26
DQM5
73
DU
74
CLK1
121
DQ24
122
DQ56
27
VDD
28
VDD
75
Vss
76
Vss
123
DQ25
124
DQ57
29
A0
30
A3
77
NC
78
31
A1
32
A4
79
NC
80
33
A2
34
A5
81
VDD
35
Vss
36
Vss
83
DQ16
37
DQ8
38
DQ40
85
39
DQ9
40
DQ41
87
41
DQ10
42
DQ42
89
43
DQ11
44
DQ43
45
VDD
46
VDD
47
DQ12
48
DQ44
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REV.1.0 (August.2002)
125
DQ26
126
DQ58
NC
127
DQ27
128
DQ59
82
VDD
129
VDD
130
VDD
84
DQ48
131
DQ28
132
DQ60
DQ17
86
DQ49
133
DQ29
134
DQ61
DQ18
88
DQ50
135
DQ30
136
DQ62
DQ19
90
DQ51
137
DQ31
138
DQ63
91
Vss
92
Vss
139
Vss
140
Vss
93
DQ20
94
DQ52
141
SDA
142
SCL
95
DQ21
96
DQ53
143
VDD
144
VDD
2
NC
HANBit Electronics Co.,Ltd.
HANBit
HSD2M64B2
FUNCTIONAL BLOCK DIAGRAM
DQ0-63
CKE0
/CA
CKE
CAS
/RAS
RAS
/CS0
CE
CKE
CAS
U1
DQM0
WE A0-A11 BA0-1 DQM4
U2
RAS
CE
DQM1
U3
CLK
DQ16-23,DQ48-55
DQM1
DQM5
CLK0B
DQM2
WE A0-A12 BA0-1 DQM6
DQM6
U4
RAS
CE
DQM0
DQM4
DQM2
RAS
CKE
CAS
CLK0A
CLK
DQ8-15,DQ40-47
WE A0-A11 BA0-1 DQM5
CKE
CAS
CE
CLK
DQ0-7,DQ32-39
CLK
DQ24-31,DQ56-63
DQM3
DQM3
WE A0-A11 BA0-1 DQM7
DQM7
/WE
A0 – A11
BA0-1
Vcc
Two 0.1uF Capacitors
per each SDRAM
Vss
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REV.1.0 (August.2002)
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HSD2M64B2
PIN FUNCTION DESCRIPTION
Pin
Name
CLK
System clock
/CE
Chip enable
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
CKE
Clock enable
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tSS prior to valid command.
Row/column addresses are multiplexed on the same pins.
A0 ~ A11
Address
Row address : RA0 ~ RA11, Column address : CA0 ~ CA8
Selects bank to be activated during row address latch time.
BA0 ~ BA1
Bank select address
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
/RAS
Row address strobe
Enables row access & precharge.
Column address
Latches column addresses on the positive going edge of the CLK with CAS low.
/CAS
strobe
Enables column access.
Enables write operation and row precharge.
/WE
Write enable
Latches data in starting from CAS, WE active.
Data input/output
Makes data output Hi-Z, tSHZ after the clock and masks the output.
DQM0 ~ 7
mask
DQ0 ~ 63
Data input/output
Power
Blocks data input when DQM active. (Byte masking)
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
VDD/VSS
supply/ground
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
VIN ,OUT
-1V to 4.6V
Voltage on Vcc Supply Relative to Vss
Vcc
-1V to 4.6V
Power Dissipation
PD
2W
TSTG
-55oC to 150oC
Voltage on Any Pin Relative to Vss
Storage Temperature
Short Circuit Output Current
IOS
100mA
Notes:
Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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REV.1.0 (August.2002)
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HANBit
HSD2M64B2
DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) )
PARAMETER
SYMBOL
MIN
TYP.
MAX
UNIT
NOTE
Supply Voltage
Vcc
3.0
3.3
3.6
V
Input High Voltage
VIH
2.0
3.0
Vcc+0.3
V
1
Input Low Voltage
VIL
-0.3
0
0.8
V
2
Output High Voltage
VOH
2.4
-
-
V
IOH = -2mA
Output Low Voltage
VOL
-
-
0.4
V
IOL = 2mA
Input leakage current
I LI
-10
10
uA
Notes:
1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
3
CAPACITANCE
(VCC = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)
DESCRIPTION
SYMBOL
MIN
MAX
UNITS
CCLK
2.5
4.0
pF
CIN
2.5
4.5
pF
Address
CADD
2.5
4.5
pF
DQ (DQ0 ~ DQ31)
COUT
4.0
6.5
pF
Clock
/RAS, /CAS,/WE,/CS, CKE, DQM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
TEST
PARAMETER
VERSION
SYMBOL
CONDITION
-8
-10
130
115
UNIT
NOTE
mA
2
Burst length = 1
Operating current
(One bank active)
ICC1
tRC ≥ tRC(min)
IO = 0mA
Precharge standby current in
ICC2P
power-down mode
ICC2PS
CKE ≤ VIL(max)
2
mA
2
mA
tCC=10ns
CKE & CLK ≤ VIL(max)
tCC=∞
CKE ≥ VIH(min)
Precharge standby current in
non power-down mode
ICC2N
CS* ≥ VIH(min),
tCC=10ns
mA
20
Input signals are changed
one time during 20ns
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REV.1.0 (August.2002)
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HANBit
HSD2M64B2
CKE ≥ VIH(min)
ICC2NS
CLK ≤ VIL(max),
tCC=∞
10
Input signals are stable
Active
standby
current
power-down mode
in
ICC3P
ICC3PS
CKE ≤ VIL(max), tCC=10ns
3
CKE&CLK ≤ VIL(max)
mA
3
tCC=∞
CKE≥VIH(min),
Active standby current in
ICC3N
CS*≥VIH(min),
tCC=10ns
non power-down mode
one time during 20ns
(One bank active)
CKE≥VIH(min)
ICC3NS
30
Input signals are changed
CLK ≤VIL(max),
mA
tCC=∞
20
Input signals are stable
IO = 0 mA
Operating current
Page burst
ICC4
(Burst mode)
150
130
mA
2
160
150
mA
3
4Banks Activated
tCCD = 2CLKs
Refresh current
ICC5
Self refresh current
ICC6
tRC ≥ tRC(min)
CKE ≤ 0.2V
2
mA
450
mA
5
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).
AC OPERATING TEST CONDITIONS
(vcc = 3.3V ± 0.3V, TA = 0 to 70°C)
PARAMETER
AC Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
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REV.1.0 (August.2002)
Value
UNIT
2.4/0.4
V
1.4
V
tr/tf = 1/1
Ns
1.4
V
See Fig. 2
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HANBit Electronics Co.,Ltd.
HANBit
HSD2M64B2
+3.3V
Vtt=1.4V
1200Ω
50Ω
DOUT
870Ω
DOUT
Z0=50Ω
50pF*
50pF
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
(Fig. 2) AC output load circuit
(Fig. 1) DC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
VERSION
PARAMETER
SYMBOL
-8
-10
UNIT
NOTE
Row active to row active delay
tRRD(min)
2
2
ns
1
RAS to CAS delay
tRP(min)
3
2
ns
1
Row precharge time
tRP(min)
3
2
ns
1
tRAS(min)
6
5
ns
1
Row active time
Row cycle time
tRAS(max)
100
tRC(min)
9
ns
7
ns
1
Last data in to row precharge
tRDL(min)
2
CLK
2.5
Last data in to new col. address delay
tCDL(min)
1
CLK
2
Last data in to burst stop
tBDL(min)
1
CLK
2
Col. address to col. address delay
tCCD(min)
1
CLK
3
ea
4
CAS latency=3
2
CAS latency=2
1
Number of valid output data
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
.
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REV.1.0 (August.2002)
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HANBit
HSD2M64B2
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
-8
PARAMETER
MIN
CLK cycle time
-10
SYMBOL
MAX
MIN
MAX
MIN
MAX
MIN
UNIT
NOTE
ns
1
ns
1,2
MAX
CAS
8
10
latency=3
tCC
1000
1000
CAS
10
12
latency=2
CLK to valid
CAS
output delay
latency=3
6
6
tSAC
CAS
6
8
latency=2
Output data
tOH
2.5
2.5
ns
2
CLK high pulse width
tCH
3
3.5
ns
3
CLK low pulse width
tCL
3
3.5
ns
3
Input setup time
tSS
2
2.5
ns
3
Input hold time
tSH
1
1
ns
3
CLK to output in Low-Z
tSLZ
1
1
ns
3
2
hold time
CLK to output
CAS
in Hi-Z
latency=3
6
6
ns
6
8
ns
tSHZ
CAS
latency=2
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered, ie., [(tr + tf)/2-1]ns should be added to
the parameter.
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REV.1.0 (August.2002)
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HANBit
HSD2M64B2
SIMPLIFIED TRUTH TABLE
COMMAND
Register
Mode register set
Auto refresh
Refresh
Entry
Self
refres
Exit
h
Bank active & row addr.
Read &
column
address
Write &
column
address
Auto
CKE
N
/C
S
/R
A
S
/C
A
S
/W
E
D
Q
M
H
X
L
L
L
L
X
OP code
L
L
L
H
X
X
X
X
H
H
L
L
H
H
X
L
H
H
H
H
X
X
X
L
L
H
H
X
BA
0,1
V
precharge
disable
Auto
CKE
n-1
precharge
H
X
L
H
L
H
X
Auto
H
X
L
H
L
L
X
H
Bank selection
e
All banks
Clock suspend or
active power down
Precharge
power
down mode
X
H
X
Entry
H
L
Exit
L
H
Entry
Exit
3
3
3
3
Column
H
(A0 ~ A9)
L
Address
H
L
DQM
H
No operation command
H
4,5
L
H
L
L
H
L
L
L
H
L
H
X
X
X
L
V
V
V
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
X
X
H
X
X
X
L
H
H
H
X
X
X
9
4
(A0 ~ A9)
4,5
X
V
L
X
H
6
X
X
X
X
X
X
V
X
X
X
(V=Valid, X=Don't care, H=Logic high, L=Logic low)
Notes :
1. OP Code : Operand code
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2 )
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REV.1.0 (August.2002)
4
Address
H
disable
Precharg
1,2
L
V
precharge
Burst Stop
NOTE
Column
precharge
disable
A9~A0
Row address
V
disable
Auto
A10/
AP
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HANBit
HSD2M64B2
TIMING DIAGRAMS
Please refer to attached timing diagram chart (II)
PACKAGING INFORMATION
Unit : mm
2.54 mm
0.25 mm MAX
MIN
1.0+ 0.1 mm
Gold: 1.04± 0.10 mm
Solder: 0.914± 0.10 mm
1.27 mm
(Solder & Gold Plating)
ORDERING INFORMATION
Part Number
Density
Org.
HMD2M64B2-10
16MByte
2Mx 64
HMD2M64B2-F10
16MByte
2Mx 64
HMD2M64B2-8
16MByte
2Mx 64
HMD2M64B2-F8
16MByte
2Mx 64
Package
144 Pin
SO-DIMM
144 Pin
SO-DIMM
144 Pin
SO-DIMM
144 Pin
SO-DIMM
Ref.
Vcc
4K
3.3V
4K
3.3V
4K
3.3V
4K
3.3V
Feature
MAX.frq
100MHz
Low Power
100MHz
125MHz
Low Power
125MHz
* F : Auto Self-Refresh with Low Power
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REV.1.0 (August.2002)
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