HANBit HSD32M64F8R Synchronous DRAM Module 256Mbyte (32Mx64bit), SMM ,16Mx16, 4Banks, 8K Ref. 3.3V Part No. HSD32M64F8R GENERAL DESCRIPTION The HSD32M64F8R is a 32M x 64 bit Synchronous Dynamic RAM high-density memory module. The module consists of eight CMOS 16M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages and 2K EEPROM in 8-pin TSSOP package on a 120-pin glass-epoxy. Three 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The HSD32M64F8R is a SMM(Stackable Memory Module type) .Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible. FEATURES • Part Identification HSD32M64F8R-10L : 100MHz (CL=3) HSD32M64F8R-10 : 100MHz (CL=2) HSD32M64F8R-13 : 133MHz (CL=3) • Burst mode operation • Auto & self refresh capability (8K Cycles/64ms) • LVTTL compatible inputs and outputs • Single 3.3V ±0.3V power supply • MRS cycle with address key programs - Latency (Access from column address) - Burst length (1, 2, 4, 8 & Full page) - Data scramble (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock • The used device is 4M x 16bit x 4Banks SDRAM URL:www.hbe.co.kr REV.1.0(August.2002). -1- HANBit Electronics Co.,Ltd HANBit HSD32M64F8R PIN ASSIGNMENT TOP BOTTOM P1 P3 P2 P4 PIN Symbo l PIN Symbo l PIN Symbo l PIN Symbol PIN Symb ol PIN Symb ol PI N Symb ol PIN Symbo l 1 Vcc 31 Vss 1 Vss 31 Vcc 1 Vcc 31 Vss 1 Vss 31 Vcc 2 DQ32 32 DQ0 2 DQ16 32 DQ48 2 DQ32 32 DQ0 2 DQ16 32 DQ48 3 DQ33 33 DQ1 3 DQ17 33 DQ49 3 DQ33 33 DQ1 3 DQ17 33 DQ49 4 DQ34 34 DQ2 4 DQ18 34 DQ50 4 DQ34 34 DQ2 4 DQ18 34 DQ50 5 DQ35 35 DQ3 5 DQ19 35 DQ51 5 DQ35 35 DQ3 5 DQ19 35 DQ51 6 DQ36 36 DQ4 6 DQ20 36 DQ52 6 DQ36 36 DQ4 6 DQ20 36 DQ52 7 DQ37 37 DQ5 7 DQ21 37 DQ53 7 DQ37 37 DQ5 7 DQ21 37 DQ53 8 DQ38 38 DQ6 8 DQ22 38 DQ54 8 DQ38 38 DQ6 8 DQ22 38 DQ54 9 DQ39 39 DQ7 9 DQ23 39 DQ55 9 DQ39 39 DQ7 9 DQ23 39 DQ55 10 Vcc 40 Vss 10 Vss 40 Vcc 10 Vcc 40 Vss 10 Vss 40 Vcc 11 DQ40 41 DQ8 11 DQ24 41 DQ56 11 DQ40 41 DQ8 11 DQ24 41 DQ56 12 DQ41 42 DQ9 12 DQ25 42 DQ57 12 DQ41 42 DQ9 12 DQ25 42 DQ57 13 DQ42 43 DQ10 13 DQ26 43 DQ58 13 DQ42 43 DQ10 13 DQ26 43 DQ58 14 DQ43 44 DQ11 14 DQ27 44 DQ59 14 DQ43 44 DQ11 14 DQ27 44 DQ59 15 DQ44 45 DQ12 15 DQ28 45 DQ60 15 DQ44 45 DQ12 15 DQ28 45 DQ60 16 DQ45 46 DQ13 16 DQ29 46 DQ61 16 DQ45 46 DQ13 16 DQ29 46 DQ61 17 DQ46 47 DQ14 17 DQ30 47 DQ62 17 DQ46 47 DQ14 17 DQ30 47 DQ62 18 DQ47 48 DQ15 18 DQ31 48 DQ63 18 DQ47 48 DQ15 18 DQ31 48 DQ63 19 Vcc 49 Vss 19 Vss 49 Vcc 19 Vcc 49 Vss 19 Vss 49 Vcc 20 DQM4 50 DQM0 20 DQM2 50 DQM6 20 DQM4 50 DQM0 20 DQM2 50 DQM6 21 DQM5 51 DQM1 21 DQM3 51 DQM7 21 DQM5 51 DQM1 21 DQM3 51 DQM7 22 REGE 52 /WE 22 NC 52 A12 22 REGE 52 /WE 22 NC 52 A12 23 CKE0 53 CLK0 23 BA0 53 A11 23 CKE0 53 CLK0 23 BA0 53 A11 24 NC 54 CLK1 24 BA1 54 A9 24 NC 54 CLK1 24 BA1 54 A9 25 Vcc 55 Vss 25 A10 55 A8 25 Vcc 55 Vss 25 A10 55 A8 26 SDA 56 /CAS 26 A0 56 A7 26 SDA 56 /CAS 26 A0 56 A7 27 SCL 57 /RAS 27 A1 57 A6 27 SCL 57 /RAS 27 A1 57 A6 28 /CS1 58 /CS0 28 A2 58 A5 28 /CS3 58 /CS2 28 A2 58 A5 29 /CS3 59 /CS2 29 A3 59 A4 29 NC 59 NC 29 A3 59 A4 30 Vcc 60 Vss 30 Vss 60 Vcc 30 Vcc 60 Vss 30 Vss 60 Vcc * Pin Names A0~A12: Address input (Multiplexed) DQ0~DQ63: Data input/output BA0~BA1: Select bank CLK0: Clock input CKE0: Clock enable input /CS0, /CS2: Chip select input /RAS: Row address strobe /WE: Write enable /CAS: Coulmn address strobe DQM0~7: DQM REGE: Register enable SDA: Serial data I/O VSS: Ground Vcc: Power supply(3.3V) SCL: Serial clock DU: Don’t use NC: No connection URL:www.hbe.co.kr REV.1.0(August.2002). -2- HANBit Electronics Co.,Ltd HANBit HSD32M64F8R Functional Block Diagram URL:www.hbe.co.kr REV.1.0(August.2002). -3- HANBit Electronics Co.,Ltd HANBit HSD32M64F8R PIN FUNCTION DESCRIPTION Pin Name Input Function CLK System clock Active on the positive going edge to sample all inputs. /CE Chip enable Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tss prior to valid command. A0 ~ A12 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA12, Column address : CA0 ~ CA8 BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. /RAS Row address strobe Latches row addresses on the positive going edge of the CLK with /RAS low. Enables row access & precharge. /CAS Column address strobe /WE Write Latches column addresses on the positive going edge of the CLK with /CAS low. Enables column access. enable Enables write operation and row precharge. Latches data in starting from /CAS, /WE active. DQM0 ~ 7 REGE Data input/output Makes data output Hi-Z, tsHZ after the clock and masks the output. mask Blocks data input when DQM active. (Byte masking) Register enable The device operates in the transparent mode when REGE is low. When REGE is high, the device operates in the registered mode. In registered mode, the Address and control inputs are latched if CLK is held at a high or low logic level. The inputs are strobed in the latch/flip-flop on the riging edge of CLK. REGE is tied to VDD through 10K ohm register on PCB. So if REGE of module is floating, this module will be operated as registerd mode. DQ0 ~ 63 Data input/output Data inputs/outputs are multiplexed on the same pins. Vcc/Vss Power Power and ground for the input buffers and the core logic. supply/ground URL:www.hbe.co.kr REV.1.0(August.2002). -4- HANBit Electronics Co.,Ltd HANBit HSD32M64F8R ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING VIN ,OUT -1V to 4.6V Voltage on Vcc Supply Relative to Vss Vcc -1V to 4.6V Power Dissipation PD 8W TSTG -55oC to 150oC Voltage on Any Pin Relative to Vss Storage Temperature Short Circuit Output Current IOS 50mA Notes: Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC OPERATING CONDITIONS (Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70°C) ) PARAMETER SYMBOL MIN TYP. MAX UNIT NOTE Supply Voltage Vcc 3.0 3.3 3.6 V Input High Voltage VIH 2.0 3.0 Vcc+0.3 V 1 Input Low Voltage VIL -0.3 0 0.8 V 2 Output High Voltage VOH 2.4 - - V IOH = -2mA Output Low Voltage VOL - - 0.4 V IOL = 2mA Input leakage current I LI -10 10 uA Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. 3 CAPACITANCE (Vcc = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV) DESCRIPTION SYMBOL MIN MAX UNITS Input capacitance(A0~A11) CIN1 2.5 5.0 pF Input capacitance(/RAS, /CAS,/WE) CIN2 2.5 5.0 pF Input capacitance(CKE0) CIN3 2.5 5.0 pF Input capacitance(CLK0) CIN4 2.5 4.0 pF Input capacitance(/CE0,CE3) CIN5 2.5 5.0 pF Input capacitance(DQM0~DQM7) CIN3 2.5 5.0 pF Input capacitance(BA0~BA1) CIN3 2.5 5.0 pF Data input/output capacitance (DQ0 ~ DQ63) COUT 4.0 6.5 pF URL:www.hbe.co.kr REV.1.0(August.2002). -5- HANBit Electronics Co.,Ltd HANBit HSD32M64F8R DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, T A = 0 to 70°C) TEST PARAMETER VERSION NOT SYMBOL UNIT CONDITION -13 -10L -10 960 880 880 E Burst length = 1 Operating current (One bank active) ICC1 tRC ≥ tRC(min) mA 1 8 mA 3 8 mA 3 mA 3 mA 3 mA 3 IO = 0mA Precharge standby ICC2P current in power-down mode ICC2PS CKE ≤ VIL(max) tCC=10ns CKE & CLK ≤ VIL(max) tCC=∞ CKE ≥ VIH(min) Precharge standby ICC2N /CE ≥ VIH(min), tcc=10ns 160 Input signals are changed one current in non power- time during 20ns down mode CKE ≥ VIH(min) ICC2NS CLK ≤ VIL(max), tcc=∞ 56 Input signals are stable Active standby current in power-down mode ICC3P ICC3PS CKE ≤ VIL(max), tcc=10ns 40 CKE&CLK ≤ VIL(max) 40 tcc=∞ CKE≥VIH(min), Active standby current in ICC3N /CE≥VIH(min), tcc=10ns 240 Input signals are changed one non power-down mode time during 20ns (One bank active) CKE≥VIH(min) ICC3NS CLK ≤VIL(max), tcc=∞ 160 Input signals are stable IO = 0 mA Operating current (Burst mode) Page burst ICC4 1.2 1 1 A 1 1.76 1.68 1.68 A 2 mA 3 4Banks Activated tCCD = 2CLKs Refresh current ICC5 tRC ≥ tRC(min) CKE ≤ 0.2V Self refresh current ICC6 Notes: 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Measured with 1PLL & 3 Drive Ics. 4. Unless otherwise noticed, input swing level is CMOS(V IH/VIL=VDDQ/VSSQ). URL:www.hbe.co.kr REV.1.0(August.2002). -6- 12 HANBit Electronics Co.,Ltd HANBit HSD32M64F8R AC OPERATING TEST CONDITIONS (Vcc = 3.3V ± 0.3V, TA = 0 to 70°C) PARAMETER Value UNIT 2.4/0.4 V 1.4 V tr/tf = 1/1 ns 1.4 V AC Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition See Fig. 2 +3.3V 1200Ω Vtt=1.4V DOUT 870Ω 50pF* 50Ω vss VOH (DC) = 2.4V, IOH = -2mA DOUT VOL (DC) = 0.4V, IOL = 2mA Z0=50Ω 50pF (Fig. 1) DC output load circuit (Fig. 2) AC output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) VERSION PARAMETER SYMBOL -13 -10L -10 UNIT NOTE Row active to row active delay tRRD(min) 15 20 20 ns 1 /RAS to /CAS delay tRCD(min) 20 20 24 ns 1 Row precharge time tRP(min) 20 20 24 ns 1 tRAS(min) 45 50 50 ns 1 Row active time tRAS(max) Row cycle time tRC(min) Last data in to row precharge tRDL(min) Last data in to Active delay 100 65 70 ns ns 1 2 CLK 2,5 tDAL(min) 2 CLK + 20 ns - 5 Last data in to new col. address delay tCDL(min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Col. address to col. address delay tCCD(min) 1 CLK 3 ea 4 CAS latency=3 2 CAS latency=2 1 Number of valid output data URL:www.hbe.co.kr REV.1.0(August.2002). -7- 80 HANBit Electronics Co.,Ltd HANBit HSD32M64F8R Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. .5. For -1H/1L, tRDL=1CLK and tDAL=1CLK+20ns is also supported . ( recommend : tRDL=2CLK and tDAL=2CLK + 20ns.) AC CHARACTERISTICS (AC operating conditions unless otherwise noted) -13 PARAMETER -10L -10 SYMBOL Min Max Min Max Min UNIT NOTE ns 1 ns 1,2 ns 2 Max CAS 7.5 CLK cycle latency=3 time CAS tCC 10 1000 10 1000 - 12 1000 13 latency=2 CLK to CAS valid latency=3 output CAS delay latency=2 5.4 6 7 tSAC - 7 7 CAS Output 2.7 3 3 latency=3 data tOH CAS hold time 3 3 latency=2 CLK high pulse width tCH 2.5 3 3.5 ns 3 CLK low pulse width tCL 2.5 3 3.5 ns 3 Input setup time tSS 1.5 2 2.5 ns 3 Input hold time tSH 0.8 1 1.5 ns 3 CLK to output in Low-Z tSLZ 1 1 1 ns 2 CAS CLK to 5.4 6 7 ns - 7 7 ns latency=3 output tSHZ CAS in Hi-Z latency=2 Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered i.e., [(tr + tf)/2-1]ns should be added to the parameter. URL:www.hbe.co.kr REV.1.0(August.2002). -8- HANBit Electronics Co.,Ltd HANBit HSD32M64F8R SIMPLIFIED TRUTH TABLE CKE n-1 COMMAND Register Mode register set Auto refresh Refresh Entry Self refres Exit h Bank active & row addr. Read & column address Write & column address Auto /R A S /C A S /W E D Q M X L L L L X OP code L L L H X X L H H H H X X X X X H L BA 0,1 L H H X L L H H X V H X L H L H X V precharge Auto precharge disable Auto precharge H H X L H L H Bank selection e All banks Clock suspend or active power down power down mode X X H X Entry H L Exit L H Entry H L Exit L H DQM H No operation command H L H H L L L H L H X X X L V V V X X X X H X X X L H H H H X X X V V V L X X H X X X L H H H X NOTE 1,2 3 3 3 3 Column H (A0 ~ A9) 4,5 L Column 4 H (A0 ~ A9) Address X V L X H -9- 4,5 6 X X X X X X V X X X (V=Valid, X=Don't care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at t RP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) URL:www.hbe.co.kr REV.1.0(August.2002). 4 Address X X A11 A9~A0 Row address V L enable Precharg A10/ AP L eable Burst Stop Precharge H /C E precharge disable Auto H CKE n HANBit Electronics Co.,Ltd 7 HANBit HSD32M64F8R TIMING DIAGRAMS td, tr = Delay of register (74LVC162835) Notes : 1. In case of module timing, command cycles 1CLK with respect to external input timing at the address and input signal because of the buffering in register (74LVC162835). Therefore, Input/Output signals of read/write function should be issued 1CLK earlier as compared to Unbuffered MODULE. 2. DIN is to be issued 1 clock after write command in external timing because D IN is issued directly to module. URL:www.hbe.co.kr REV.1.0(August.2002). - 10 - HANBit Electronics Co.,Ltd HANBit URL:www.hbe.co.kr REV.1.0(August.2002). HSD32M64F8R - 11 - HANBit Electronics Co.,Ltd HANBit URL:www.hbe.co.kr REV.1.0(August.2002). HSD32M64F8R - 12 - HANBit Electronics Co.,Ltd HANBit URL:www.hbe.co.kr REV.1.0(August.2002). HSD32M64F8R - 13 - HANBit Electronics Co.,Ltd HANBit URL:www.hbe.co.kr REV.1.0(August.2002). HSD32M64F8R - 14 - HANBit Electronics Co.,Ltd HANBit URL:www.hbe.co.kr REV.1.0(August.2002). HSD32M64F8R - 15 - HANBit Electronics Co.,Ltd HANBit URL:www.hbe.co.kr REV.1.0(August.2002). HSD32M64F8R - 16 - HANBit Electronics Co.,Ltd HANBit URL:www.hbe.co.kr REV.1.0(August.2002). HSD32M64F8R - 17 - HANBit Electronics Co.,Ltd HANBit URL:www.hbe.co.kr REV.1.0(August.2002). HSD32M64F8R - 18 - HANBit Electronics Co.,Ltd HANBit URL:www.hbe.co.kr REV.1.0(August.2002). HSD32M64F8R - 19 - HANBit Electronics Co.,Ltd HANBit URL:www.hbe.co.kr REV.1.0(August.2002). HSD32M64F8R - 20 - HANBit Electronics Co.,Ltd HANBit URL:www.hbe.co.kr REV.1.0(August.2002). HSD32M64F8R - 21 - HANBit Electronics Co.,Ltd HANBit URL:www.hbe.co.kr REV.1.0(August.2002). HSD32M64F8R - 22 - HANBit Electronics Co.,Ltd HANBit URL:www.hbe.co.kr REV.1.0(August.2002). HSD32M64F8R - 23 - HANBit Electronics Co.,Ltd HANBit URL:www.hbe.co.kr REV.1.0(August.2002). HSD32M64F8R - 24 - HANBit Electronics Co.,Ltd HANBit URL:www.hbe.co.kr REV.1.0(August.2002). HSD32M64F8R - 25 - HANBit Electronics Co.,Ltd HANBit URL:www.hbe.co.kr REV.1.0(August.2002). HSD32M64F8R - 26 - HANBit Electronics Co.,Ltd HANBit URL:www.hbe.co.kr REV.1.0(August.2002). HSD32M64F8R - 27 - HANBit Electronics Co.,Ltd HANBit URL:www.hbe.co.kr REV.1.0(August.2002). HSD32M64F8R - 28 - HANBit Electronics Co.,Ltd HANBit URL:www.hbe.co.kr REV.1.0(August.2002). HSD32M64F8R - 29 - HANBit Electronics Co.,Ltd HANBit HSD32M64F8R PACKAGING INFORMATION Unit : inch [mm] TOLERANCE : ±0.008 [ ±0.20 ] Front – Side Rear-Side ORDERING INFORMATION Part Number Density Org. HSD32M64F8R-10 256MByte 32M x 64 HSD32M64F8R-10L 256MByte 32M x 64 HSD32M64F8R-13 256MByte 32M x 64 URL:www.hbe.co.kr REV.1.0(August.2002). Package 120PIN STACKABLE 120PIN STACKABLE 120PIN STACKABLE - 30 - Ref. Vcc 8K 3.3V 8K 3.3V 8K 3.3V MODE MAX.frq 100Mhz CL=2 100Mhz CL=3 133Mhz CL=3 HANBit Electronics Co.,Ltd