HM62V256 Series 32,768-word × 8-bit Low Voltage Operation CMOS Static RAM ADE-203-136E (Z) Rev. 5.0 Jun. 19, 1995 Features • Low voltage operation SRAM Operating Supply Voltage: 2.7 V to 3.6 V • 0.8 µm Hi-CMOS process • High speed Access time: 70/85/100 ns (max) • Low power Standby: 0.15 µW (typ) • Completely static memory No clock or timing strobe required • Directly LVTTL compatible: All inputs and outputs Ordering Information Type No. Access Time Package HM62V256LFP-10T 100 ns 450 mil 280 pin plastic SOP (FP-28DA) HM62V256LFP-7SLT HM62V256LFP-10SLT 70 ns 100 ns HM62V256LFP-8ULT 85 ns HM62V256LT-10 100 ns HM62V256LT-8SL 85 ns HM62V256LTM-10 100 ns HM62V256LTM-7SL HM62V256LTM-10SL 70 ns 100 ns HM62V256LTM-8UL 85 ns 8 mm × 14 mm 32 pin TSOP (normal type) (TFP-32DA) 8 mm × 13.4 mm 28-pin TSOP (normal type) (TFP-28DA) HM62V256 Series Pin Arrangement HM62W256LFP Series A14 1 28 VCC A12 2 27 WE A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 OE A2 8 21 A10 A1 9 20 CS A0 10 19 I/O7 I/O0 11 18 I/O6 I/O1 12 17 I/O5 I/O2 13 16 I/O4 VSS 14 15 I/O3 (Top View) HM62W256LT Series OE A11 NC A9 A8 A13 WE VCC A14 A12 A7 A6 A5 NC A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A10 CS NC I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 NC A1 A2 21 20 19 18 17 16 15 14 13 12 11 10 9 8 A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 V SS I/O2 I/O1 I/O0 A0 A1 A2 (Top View) HM62W256LTM Series OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 22 23 24 25 26 27 28 1 2 3 4 5 6 7 (Top View) 2 HM62V256 Series Pin Description Pin name Function A0 to A14 Address inputs I/O0 to I/O7 Data input/output CS Chip select WE Write enable OE Output enable NC No connection VCC Power supply VSS Ground 3 HM62V256 Series Block Diagram V CC (MSB) A12 V SS A5 A7 A6 A8 • • • • A13 A14 • • Row Decoder Memory Matrix 512 × 512 • • • • A4 (LSB) A3 I/O0 • • • • • • • Column I/O • • • • • • Input Data Control Column Decoder • • I/O7 • • A2 A1 A0 A10 A9 A11 (LSB) • • CS WE OE 4 Timing Pulse Generator Read/Write Control (MSB) • • HM62V256 Series Function Table WE CS OE Mode VCC Current I/O Pin Ref. Cycle X H X Not selected ISB , ISB1 High-Z — H L H Output disable ICC High-Z — H L L Read ICC Dout Read cycle (1)–(3) L L H Write ICC Din Write cycle (1) L L L Write ICC Din Write cycle (2) Note: X: H or L Absolute Maximum Ratings Parameter Power supply voltage *1 Symbol Value VCC –0.5 to 4.6 2 Unit V *1 *3 Terminal voltage VT –0.5* to VCC+0.5 Power dissipation PT 1.0 W Operating temperature Topr 0 to + 70 °C Storage temperature Tstg –55 to +125 °C Storage temperature under bias Tbias –10 to +85 °C V Notes: 1. Relative to VSS 2. VT min: –3.0 V for pulse half-width ≤ 50 ns 3. Maximum voltage is 4.6V Recommended DC Operating Conditions (Ta = 0 to +70°C) Parameter Symbol Min Typ Max Unit Supply voltage VCC 2.7 3.0 3.6 V VSS 0 0 0 V VIH 0.7VCC — VCC+0.3 V VIL *1 — 0.2VCC V Input high(logic 1) voltage Input low(logic 0) voltage Note: –0.3 1. VT min: –3.0 V for pulse half-width ≤ 50 ns 5 HM62V256 Series DC Characteristics (Ta = 0 to +70°C, VCC = 2.7 V to 3.6V, VSS = 0 V) Parameter Symbol Min Typ*1 Max Unit Test conditions Input leakage current |ILI| — — 1 µA VSS ≤ Vin ≤ VCC Output leakage current |ILO | — — 1 µA CS = VIH or OE = VIH or WE = VIL, VSS ≤ VI/O ≤ VCC Operating power supply current (DC) ICCDC1 — — 15 mA CS = VIL, others = VIH/VIL II/O = 0 mA ICCDC2 — — 10 mA CS ≤ 0.2 V, VIH ≥ VCC – 0.2 V, VIL ≤ 0.2 V, II/O = 0 mA HM62V256-7 ICCAC1 — — 30 mA min cycle, duty = 100 %, II/O = 0 mA CS = VIL, others = VIH/VIL HM62V256-8 ICCAC1 — — 27 HM62V256-10 ICCAC1 — — 24 ICCAC2 — — 15 mA Cycle time ≥ 1 µs, duty = 100% II/O = 0 mA, CS ≤ 0.2 V, VIH ≥ VCC – 0.2 V, VIL ≤ 0.2 V ISB — 0.1 1 mA CS = VIH ISB1 — 0.05 50 µA Vin ≥ 0 V, CS ≥ VCC – 0.2 V, Average operating power supply current Standby power supply current *2 — 0.05 10 — 0.05 4*3 Output low voltage VOL — — 0.2 V IOL = 20 µA Output high voltage VOH VCC – 0.2 — — V IOH = –20 µA Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25°C and not guaranteed. 2. This characteristic is guaranteed only for L-SL version. 3. This characteristic is guaranteed only for L-UL version. Capacitance (Ta = 25°C, f = 1.0 MHz) Parameter Input capacitance *1 *1 Input/output capacitance Note: 6 Symbol Min Typ Max Unit Test Conditions Cin — — 5 pF Vin = 0 V CI/O — — 8 pF VI/O = 0 V 1. This parameter is sampled and not 100% tested. HM62V256 Series AC Characteristics (Ta = 0 to +70°C, VCC = 2.7 V to 3.6 V, unless otherwise noted.) Test Conditions • Input pulse levels: 0.4 V to 2.4 V • Input rise and fall time: 5 ns • Input and output timing reference level: 1.4 V Output Load 500Ω Dout 50 pF* 1.4 V (Including scope & jig) Read Cycle HM62V256 -7 Parameter Symbol Min Read cycle time tRC Address access time -8 -10 Max Min Max Min Max Unit Notes 70 — 85 — 100 — ns tAA — 70 — 85 — 100 ns Chip select access time tACS — 70 — 85 — 100 ns Output enable to output valid tOE — 35 — 45 — 50 ns Chip selection to output in low-Z tCLZ 10 — 10 — 10 — ns 2 Output enable to output in low-Z tOLZ 5 — 5 — 5 — ns 2 Chip deselection to output in high-Z tCHZ 0 25 0 30 0 35 ns 1, 2 Output disable to output in high-Z tOHZ 0 25 0 30 0 35 ns 1, 2 Output hold from address change tOH 10 — 10 — 10 — ns Notes: 1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 7 HM62V256 Series Read Timing Waveform (1) (WE = VIH) t RC Address Valid address t AA t ACS CS t OH t OE t OLZ OE t OHZ t CHZ High impedance Dout Valid data Read Timing Waveform (2) (WE = VIH, CS = VIL , OE = VIL ) t RC Valid address Address tAA t OH t OH Dout Valid data Read Timing Waveform (3) (WE = VIH, OE = VIL )*1 t ACS CS t CLZ Dout High impedance t CHZ Valid data Note: 1. Address must be valid prior to or simultaneously with CS going low. 8 HM62V256 Series Write Cycle HM62V256 -7 Parameter Symbol Min Write cycle time tWC Chip selection to end of write -8 -10 Max Min Max Min Max Unit Notes 70 — 85 — 100 — ns tCW 50 — 75 — 80 — ns 4 Address setup time tAS 0 — 0 — 0 — ns 5 Address valid to end of write tAW 50 — 75 — 80 — ns Write pulse width tWP 45 — 55 — 60 — ns 3, 8 Write recovery time tWR 0 — 0 — 0 — ns 6 Write to output in high-Z tWHZ 0 25 0 30 0 35 ns 1, 2, 7 Data to write time overlap tDW 30 — 35 — 40 — ns Data hold from write time tDH 0 — 0 — 0 — ns Output active from end of write tOW 10 — 10 — 10 — ns 2 Output disable to output in high-Z tOHZ 0 25 0 30 0 35 ns 1, 2, 7 Notes: 1. tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. A write occurs during the overlap (tWP) of a low CS and a low WE. A write begins at the later transition of CS going low or WE going low. A write ends at the earlier transition of CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 4. tCW is measured from CS going low to the end of write. 5. tAS is measured from the address valid to the beginning of write. 6. tWR is measured from the earlier of WE or CS going high to the end of write cycle. 7. During this period, I/O pins are in the output state so that the input signals of the opposite phase to the outputs must not be applied. 8. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of data bus contention, tWP ≥ tWHZ max + tDW min. 9 HM62V256 Series Write Timing Waveform (1) (OE Clock) t WC Address Valid address t AW t WR OE t CW CS *1 t WP t AS WE t OHZ High impedance Dout t DW Din High impedance t DH Valid data Notes: 1. If CS goes low simultaneously with WE going low or after WE going low, the outputs remain in the high impedance state. 10 HM62V256 Series Write Timing Waveform (2) (OE Low Fixed) t WC Address Valid address t WR t CW CS *1 t AW t OH tWP WE tAS t WHZ t OW *2 *3 Dout t DW t DH *4 Din High impedance Valid data Notes: 1. If CS goes low simultaneously with WE going low or after WE going low, the outputs remain in the high impedance state. 2. Dout is the same phase of the write data of this write cycle. 3. Dout is the read data of next address. 4. If CS is low during this period, I/O pins are in the output state. Therefore, the input signals of theopposite phase to the output must not be applied to them. 11 HM62V256 Series Low VCC Data Retention Characteristics (Ta = 0 to +70°C) Parameter Symbol Min Typ*1 Max Unit Test conditions*6 VCC for data retention VDR 2.0 — V CS ≥ VCC – 0.2 V, Vin ≥ 0 V µA VCC = 2.7 V, Vin ≥ 0 V CS ≥ VCC – 0.2 V See retention waveform Data retention current ICCDR Chip deselect to data retention time Operation recovery time Notes: 1. 2. 3. 4. 5. 6. tCDR tR 3.6 *2 — 0.05 27 — 0.05 7*3 — 0.05 2*4 — — ns — — ns 0 *5 tRC Typical values are at VCC = 2.7 V, Ta = 25°C and not guaranteed. 9 µA max at Ta = 0 to 40°C. This characteristics guaranteed for only L-SL version. 2.0 µA max at Ta = 0 to 40°C. This characteristics guaranteed for only L-UL version. 0.4 µA max at Ta = 0 to 40°C. tRC = read cycle time. CS controls address buffer, WE buffer, OE buffer, and Din buffer. If CS controls data retention mode, other input levels (address, WE, OE, I/O) can be in the high impedance state. Low VCC Data Retention Timing Waveform Data retention mode V CC 2.7 V tR t CDR 0.7 V CC V DR CS 0V 12 CS > VCC – 0.2 V HM62V256 Series Package Dimensions HM62V256LFP Series (FP-28DA) Unit: mm 18.00 18.75 Max 15 1.27 Max 11.80 ± 0.30 1.70 0 – 10 ° 0.20 ± 0.10 + 0.10 0.40 – 0.05 1.27 ± 0.10 + 0.08 – 0.07 14 0.17 1 3.00 Max 8.40 28 1.00 ± 0.20 HM62V256LT Series (TFP-32DA) Unit: mm 8.00 8.20 Max 17 1 16 12.40 32 0.50 0.08 M 14.00 ± 0.20 0.10 0.17 ± 0.05 1.20 Max 0.45 Max 0.13 ± 0.05 0.20 ± 0.10 0.80 0–5° 0.50 ± 0.10 13 HM62V256 Series HM62V256LTM Series (TFP-28DA) Unit: mm 8.00 8.15 Max 8 11.80 21 22 7 0.55 0.20 +0.10 –0.05 0.10 M +0.10 0.05 –0.05 +0.05 –0.02 0.15 1.2 Max 14 0.10 0.80 13.4 ± 0.3 0.63 Max 5° Max 0.50 ± 0.10