HM62W16255HCI Series Wide Temperature Range Version 4M High Speed SRAM (256-kword × 16-bit) ADE-203-1263A (Z) Rev. 1.0 Nov. 1, 2001 Description The HM62W16255HCI is a 4-Mbit high speed static RAM organized 256-kword × 16-bit. It has realized high speed access time by employing CMOS process (6-transistor memory cell) and high speed circuit designing technology. It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. The HM62W16255HCI is packaged in 400-mil 44-pin SOJ and 400-mil 44-pin plastic TSOPII for high density surface mounting. Features • Single 3.3 V supply: 3.3 V ± 0.3 V • Access time: 12 ns (max) • Completely static memory No clock or timing strobe required • Equal access and cycle times • Directly TTL compatible All inputs and outputs • Operating current: 130 mA (max) • TTL standby current: 40 mA (max) • CMOS standby current: 5 mA (max) • Center VCC and VSS type pinout • Temperature range: –40 to +85°C HM62W16255HCI Series Ordering Information Type No. Access time Device marking Package HM62W16255HCJPI-12 12 ns HM62W16255CJPI12 400-mil 44-pin plastic SOJ (CP-44D) HM62W16255HCTTI-12 12 ns HM62W16255CTTI12 400-mil 44-pin plastic TSOPII (TTP-44DE) Rev.1, Nov. 2001, page 2 of 17 HM62W16255HCI Series Pin Arrangement Pin Description Pin name Function A0 to A17 Address input I/O1 to I/O16 Data input/output CS Chip select OE Output enable WE Write enable UB Upper byte select LB Lower byte select VCC Power supply VSS Ground NC No connection Rev.1, Nov. 2001, page 3 of 17 HM62W16255HCI Series Block Diagram Rev.1, Nov. 2001, page 4 of 17 HM62W16255HCI Series Operation Table CS OE WE LB UB Mode VCC current I/O1–I/O8 I/O9–I/O16 Ref. cycle H × × × × Standby ISB, ISB1 High-Z High-Z — L H H × × Output disable ICC High-Z High-Z — L L H L L Read ICC Output Output Read cycle L L H L H Lower byte read ICC Output High-Z Read cycle L L H H L Upper byte read ICC High-Z Output Read cycle L L H H H — ICC High-Z High-Z — L × L L L Write ICC Input Input Write cycle L × L L H Lower byte write ICC Input High-Z Write cycle L × L H L Upper byte write ICC High-Z Input Write cycle L × L H H — High-Z High-Z — Note: ICC H: VIH, L: VIL, ×: VIH or VIL Absolute Maximum Ratings Parameter Symbol Value Supply voltage relative to VSS VCC –0.5 to +4.6 1 Unit V 2 Voltage on any pin relative to VSS VT –0.5* to VCC + 0.5* V Power dissipation PT 1.0 W Operating temperature Topr –40 to +85 °C Storage temperature Tstg –55 to +125 °C Storage temperature under bias Tbias –40 to +85 °C Notes: 1. VT (min) = –2.0 V for pulse width (under shoot) ≤ 6 ns 2. VT (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns Rev.1, Nov. 2001, page 5 of 17 HM62W16255HCI Series Recommended DC Operating Conditions (Ta = –40 to +85°C) Parameter Supply voltage Input voltage Symbol Min Typ Max Unit VCC* 3 3.0 3.3 3.6 V VSS* 4 0 0 0 VIH 2.0 VIL –0.5* 1 — VCC + 0.5* — 0.8 V 2 V V Notes: 1. VIL (min) = –2.0 V for pulse width (under shoot) ≤ 6 ns 2. VIH (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns 3. The supply voltage with all VCC pins must be on the same level. 4. The supply voltage with all VSS pins must be on the same level. DC Characteristics (Ta = –40 to +85°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) 1 Parameter Symbol Min Typ* Max Unit Test conditions Input leakage current |ILI| — — 2 µA Vin = VSS to VCC Output leakage current |ILO| — — 2 µA Vin = VSS to VCC Operating power supply current ICC — — 130 mA Min cycle CS = VIL, Iout = 0 mA Other inputs = VIH/VIL Standby power supply current ISB — — 40 mA Min cycle, CS = VIH, Other inputs = VIH/VIL ISB1 — 2.5 5 mA f = 0 MHz VCC ≥ CS ≥ VCC – 0.2 V, (1) 0 V ≤ Vin ≤ 0.2 V or (2) VCC ≥ Vin ≥ VCC – 0.2 V VOL — — 0.4 V IOL = 8 mA VOH 2.4 — — V IOH = –4 mA Output voltage Notes: 1. Typical values are at VCC = 3.3 V, Ta = +25°C and not guaranteed. Rev.1, Nov. 2001, page 6 of 17 HM62W16255HCI Series Capacitance (Ta = +25°C, f = 1.0 MHz) Parameter Input capacitance* 1 Input/output capacitance* Note: 1 Symbol Min Typ Max Unit Test conditions Cin — — 6 pF Vin = 0 V CI/O — — 8 pF VI/O = 0 V 1. This parameter is sampled and not 100% tested. Rev.1, Nov. 2001, page 7 of 17 HM62W16255HCI Series AC Characteristics (Ta = –40 to +85°C, VCC = 3.3 V ± 0.3 V, unless otherwise noted.) Test Conditions • Input pulse levels: 3.0 V/0.0 V • Input rise and fall time: 3 ns • Input and output timing reference levels: 1.5 V • Output load: See figures (Including scope and jig) Read Cycle HM62W16255HCI -12 Parameter Symbol Min Max Unit Read cycle time tRC 12 — ns Address access time tAA — 12 ns Chip select access time tACS — 12 ns Output enable to output valid tOE — 6 ns Byte select to output valid tLB, tUB — 6 ns Output hold from address change tOH 3 — ns Chip select to output in low-Z tCLZ 3 — ns 1 Output enable to output in low-Z tOLZ 0 — ns 1 Byte select to output in low-Z tLBLZ, tUBLZ 0 — ns 1 Chip deselect to output in high-Z tCHZ — 6 ns 1 Output disable to output in high-Z tOHZ — 6 ns 1 Byte deselect to output in high-Z tLBHZ, tUBHZ — 6 ns 1 Rev.1, Nov. 2001, page 8 of 17 Notes HM62W16255HCI Series Write Cycle HM62W16255HCI -12 Parameter Symbol Min Max Unit Notes Write cycle time tWC 12 — ns Address valid to end of write tAW 8 — ns Chip select to end of write tCW 8 — ns 8 Write pulse width tWP 8 — ns 7 Byte select to end of write tLBW, tUBW 8 — ns 9, 10 Address setup time tAS 0 — ns 5 Write recovery time tWR 0 — ns 6 Data to write time overlap tDW 6 — ns Data hold from write time tDH 0 — ns Write disable to output in low-Z tOW 3 — ns 1 Output disable to output in high-Z tOHZ — 6 ns 1 Write enable to output in high-Z tWHZ — 6 ns 1 Notes: 1. Transition is measured ±200 mV from steady voltage with output load (B). This parameter is sampled and not 100% tested. 2. If the CS or LB or UB low transition occurs simultaneously with the WE low transition or after the WE transition, output remains a high impedance state. 3. WE and/or CS must be high during address transition time. 4. If CS, OE, LB and UB are low during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 5. tAS is measured from the latest address transition to the latest of CS, WE, LB or UB going low. 6. tWR is measured from the earliest of CS, WE, LB or UB going high to the first address transition. 7. A write occurs during the overlap of low CS, low WE and low LB or low UB. 8. tCW is measured from the later of CS going low to the end of write. 9. tLBW is measured from the later of LB going low to the end of write. 10. tUBW is measured from the later of UB going low to the end of write. Rev.1, Nov. 2001, page 9 of 17 HM62W16255HCI Series Timing Waveforms Read Timing Waveform (1) (WE = VIH) Rev.1, Nov. 2001, page 10 of 17 HM62W16255HCI Series Read Timing Waveform (2) (W W E = VIH, L B = VIL, U B , = VIL) Rev.1, Nov. 2001, page 11 of 17 HM62W16255HCI Series Write Timing Waveform (1) (LB, UB Controlled) Rev.1, Nov. 2001, page 12 of 17 HM62W16255HCI Series Write Timing Waveform (2) (WE Controlled) Rev.1, Nov. 2001, page 13 of 17 HM62W16255HCI Series Write Timing Waveform (3) (CS Controlled) Rev.1, Nov. 2001, page 14 of 17 HM62W16255HCI Series Package Dimensions HM62W16255HCJPI Series (CP-44D) Rev.1, Nov. 2001, page 15 of 17 HM62W16255HCI Series HM62W16255HCTTI Series (TTP-44DE) Rev.1, Nov. 2001, page 16 of 17 HM62W16255HCI Series Disclaimer 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Sales Offices Title: (adaddsem010416.EPS) Creator: Adobe Illustrator(TM) 5.5 Preview: This EPS picture was not saved with a preview included in it. Comment: This EPS picture will print to a PostScript printer, but not to other types of printers. Rev.1, Nov. 2001, page 17 of 17