HYNIX HY29DL163BT-70I

HY29DL162/HY29DL163
16 Megabit (2M x 8/1M x16) Low Voltage,
Dual Bank, Simultaneous Read/Write Flash Memory
KEY FEATURES
n Single Power Supply Operation
n
n
n
n
n
n
n
n
n
n
n
− Read, program, and erase operations
from 2.7 to 3.6 V
− Ideal for battery-powered applications
Simultaneous Read/Write Operations
− Host system can program or erase in one
bank while simultaneously reading from any
sector in the other bank with zero latency
between read and write operations
High Performance
− 70 and 80 ns access time versions with
30pF load
− 90 and 120 ns access time versions with
100pF load
Ultra Low Power Consumption (Typical
Values)
− Automatic sleep mode current: 200 nA
− Standby mode current: 200 nA
− Read current: 10 mA (at 5 MHz)
− Program/erase current: 15 mA
Boot-Block Sector Architecture with 39
Sectors in Two Banks for Fast In-System
Code Changes
Secured Sector: An Extra 64 Kbyte Sector
that Can Be:
− Factory locked and identifiable: 16 bytes
available for a secure, random factoryprogrammed Electronic Serial Number
− Customer lockable: Can be read, programmed, or erased just like other sectors
Flexible Sector Architecture
− Sector Protection allows locking of a
sector or sectors to prevent program or
erase operations within that sector
− Temporary Sector Unprotect allows
changes in locked sectors (requires high
voltage on RESET# pin)
Automatic Erase Algorithm Erases Any
Combination of Sectors or the Entire Chip
Automatic Program Algorithm Writes and
Verifies Data at Specified Addresses
Compliant with Common Flash Memory
Interface (CFI) Specification
Minimum 100,000 Write Cycles per Sector
(1,000,000 cycles Typical)
Compatible with JEDEC Standards
− Pinout and software compatible with
single-power supply Flash devices
− Superior inadvertent write protection
Preliminary
Revision 1.3, June 2001
n Data# Polling and Toggle Bits
n
n
n
n
n
n
− Provide software confirmation of completion
of program or erase operations
Ready/Busy# Pin
− Provides hardware confirmation of
completion of program or erase operations
Erase Suspend
− Suspends an erase operation to allow
programming data to or reading data from
a sector in the same bank
− Erase Resume can then be invoked to
complete the suspended erasure
Hardware Reset Pin (RESET#) Resets the
Device to Reading Array Data
WP#/ACC Input Pin
− Write protect (WP#) function allows
hardware protection of two outermost boot
sectors, regardless of sector protect status
− Acceleration (ACC) function provides
accelerated program times
Fast Program and Erase Times
− Sector erase time: 0.5 sec typical
− Byte/Word program time utilizing
Acceleration function: 10 µs typical
Space Efficient Packaging
− 48-pin TSOP and 48-ball FBGA packages
LOGIC DIAGRAM
20
8
A[19:0]
DQ[7:0]
7
CE#
DQ[14:8]
OE#
DQ[15]/A[-1]
WE#
WP#/ACC
RESET#
BYTE#
RY/BY#
HY29DL162/HY29DL163
GENERAL DESCRIPTION
The HY29DL162/HY29DL163 (HY29DL16x) is a
16 Mbit, 3 volt-only CMOS Flash memory organized as 2,097,152 (2M) bytes or 1,048,576 (1M)
words. The device is available in 48-pin TSOP
and 48-ball FBGA packages. Word-wide data
(x16) appears on DQ[15:0] and byte-wide (x8) data
appears on DQ[7:0].
The HY29DL16x Flash memory array is organized
into 39 sectors in two banks. Bank 1 contains
eight 8 Kbyte boot/parameter sectors and 3 or 7
larger sectors of 64 Kbytes each, depending on
the version of the device. Bank 2 contains the
rest of the memory array, organized as 28 or 24
sectors of 64 Kbytes:
Bank 1
Bank 2
HY29DL162
8 x 8KB/4KW
3 x 64KB/32KW
28 x 64KB/32KW
HY29DL163
8 x 8KB/4KW
7 x 64KB/32KW
24 x 64KB/32KW
The device features simultaneous read/write operation which allows the host system to invoke a
program or erase operation in one bank and immediately and simultaneously read data from the
other bank, except if that bank has any sectors
marked for erasure, with zero latency. This releases the system from waiting for the completion
of program or erase operations, thus improving
overall system performance.
The HY29DL16x can be programmed and erased
in-system with a single 2.7 - 3.6 volt VCC supply.
Internally generated and regulated voltages are
provided for program and erase operations, so that
the device does not require a higher voltage VPP
power supply to perform those functions. The device can also be programmed in standard EPROM
programmers. Access times as low as 70 ns are
offered for timing compatibility with the zero wait
state requirements of high speed microprocessors. To eliminate bus contention, the HY29DL16x
has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
The device is compatible with the JEDEC singlepower-supply Flash command set standard. Commands are written to the command register using
standard microprocessor write timings, from where
they are routed to an internal state-machine that
controls the erase and programming circuits.
2
Device programming is performed a byte/word at
a time by executing the four-cycle Program Command write sequence. This initiates an internal
algorithm that automatically times the program
pulse widths and verifies proper cell margin. Faster
programming times can be achieved by placing
the HY29DL16x in the Unlock Bypass mode, which
requires only two write cycles to program data instead of four.
The HY29DL16x’s sector erase architecture allows
any number of array sectors, in one or both banks,
to be erased and reprogrammed without affecting
the data contents of other sectors. Device erasure
is initiated by executing the Erase Command sequence. This initiates an internal algorithm that
automatically preprograms the sector before executing the erase operation. As during programming cycles, the device automatically times the
erase pulse widths and verifies proper cell margin. Hardware Sector Group Protection optionally disables both program and erase operations
in any combination of the sector groups, while
Temporary Sector Group Unprotect, which requires a high voltage on one pin, allows in-system
erasure and code changes in previously protected
sector groups. Erase Suspend enables the user
to put erase on hold in a bank for any period of
time to read data from or program data to any
sector in that bank that is not selected for erasure. True background erase can thus be
achieved. Because the HY29DL16x features simultaneous read/write capability, there is no need
to suspend to read from a sector located within a
bank that does not contain sectors marked for erasure. The device is fully erased when shipped
from the factory.
Addresses and data needed for the programming
and erase operations are internally latched during
write cycles. The host system can detect completion of a program or erase operation by observing
the RY/BY# pin or by reading the DQ[7] (Data#
Polling) and DQ[6] (Toggle) status bits. Hardware
data protection measures include a low VCC detector that automatically inhibits write operations
during power transitions.
After a program or erase cycle has been completed, or after assertion of the RESET# pin (which
terminates any operation in progress), the device
is ready to read data or to accept another comr1.3/June 01
HY29DL162/HY29DL163
mand. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
The Secured Sector is an extra 64 Kbyte sector
capable of being permanently locked at the factory or by customers. The Secured Indicator Bit
(accessed via the Electronic ID mode) is permanently set to a 1 if the part is factory locked, and
permanently set to a 0 if customer lockable. This
way, customer lockable parts can never be used
to replace a factory locked part. Factory locked
parts provide several options. The Secured Sector may store a secure, random 16-byte ESN (Electronic Serial Number), customer code programmed
at the factory, or both. Customer Lockable parts
may utilize the Secured Sector as bonus space,
reading and writing like any other Flash sector, or
may permanently lock their own code there.
The WP#/ACC pin provides access to two functions. The Write Protect function provides a hardware method of protecting certain boot sectors
without using a high voltage. The Accelerate function speeds up programming operations, and is
intended primarily to allow faster manufacturing
throughput.
Two power-saving features are embodied in the
HY29DL16x. When addresses have been stable
for a specified amount of time, the device enters
the automatic sleep mode. The host can also place
the device into the standby mode. Power consumption is greatly reduced in both these modes.
Common Flash Memory Interface (CFI)
To make Flash memories interchangeable and to
encourage adoption of new Flash technologies,
major Flash memory suppliers developed a flexible method of identifying Flash memory sizes and
configurations in which all necessary Flash device
parameters are stored directly on the device.
Parameters stored include memory size, byte/word
configuration, sector configuration, necessary voltages and timing information. This allows one set
of software drivers to identify and use a variety of
different, current and future Flash products. The
standard which details the software interface necessary to access the device to identify it and to
determine its characteristics is the Common Flash
Memory Interface (CFI) Specification. The
HY29DL16x is fully compliant with this specification.
BLOCK DIAGRAM
DQ[15:0]
A[19:0], A[-1]
STATE
CONTROL
ERASE VOLTAGE
GENERATOR AND
SECTOR SWITCHES
COMMAND
REGISTER
WE#
CE#
OE#
RESET#
CFI
CONTROL
I/O BUFFERS
CFI DATA
MEMORY
I/O CONTROL
DATA LATCH
PROGRAM
VOLTAGE
GENERATOR
BYTE#
WP#/ACC
TIMER
V CC
DETECTOR
A[19:0], A[-1]
ADDRESS LATCH
RY/BY#
Y-DECODER
X-DECODER
Y-GATING
16 Mb FLASH
MEMORY
ARRAY
(2 Banks,
39 Sectors)
0.5 Mb FLASH
Security Sector
r1.3/June 01
3
HY29DL162/HY29DL163
PIN CONFIGURATIONS
A[15]
A[14]
A[13]
A[12]
A[11]
A[10]
A[9]
A[8]
A[19]
NC
WE#
RESET#
NC
WP#/ACC
RY/BY#
A[18]
A[17]
A[7]
A[6]
A[5]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A[4]
A[3]
A[2]
A[1]
21
22
23
24
TSOP48
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
A[16]
BYTE#
V SS
DQ[15]/A[-1]
DQ[7]
DQ[14]
DQ[6]
DQ[13]
DQ[5]
DQ[12]
DQ[4]
V CC
DQ[11]
DQ[3]
DQ[10]
DQ[2]
DQ[9]
DQ[1]
DQ[8]
DQ[0]
28
27
26
25
OE#
V SS
CE#
A[0]
48-Ball FBGA (Top View, Balls Facing Down)
4
A6
B6
C6
D6
E6
F6
G6
H6
A[13]
A[12]
A[14]
A[15]
A[16]
BYTE#
DQ[15]/A[-1]
V SS
A5
B5
C5
D5
E5
F5
G5
H5
A[9]
A[8]
A[10]
A[11]
DQ[7]
DQ[14]
DQ[13]
DQ[6]
A4
B4
C4
D4
E4
F4
G4
H4
WE#
RESET#
NC
A[19]
DQ[5]
DQ[12]
VCC
DQ[4]
A3
B3
C3
D3
E3
F3
G3
H3
RY/BY#
WP#/ACC
A[18]
NC
DQ[2]
DQ[10]
DQ[11]
DQ[3]
A2
B2
C2
D2
E2
F2
G2
H2
A[7]
A[17]
A[6]
A[5]
DQ[0]
DQ[8]
DQ[9]
DQ[1]
A1
B1
C1
D1
E1
F1
G1
H1
A[3]
A[4]
A[2]
A[1]
A[0]
CE#
OE#
V SS
r1.3/June 01
HY29DL162/HY29DL163
SIGNAL DESCRIPTIONS
Name
A[19:0]
DQ[15]/A[-1],
DQ[14:0]
Type
Description
Inputs
Address, active High. In word mode, these 20 inputs select one of 1,048,576
(1M) words within the array for read or write operations. In byte mode, these
inputs are combined with the DQ[15]/A[-1] input (LSB) to select one of 2,097,152
(2M) bytes within the array for read or write operations.
Data Bus, active High. In word mode, these pins provide a 16-bit data path
Inputs/Outputs for read and write operations. In byte mode, DQ[7:0] provide an 8-bit data path
Tri-state
and DQ[15]/A[-1] is used as the LSB of the 21-bit byte address input. DQ[14:8]
are unused and remain tri-stated in byte mode.
BY TE#
Input
Byte Mode, active Low. Controls the Byte/Word configuration of the device.
Low selects Byte mode, High selects Word mode.
CE#
Input
Chip Enable, active Low. This input must be asserted to read data from or
write data to the HY 29DL16x. When High, the data bus is tri-stated and the
device is placed in the Standby mode.
Input
Output Enable, active Low. This input must be asserted for read operations
and negated for write operations. BY TE# determines whether a byte or a word
is read during the read operation. When High, data outputs from the device are
disabled and the data bus pins are placed in the high impedance state.
Input
Write Enable, active Low. Controls writing of command sequences in order to
program data or erase sectors of the memory array. A write operation takes
place w hen WE# is asser t ed w hile CE# is Low and O E# is High. BY TE#
determines whether a byte or a word is written during the write operation.
RESET#
Input
Hardware Reset, active Low. Provides a hardware method of resetting the
HY 29DL16x to the read array state. When the device is reset, it immediately
terminates any operation in progress. The data bus is tri-stated and all read/write
commands are ignored while the input is asserted. While RESET# is asserted,
the device will be in the Standby mode.
RY /BY #
Output
Open Drain
Re a dy / Bus y St a t us . I nd ic a t e s w he t he r a w r it e o r e r a s e c o mma nd is in
progress or has been completed. Valid after the rising edge of the final WE#
pulse of a command sequence. I t remains Low w hile t he device is act ively
programming data or erasing, and goes High when it is ready to read array data.
WP#/ACC
Input
Write Protect, active Low/Accelerate (VHH).
Wr it e Pr ot ect Funct ion: Placing t his pin at VIL disables pr ogr am and er ase
oper at ions in t w o of t he eight 8 Kbyt e/ 4 Kw or d boot sect or s. The af f ect ed
sectors are S0 and S1 in a bottom-boot device, or S37 and S38 in a top-boot
device. If the pin is placed at VIH, the protection state of those tw o sectors
reverts to whether they were last set to be protected or unprotected using the
method described in the Sector Group Protection and Unprotection sections.
Accelerate Function: If VHH is applied to this input, the device enters the Unlock
Bypass mode, t empor ar ily unpr ot ect s any pr ot ect ed sect or s, and uses t he
higher voltage on the pin to reduce the time required for program operations.
The syst em w ould t hen use t he t w o- cycle pr ogr am command sequence as
required by the Unlock Bypass mode. Removing VHH from the pin returns the
device to normal operation.
This pin must not be at VHH for operations other than accelerated programming,
or devic e damage may r es ult . Leaving t he pin unc onnec t ed may r es ult in
inconsistent device operation.
VCC
--
3-volt (nominal) power supply.
VSS
--
Power and signal ground.
OE#
WE#
r1.3/June 01
5
HY29DL162/HY29DL163
CONVENTIONS
Unless otherwise noted, a positive logic (active
High) convention is assumed throughout this document, whereby the presence at a pin of a higher,
more positive voltage (VIH) causes assertion of the
signal. A ‘#’ symbol following the signal name,
e.g., RESET#, indicates that the signal is asserted
in the Low state (VIL). See DC specifications for
VIH and VIL values.
Whenever a signal is separated into numbered
bits, e.g., DQ[7], DQ[6], ..., DQ[0], the family of
bits may also be shown collectively, e.g., as
DQ[7:0].
The designation 0xNNNN (N = 0, 1, 2, . . . , 9, A, .
. . , E, F) indicates a number expressed in hexadecimal notation. The designation 0bXXXX indicates a
number expressed in binary notation (X = 0, 1).
MEMORY ARRAY ORGANIZATION
The 16 Mbit Flash memory array is organized into
39 blocks called sectors (S0, S1, . . . , S38). A
sector or several contiguous sectors are defined
as a sector group. A sector is the smallest unit
that can be erased and a sector group is the smallest unit that can be protected to prevent accidental or unauthorized erasure.
Sectors are also
combined into two ‘super’ groups designated as
banks.
In the HY29DL16x, eight of the sectors, which comprise the boot block, are sized at eight Kbytes (four
Kwords), while the remaining 31 sectors are sized
at 64 Kbytes (32 Kwords). The boot block can be
located at the bottom of the address range
(HY29DL16xB) or at the top of the address range
(HY29DL16xT).
Tables 1 and 2 define the sector addresses and
corresponding array address ranges for the top
and bottom boot block versions of the HY29DL16x.
Table 3 specifies the bank organizations and corresponding bank addresses. See Tables 7 and 8
for sector group definitions.
Secured Sector Flash Memory Region
The Secured Sector (Sec2) feature provides a 64
Kbyte (32 Kword) Flash memory region that enables permanent part identification through an
Electronic Serial Number (ESN). An associated
‘Sec2 Indicator’ bit, which is permanently set at
the factory and cannot be changed, indicates
whether or not the Sec2 is locked when shipped
from the factory.
The device is offered with the Sec2 either factory
locked or customer lockable. The factory-locked
version is always protected when shipped from
the factory, and has the Sec2 Indicator bit permanently set to a ‘1’. The customer-lockable version
is shipped with the Sec2 unprotected, allowing
6
customers to utilize the sector in any manner they
choose, and has the Sec2 Indicator bit permanently
set to a ‘0’. Thus, the Sec2 Indicator bit prevents
customer-lockable devices from being used to replace devices that are factory locked. The bit prevents cloning of a factory locked part and thus
ensures the security of the ESN once the product
is shipped to the field.
The system accesses the Sec2 through a command sequence (see “Enter/Exit Secured Sector
Command Sequence”). After the system has written the Enter Secured Sector command sequence,
it may read the Sec2 by using the addresses normally occupied by the boot sectors, as specified
in Table 4. This mode of operation continues until
the system issues the Exit Secured Sector command sequence, or until power is removed from
the device. On power-up, or following a hardware
reset, the device reverts to addressing the boot
sectors.
Sec2 Programmed and Protected At the Factory
In a factory-locked device, the Sec2 is protected
when the device is shipped from the factory and
cannot be modified in any way. The device is available preprogrammed with one of the following:
n A random, secure ESN only
n Customer code
n Both a random, secure ESN and customer
code
In devices that have an ESN, it will be located at
the bottom of the lowest 8 Kbyte boot sector: starting at byte address 0x000000 and ending at
0x00000F for a Bottom Boot device, and starting
at byte address 0x1F0000 and ending at 0x1F000F
for a Top Boot device.
r1.3/June 01
HY29DL162/HY29DL163
Table 1. HY29DL16xT (Top Boot Block) Memory Array Organization
Sector Address 1
SectSize
or (KB/KW) A[19] A[18] A[17] A[16] A[15] A[14] A[13] A[12]
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
0
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
Byte Mode
Address Range 2
Word Mode
Address Range 3
0x000000 - 0x00FFFF
0x010000 - 0x01FFFF
0x020000 - 0x02FFFF
0x030000 - 0x03FFFF
0x040000 - 0x04FFFF
0x050000 - 0x05FFFF
0x060000 - 0x06FFFF
0x070000 - 0x07FFFF
0x080000 - 0x08FFFF
0x090000 - 0x09FFFF
0x0A0000 - 0x0AFFFF
0x0B0000 - 0x0BFFFF
0x0C0000 - 0x0CFFFF
0x0D0000 - 0x0DFFFF
0x0E0000 - 0x0EFFFF
0x0F0000 - 0x0FFFFF
0x100000 - 0x10FFFF
0x110000 - 0x11FFFF
0x120000 - 0x12FFFF
0x130000 - 0x13FFFF
0x140000 - 0x14FFFF
0x150000 - 0x15FFFF
0x160000 - 0x16FFFF
0x170000 - 0x17FFFF
0x180000 - 0x18FFFF
0x190000 - 0x19FFFF
0x1A0000 - 0x1AFFFF
0x1B0000 - 0x1BFFFF
0x1C0000 - 0x1CFFFF
0x1D0000 - 0x1DFFFF
0x1E0000 - 0x1EFFFF
0x1F0000 - 0x1F1FFF
0x1F2000 - 0x1F3FFF
0x1F4000 - 0x1F5FFF
0x1F6000 - 0x1F7FFF
0x1F8000 - 0x1F9FFF
0x1FA000 - 0x1FBFFF
0x1FC000 - 0x1FDFFF
0x1FE000 - 0x1FFFFF
0x00000 - 0x07FFF
0x08000 - 0x0FFFF
0x10000 - 0x17FFF
0x18000 - 0x1FFFF
0x20000 - 0x27FFF
0x28000 - 0x2FFFF
0x30000 - 0x37FFF
0x38000 - 0x3FFFF
0x40000 - 0x47FFF
0x48000 - 0x4FFFF
0x50000 - 0x57FFF
0x58000 - 0x5FFFF
0x60000 - 0x67FFF
0x68000 - 0x6FFFF
0x70000 - 0x77FFF
0x78000 - 0x7FFFF
0x80000 - 0x87FFF
0x88000 - 0x8FFFF
0x90000 - 0x97FFF
0x98000 - 0x9FFFF
0xA0000 - 0xA7FFF
0xA8000 - 0xAFFFF
0xB0000 - 0xB7FFF
0xB8000 - 0xBFFFF
0xC0000 - 0xC7FFF
0xC8000 - 0xCFFFF
0xD0000 - 0xD7FFF
0xD8000 - 0xDFFFF
0xE0000 - 0xE7FFF
0xE8000 - 0xEFFFF
0xF0000 - 0xF7FFF
0xF8000 - 0xF8FFF
0xF9000 - 0xF9FFF
0XFA000 - 0xFAFFF
0xFB000 - 0xFBFFF
0xFC000 - 0xFCFFF
0xFD000 - 0xFDFFF
0XFE000 - 0xFEFFF
0xFF000 - 0xFFFFF
Notes:
1. ‘X’ indicates don’t care.
2. ‘0xN. . . N’ indicates an address in hexadecimal notation.
3. The address range in byte mode is A[19:0, -1]. The address range in word mode is A[19:0].
r1.3/June 01
7
HY29DL162/HY29DL163
Table 2. HY29DL16xB (Bottom Boot Block) Memory Array Organization
Sector Address 1
Sect- Size
or (KB/KW) A[19] A[18] A[17] A[16] A[15] A[14] A[13] A[12]
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
0
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Byte Mode
Address Range 2
Word Mode
Address Range 3
0x000000 - 0x001FFF
0x002000 - 0x003FFF
0x004000 - 0x005FFF
0x006000 - 0x007FFF
0x008000 - 0x009FFF
0x00A000 - 0x00BFFF
0x00C000 - 0x00DFFF
0x00E000 - 0x00FFFF
0x010000 - 0x01FFFF
0x020000 - 0x02FFFF
0x030000 - 0x03FFFF
0x040000 - 0x04FFFF
0x050000 - 0x05FFFF
0x060000 - 0x06FFFF
0x070000 - 0x07FFFF
0x080000 - 0x08FFFF
0x090000 - 0x09FFFF
0x0A0000 - 0x0AFFFF
0x0B0000 - 0x0BFFFF
0x0C0000 - 0x0CFFFF
0x0D0000 - 0x0DFFFF
0x0E0000 - 0x0EFFFF
0x0F0000 - 0x0FFFFF
0x100000 - 0x10FFFF
0x110000 - 0x11FFFF
0x120000 - 0x12FFFF
0x130000 - 0x13FFFF
0x140000 - 0x14FFFF
0x150000 - 0x15FFFF
0x160000 - 0x16FFFF
0x170000 - 0x17FFFF
0x180000 - 0x18FFFF
0x190000 - 0x19FFFF
0x1A0000 - 0x1AFFFF
0x1B0000 - 0x1BFFFF
0x1C0000 - 0x1CFFFF
0x1D0000 - 0x1DFFFF
0x1E0000 - 0x1EFFFF
0x1F0000 - 0x1FFFFF
0x00000 - 0x00FFF
0x01000 - 0x01FFF
0X02000 - 0x02FFF
0x03000 - 0x03FFF
0x04000 - 0x04FFF
0x05000 - 0x05FFF
0X06000 - 0x06FFF
0x07000 - 0x07FFF
0x08000 - 0x0FFFF
0x10000 - 0x17FFF
0x18000 - 0x1FFFF
0x20000 - 0x27FFF
0x28000 - 0x2FFFF
0x30000 - 0x37FFF
0x38000 - 0x3FFFF
0x40000 - 0x47FFF
0x48000 - 0x4FFFF
0x50000 - 0x57FFF
0x58000 - 0x5FFFF
0x60000 - 0x67FFF
0x68000 - 0x6FFFF
0x70000 - 0x77FFF
0x78000 - 0x7FFFF
0x80000 - 0x87FFF
0x88000 - 0x8FFFF
0x90000 - 0x97FFF
0x98000 - 0x9FFFF
0xA0000 - 0xA7FFF
0xA8000 - 0xAFFFF
0xB0000 - 0xB7FFF
0xB8000 - 0xBFFFF
0xC0000 - 0xC7FFF
0xC8000 - 0xCFFFF
0xD0000 - 0xD7FFF
0xD8000 - 0xDFFFF
0xE0000 - 0xE7FFF
0xE8000 - 0xEFFFF
0xF0000 - 0xF7FFF
0xF8000 - 0xFFFFF
Notes:
1. ‘X’ indicates don’t care.
2. ‘0xN. . . N’ indicates an address in hexadecimal notation.
3. The address range in byte mode is A[19:0, -1]. The address range in word mode is A[19:0].
8
r1.3/June 01
HY29DL162/HY29DL163
Table 3. HY29DL16x Bank Options
Bank 1
Device
Reference Size (Mbit)
Sectors
Bank 2
Bank Address Size (Mb)
Sectors
Bank Address
HY 29DL162T
Table 1
2
S28 - S38
A[19:17] = 111
14
S0 - S27
A[19:17] ≤ 110
HY 29DL163T
Table 1
4
S24 - S38
A[19:18] = 11
12
S0 - S23
A[19:18] ≤ 10
HY 29DL162B
Table 2
2
S0 - S10
A[19:17] = 000
14
S11 - S38
A[19:17] ≥ 001
HY 29DL163B
Table 2
4
S0 - S14
A[19:18] = 00
12
S15 - S38
A[19:18] ≥ 01
Table 4. HY29DL16x Secure Sector Addressing
Device
Sector Size
KB/KW
Sector Address
A[19:12] 1
Byte Mode
Address Range 2, 3
Word Mode
Address Range 2, 3
HY 29DL162T/163T
64/32
11111XXX
0x1F0000 - 0x1FFFFF
0xF8000 - 0xFFFFF
HY 29DL162B/163B
64/32
00000XXX
0x000000 - 0x00FFFF
0x00000 - 0x07FFF
Notes:
1. ‘X’ indicates don’t care.
2. ‘0xN. . . N’ indicates an address in hexadecimal notation.
3. The address range in byte mode is A[19:0, -1]. The address range in word mode is A[19:0].
Sec2 NOT Programmed or Protected at the Factory
If the security feature is not required, the Sec2 can
be treated as an additional Flash memory space
of 64 Kbytes. The Sec2 can be read, programmed,
and erased as often as required. The Sec2 area
can be protected using the following procedure:
n Write the three-cycle Enter Secure Sector Region command sequence
n Then follow the sector protect algorithm shown
in Figure 1, except that RESET# may be at
either VIH or VID. This allows in-system protection of the Secure Sector without raising any
device pin to a high voltage. Note that this
method is only applicable to the Secure Sector.
n Once the Secure Sector is locked and verified,
the system must write the Exit Secure Sector
command sequence to return to reading and
writing the remainder of the array.
Sec2 protection must be used with caution since,
once protected, there is no procedure available
for unprotecting the Sec2 area and none of the
bits in the Sec2 memory space can be modified in
any way.
BUS OPERATIONS
Device bus operations are initiated through the
internal command register, which consists of sets
of latches that store the commands, along with
the address and data information, if any, needed
to execute the specific command. The command
register itself does not occupy any addressable
memory location. The contents of the command
register serve as inputs to an internal state machine whose outputs control the operation of the
device. Table 5 lists the normal bus operations,
the inputs and control levels they require, and the
resulting outputs. Certain bus operations require
r1.3/June 01
a high voltage on one or more device pins. Those
are described in Table 6.
Read Operation
Data is read from the HY29DL16x by using standard microprocessor read cycles while placing the
byte or word address on the device’s address inputs. The host system must drive the CE# and
OE# pins Low and drive WE# High for a valid read
operation to take place. The BYTE# pin determines whether the device outputs array data in
words (DQ[15:0]) or in bytes (DQ[7:0]).
9
HY29DL162/HY29DL163
Table 5. HY29DL16x Normal Bus Operations 1
Operation
CE#
OE# WE#
RESET # WP#/ACC Address 2 DQ[7:0]
DQ[15:8] 3
BYTE# = H BYTE# = L
Read
L
L
H
H
L/H
AIN
DOUT
DOUT
High-Z
Write
L
H
L
H
Note 4
AIN
DIN
DIN
High-Z
Output Disable
L
H
H
H
L/H
X
High-Z
High-Z
High-Z
CE# Normal
Standby
H
X
X
H
H
X
High-Z
High-Z
High-Z
X
X
VCC ± 0.3V
H
X
High-Z
High-Z
High-Z
X
X
X
L
L/H
X
High-Z
High-Z
High-Z
X
X
X
VSS ± 0.3V
L/H
X
High-Z
High-Z
High-Z
CE# Deep Standby VCC ± 0.3V
Hardware Reset
(Normal Standby)
Hardware Reset
(Deep Standby)
Notes:
1. L = VIL, H = VIH, X = Don’t Care (L or H), DOUT = Data Out, DIN = Data In. See DC Characteristics for voltage levels.
2. Address is A[19:0, -1] in Byte Mode and A[19:0] in Word Mode.
3. DQ[15] is the A[-1] input in Byte Mode (BYTE# = L).
4. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the protection state of the two
outermost boot sectors depends on whether they were last protected or unprotected using the method described in
“Sector/Sector Block Protection and Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected.
Table 6. HY29DL16x Bus Operations Requiring High Voltage 1, 2
Operation 3
Sector Group Protect
Sector Unprotect
Temporary Sector
Unprotect 6, 7
Manufacturer Code
DQ[15: 8]
CE# OE# WE# RESET# A[19:12] A[9] A[6] A[1] A[0] DQ[7: 0] BYTE# BYTE#
=H
= L5
L
H
L
VID
SGA 4
X
L
H
L
DIN
X
X
X
X
H
H
L
DIN
X
X
L
H
L
VID
--
--
--
VID
--
--
--
--
--
--
--
--
L
L
H
H
X
VID
L
L
L
X
High-Z
L
L
H
H
X
VID
L
L
H
0xAD
0x2E
0x2D
0x2B
0x28
0x22
High-Z
L
L
H
H
SA 4
VID
L
H
L
X
High-Z
VID
L
X
High-Z
HY29DL162B
D evi ce HY29DL162T
C ode HY29DL163B
HY29DL163T
Sector Unprotected
Protect
Protected
State
Factory
Secure
L o cke d
Sector
Indicator Not Factory
Bi t
L o cke d
0x00
0x01
0x80
L
L
H
H
X
H
H
0x00
Notes:
1. L = VIL, H = VIH, X = Don’t Care (L OR H), VID = 10V nominal. See DC Characteristics for voltage levels.
2. Address bits not specified are Don’t Care.
3. See text and Appendix for additional information.
4. SA = Sector Address, SGA = Sector Group Address. See Tables 1, 2, 7, and 8.
5. DQ[15] is the A[-1] input in Byte Mode (BYTE# = L).
6. Normal read, write and output disable operations are used in this mode. See Table 5.
7. If WP#/ACC = VIL, the two outermost boot sectors remain protected.
10
r1.3/June 01
HY29DL162/HY29DL163
The HY29DL16x is automatically set for reading
array data after device power-up and after a hardware reset to ensure that no spurious alteration of
the memory content occurs during the power transition. No command is necessary in this mode to
obtain array data, and both banks of the device
remain enabled for read accesses until the command register contents are altered.
This device features the capability of reading data
from one bank of the memory while a program or
erase operation is in progress in the other bank.
If the host reads from an address within an erasing or erase-suspended sector, or from a bank
where a programming operation is taking place,
the device outputs status data instead of array data
(see Write Operation Status section). After completing an Automatic Program or Automatic Erase
algorithm within a bank, that bank automatically
returns to the read array data mode.
When the host issues an Erase Suspend command, the bank specified in the command enters
the Erase- Suspended Read mode. While in that
mode, the host can read data from, or program
data into, any sector in that bank except the
sector(s) being erased. After completing a programming operation in the Erase Suspend mode,
the system may once again read array data with
the same exception noted above.
The host must issue a hardware reset or the software reset command to return a sector to the read
array data mode if DQ[5] goes high during a program or erase cycle, or to return the device to the
read array data mode while it is in the Electronic
ID mode.
Write Operation
Certain operations, including programming data
and erasing sectors of memory, require the host
to write a command or command sequence to the
HY29DL16x. Writes to the device are performed
by placing the byte or word address on the device’s
address inputs while the data to be written is input
on DQ[15:0] (BYTE# = High) or DQ[7:0] (BYTE#
= Low). The host system must drive the CE# and
WE# pins Low and drive OE# High for a valid write
operation to take place. All addresses are latched
on the falling edge of WE# or CE#, whichever
happens later. All data is latched on the rising
edge of WE# or CE#, whichever happens first.
r1.3/June 01
The “Device Commands” section of this data sheet
provides details on the specific device commands
implemented in the HY29DL16x.
Accelerated Program Operation
This device offers improved performance for programming operations through the ‘Accelerate
(ACC)’ function. This is one of two functions provided by the WP#/ACC pin and is intended primarily to allow faster manufacturing throughput at the
factory.
If VHH is applied to this input, the device enters the
Unlock Bypass mode, temporarily unprotects any
protected sectors, and uses the higher voltage on
the pin to reduce the time required for program
operations. The host system would then use the
two-cycle program command sequence as required by the Unlock Bypass mode. Removing
VHH from the pin returns the device to normal operation.
This pin must not be at VHH for operations other
than accelerated programming, or device damage
may result. Leaving the pin floating or unconnected may result in inconsistent device operation.
Write Protect Function
The Write Protect function provides a hardware
method of protecting certain boot sectors without
using VID. This is the second function provided by
the WP#/ACC pin.
Placing this pin at VIL disables program and erase
operations in two of the eight 8 Kbyte (4 Kword)
boot sectors. The affected sectors are sectors S0
and S1 in a bottom-boot device, or S37 and S38
in a top-boot device. If the pin is placed at VIH, the
protection state of those two sectors reverts to
whether they were last set to be protected or unprotected using the method described in the Sector Group Protection and Unprotection sections.
Standby Operation
When the system is not reading or writing to the
device, it can place the device in the Standby
mode. In this mode, current consumption is greatly
reduced, and the data bus outputs are placed in
the high impedance state, independent of the OE#
input. The Standby mode can invoked using two
methods.
11
HY29DL162/HY29DL163
The device enters the CE# controlled Deep
Standby mode when the CE# and RESET# pins
are both held at VCC ± 0.3V. Note that this is a
more restricted voltage range than VIH. If both CE#
and RESET# are held at VIH , but not within VCC ±
0.3V, the device will be in the Normal Standby
mode, but the standby current will be greater.
The device enters the RESET# controlled Deep
Standby mode when the RESET# pin is held at
VSS ± 0.3V. If RESET# is held at VIL but not within
VSS ± 0.3V, the standby current will be greater.
See RESET# section for additional information on
the reset operation.
The device requires standard access time (tCE) for
read access when the device is in any of the
standby modes, before it is ready to read data. If
the device is deselected during erasure or programming, it continues to draw active current until
the operation is completed.
Sleep Mode
The Sleep mode automatically minimizes device
power consumption. This mode is automatically
entered when addresses remain stable for tACC +
30 ns (typical) and is independent of the state of
the CE#, WE#, and OE# control signals. Standard address access timings provide new data
when addresses are changed. While in Sleep
mode, output data is latched and always available
to the system.
NOTE: Sleep mode is entered only when the device is
in Read mode. It is not entered if the device is executing
an automatic algorithm, if it is in erase suspend mode,
or during receipt of a command sequence.
Output Disable Operation
When the OE# input is at VIH, output data from the
device is disabled and the data bus pins are placed
in the high impedance state.
Reset Operation
The RESET# pin provides a hardware method of
resetting the device to reading array data. When
the RESET# pin is driven low for the minimum
specified period, the device immediately terminates any operation in progress, tri-states the data
bus pins, and ignores all read/write commands for
the duration of the RESET# pulse. The device also
resets the internal state machine to reading array
data. If an operation was interrupted by the as12
sertion of RESET#, it should be reinitiated once
the device is ready to accept another command
sequence to ensure data integrity.
Current is reduced for the duration of the RESET#
pulse as described in the Standby Operation section above.
If RESET# is asserted during a program or erase
operation, the RY/BY# pin remains Low (busy) until
the internal reset operation is complete, which requires a time of tREADY (during Automatic Algorithms). The system can thus monitor RY/BY# to
determine when the reset operation completes,
and can perform a read or write operation tRB after
RY/BY# goes High. If RESET# is asserted when
a program or erase operation is not executing (RY/
BY# pin is High), the reset operation is completed
within a time of tRP. In this case, the host can perform a read or write operation tRH after the RESET# pin returns High .
The RESET# pin may be tied to the system reset
signal. Thus, a system reset would also reset the
device, enabling the system to read the boot-up
firmware from the Flash memory.
Sector Group Protect Operation
The hardware sector group protection feature disables both program and erase operations in any
combination of sector groups. A sector group consists of a single sector or a group of adjacent sectors, as specified in Tables 7 and 8. This function
can be implemented either in-system or by using
programming equipment. It requires a high voltage (VID) on the RESET# pin and uses standard
microprocessor bus cycle timing to implement
sector protection. The flow chart in Figure 1 illustrates the algorithm.
The HY29DS16x is shipped with all sector groups
unprotected. It is possible to determine whether
a sector is protected or unprotected. See the Electronic ID Mode section for details.
Sector Unprotect Operation
The hardware sector unprotection feature re-enables both program and erase operations in previously protected sector groups. This function can
be implemented either in-system or by using programming equipment. Note that to unprotect any
sector, all unprotected sector groups must first be
protected prior to the first sector unprotect write
r1.3/June 01
HY29DL162/HY29DL163
Table 7. Sector Groups - Top Boot Versions
SG0
Sectors
(Table 1)
S0
SG1
S1 - S3
SG2
SG3
SG4
SG5
SG6
SG7
S4 - S7
S8 -S11
S12 - S15
S16 - S19
S20 - S23
S24 - S27
SG8
S28 - S30
SG9
SG10
SG11
SG12
SG13
SG14
SG15
SG16
S31
S32
S33
S34
S35
S36
S37
S38
Group
Table 8. Sector Groups - Bottom Boot Versions
Group Address Block Size
A[19:12]
KB/KW
0 0 0 0 0XXX
64/32
0 0 0 0 1X X X
0 0 0 1 0 X X X 192/96
0 0 0 1 1X X X
0 0 1 X X X X X 256/128
0 1 0 X X X X X 256/128
0 1 1 X X X X X 256/128
1 0 0 X X X X X 256/128
1 0 1 X X X X X 256/128
1 1 0 X X X X X 256/128
1 1 10 0XXX
1 1 1 0 1 X X X 192/96
1 1 1 10XXX
1 1 1 1 10 0 0
8/4
1 1 1 1 10 0 1
8/4
1 1 1 1 10 10
8/4
1 1 1 1 10 1 1
8/4
1 1 1 1 1 10 0
8/4
1 1 1 1 1 10 1
8/4
1 1 1 1 1 1 10
8/4
1 1 1 1 1 1 1 1
8/4
SG0
SG1
SG2
SG3
SG4
SG5
SG6
SG7
Sectors
(Table 2)
S0
S1
S2
S3
S4
S5
S6
S7
SG8
S8 - S10
SG9
SG10
SG11
SG12
SG13
SG14
S11 - S14
S15 - S18
S19 - S22
S23 - S26
S27 - S30
S31 - S34
SG15
S35 - S37
SG16
S38
Group
Group Address Block Size
A[19:12]
KB/KW
0 0 0 000 0 0
8/4
0 0 0 000 0 1
8/4
0 0 0 000 10
8/4
0 0 0 000 1 1
8/4
0 0 0 00 10 0
8/4
0 0 0 00 10 1
8/4
0 0 0 00 1 10
8/4
0 0 0 00 1 1 1
8/4
0 0 0 0 1X X X
0 0 0 1 0 X X X 192/96
0 0 0 1 1X X X
0 0 1 X X X X X 256/128
0 1 0 X X X X X 256/128
0 1 1 X X X X X 256/128
1 0 0 X X X X X 256/128
1 0 1 X X X X X 256/128
1 1 0 X X X X X 256/128
1 1 10 0XXX
1 1 1 0 1 X X X 192/96
1 1 1 10XXX
1 1 1 1 1X X X
64/32
START
Wait 150 us
R E S E T # = V IH
R E S E T # = V ID
Write 0x40 to Address
Write Reset Command
Wait 1 us
Wait 1 us
Write 0x60 to device
Read from Address
TRYCNT = 1
Data = 0x01?
Set Address:
A[19:12] = Group to Protect
A[6] = 0, A[1] = 1, A[0] = 0
SECTOR GROUP
PROTECT COMPLETE
NO
YES
Protect Another
Group?
TRYCNT = 25?
YES
NO
NO
DEVICE FAILURE
Increment TRYCNT
Write 0x60 to Address
YES
Figure 1. Sector Group Protect Algorithm
r1.3/June 01
13
HY29DL162/HY29DL163
cycle. Also, the unprotect procedure will cause
all sectors to become unprotected, thus, sector
groups that require protection must be protected
again after the unprotect procedure is run.
Electronic ID Operation (High Voltage Method)
The Electronic ID mode provides manufacturer and
device identification, sector protection verification
and Sec2 region protection status through identifier codes output on DQ[7:0]. This mode is intended primarily for programming equipment to automatically match a device to be programmed with
its corresponding programming algorithm.
This procedure requires VID on the RESET# pin
and uses standard microprocessor bus cycle timing to implement sector unprotection. The flow
chart in Figure 2 illustrates the algorithm.
Two methods are provided for accessing the Electronic ID data. The first requires VID on address
pin A[9], with additional requirements for obtaining specific data items listed in Table 6. The Electronic ID data can also be obtained by the host
through specific commands issued via the command register, as described later in the ‘Device
Commands’ section of this data sheet.
Temporary Sector Unprotect Operation
This feature allows temporary unprotection of protected sectors to allow changing the data in-system. Temporary Sector Unprotect mode is activated by setting the RESET# pin to VID. While in
this mode, formerly protected sectors can be programmed or erased by invoking the appropriate
commands (see Device Commands section).
Once VID is removed from RESET#, all the previously protected sector groups are protected again.
Figure 3 illustrates the algorithm.
While in the high-voltage Electronic ID mode, the
system may read at specific addresses to obtain
certain device identification and status information:
NOTE: If WP#/ACC = VIL, the two outermost boot sectors remain protected.
n A read cycle at address 0xXXX00 retrieves the
manufacturer code.
n A read cycle at address 0xXXX01 in word mode
or 0xXXX02 in byte mode returns the device
code.
START
(Note: All sector groups
must be protected prior to
sector unprotect)
Set Address:
A[19:12] = Group GNUM
A[6] = 1, A]1] = 1, A]0] = 0
R E S E T # = V IH
Write 0x40 to Address
TRYCNT = 1
GNUM = 0
Write Reset Command
Wait 1 us
R E S E T # = V ID
SECTOR GROUP
UNPROTECT COMPLETE
Read from Address
Wait 1 us
Data = 0x00?
NO
TRYCNT = 1000?
YES
Write 0x60 to device
NO
YES
Set Address:
A[6] = 1, A]1] = 1, A]0] = 0
Increment TRYCNT
GNUM = 16?
YES
DEVICE FAILURE
Write 0x60 to Address
Wait 15 ms
NO
GNUM = GNUM + 1
Figure 2. Sector Unprotect Algorithm
14
r1.3/June 01
HY29DL162/HY29DL163
n A read cycle containing a sector address (SA)
START
R E S E T # = V ID
(All protected sectors
become unprotected)
Perform Program or Erase
Operations
within the designated bank in A[19:12] and the
address 0x04 in A[6:0, A-1] in byte mode, or
0x02 in A[7:0] in word mode, returns 0x01 if
that sector is protected, or 0x00 if it is unprotected.
n A read cycle at address 0xXXX03 in word mode
or 0xXXX06 in byte mode returns 0x80 if the
Sec2 region is protected and locked at the factory and 0x00 if it is not.
R E S E T # = V IH
(All previously protected
sectors return to protected
state)
TEMPORARY SECTOR
UNPROTECT COMPLETE
Figure 3. Temporary Sector Unprotect
Algorithm
DEVICE COMMANDS
Device operations are initiated by writing designated address and data command sequences into
the device. Addresses are latched on the falling
edge of WE# or CE#, whichever happens later.
Data is latched on the rising edge of WE# or CE#,
whichever happens first.
A command sequence is composed of one, two
or three of the following sub-segments: an unlock
cycle, a command cycle and a data cycle. Table
9 summarizes the composition of the valid command sequences implemented in the HY29DL16x,
and these sequences are fully described in Table
10 and in the sections that follow.
Writing incorrect address and data values or writing them in the improper sequence resets the
HY29DL16x to the Read mode.
Reading Data
The device automatically enters the Read mode
after device power-up, after the RESET# input is
asserted and upon the completion of certain commands. Commands are not required to retrieve
data in this mode. See Read Operation section
for additional information.
Table 9. Composition of Command Sequences
Number of Bus Cycles
Unlock Command
Data
Read
0
0
Note 1
Reset
0
1
0
2
1
0
Enter Sec2 Region
Exit Sec2 Region
2
1
1
Byte/Word Program
2
1
1
Unlock Bypass
2
1
0
Unlock Bypass
0
1
1
Reset
Unlock Bypass
0
1
1
Byte/Word Program
Chip Erase
4
1
1
Sector Erase
4
1
1 (Note 2)
Erase Suspend
0
1
0
Erase Resume
0
1
0
Electronic ID
2
1
Note 3
CFI Query
0
1
Note 4
Command
Sequence
Notes:
1. Any number of Flash array read cycles are permitted.
2. Additional data cycles may follow. See text.
3. Any number of Electronic ID read cycles are permitted.
4. Any number of CFI data read cycles are permitted.
Reset Command
Writing the Reset command resets the sectors to
the Read or Erase-Suspend mode. Address bits
are don’t cares for this command.
r1.3/June 01
15
Byte
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
See next page for legend and notes.
Common Flash Interface (CFI)
Query 8
Sec2 Region Indicator
Bi t
Sector Protect Verify
Device Code
Manufacturer Code
1
3
3
3
3
1
Word
1
6
6
Erase Resume 5
Byte
Word
Byte
Word
Erase Suspend 4
Sector Erase
Chip Erase
2
2
3
Unlock Bypass Program 9
Byte
Word
Byte
4
4
4
Word
Word
3
Byte
Unlock Bypass Reset
Unlock Bypass
Normal Program
Exit Sec2 Region
3
Word
1
Enter Sec2 Region
0
Reset 7
Write
Cycles
Read
Electronic ID 6
16
Command Sequence
RA
(BA)XAA
(BA)X55
AAA
555
AAA
555
AAA
555
AAA
555
BA
BA
AAA
555
AAA
555
XXX
XXX
AAA
555
AAA
555
AAA
555
AAA
555
XXX
98
AA
AA
AA
AA
30
B0
AA
AA
A0
90
AA
AA
AA
AA
F0
RD
Data
First
Add
Table 10. HY29DL16x Command Sequences
555
2A A
555
2A A
555
2A A
555
2A A
555
2A A
555
2A A
PA
XXX
555
2A A
555
2A A
555
2A A
555
2A A
Add
55
55
55
55
55
55
PD
00
55
55
55
55
Data
S eco n d
(BA)AAA
(BA)555
(BA)AAA
(BA)555
(BA)AAA
(BA)555
(BA)AAA
(BA)555
AAA
555
AAA
555
AAA
555
AAA
555
AAA
555
AAA
555
Add
90
90
90
90
80
80
20
A0
90
88
Data
Third
AD
AA
AA
PD
00
Data
555
2A A
555
2A A
Add
55
55
Data
Fifth
SA
AAA
555
Add
30
10
Data
Sixth
(BA)X03 00 = NOT protected and locked at factory
(BA)X06 80 = Protected and locked at factory
(SA)X02 00 = Unprotected Sector
(SA)X04 01 = Protected Sector
(BA)X01 2D = '162T, 2E = '162B
(BA)X02 28 = '163T, 2B = '163B
(BA)X00
AAA
555
AAA
555
PA
XXX
XXX
Add
Fourth
Bus Cycles 1, 2, 3
HY29DL162/HY29DL163
r1.3/June 01
HY29DL162/HY29DL163
Legend and notes for Table 10:
Legend:
X = Don’t Care
RA/RD = Memory address/data for the read operation
PA/PD = Memory address/data for the program operation
SA = A[19:12], sector address of the sector to be erased or verified (see Note 3 and Tables 1 and 2).
BA = A[19:18] or A[19:17], depending on the device version, bank address, see Note 3 and Table 3.
Notes:
1. All values are in hexadecimal. DQ[15:8] are don’t care for unlock and command cycles.
2. All bus cycles are write operations unless otherwise noted.
3. Address is A[10:0] in Word mode and A[10:0, -1] in Byte mode. A[19:11] are don’t care except as follows:
• For RA and PA, A[19:11] are the upper address bits of the byte to be read or programmed.
• Where ‘SA’ is indicated, A[19:12] are the sector address.
• Where ‘BA’ is indicated, A[19:18] or A[19:17], depending on the device version, are the bank address.
4. The Erase Suspend command is valid only during a sector erase operation. The system may read and program in nonerasing sectors, or enter the Electronic ID mode, while in the Erase Suspend mode.
5. The Erase Resume command is valid only during the Erase Suspend mode.
6. The fourth bus cycle is a read cycle.
7. The command is required only to return to the Read mode when the device is in the Electronic ID command mode or in
the CFI Query mode. It must also be issued to return to read mode if DQ[5] goes High during a program or erase
operation. It is not required for normal read operations.
8 This command is valid only when the device is in Read mode or in Electronic ID mode.
9. The Unlock Bypass command is required prior to the Unlock Bypass Program command.
As described above, a Reset command is not normally required to begin reading array data. However, a Reset command must be issued in order
to read array data in the following cases:
n If the device is in the Electronic ID mode, a
Reset command must be written to return to
the Read mode. If the device was in the Erase
Suspend mode when the device entered the
Electronic ID mode, writing the Reset command
returns the device to the Erase Suspend mode.
Note: When in the Electronic ID bus operation mode,
the device returns to the Read mode when VID is removed from the A[9] pin. The Reset command is not
required in this case.
n If the device is in the CFI Query mode, a Reset
command must be written to return to the array Read mode.
n If DQ[5] (Exceeded Time Limit) goes High during a program or erase operation, a Reset command must be invoked to return the sectors to
the Read mode (or to the Erase Suspend mode
if the device was in Erase Suspend when the
Program command was issued).
The Reset command may also be used to abort
certain command sequences:
n In a Sector Erase or Chip Erase command sequence, the Reset command may be written
at any time before erasing actually begins, including, for the Sector Erase command, ber1.3/June 01
tween the cycles that specify the sectors to be
erased (see Sector Erase command description). This aborts the command and resets the
device to the Read mode. Once erasure begins, however, the device ignores the Reset
command until the operation is complete.
n In a Program command sequence, the Reset
command may be written between the sequence cycles before programming actually begins. This aborts the command and resets the
device to the Read mode, or to the Erase Suspend mode if the Program command sequence
is written while the device is in the Erase Suspend mode. Once programming begins, however, the device ignores the Reset command
until the operation is complete.
n The Reset command may be written between
the cycles in an Electronic ID command sequence to abort that command. As described
above, once in the Electronic ID mode, the
Reset command must be written to return to
the array Read mode.
Enter /Exit Sec2 Command Sequence
The system can access the Sec2 region of the
device by issuing the Enter Sec2 Region command
sequence. The device continues to access the
Sec2 region until the system issues the Exit Sec2
Region command sequence, which returns the
device to normal operation.
17
HY29DL162/HY29DL163
Note: A hardware reset will reset the device to the read
array mode.
Program Command
The system programs the device a word or byte
at a time by issuing the appropriate four-cycle Program command sequence, as shown in Table 10.
The sequence begins by writing two unlock cycles,
followed by the program setup command and,
lastly, the program address and data. This initiates the Automatic Program algorithm that automatically provides internally generated program
pulses and verifies the programmed cell margin.
The host is not required to provide further controls or timings during this operation. When the
Automatic Program algorithm is complete, that
bank returns to the Read mode. Several methods are provided to allow the host to determine
the status of the programming operation, as described in the Write Operation Status section.
While the Automatic Program algorithm is in
progress in one bank, the host may read data from
the non-programming bank.
Commands written to the device during execution
of the Automatic Program algorithm are ignored.
Note that a hardware reset immediately terminates
the programming operation. To ensure data integrity, the aborted program command sequence
should be reinitiated once the reset operation is
complete.
Programming is allowed in any sequence. Only
erase operations can convert a stored ‘0’ to a ‘1’.
Thus, a bit cannot be programmed from a ‘0’ back
to a ‘1’. Attempting to do so may cause that bank
to halt the operation and set DQ[5] to ‘1’, or cause
the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read
will show that the data is still ‘0’.
Unlock Bypass/Bypass Program/Bypass Reset
Commands
Unlock Bypass provides a faster method than the
normal Program command for the host system to
program bytes or words to a bank. As shown in
Table 10, the Unlock Bypass command sequence
consists of two unlock write cycles followed by a
third write cycle containing the Unlock Bypass
command, 0x20. That bank then enters the Unlock Bypass mode. In this mode, a two-cycle Unlock Bypass Program command sequence is used
18
instead of the standard four-cycle program sequence to invoke a programming operation. The
first cycle in this sequence contains the Unlock
Bypass Program command, 0xA0, and the second cycle specifies the program address and data,
thus eliminating the initial two unlock cycles required in the standard Program command sequence. Additional data is programmed in the
same manner.
During the Unlock Bypass mode, only the Unlock
Bypass Program and Unlock Bypass Reset commands are valid. To exit the Unlock Bypass mode,
the host must issue the two-cycle Unlock Bypass
Reset command sequence shown in Table 10.
The bank specified in the first cycle of that command then returns to the Read array data mode.
Figure 4 illustrates the procedures for the normal
and unlock bypass program operations.
Note: The device automatically enters the Unlock Bypass mode when it is placed in Accelerate mode via the
WP#/ACC pin.
Chip Erase Command
The Chip Erase command sequence consists of
two unlock cycles, followed by a set-up command,
two additional unlock cycles and then the Chip
Erase command. This sequence invokes the Automatic Erase algorithm that automatically
preprograms (if necessary) and verifies the entire
memory for an all zero data pattern prior to electrical erase. The host system is not required to provide any controls or timings during these operations.
If all sectors in the device are protected, the device returns to reading array data after approximately 100 µs. If at least one sector is unprotected, the erase operation erases the unprotected
sectors, and ignores the command for the sectors
that are protected. However, even if every sector
in one of the banks is protected, reads from that
bank are not permitted until the completion of the
Automatic Erase algorithm for the unprotected
sectors in the other bank.
Commands written to the device during execution
of the Automatic Erase algorithm are ignored. Note
that a hardware reset immediately terminates the
chip erase operation. To ensure data integrity,
the aborted Chip Erase command sequence
should be reissued once the reset operation is
complete.
r1.3/June 01
HY29DL162/HY29DL163
START
Check Programming Status
(See Write Operation Status
Section)
NO
Enable Fast
Programming?
YES
DQ[5] Error Exit
Programming Verified
NO
Issue UNLOCK BYPASS
Command to Bank
Last Word/Byte
Done?
YES
Setup Next Address/Data for
Program Operation
NO
Bank in Unlock
Bypass Mode?
Issue NORMAL PROGRAM
Command
NO
Bank in Unlock
Bypass Mode?
YES
Issue UNLOCK BYPASS
RESET Command to Bank
YES
Issue UNLOCK BYPASS
PROGRAM Command
PROGRAMMING
COMPLETE
GO TO ERROR
RECOVERY PROCEDURE
Figure 4. Normal and Unlock Bypass Programming Procedures
When the Automatic Erase algorithm is complete,
the device returns to the reading array data mode.
Several methods are provided to allow the host to
determine the status of the erase operation, as
described in the Write Operation Status section.
Figure 5 illustrates the chip erase procedure.
Sector Erase Command
The Sector Erase command sequence consists
of two unlock cycles, followed by a set-up com-
START
Issue CHIP ERASE
Command Sequence
Check Erase Status
(See Write Operation Status
Section)
DQ[5] Error Exit
Normal Exit
CHIP ERASE COMPLETE
GO TO
ERROR RECOVERY
mand, two additional unlock cycles and then the
Sector Erase command, which specifies which
sector is to be erased. This sequence invokes
the Automatic Erase algorithm that automatically
preprograms (if necessary) and verifies the specified sector for an all zero data pattern prior to electrical erase. The host system is not required to
provide any controls or timings during these operations.
After the sector erase data cycle (the sixth cycle)
of the command sequence is issued, a sector
erase time-out of 50 µs (min) begins, measured
from the rising edge of the final WE# pulse in the
command sequence. During this time, an additional sector address and sector erase data cycle
may be written into an internal sector erase buffer.
This buffer may be loaded in any sequence, and
the number of sectors designated for erasure may
be from one sector to all sectors. The only restriction is that the time between these additional
cycles must be less than 50 µs, otherwise erasure may begin before the last address and command are accepted. To ensure that all commands
are accepted, it is recommended that host processor interrupts be disabled during the time that
Figure 5. Chip Erase Procedure
r1.3/June 01
19
HY29DL162/HY29DL163
the additional sector erase commands are being
issued and then be re-enabled afterwards.
The system can monitor DQ[3] to determine if the
50 µs sector erase time-out has expired, as described in the Write Operation Status section. If
the time between additional sector erase commands can be assured to be less than the timeout, the system need not monitor DQ[3].
Any command other than Sector Erase or Erase
Suspend during the time-out period resets the
bank(s) to reading array data. The system must
then rewrite the command sequence, including any
additional sector addresses. Once the sector
erase operation itself has begun, only the Erase
Suspend command is valid. All other commands
are ignored.
As for the Chip Erase command, note that a hardware reset immediately terminates the erase operation. To ensure data integrity, the aborted Sector Erase command sequence should be reissued
once the reset operation is complete.
If all sectors designated for erasing are protected,
the device returns to reading array data after approximately 100 µs. If at least one designated
sector is unprotected, the erase operation erases
the unprotected sectors, and ignores the command
for the sectors that are protected. If sectors in a
bank are designated for erasure, read array operations from that bank cannot take place until the
Automatic Erase algorithm terminates, even if all
of those sectors are protected. However, the
HY29DL16x’s simultaneous read feature allows
data to be read from a bank that does not contain
any sectors that are designated for erasure while
the erase algorithm is in progress in the other bank.
When the Automatic Erase algorithm is complete,
the device returns the erased sector(s) to the Read
array data mode. Several methods are provided
to allow the host to determine the status of the
erase operation, as described in the Write Operation Status section.
Figure 6 illustrates the sector erase procedure.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system
to interrupt a sector erase operation to program
data into, or to read data from, any sector not
designated for erasure. (The HY29DL16x’s simultaneous read feature allows data to be read from
a bank that does not contain any sectors marked
for erasure even while the erase operation is not
suspended). The command, which requires the
START
Check Erase Status
(See Write Operation Status
Section)
DQ[5] Error Exit
Normal Exit
Write First Five Cycles of
SECTOR ERASE
Command Sequence
ERASE COMPLETE
GO TO
ERROR RECOVERY
Setup First (or Next) Sector
Address for Erase Operation
Write Last Cycle (SA/0x30)
of SECTOR ERASE
Command Sequence
Sectors which require erasure
but which were not specified in
this erase cycle must be erased
later using a new command
sequence
NO
Erase An
Additional Sector?
YES
Sector Erase
Time-out (DQ[3])
Expired?
YES
NO
Figure 6. Sector Erase Procedure
20
r1.3/June 01
HY29DL162/HY29DL163
bank address, causes the erase operation to be
suspended in all sectors designated for erasure
in the specified bank. This command is valid only
during the sector erase operation, including during the 50 µs time-out period at the end of the
command sequence, and is ignored if it is issued
during chip erase or programming operations.
The HY29DL16x requires a maximum of 20 µs to
suspend the erase operation if the erase suspend
command is issued during active sector erasure.
However, if the command is written during the
sector erase time-out, the time-out is terminated
and the erase operation is suspended immediately.
Once the erase operation has been suspended in
the bank, the system can read array data from or
program data into any sector in that bank that is
not designated for erasure. Normal read and write
timings and command definitions apply. Reading
at any address within erase-suspended sectors
produces status data on DQ[7:0]. The host can
use DQ[7], or DQ[6] and DQ[2] together, to determine if a sector is actively erasing or is erase-suspended. See ‘Write Operation Status’ for information on these status bits.
After an erase-suspended program operation is
complete, the bank returns to the erase-suspended
read state and the host can initiate another programming operation (or read operation) within nonsuspended sectors. The host can determine the
status of a program operation during the erase-
suspended state just as in the standard programming operation.
The host may also write the Electronic ID command sequence when the bank is in the Erase
Suspend mode. The device allows reading Electronic ID codes even at addresses within erasing
sectors, since the codes are not stored in the
memory array. When the device exits the Electronic ID mode, the bank reverts to the Erase Suspend mode, and is ready for another valid operation. See the Electronic ID Command section for
more information.
The system must write the Erase Resume command to the erase-suspended bank to exit the
Erase Suspend mode and continue the sector
erase operation. Further writes of the Resume
command are ignored. Another Erase Suspend
command can be written after the device has resumed erasing.
Table 11 summarizes the erase operations in the
HY29DL16x.
Electronic ID Command
The Electronic ID mode provides manufacturer and
device identification and sector protection verification through identifier codes output on DQ[7:0].
This mode is intended primarily for programming
equipment to automatically match a device to be
programmed with its corresponding programming
algorithm.
Table 11. HY29DL16x Erase Operations Summary 7
Erase Suspend
Allowed?
Operation in Progress
No erase
Chip Erase
Sector Erase in Bank 1 Only
Sector Erase in Bank 2 Only
Sector Erase in Banks 1 and 2
Bank 1
n/a
No
Yes
No
Yes
Bank 2
n/a
No
No
Yes
Yes
Programming
Allowed? 1
Bank 1
Yes
No
Yes 2
Yes 6
Yes 2
Bank 2
Yes
No
Yes 6
Yes 2
Yes 2
Output from Read Operation 3
ES Sector 4
Non-ES Sector 5
Bank 1 Bank 2 Bank 1 Bank 2
n/a
n/a
Data
Data
n/a
n/a
Status
Status
Status
n/a
Data
Data
n/a
Status
Data
Data
Status
Status
Data
Data
Notes:
1. Only one simultaneous programming operation is permitted.
2. Allowed only when the bank is in erase suspend state and only into a sector that is not designated for erasure.
3. Output may differ if program operation is in progress. See Write Operation Status section for additional information.
4. Read from a sector that is designated for erasure while the bank is in erase suspend state.
5. Read from a sector that is not designated for erasure while the bank is in erase suspend state, or read from any sector
in a bank where an erase operation has not been commanded, or any read for the Chip Erase operation.
6. Erase operation in the other bank must be suspended.
7. n/a = not applicable. Condition cannot exist.
Data = array data from addressed location.
Status = write operation status (see Write Operation Status section for additional information).
r1.3/June 01
21
HY29DL162/HY29DL163
Two methods are provided for accessing the Electronic ID data. The first requires VID on address
pin A[9], as described previously in the Device
Operations section.
The Electronic ID data can also be obtained by
the host through specific commands issued via
the command register, as shown in Table 10. This
method does not require VID. The Electronic ID
command sequence may be written to an address
within a bank that is in the read mode or in the
Erase Suspend mode. The command may not be
written while the device is actively programming
or erasing in the other bank.
The Electronic ID command sequence is initiated
by writing two unlock cycles, followed by a third
write cycle that contains the bank address and the
Electronic ID command. The addressed bank then
enters the Electronic ID mode, and the system may
read at any address in that bank any number of
times, without initiating another command sequence.
n A read cycle at address 0x(BA)X00, where BA
is the Bank Address, retrieves the manufacturer code.
n A read cycle at address 0x(BA)X01 in word
mode or 0x(BA)X02 in byte mode returns the
device code.
n A read cycle containing a sector address (SA)
within the designated bank in A[19:12] and the
address 0x04 in A[6:0, A-1] in byte mode, or
0x02 in A[7:0] in word mode, returns 0x01 if
that sector is protected, or 0x00 if it is unprotected.
n A read cycle at address 0x(BA)X03 in word
mode or 0x(BA)X06 in byte mode returns 0x80
if the Sec2 region is protected and locked at
the factory and 0x00 if it is not.
Array data may be read from the other bank while
the designated bank is in the Electronic ID mode.
The system must write the Reset command to exit
the Electronic ID mode and return the bank to the
normal Read mode, or to the Erase-Suspended
read mode if the bank was in that mode when the
Electronic ID command was invoked. In the latter
case, an Erase Resume command to that bank
will continue the suspended erase operation.
22
Query Command and Common Flash Interface (CFI) Mode
The HY29DL16x is capable of operating in the
Common Flash Interface (CFI) mode. This mode
allows the host system to determine the manufacturer of the device, its operating parameters, its
configuration and any special command codes that
the device may accept. With this knowledge, the
system can optimize its use of the chip by using
appropriate timeout values, optimal voltages and
commands necessary to use the chip to its full
advantage.
Two commands are employed in association with
CFI mode. The first places the device in CFI mode
(Query command) and the second takes it out of
CFI mode (Reset command). These are described
in Table 10.
The single cycle Query command is valid only
when the device is in the Read mode, including
during Erase Suspend and Standby states and
while in Electronic ID command mode, but is ignored otherwise. The command is not valid while
the HY29DL16x is in the Electronic ID bus operation mode. The command places the Bank designated in the ‘Bank Address’ field of the command
in the CFI Query mode. Array data may be read
from the other bank while the designated bank is
in the CFI Query mode. Read cycles at appropriate addresses within the designated bank while in
the Query mode provide CFI data as described
later in this section. Write cycles are ignored, except for the Reset command.
The Reset command returns the device from the
CFI mode to the array Read mode, or to the Erase
Suspend mode if the device was in that mode prior
to entering CFI mode, or to the Electronic ID mode
if the device was in that mode prior to entering
CFI mode. The command is valid only when the
device is in the CFI mode and as otherwise described for the normal Reset command.
Tables 12 - 15 specify the data provided by the
HY29DL16x during CFI mode. Data at unspecified addresses reads out as 0x00. Note that a
value of 0x00 for a data item normally indicates
that the function is not supported. All values in
these tables are in hexadecimal.
r1.3/June 01
HY29DL162/HY29DL163
Table 12. CFI Mode: Identification Data Values
Word Mode
Description
Byte Mode
Address
Data
Address
Data
Query-unique ASCII string "QRY "
10
11
12
0051
0052
0059
20
22
24
51
52
59
Primary vendor command set and control interface ID
code
13
14
0002
0000
26
28
02
00
Address for primary algorithm extended query table
15
16
0040
0000
2A
2C
40
00
Alternate vendor command set and control interface ID
code (none)
17
18
0000
0000
2E
30
00
00
Address for secondary algorithm extended query table
(none)
19
1A
0000
0000
32
34
00
00
Table 13. CFI Mode: System Interface Data Values
Word Mode
Byte Mode
Description
Address
Data
Address
Data
VCC supply, minimum (2.7V)
VCC supply, maximum (3.6V)
VPP supply, minimum (none)
VPP supply, maximum (none)
Typical timeout for single word/byte write (2N µs)
Typical timeout for maximum size buffer write (2N µs)
Typical timeout for individual block erase (2N ms)
Typical timeout for full chip erase (2N ms)
Maximum timeout for single word/byte write (2N x Typ)
Maximum timeout for maximum size buffer write (2N x Typ)
Maximum timeout for individual block erase (2N x Typ)
Maximum timeout for full chip erase (not supported)
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
0027
0036
0000
0000
0004
0000
000A
000F
0005
0000
0004
0000
36
38
3A
3C
3E
40
42
44
46
48
4A
4C
27
36
00
00
04
00
0A
0F
05
00
04
00
r1.3/June 01
23
HY29DL162/HY29DL163
Table 14. CFI Mode: Device Geometry Data Values
Word Mode
Description
Byte Mode
Address
Data
Address
Data
Device size (2N bytes)
27
0015
4E
15
Flash device interface code (02 = asynchronous x8/x16)
28
29
0002
0000
50
52
02
00
Maximum number of bytes in multi-byte write (not
supported)
2A
2B
0000
0000
54
56
00
00
Number of erase block regions
2C
0002
58
02
2D
2E
2F
30
0007
0000
0020
0000
5A
5C
5E
60
07
00
20
00
31
32
33
34
001E
0000
0000
0001
62
64
66
68
1E
00
00
01
Erase block region 1 information
[2E, 2D] = # of blocks in region - 1
[30, 2F] = size in multiples of 256-bytes
Erase block region 2 information
Table 15. CFI Mode: Vendor-Specific Extended Query Data Values
Word Mode
Description
Byte Mode
Address
Data
Address
Data
Query-unique ASCII string "PRI"
40
41
42
0050
0052
0049
80
82
84
50
52
49
Major version number, ASCII
43
0031
86
31
Minor version number, ASCII
44
0030
88
30
Address sensitive unlock (0 = required, 1 = not required)
45
0000
8A
00
Erase suspend (2 = to read and write)
46
0002
8C
02
Sector protect (N = # of sectors/group)
47
0001
8E
01
Temporary sector unprotect (1 = supported)
48
0001
90
01
Sector protect/unprotect scheme (4 = Am29LV800A method)
49
0004
92
04
4A
001C or
0018
94
1C or
18
4B
0000
96
00
Simultaneous R/W operation
(xx = number of sectors in Bank 2: HY29DL162 = 1C, HY29DL163 = 18)
Burst mode type (0 = not supported)
Page mode type (0 = not supported)
4C
0000
98
00
ACC Supply minimum (8.5V)
4D
0085
9A
85
ACC Supply maximum (9.5V)
4E
0095
9C
95
Top/bottom boot version (BB = Bottom Boot, TB = Top Boot)
4F
0002 (BB)
0003 (TB)
9E
02 (BB)
03 (TB)
24
r1.3/June 01
HY29DL162/HY29DL163
WRITE OPERATION STATUS
The HY29DL16x provides a number of facilities to
determine the status of a program or erase operation. These are the RY/BY# (Ready/Busy#)
pin and certain bits of a status word which can be
read from the device during the programming and
erase operations. Table 16 summarizes the status indications and further detail is provided in the
subsections which follow.
RY/BY# - Ready/Busy#
RY/BY# is an open-drain output pin that indicates
whether a programming or erase Automatic Algorithm is in progress or has completed. A pull-up
resistor to VCC is required for proper operation. RY/
BY# is valid after the rising edge of the final WE#
pulse in the corresponding command sequence,
including during the sector erase time-out.
If the output is Low (busy), the device is actively
erasing or programming, including programming
while in the Erase Suspend mode. If the output is
High (ready), the device has completed the operation and is ready to read array data, is in the
standby mode, or at least one bank is in the erasesuspend read mode.
DQ[7] - Data# Polling
The Data# Polling bit, DQ[7], indicates to the host
system whether an Automatic Algorithm is in
progress or completed, or whether a bank is in
Erase Suspend mode. Data# Polling is valid after
the rising edge of the final WE# pulse in the program or erase command sequence.
While a programming operation is in progress, the
device outputs the complement of the value programmed to DQ[7]. When the programming operation is complete, the device outputs the value
programmed to DQ[7]. If a program operation is
attempted within a protected sector, Data# Polling on DQ[7] is active for approximately 1 µs, then
the device returns to reading array data. The host
system must do a read at the program address to
obtain valid programming status information on this
bit.
During an erase operation, Data# Polling produces
a “0” on DQ[7]. When the erase operation is complete, or if the bank enters the Erase Suspend
mode, Data# Polling produces a “1” on DQ[7]. The
host must read at an address within any of the
non-protected sectors designated for erasure to
Table 16. Write and Erase Operation Status Summary
Mode
Operation
DQ[7]
Programming in progress
Normal
DQ[7]#
Programming completed
Data
Erase in progress
Erase completed
0
5
Read within erase suspended
sector
Read within non-erase
Erase
Suspend suspended sector
Programming in progress
Programming completed 6
1
6
DQ[6]
Toggle
DQ[5]
0/1
2
4
Data
Toggle
2
Data
Data
Data
1
4
0/1
1
DQ[3]
DQ[2]
N/A
N/A
0
Data
Data
1
Toggle
0
4
1
1
3
RY/BY#
Data
Data
Data
No toggle
0
N/A
Toggle
1
Data
Data
Data
Data
Data
1
DQ[7]#
Toggle
0/1 2
N/A
N/A
0
Data
Data 4
Data
Data
Data
1
Notes:
1. A valid address within the bank where an Automatic algorithm is in progress is required when reading status information
except RY/BY#. For a programming operation, the address used for the read cycle should be the program address. For
an erase operation, the address used for the read cycle should be any address within a non-protected sector marked for
erasure (any address for the chip erase operation).
2. DQ[5] status switches to a ‘1’ when a program or erase operation exceeds the maximum timing limit.
3. A ‘1’ during sector erase indicates that the 50 µs time-out has expired and active erasure is in progress. DQ[3] is not
applicable to the chip erase operation.
4. Equivalent to ‘No Toggle’ because data is obtained in this state.
5. Data (DQ[7:0]) = 0xFF immediately after erasure.
6. Programming can be done only in a non-suspended sector (a sector not specified for erasure).
r1.3/June 01
25
HY29DL162/HY29DL163
obtain valid erase status information on DQ[7]. If
all sectors designated for erasing are protected,
Data# Polling on DQ[7] is active for approximately
100 µs, then the bank returns to reading array data.
the final WE# pulse in the Program or Erase command sequence, including during the sector erase
time-out. The system may use either OE# or CE#
to control the read cycles.
When the system detects that DQ[7] has changed
from the complement to true data (or “0” to “1” for
erase), it should do an additional read cycle to
ensure that valid data is read on DQ[7:0] or
DQ[15:0]. This is because DQ[7] may change
asynchronously with respect to the other data bits
while Output Enable (OE#) is asserted low.
During an Automatic Program algorithm operation
(including programming while in Erase Suspend
mode), successive read cycles at any address in
the bank where the program operation is taking
place cause DQ[6] to toggle. DQ[6] stops toggling when the operation is complete. If a program address falls within a protected sector, DQ[6]
toggles for approximately 1 µs after the Program
command sequence is written, then returns to
reading array data.
Figure 7 shows the Data# Polling test algorithm.
DQ[6] - Toggle Bit I
Toggle Bit I on DQ[6] indicates whether an Automatic Program or Erase algorithm is in progress
or complete, or whether the device has entered
the Erase Suspend mode. Toggle Bit I may be
read at any address within the programming or
erasing bank and is valid after the rising edge of
While erasing, successive read cycles within any
sector designated for erasure (or any sector for
the chip erase operation) cause DQ[6] to toggle.
DQ[6] stops toggling when the erase operation is
complete or when the device is placed in the Erase
Suspend mode. The host may use DQ[2] to determine which sectors are erasing or erase-suspended (see below).
START
After an Erase command sequence is written, if
all the sectors designated for erasure are protected, DQ[6] toggles for approximately 100 µs,
and the device then returns to reading array data.
Read DQ[7:0]
at Valid Address (Note 1)
Test for DQ[7] = 1?
for Erase Operation
DQ[7] = Data?
YES
Toggle Bit II, DQ[2], when used with DQ[6], indicates whether a particular sector is actively erasing or whether that sector is erase-suspended.
Toggle Bit II is valid after the rising edge of the
final WE# pulse in the command sequence. The
device toggles DQ[2] with each OE# or CE# read
cycle.
NO
NO
DQ[5] = 1?
YES
Read DQ[7:0]
at Valid Address (Note 1)
Test for DQ[7] = 1?
for Erase Operation
DQ[7] = Data?
(Note 2)
YES
NO
PROGRAM/ERASE
EXCEEDED TIME ERROR
DQ[2] - Toggle Bit II
PROGRAM/ERASE
COMPLETE
Notes:
1. During programming , the program address. During sector erase , an
address within any non-protected sector specified for erasure. During
chip erase , an address within any non-protected sector.
2. Recheck DQ[7] since it may change asynchronously to DQ[5].
DQ[2] toggles when the host reads at addresses
within sectors that have been designated for erasure, but cannot distinguish whether the sector is
actively erasing or is erase-suspended. DQ[6],
by comparison, indicates whether the device is
actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are designated for
erasure. Thus, both status bits are required for
sector and mode information.
Figure 8 illustrates the operation of Toggle Bits I
and II.
Figure 7. Data# Polling Test Algorithm
26
r1.3/June 01
HY29DL162/HY29DL163
DQ[5] - Exceeded Timing Limits
DQ[5] is set to a ‘1’ when the program or erase
time has exceeded a specified internal pulse count
limit. This is a failure condition that indicates that
the program or erase cycle was not successfully
completed. DQ[5] status is valid only while DQ[7]
or DQ[6] indicate that the Automatic Algorithm is
in progress.
The DQ[5] failure condition will also be signaled if
the host tries to program a ‘1’ to a location that is
previously programmed to ‘0’, since only an erase
operation can change a ‘0’ to a ‘1’.
For both of these conditions, the host must issue
a Reset command to return the device to the Read
mode.
DQ[3] - Sector Erase Timer
After writing a Sector Erase command sequence,
the host may read DQ[3] to determine whether or
not an erase operation has begun. When the
sector erase time-out expires and the sector erase
operation commences, DQ[3] switches from a ‘0’
to a ‘1’. Refer to the “Sector Erase Command”
section for additional information. Note that the
sector erase timer does not apply to the Chip Erase
command.
After the initial Sector Erase command sequence
is issued, the system should read the status on
DQ[7] (Data# Polling) or DQ[6] (Toggle Bit I) to
ensure that the device has accepted the command
sequence, and then read DQ[3]. If DQ[3] is a ‘1’,
the internally controlled erase cycle has begun and
all further sector erase data cycles or commands
(other than Erase Suspend) are ignored until the
erase operation is complete. If DQ[3] is a ‘0’, the
device will accept a sector erase data cycle to mark
an additional sector for erasure. To ensure that
the data cycles have been accepted, the system
software should check the status of DQ[3] prior to
and following each subsequent sector erase data
cycle. If DQ[3] is high on the second status check,
the last data cycle might not have been accepted.
START
DQ[5] = 1?
Read DQ[7:0]
at Valid Address (Note 1)
NO
Read DQ[7:0]
YES
Read DQ[7:0]
at Valid Address (Note 1)
YES
NO
(Note 4)
DQ[6] Toggled?
NO
(Note 3)
PROGRAM/ERASE
COMPLETE
NO
Read DQ[7:0]
at Valid Address (Note 1)
Read DQ[7:0]
DQ[6] Toggled?
(Note 2)
DQ[2] Toggled?
NO
YES
YES
PROGRAM/ERASE
EXCEEDED TIME ERROR
SECTOR BEING READ
IS IN ERASE SUSPEND
SECTOR BEING READ
IS NOT IN ERASE SUSPEND
Notes:
1. During programming, the program address.
During sector erase, an address within any sector scheduled for erasure.
2. Recheck DQ[6] since toggling may stop at the same time as DQ[5] changes from 0 to 1.
3. Use this path if testing for Program/Erase status.
4. Use this path to test whether sector is in Erase Suspend mode.
Figure 8. Toggle Bit I and II Test Algorithm
r1.3/June 01
27
HY29DL162/HY29DL163
HARDWARE DATA PROTECTION
The HY29DL16x provides several methods of protection to prevent accidental erasure or programming which might otherwise be caused by spurious system level signals during VCC power-up and
power-down transitions, or from system noise.
These methods are described in the sections that
follow.
Command Sequences
Commands that may alter array data require a
sequence of cycles as described in Table 10. This
provides data protection against inadvertent writes.
Low VCC Write Inhibit
To protect data during VCC power-up and powerdown, the device does not accept write cycles
when VCC is less than VLKO (typically 2.4 volts). The
command register and all internal program/erase
circuits are disabled, and the device resets to the
Read mode. Writes are ignored until VCC is greater
than VLKO. The system must provide the proper
signals to the control pins to prevent unintentional
writes when VCC is greater than VLKO.
28
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#,
CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by asserting any one of
the following conditions: OE# = VIL , CE# = VIH, or
WE# = VIH. To initiate a write cycle, CE# and WE#
must be a logical zero while OE# is a logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power
up, the device does not accept commands on the
rising edge of WE#. The internal state machine is
automatically reset to the Read mode on powerup.
Sector Protection
Additional data protection is provided by the
HY29DL16x’s sector protect features, described
previously, which can be used to protect sensitive
areas of the Flash array from accidental or unauthorized attempts to alter the data.
r1.3/June 01
HY29DL162/HY29DL163
ABSOLUTE MAXIMUM RATINGS 1
Symbol
Parameter
Value
Unit
TSTG
Storage Temperature
-65 to +150
ºC
TBIAS
Ambient Temperature with Power Applied
-55 to +125
ºC
VIN2
Voltage on Pin with Respect to VSS:
VCC 2
WP#/ACC 3
A[9], OE#, RESET# 3
All Other Pins 2
-0.5 to +4.0
-0.5 to +9.5
-0.5 to +12.5
-0.5 to (VCC + 0.5)
V
V
V
V
I OS
Output Short Circuit Current 4
200
mA
Notes:
1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or any other conditions above those indicated in the
operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for
extended periods may affect device reliability.
2. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to
-2.0V for periods of up to 20 ns. See Figure 9. Maximum DC voltage on input or I/O pins is VCC + 0.5 V. During voltage
transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 10.
3. Minimum DC input voltage on pins WP#/ACC, A[9], OE#, and RESET# is -0.5 V. During voltage transitions, A[9], OE#
and RESET# may undershoot VSS to -2.0 V for periods of up to 20 ns. See Figure 9. Maximum DC input voltage on pins
A[9], OE#, and RESET#] is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns. Maximum DC input voltage
on pin WP#/ACC is +9.5 V which may overshoot to 12.0 V for periods up to 20 ns.
4. No more than one output at a time may be shorted to VSS. Duration of the short circuit should be less than one second.
RECOMMENDED OPERATING CONDITIONS 1
Symbol
Parameter
TA
Ambient Operating Temperature:
Commercial Temperature Devices
Industrial Temperature Devices
VCC
Operating Supply Voltage
Value
Unit
0 to +70
-40 to +85
ºC
ºC
+2.7 to +3.6
V
Notes:
1. Recommended Operating Conditions define those limits between which the functionality of the device is guaranteed.
20 ns
20 ns
20 ns
V C C + 2.0 V
0.8 V
- 0.5 V
V C C + 0.5 V
2.0 V
- 2.0 V
20 ns
Figure 9. Maximum Undershoot Waveform
r1.3/June 01
20 ns
20 ns
Figure 10. Maximum Overshoot Waveform
29
HY29DL162/HY29DL163
DC CHARACTERISTICS
Parameter
Description
ILI
Input Load Current
A[9] Input Load Current
ILIT
Output Leakage Current
ILO
ICC1
ICC2
ICC3
VCC Active Read Current 1
VCC Active Read While Write
(Program or Erase) Current 1
3, 4
VHH
VCC Active Write Current
VCC CE# Controlled Deep
Standby Current
VCC RESET# Controlled Deep
Standby Current
Automatic Sleep Mode
Current 5
VCC CE# Controlled Normal
Standby Current
VCC RESET# Controlled
Normal Standby Current 2
Accelerated Program Current,
Byte or Word Mode
Input Low Voltage
Input High Voltage
Voltage for Electronic ID and
Temporary Sector Unprotect
Voltage for Program
Acceleration
VOL1
Output Low Voltage
ICC4
ICC5
ICC6
ICC7
ICC8
IACC
VIL
VIH
VID
VOH1
Output High Voltage
VOH2
V LK O
Low VCC Lockout Voltage4
Test Setup 2
VIN = VSS to VCC
A[9] = 12.5 V
VOUT = VSS to VCC
CE# = VIL,
5 MHz
OE# = VIH,
1 MHz
Byte Mode
Min
Typ
Max
±1.0
35
±1.0
Unit
µA
µA
µA
10
16
mA
2
4
mA
10
16
mA
2
4
mA
21
45
mA
16
34
mA
21
45
mA
16
34
mA
15
35
mA
0.2
5
µA
RESET# = VSS ± 0.3 V
0.2
5
µA
VIH = VCC ± 0.3 V,
VIL = VSS ± 0.3 V
0.2
5
µA
CE# = RESET# = VIH
50
300
µA
RESET# = VIL
50
300
µA
5
15
-0.5
0.7 x VCC
10
30
0.8
VCC + 0.3
mA
mA
V
V
VCC = 3.0V ± 10%
8.5
12.5
V
VCC = 3.0V ± 10%
8.5
9.5
V
0.45
V
CE# = VIL,
5 MHz
OE# = VIH,
1 MHz
Word Mode
CE# = VIL,
5 MHz
OE# = VIH,
1 MHz
Byte Mode
CE# = VIL,
5 MHz
OE# = VIH,
1 MHz
Word Mode
CE# = VIL, OE# = VIH
CE# = VCC ± 0.3 V,
RESET# = VCC ± 0.3 V
CE# = VIL,
OE# = VIH
VCC = VCC Min,
IOL = 4.0 mA
VCC = VCC Min,
IOH = -2.0 mA
VCC = VCC Min,
IOH = -100 µA
VHH
VCC
0.85 x VCC
V
VCC - 0.4
V
2.3
2.5
V
Notes:
1. The ICC current is listed is typically less than 2 mA/MHz with OE# at VIH. Typical VCC is 3.0 V.
2. All parameters are tested with VCC = VCC Max unless otherwise noted.
3. ICC active while the Automatic Erase or Automatic Program algorithm is in progress.
4. Not 100% tested.
5. Automatic sleep mode is enabled when addresses remain stable for tACC + 30 ns (typical).
30
r1.3/June 01
HY29DL162/HY29DL163
DC CHARACTERISTICS
Zero Power Flash
20
Supply Current in ma
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1 MHz.
Figure 11. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
12
3.6 V
10
2.7 V
Supply Current in ma
8
6
4
2
0
1
Note: T = 25 °C.
2
3
4
5
6
Frequency in MHz
Figure 12. Typical ICC1 Current vs. Frequency
r1.3/June 01
31
HY29DL162/HY29DL163
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUT S
OUT PUT S
Steady
Changing from H to L
Changing from L to H
Don't Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Centerline is High Impedance State
(High Z)
TEST CONDITIONS
Table 17. Test Specifications
+ 3.3V
Test
Condition
- 70
- 80
Output Load
2.7
KOhm
Output Load Capacitance (CL)
CL
6.2
KOhm
Figure 13. Test Setup
All diodes
are
1N3064
or
equivalent
Unit
Figure 13
30
Input Rise and Fall Times
DEVICE
UNDER
TEST
- 90
- 12
100
pF
5
ns
Input Signal Low Level
0.0
V
Input Signal High Level
3.0
V
Input Timing Measurement
Signal Level
1.5
V
Output Timing Measurement
Signal Level
1.5
V
Note: Timing measurements are made at the reference
levels specified above regardless of where the illustrations
in the timing diagrams appear to indicate the measurement
is made
3.0 V
Input
1.5 V
Measurement Level
1.5 V
Output
0.0 V
Figure 14. Input Waveforms and Measurement Levels
32
r1.3/June 01
HY29DL162/HY29DL163
AC CHARACTERISTICS
Read Operations
Parameter
Description
JEDEC
Std
tAVAV
tRC
Read Cycle Time 1
tAVQV
tACC
Address to Output Delay
tELQV
tCE
Chip Enable to Output Delay
tEHQZ
tDF
Chip Enable to Output High Z 1
tGLQV
t OE
Output Enable to Output Delay
tGHQZ
tAXQX
Speed Option
Test Setup
- 80
- 90
- 12
Min
70
80
90
120
ns
CE# = VIL
OE# = VIL
Max
70
80
90
120
ns
OE# = VIL
Max
70
80
90
120
ns
Max
30
30
40
50
ns
Max
25
25
30
30
ns
Max
25
25
30
30
ns
CE# = VIL
1
tDF
Output Enable to Output High Z
tOEH
Output Enable
Hold Time 1
t OH
Output Hold Time from Addresses, CE#
or OE#, Whichever Occurs First 1
Unit
- 70
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
Min
0
ns
Notes:
1. Not 100% tested.
tR C
Addresses Stable
Addresses
tA C C
CE#
tO E
OE#
tO E H
WE#
tD F
tC E
tO H
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 15. Read Operation Timings
r1.3/June 01
33
HY29DL162/HY29DL163
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Description
Std
Speed Option
Test Setup
- 70
- 80
- 90
- 12
Unit
tREADY
RESET# Pin Low (During Automatic
Algorithms) to Read or Write 1
Max
20
µs
tREADY
RESET# Pin Low (NOT During
Automatic Algorithms) to Read or Write1
Max
500
ns
RESET# Pulse Width
Min
500
ns
Min
50
ns
tRP
1
tRH
RESET# High Time Before Read
tRPD
RESET# Low to Standby Mode
Max
20
µs
tRB
RY /BY # Recovery Time
Min
0
ns
Notes:
1. Not 100% tested.
RY/BY#
0V
CE#, OE#
tR H
RESET#
tR P
t Ready
Reset Timings NOT During Automatic Algorithms
t Ready
RY/BY#
tRB
CE#, OE#
RESET#
tR P
Reset Timings During Automatic Algorithms
Figure 16. RESET# Timings
34
r1.3/June 01
HY29DL162/HY29DL163
AC CHARACTERISTICS
Word/Byte Configuration (BYTE#)
Parameter
JEDEC
Speed Option
Description
Std
- 70
- 80
- 90
- 12
Unit
tELFL
CE# to BY TE# Switching Low
Max
5
ns
tELFH
CE# to BY TE# Switching High
Max
5
ns
tFLQZ
BY TE# Switching Low to Output High-Z
Max
25
25
30
30
ns
tFHQV
BY TE# Switching High to Output Active
Min
70
80
90
120
ns
CE#
OE#
BYTE#
BYTE#
switching
from word to
byte mode
DQ[14:0]
tELFL
Data Output DQ[14:0]
DQ[15]/A-1
Output DQ[15]
Data Output DQ[7:0]
Address Input A-1
tF L Q Z
BYTE#
switching
from byte to
word mode
BYTE#
DQ[14:0]
Data Output DQ[7:0]
DQ[15]/A-1
Data Output DQ[14:0]
Address Input A-1
tE L F H
Data Output DQ[15]
tF H Q V
Figure 17. BYTE# Timings for Read Operations
CE#
Falling edge of the last WE# signal
WE#
t S E T (t A S )
BYTE#
t H O L D (t A H )
Note: Refer to the Program/Erase Operations table for tAS and tAH specifications.
Figure 18. BYTE# Timings for Write Operations
r1.3/June 01
35
HY29DL162/HY29DL163
AC CHARACTERISTICS
Program and Erase Operations
Parameter
JEDEC Std
tAVAV
tWC
tAS
tAVWL
tAH
tWLAX
tAST
tAHT
tDS
tDVWH
tDH
tWHDX
tGHWL
tGHWL
tCS
tELWL
tCH
tWHEH
tOEPH
tCEPH
tWP
tWLWH
tWPH
tWHWL
tSR/W
Description
Write Cycle Time 1
Address Setup Time
Address Hold Time
Address Setup Time for Toggle Bit Test
Address Hold Time for Toggle Bit Test
Data Setup Time
Data Hold Time
Read Recovery Time Before Write
CE# Setup Time
CE# Hold Time
OE# High Time for Toggle Bit Test
CE# High Time for Toggle Bit Test
Write Pulse Width
Write Pulse Width High
Latency Between Read and Write Operations
Byte Mode
Programming Operation
tWHWH1
1, 2, 3
tWHWH1
Word Mode
Accelerated Programming
Operation 1, 2, 3 (WP#/ACC = VHH)
Byte or
Word Mode
Byte Mode
Chip Programming Operation 1, 2, 3, 5
Word Mode
tWHWH2
tWHWH2 Sector Erase Operation 1, 2, 4
tWHWH3
tWHWH3 Chip Erase Operation 1, 2, 4
Erase and Program Cycle Endurance 1
tVCS
tRB
tBUSY
VCC Setup Time 1
Recovery Time from RY/BY#
WE# High to RY/BY# Delay
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Max
Typ
Max
Typ
Max
Typ
Max
Typ
Max
Typ
Max
Typ
Typ
Min
Min
Min
Min
Speed Option
- 80 - 90 - 12
80
90
120
0
45
45
45
50
15
0
35
35
45
50
0
0
0
0
20
20
30
30
35
50
30
0
10
150
15
210
10
150
20
60
16
48
0.5
7.5
16
1,000,000
100,000
50
0
90
- 70
70
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
µs
µs
se c
se c
se c
se c
se c
se c
se c
cycles
cycles
µs
ns
ns
Notes:
1. Not 100% tested.
2. Typical program and erase times assume the following conditions: 25 °C, VCC = 2.0 volts, 100,000 cycles. In addition,
programming typicals assume a checkerboard pattern. Maximum program and erase times are under worst case conditions of 90 °C, VCC = 1.8 volts, 100,000 cycles.
3. Excludes system-level overhead, which is the time required to execute the four-bus-cycle sequence for the Program
command. See Table 10 for further information on command sequences.
4. Excludes 0x00 programming prior to erasure. In the preprogramming step of the Automatic Erase algorithm, all bytes
are programmed to 0x00 before erasure.
5. The typical chip programming time is considerably less than the maximum chip programming time listed since most
bytes/words program faster than the maximum programming times specified. The device sets DQ[5] = 1 only If the
maximum byte/word program time specified is exceeded. See Write Operation Status section for additional information.
36
r1.3/June 01
HY29DL162/HY29DL163
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
tW C
Addresses
tA S
0x555
Read Status Data (last two cycles)
tA H
PA
PA
PA
CE#
tG H W L
OE#
tC H
tW P
WE#
tC S
tW P H
tD S
tW H W H 1
tD H
0xA0
Data
PD
Status
tB U S Y
D OUT
tR B
RY/BY#
V CC
tV C S
Notes:
1. PA = Program Address, PD = Program Data, DOUT is the true data at the program address.
2. Commands shown are for Word mode operation.
3. VCC shown only to illustrate tVCS measurement references. It cannot occur as shown during a valid command sequence.
Figure 19. Program Operation Timings
r1.3/June 01
37
HY29DL162/HY29DL163
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
tW C
Addresses
tA S
0x2AA
Read Status Data (last two cycles)
tA H
SA
VA
VA
Address = 0x555
for chip erase
CE#
tG H W L
OE#
tC H
tW P
WE#
tC S
tW P H
tD S
Data = 0x10
for chip erase
tD H
Data
0x55
0x30
t W H W H 2 or
tW H W H 3
Status
tB U S Y
D OUT
tR B
RY/BY#
V CC
tV C S
Notes:
1. SA =Sector Address (for sector erase), VA = Valid Address for reading status data (see Write Operation Status section),
DOUT is the true data at the read address. (0xFF after an erase operation).
2. Commands shown are for Word mode operation.
3. VCC shown only to illustrate tVCS measurement references. It cannot occur as shown during a valid command sequence.
Figure 20. Sector/Chip Erase Operation Timings
38
r1.3/June 01
HY29DL162/HY29DL163
AC CHARACTERISTICS
tW C
Addresses
tR C
Valid PA
tW C
Valid RA
tA S
tW C
Valid PA
tA C C
Valid PA
tC P H
CE#
tA H
tC P
tC E
OE#
tOEH
tG H W L
tD F
WE#
tW P H
tW P
tD S
Data Bus
tO E
tO H
tD H
Valid D IN
WE# Controlled Write Cycle
Valid D O U T
Read Cycle
Valid D IN
Valid D IN
CE# Controlled Write Cycles
tS R / W
Notes:
1. PA = Program Address, RA = Read Address, DOUT is the data at the read address.
Figure 21. Back-to-Back Read/Write Operation Timings
r1.3/June 01
39
HY29DL162/HY29DL163
AC CHARACTERISTICS
tR C
VA
Addresses
VA
VA
tA C C
tC H
CE#
tC E
OE#
tD F
tO E H
WE#
tO E
tO H
DQ[7]
Complement
DQ[6:0]
Status Data
Complement
Status Data
True
Valid Data
Data
Valid Data
tB U S Y
RY/BY#
Notes:
1. VA = Valid Address for reading Data# Polling status data (see Write Operation Status section).
2. Illustration shows first status cycle after command sequence, last status read cycle and array data read cycle.
Figure 22. Data# Polling Timings (During Automatic Algorithms)
tA C C
tR C
VA
Addresses
VA
VA
VA
Valid Data
tA H T
tA S T
tC E
CE#
tC H
tO E
tC E P H
tO E P H
OE#
tO E H
WE#
tD F
tO H
DQ[6], [2]
tB U S Y
Valid Status
Valid Status
Valid Status
(first read)
(second read)
(stops toggling)
RY/BY#
Notes:
1. VA = Valid Address for reading Toggle Bits (DQ[2], DQ[6]) status data (see Write Operation Status section).
2. Illustration shows first two status read cycles after command sequence, last status read cycle and array data read cycle.
Figure 23. Toggle Polling Timings (During Automatic Algorithms)
40
r1.3/June 01
HY29DL162/HY29DL163
AC CHARACTERISTICS
Enter Automatic
Erase
Erase
Suspend
WE#
Erase
Erase
Suspend
Read
Enter Erase
Suspend
Program
Erase
Resume
Erase
Suspend
Program
Erase
Suspend
Read
Erase
Complete
Erase
DQ[6]
DQ[2]
Notes:
1. The system may use CE# or OE# to toggle DQ[2] and DQ[6]. DQ[2] toggles only when read at an address within an
erase-suspended sector.
Figure 24. DQ[2] and DQ[6] Operation
Sector Group Protect/Unprotect, Temporary Sector Unprotect, Accelerated Program
Parameter
JE D E C
Description
Std
tVIDR
tVHH
tRSP
tRRB
tVRST
tPROT
tUNPR
tVERW
Speed Option
- 70 - 80
VID Transition Time for Temporary Sector Unprotect 1
Min
1
VHH Transition Time for Accelerated Programming
Min
RESET# Setup Time for Temporary Sector Unprotect Min
RESET# Hold Time for Temporary Sector Unprotect
Min
RESET# Setup Time for Sector Group Protect and
Min
Unprotect
Sector Group Protect Time
Max
Sector Unprotect Time
Max
Protect/Unprotect Verify Wait Time
Min
- 90
- 12
Unit
500
250
4
4
ns
ns
µs
µs
1
µs
150
15
1
µs
ms
µs
Notes:
1. Not 100% tested.
V ID
RESET#
V IL or V IH
V IL or V IH
t VIDR
t VIDR
CE#
WE#
tR S P
tR R B
RY/BY#
Figure 25. Temporary Sector Unprotect Timings
r1.3/June 01
41
HY29DL162/HY29DL163
AC CHARACTERISTICS
VHH
WP#/ACC
V IL or V IH
V IL or V IH
tV H H
tV H H
Figure 26. Accelerated Programming Timings
V ID
RESET#
V IH
SA, A[6],
A[1], A[0]
Don't Care
Valid *
Valid *
Sector Protect/Unprotect
Data
0x60
tV R S T
Valid *
Verify
0x60
0x40
tP R O T
Status
tV E R W
CE#
tU N P R
WE#
OE#
Note: For Sector Group Protect, A[6] = 0, A[1] = 1, A[0] = 0. For Sector Unprotect, A[6] = 1, A[1] = 1, A[0] = 0.
Figure 27. Sector Group Protect and Unprotect Timings
42
r1.3/June 01
HY29DL162/HY29DL163
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Parameter
JE D E C
Std
tAVAV
tAVEL
tELAX
tDVEH
tEHDX
tGHEL
tWLEL
tEHWH
tELEH
tEHEL
tWC
tAS
tAH
tDS
tDH
tGHEL
tWS
tWH
tCP
tCPH
Speed Option
Description
Write Cycle Time 1
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Read Recovery Time Before Write
WE# Setup Time
WE# Hold Time
CE# Pulse Width
CE# Pulse Width High
Byte Mode
Programming Operation
tWHWH1
1, 2, 3
tWHWH1
Word Mode
Accelerated Programming
Operation 1, 2, 3 (WP#/ACC = VHH)
Byte or
Word Mode
Byte Mode
Chip Programming Operation 1, 2, 3, 5
Word Mode
tWHWH2
tWHWH2 Sector Erase Operation 1, 2, 4
tWHWH3
tWHWH3 Chip Erase Operation 1, 2, 4
Erase and Program Cycle Endurance 1
tBUSY
CE# to RY/BY# Delay
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Max
Typ
Max
Typ
Max
Typ
Max
Typ
Max
Typ
Max
- 70
- 80
- 90
- 12
70
80
90
120
45
45
50
50
45
50
Unit
30
10
150
15
210
10
150
20
60
16
48
0.5
7.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
µs
µs
se c
se c
se c
se c
se c
se c
Typ
16
se c
Typ
Min
Min
1,000,000
100,000
90
cycles
cycles
ns
0
45
35
45
35
0
0
0
0
30
30
Notes:
1. Not 100% tested.
2. Typical program and erase times assume the following conditions: 25 °C, VCC = 3.0 volts, 100,000 cycles. In addition,
programming typicals assume a checkerboard pattern. Maximum program and erase times are under worst case conditions of 90 °C, VCC = 2.7 volts, 100,000 cycles.
3. Excludes system-level overhead, which is the time required to execute the four-bus-cycle sequence for the Program
command. See Table 10 for further information on command sequences.
4. Excludes 0x00 programming prior to erasure. In the preprogramming step of the Automatic Erase algorithm, all bytes
are programmed to 0x00 before erasure.
5. The typical chip programming time is considerably less than the maximum chip programming time listed since most
bytes program faster than the maximum programming times specified. The device sets DQ[5] = 1 only If the maximum
byte program time specified is exceeded. See Write Operation Status section for additional information.
r1.3/June 01
43
HY29DL162/HY29DL163
AC CHARACTERISTICS
0x555 for Program
0x2AA for Erase
PA for Program
SA for Sector Erase
0x555 for Chip Erase
Addresses
VA
tW C
tA S
tA H
WE#
tG H E L
tW H
OE#
tW S
tC P
tC P H
t W H W H 1 or t W H W H 2 or t W H W H 3
CE#
tD S
tD H
tB U S Y
Data
Status
0xA0 for Program
0x55 for Erase
D OUT
PD for Program
0x30 for Sector Erase
0x10 for Chip Erase
RY/BY#
tR H
RESET#
Notes:
1. PA = program address, PD = program data, VA = Valid Address for reading program or erase status (see Write
Operation Status section), DOUT = array data read at VA.
2.
Illustration shows the last two cycles of the program or erase command sequence and the last status read cycle.
3.
Word mode addressing shown.
4.
RESET# shown only to illustrate tRH measurement references. It cannot occur as shown during a valid command
sequence.
Figure 28. Alternate CE# Controlled Write Operation Timings
44
r1.3/June 01
HY29DL162/HY29DL163
Latchup Characteristics
Description
Minimum
Maximum
Unit
Input voltage with respect to VSS on all pins except I/O pins
(including A[9], OE# and RESET#)
- 1.0
12.5
V
Input voltage with respect to VSS on all I/O pins
- 1.0
VCC + 1.0
V
VCC Current
- 100
100
mA
Notes:
1. Includes all pins except VCC. Test conditions: VCC = 1.8 V, one pin at a time.
TSOP Pin Capacitance
Symbol
Parameter
CIN
Test Setup
Typ
Max
Unit
VIN = 0
6
7.5
pF
VOUT = 0
8.5
12
pF
VIN = 0
7.5
9
pF
Test Conditions
Minimum
Unit
150 ºC
10
Years
125 ºC
20
Years
Input Capacitance
COUT
Output Capacitance
CIN2
Control Pin Capacitance
Notes:
1. Sampled, not 100% tested.
2. Test conditions: TA = 25 ºC, f = 1.0 MHz.
Data Retention
Parameter
Minimum Pattern Data Retention Time
PACKAGE DRAWINGS
Physical Dimensions
TSOP48 - 48-pin Thin Small Outline Package (measurements in millimeters)
0.95
1.05
Pin 1 ID
1
48
0.50 BSC
11.90
12.10
24
25
18.30
18.50
0.05
0.15
19.80
20.20
0.08
0.20
1.20
MAX
0.10
0.21
o
0.25MM (0.0098") BSC
0
o
5
0.50
0.70
r1.3/June 01
45
HY29DL162/HY29DL163
PACKAGE DRAWINGS
Physical Dimensions
FBGA48 - 48-Ball Fine-Pitch Ball Grid Array, 8 x 9 mm (measurements in millimeters)
Note: Unless otherwise specified, tolerance = ± 0.05 mm
0.10 C
9.00 ± 0.10
A
1.80
± 0.10
A1 CORNER
INDEX AREA
2.10 ± 0.10
C
8.00 ± 0.10
0.10 C
B
C
0.10 C
0.76
TYP
1.10
MAX
Seating
Plane
0.20
MIN
C
0.08 C
5.60 BSC
H
G
F
E
D
C
B
A
6
5
0.40
BSC
4
C
4.00 BSC
3
2
1
0.80 TYP
Ø 0.30 ± 0.05
Ø 0.15 M C A B
Ø 0.08 M C
46
0.40
BSC
Pin A1
Index Mark
C
r1.3/June 01
HY29DL162/HY29DL163
ORDERING INFORMATION
Hynix products are available in several speeds, packages and operating temperature ranges. The
ordering part number is formed by combining a number of fields, as indicated below. Refer to the ‘Valid
Combinations’ table, which lists the configurations that are planned to be supported in volume. Please
contact your local Hynix representative or distributor to confirm current availability of specific configurations and to determine if additional configurations have been released.
HY29DL16x X
X
-
X
X
X
SPECIAL INST RUCT IONS
T EMPERAT URE RANGE
Blank = Commercial ( 0 to +70 °C)
I = Industrial (-40 to +85 °C)
SPEED OPT ION
70 =
80 =
90 =
12 =
70 ns
80 ns
90 ns
120 ns
PACKAGE T YPE
T = 48-Pin Thin Small Outline Package (TSOP)
F = 48-Ball Fine-Pitch Ball Grid Array (FBGA), 8 x 9 mm
BOOT BLOCK LOCAT ION
T = Top Boot Block Option
B = Bottom Boot Block Option
DEVICE NUMBER
HY 29DL162 = 16 Megabit (2M x 8/1M x 16) CMOS 3 Volt-Only Sector
Erase Flash Memory with 2Mb/14Mb Bank Split
HY 29DL163 = 16 Megabit (2M x 8/1M x 16) CMOS 3 Volt-Only Sector
Erase Flash Memory with 4Mb/12Mb Bank Split
VALID COMBINATIONS
Package and Speed
FBGA
T SOP
Temperature
70 ns
80 ns
90 ns
120ns
70 ns
80 ns
90 ns
120ns
Commercial
F-70
F-80
F-90
F-12
T-70
T-80
T-90
T-12
Industrial
F-70I
F-80I
F-90I
F-12I
T-70I
T-80I
T-90I
T-12I
Note:
1. The complete part number is formed by appending the suffix shown in the table to the Device Number. For example, the
part number for a 120 ns, Industrial temperature range, 2Mb/14Mb bank-split device in the TSOP package with the top
boot block option is HY29DL162TT-12I.
2. Please contact your local Hyundai representative or distributor for current product availability.
r1.3/June 01
47
HY29DL162/HY29DL163
Important Notice
© 2001 by Hynix Semiconductor America. All rights reserved.
No part of this document may be copied or reproduced in any
form or by any means without the prior written consent of Hynix
Semiconductor Inc. or Hynix Semiconductor America (collectively “Hynix”).
tions of Sale only. Hynix makes no warranty, express, statutory, implied or by description, regarding the information set
forth herein or regarding the freedom of the described devices
from intellectual property infringement. Hynix makes no warranty of merchantability or fitness for any purpose.
The information in this document is subject to change without
notice. Hynix shall not be responsible for any errors that may
appear in this document and makes no commitment to update
or keep current the information contained in this document.
Hynix advises its customers to obtain the latest version of the
device specification to verify, before placing orders, that the
information being relied upon by the customer is current.
Hynix’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed
between the customer and Hynix prior to use. Life support
devices or systems are those which are intended for surgical
implantation into the body, or which sustain life whose failure to
perform, when properly used in accordance with instructions
for use provided in the labeling, can be reasonably expected to
result in significant injury to the user.
Devices sold by Hynix are covered by warranty and patent indemnification provisions appearing in Hynix Terms and Condi-
Revision Record
Rev.
Date
1.0
5/00
Original issue.
7/00
Corrected description of CFI Query and Reset commands in CFI mode description section.
Minor typographical corrections.
1.2
4/01
Change to Hynix format.
Removed 'BA' as requirement for several operations in Table 6 and corrected description of Electronic ID Operation
(High Voltage Method).
Added Bank Address to CFI Query command and changed operational description in CFI section.
Removed high voltage sector group protect/unprotect method and all references to such.
1.3
6/01
Changed program and erase parameter values. Corrected error in CFI Table 13.
1.1
Details
Memory Sales and Marketing Division
Hynix Semiconductor Inc.
10 Fl., Hynix Youngdong Building
89, Daechi-dong
Kangnam-gu
Seoul, Korea
Telephone: +82-2-580-5000
Fax: +82-2-3459-3990
Flash Memory Business Unit
Hynix Semiconductor America Inc.
3101 North First Street
San Jose, CA 95134
USA
Telephone: (408) 232-8800
Fax: (408) 232-8805
http://www.us.hynix.com
http://www.hynix.com
48
r1.3/June 01