1 Data Book AU6391 USB2.0 to ATA/ATAPI Bridge Controller Technical Reference Manual Product Specification Official Release Revision 1.00W Public Feb 2007 Data book status Objective specification This data book contains target specifications for product development. Preliminary specification This data book contains preliminary supplementary data may be published later. Product specification This data book contains final product specifications. data; Revision History Date Revision Feb 2007 1.00W Description Initial release Page 2 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public Copyright Notice Copyright 1997 - 2007 Alcor Micro Corp. All Rights Reserved. Trademark Acknowledgements The company and product names mentioned in this document may be the trademarks or registered trademarks of their manufacturers. Disclaimer Alcor Micro Corp. reserves the right to change this product without prior notice. Alcor Micro Corp. makes no warranty for the use of its products and bears no responsibility for any error that appear in this document. Specifications are subject to change without prior notice. Contact Information: Web site: http://www.alcormicro.com/ Taiwan Alcor Micro Corp. 4F, No 200 Kang Chien Rd., Nei Hu, Taipei, Taiwan, R.O.C. Phone: 886-2-8751-1984 Fax: 886-2-2659-7723 China ShenZhen Office Rm.2407-08, Industrial Bank Building No.4013, Shennan Road ,ShenZhen,China. 518026 Phone: (0755) 8366-9039 Fax: (0755) 8366-9101 Santa Clara Office 2901 Tasman Drive, Suite 206 Santa Clara, CA 95054 USA Phone: (408) 845-9300 Fax: (408) 845-9086 Los Angeles Office 9070 Rancho Park Court Rancho Cucamonga, CA 91730 USA Phone: (909) 483-9900 Fax: (909) 944-0464 Page 3 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public Table of Contents 1 Introduction…………………………………………………………….. 6 1.1 Description…………………………………………………………………………….. 6 1.2 Features…………………………………………………………………………………. 6 2 Application Block Diagram…………………………………………. 7 3 Pin Assignment………………………………………………………… 8 4 System Architecture and Reference Design………………….. 14 4.1 AU6391 Block Diagram…………………………………………………………. 14 5 Electrical Characteristics…………………………………………… 15 5.1 Absolute Maximum Ratings………………………………………………….. 15 5.2 Recommended Operating Conditions…………………………………… 15 5.3 General DC Characteristics…………………………………………………… 15 5.4 DC Electrical Characteristics for 5 volts operation……………… 16 5.5 USB Transceiver Characteristics…………………………………………… 17 6 Mechanical Information……………………………………………… 20 7 Abbreviations…………………..……………………………………… 21 Page 4 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public List of Figures 2.1 Block Diagram………………………………………………………………………………….. 7 3.1 GBL bonding Pin Assignment Diagram…………………………………………….. 8 3.2 GEL bonding Pin Assignment Diagram……………………………………………. 11 4.1 AU6391 Block diagram……………………………………………………………………… 14 6.1 Mechanical Information Diagram…………………………………………………….. 20 List of Tables 3.1 GBL bonding Pin Descriptions……………………………………………………... 3.2 GEL bonding Pin Descriptions……………………………………………………… 12 5.1 Absolute Maximum Ratings…………………………………………………………. 15 5.2 Recommended Operating Conditions………………………………………….. 15 5.3 General DC Characteristics………………………………………………………….. 15 5.4 DC Electrical Characteristics of 3.3V I/O Cells……………………… 5.5 Recommended Operation Conditions………………………………………….. 17 5.6 Static characteristic：Digital in ………………………………………………….. 17 5.7 Static characteristic：Analog I/O pins（DP/DM）………………………… 18 5.8 Dynamic characteristic：Analog I/O pins（DP/DM）…………………… 19 Page 5 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public 9 16 1.0 Introduction 1.1 Description The AU6391 is a single chip controller designed for bridgingg USB 2.0 to ATA/ATAPI bus interface. It is used as the primary controller of building an external USB 2.0 hard disk or CD/DVD drives. To maximize the data throughput and achieve the best compatibility, AU6391 is equipped with Alcor’s proprietary automatic speed negotiation (ASN) algorithm. The ASN algorithm allows AU6391 to select optimized operating mode that device can best support a reliable data transfer from PIO mode 0~4 and Ultra DMA mode 2/4. The silicon would work with the default device driver from Windows ME, Windows 2000, Windows XP and Mac OS X, however, vendor device driver provided by Alcor Micro would enable the built device working under Windows 98, Windows 2000 (SP1/SP2) and Mac OS 9. 1.2 Features Supports USB 2.0 specification and USB Device Class Definition for Mass Storage, Bulk-Transport V1.0 Supports ATA/ATAPI-6 specification Revision 1.0 PIO mode 0~4 UDMA mode 2/4 Supports ATA/ATAPI device configured in master or slave mode Supports 48-bit addressing for large capacity hard drive Hardware DMA engine integrated inside for performance enhancement Works with default device driver from Windows ME/2000/XP and Mac OS X. One spared LED pin for disk access indication Built-in voltage regulator 48-pin LQFP package Page 6 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public 2.0 Application Block Diagram The following picture is an application diagram of a typical removable USB2.0 ATA/ATAPI device. With such kinds of devices, users can exchange recorded digital content between ATA/ATAPI device and PC (Notebook) via USB. 2.1 Block Diagram PC with USB Host Controller HD AU6391 CD-ROM, CD-R/W DVD-ROM, VCD-R/W Page 7 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public 3.0 Pin Assignment There are two different form factor packages available to choose from. The following figure shows signal names for each pin and the table in the page after describes each pin in details. Figure 3.1 GBL bonding Pin Assignment Diagram ATADMARQ ATADIOWN ATADIORN ATAIORDY ATADMACKN ATAINTRQ ATADATA15 ATADATA14 ATADATA13 ATADATA12 ATACS1N ATACS0N 48 47 46 45 44 43 42 41 40 39 38 37 GNDU 1 36 ATADATA11 VDDU 2 35 ATADATA10 DM 3 34 ATADATA9 DP 4 33 ATADATA8 REXT 5 32 ATADATA7 VDD33 6 31 ATADATA6 VSS33P 7 30 ATADATA5 VSSA 8 29 ATADATA4 XI 9 28 ATADATA3 XO 10 27 ATADATA2 VDDA 11 26 ATADATA1 25 ATADATA0 GND ALCOR MICRO AU6391-GBL 48PIN LQFP 12 14 15 16 17 18 19 20 21 22 23 AVDD5V VDD3V V18 ATAAD2 ATAAD1 ATAAD0 ATARESETN EEPDATA EEPCLK GPI3 CHIPRESETN 24 GPON7 13 Page 8 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public Table 3.1 GBL bonding Pin Descriptions Pin # Pin Name I/O Description 1 GNDU PWR GND for UTMI Power 2 VDDU PWR Power for UTMI core 3 DM I/O USB DM 4 DP I/O USB DP 5 REXT I 6 VDD33 PWR UTMI power 3.3V 7 VSS33P PWR UTMI power GND 8 VSSA PWR Analog GND 9 XI I 12 MHz crystal input. 10 XO O 12 MHz crystal output. 11 VDDA PWR 12 GND 13 AVDD5V I 5V power supply input 14 VDD3V O 3.3V Power Out 15 V18 PWR 16 ATAAD2 O ATA Address bus 2 17 ATAAD1 O ATA Address bus 1 18 ATAAD0 O ATA Address bus 0 19 ATARESETN O ATA Reset 20 EEPDATA B EEPDATA 21 EEPCLK B EEPCLK 22 GPI3 I GPI for customized software triggle 23 CHIPRESETN I Reset (low active to reset the whole chip), must be pull up with RC. 24 GPON7 O LED indicator Connect pull-low resistor for impedance match Analog 1.8V power GND for IO pad 1.8 V output for core power Page 9 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public Pin # Pin Name I/O Description 25 ATADATA0 I/O ATA Data Bus 0 26 ATADATA1 I/O ATA Data Bus 1 27 ATADATA2 I/O ATA Data Bus 2 28 ATADATA3 I/O ATA Data Bus 3 29 ATADATA4 I/O ATA Data Bus 4 30 ATADATA5 I/O ATA Data Bus 5 31 ATADATA6 I/O ATA Data Bus 6 32 ATADATA7 I/O ATA Data Bus 7 33 ATADATA8 I/O ATA Data Bus 8 34 ATADATA9 I/O ATA Data Bus 9 35 ATADATA10 I/O ATA Data Bus 10 36 ATADATA11 I/O ATA Data Bus 11 37 ATACS0N O ATA Chip Select0 38 ATACS1N O ATA Chip Select1 39 ATADATA12 I/O ATA Data Bus 12 40 ATADATA13 I/O ATA Data Bus 13 41 ATADATA14 I/O ATA Data Bus 14 42 ATADATA15 I/O ATA Data Bus 15 43 ATAINTRQ I ATA Interput request 44 ATADMACKN O ATA Control Signal DMACKN 45 ATAIORDY I ATA Control Signal IORDY 46 ATADIORN O ATA Control Signal DIORN 47 ATADIOWN O ATA Control Signal DIOWN 48 ATADMARQ I ATA Control Signal DMARQ Page 10 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public The following figure shows signal names of each pin of the 48-pin package and the table in the page after describes each pin in details. Figure 3.1 GEL bonding Pin Assignment Diagram ATADMARQ ATADIOWN ATADIORN ATAIORDY ATADMACKN ATAINTRQ ATADATA15 ATADATA14 ATADATA13 ATADATA12 ATACS1N ATACS0N 48 47 46 45 44 43 42 41 40 39 38 37 GNDU 1 36 ATADATA11 VDD 2 35 ATADATA10 VDDU 3 34 ATADATA9 DM 4 33 ATADATA8 DP 5 32 ATADATA7 REXT 6 31 ATADATA6 VDD33 7 30 ATADATA5 VSS33P 8 29 ATADATA4 VSSA 9 28 ATADATA3 XI 10 27 ATADATA2 XO 11 26 ATADATA1 25 ATADATA0 VDDA ALCOR MICRO AU6391-GEL 48PIN LQFP 12 14 15 16 17 18 19 20 21 22 23 AGND5V AVDD5V VDD3V V18 VSSHM ATAAD2 ATAAD1 ATAAD0 ATARESETN GPI3 CHIPRESETN 24 GPON7 13 Page 11 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public Table 3.1 GEL bonding Pin Descriptions Pin # Pin Name I/O Description 1 GNDU GND Ground 2 VDD PWR 1.8V 3 VDDU PWR Power for UTMI core 4 DM I/O USB DM 5 DP I/O USB DP 6 REXT I 7 VDD33 PWR 3.3V 8 VSS33P PWR UTMI power GND 9 VSSA PWR Analog GND 10 XI I 12 MHz crystal input. 11 XO O 12 MHz crystal output. 12 VDDA PWR 1.8V 13 AGND5V GND Ground 14 AVDD5V I 5V Power Source 15 VDD3V O 3.3 V Power Out 16 V18 PWR 1.8 V output for core power 17 VSSHM GND Ground 18 ATAAD2 O ATA Address bus [2] 19 ATAAD1 O ATA Address bus [1] 20 ATAAD0 O ATA Address bus [0] 21 ATARESETN O ATA Reset 22 GPI3 I General Purpose Input. 23 CHIPRESETN I Reset (low active to reset the whole chip), must be pull up with RC. 24 GPON7 O General Purpose Output. 25 ATADATA0 I/O Connect pull-low resistor for impedance match ATA Data Bus [0] Page 12 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public Pin # Pin Name I/O Description 26 ATADATA1 I/O ATA Data Bus [1] 27 ATADATA2 I/O ATA Data Bus [2] 28 ATADATA3 I/O ATA Data Bus [3] 29 ATADATA4 I/O ATA Data Bus [4] 30 ATADATA5 I/O ATA Data Bus [5] 31 ATADATA6 I/O ATA Data Bus [6] 32 ATADATA7 I/O ATA Data Bus [7] 33 ATADATA8 I/O ATA Data Bus [8] 34 ATADATA9 I/O ATA Data Bus [9] 35 ATADATA10 I/O ATA Data Bus [10] 36 ATADATA11 I/O ATA Data Bus [11] 37 ATACS0N O ATA Chip Select0 38 ATACS1N O ATA Chip Select1 39 ATADATA12 I/O ATA Data Bus [12] 40 ATADATA13 I/O ATA Data Bus [13] 41 ATADATA14 I/O ATA Data Bus [14] 42 ATADATA15 I/O ATA Data Bus [15] 43 ATAINTRQ I ATA Interput request 44 ATADMACKN O ATA Control Signal DMACKN 45 ATAIORDY I ATA Control Signal IORDY 46 ATADIORN O ATA Control Signal DIORN 47 ATADIOWN O ATA Control Signal DIOWN 48 ATADMARQ I ATA Control Signal DMARQ Page 13 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public 4.0 System Architecture and Reference Design 4.1 AU6391 Block Diagram Figure 4.1 AU6391 Block Diagram USB Upstream Port USB XCVR RAM SIE Processor 1.8 V 3.3 V ATA Control FIFO ROM Arbitrator 3.3V and 1.8V Voltage Regulator /Power Switch 5V 12MHz XTAL Page 14 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public ATA 5.0 Electrical Characteristics 5.1 Absolute Maximum Ratings Table 5.1 Absolute Maximum Ratings SYMBOL PARAMETER RATING UNITS VDDHM Power Supply -0.3 to VDDHM +0.3 V VIN Input signal Voltage -0.3 to 3.6 V VOUT Output signal Voltage -0.3 to VDDHM +0.3 V TSTG Storage Temperature -40 to 150 O C 5.2 Recommended Operating Conditions Table 5.2 Recommended Operating Conditions SYMBOL PARAMETER MIN TYP MAX UNITS AVDD5V Power Supply 4.75 5.0 5.25 V VDDHM Power Supply 3.0 3.3 3.6 V VDD V18 Digital Supply 1.62 1.8 1.98 V VIN Input signal Voltage 0 3.3 3.6 V TOPR Operating Temperature 0 70 O MAX UNITS C 5.3 Leakage Current and Capacitance Table 5.3 General DC Characteristics SYMBOL PARAMETER CONDITIONS MIN TYP IIN Input current no pull-up or pull-down -10 ±1 10 µA IOZ Tri-state leakage current -10 ±1 10 µA CIN Input capacitance Pad Limit 2.8 ρF COUT Output capacitance Pad Limit 2.8 ρF CBID Bi-directional buffer capacitance Pad Limit 2.8 ρF Page 15 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public 5.4 DC Electrical Characteristics of 3.3V I/O Cells Table 5.4 DC Electrical Characteristics of 3.3V I/O Cells Limits SYMBOL PARAMETER CONDITIONS MIN TYP 3.0 3.0 UNIT VDDHM Power supply Vil Input low voltage Vih Input high voltage Vol Output low voltage ∣Iol∣=2~16mA Voh Output high voltage ∣Ioh∣=2~16mA 2.4 Rpu Input pull-up resistance PU=high, PD=low 55 75 110 KΩ Input pull-down resistance PU=low, PD=high 40 75 150 KΩ -10 ±1 10 μA -10 ±1 10 μA Rpd 3.3V I/O MAX 3.6 V 0.8 V LVTTL Iin Input leakage current Ioz Tri-state output leakage current 2.0 Vin= VDDHM or 0 V 0.4 V Page 16 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public V 5.5 USB Transceiver Characteristics Table 5.5 Electrical characteristics Symbol Parameter VDD33 Min. Typ. Max. Unit Analog supply voltage 3.0 3.3 3.6 V VDD V18 Digital supply voltage 1.62 1.8 1.98 V ICC Operating supply current 55 mA 120 µA ICC(susp) Conditions High speed operating at 480 MHz In suspend mode, current with 1.5kΩ Suspend supply current pull-up resistor on pin RPU disconnected Table 5.6 Static characteristic：Digital pin Symbol Parameter Conditions Min. Typ. Max. Unit 0.8 V Input levels VIL Low-level input voltage VIH High-level input voltage 2.0 V Output levels VOL Low-level output voltage VOH High-level output voltage 0.2 VDDH*-0.2 V Page 17 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public V Table 5.7 Static characteristic：Analog I/O pins（DP/DM） Symbol VHSDIFF VHSCM Parameter Conditions Min. USB2.0 Transceiver（HS） Input Levels（differential receiver） ∣VI（DP）-VI（DM）∣ High speed differential measured at the 300 input sensitivity connection as application circuit High speed data signaling common mode voltage -50 range VHSSQ High speed squelch detection threshold VHSDSC High speed disconnection detection threshold VHSOI VHSOL VHSOH VCHIRPJ VCHIRPK RDRV VTERM VDI VCM Typ. Disconnection detected Disconnection not detected Output Levels High speed idle level output voltage(differential) High speed low level output voltage(differential) High speed high level output voltage(differential) Chirp-J output voltage （differential） Chirp-K output voltage （differential） Unit mV Squelch detected No squelch detected Max. 500 mV 100 mV 150 mV 625 mV 525 mV -10 10 mV -10 10 mV -360 400 mV 700 1100 mV -900 -500 mV Resistance Equivalent resistance 3 used as internal chip only Driver output impedance Overall resistance 40.5 including external resistor Termination Termination voltage for 3.0 pull-up resistor on pin RPU USB1.1 Transceiver（FS/LS） Input Levels（differential receiver） Differential input ∣VI（DP）-VI（DM）∣ 0.2 sensitivity Differential common 0.8 mode voltage Input Levels（single-ended receivers） 6 9 Ω 45 49.5 3.6 V V 2.5 V Page 18 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public VSE Single ended receiver threshold 0.8 2.0 V Output levels VOL Low-level output voltage 0 0.3 V VOH High-level output voltage 2.8 3.6 V Table 5.8 Dynamic characteristic：Analog I/O pins（DP/DM） Symbol Parameter Conditions Min. Typ. Max. Unit Driver Characteristics High-Speed Mode tHSR tHSF High-speed differential rise time High-speed differential fall time 500 ps 500 ps Full-Speed Mode tFR tFF tFRMA VCRS CL=50pF；10 to 90﹪ of∣VOH-VOL∣； CL=50pF；90 to 10﹪ Fall time of∣VOH-VOL∣； Excluding the first Differential rise/fall time transition from idle matching（tFR / tFF） mode Excluding the first Output signal crossover transition from idle voltage mode Rise time 4 20 ns 4 20 ns 90 110 ％ 1.3 2.0 V 75 300 ns 75 300 ns 80 125 ％ 1.3 2.0 V 2.8 3.6 V Low-Speed Mode tLR tLF tLRMA VCRS VOH CL=200pF-600pF； 10 to 90﹪of ∣VOH-VOL∣； CL=200pF-600pF； 90 to 10﹪of Fall time ∣VOH-VOL∣； Excluding the first Differential rise/fall time transition from idle matching（tLR / tLF） mode Excluding the first Output signal crossover transition from idle voltage mode Rise time High-level output voltage Page 19 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public 6.0 Mechanical Information Figure 6.1 Mechanical Information Diagram Page 20 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public 7.0 Abbreviations This chapter lists and defines terms and abbreviations used throughout this specification. SIE ATA UTMI Serial Interface Engine Advanced Technology Attachment USB Transceiver Macrocell Interface Page 21 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public 【MEMO】 About Alcor Micro, Corp Alcor Micro, Corp. designs, develops and markets highly integrated and advanced peripheral semiconductor, and software driver solutions for the personal computer and consumer electronics markets worldwide. We specialize in USB solutions and focus on emerging technology such as USB and IEEE 1394. The company offers a range of semiconductors including controllers for USB hub, integrated keyboard/USB hub and USB Flash memory card reader…etc. Alcor Micro, Corp. is based in Taipei, Taiwan, with sales offices in Taipei, Japan, Korea and California. Alcor Micro is distinguished by its ability to provide innovative solutions for spec-driven products. Innovations like single chip solutions for traditional multiple chip products and on-board voltage regulators enable the company to provide cost-efficiency solutions for the computer peripheral device OEM customers worldwide. Page 22 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public