ETC ES6028

ES6028
Vibratto DVD Processor
Product Brief
ESS Technology, Inc.
DESCRIPTION
FEATURES
The ES6028 Vibratto DVD processor is a single-chip
MPEG video decoder that integrates a state-of-the-art
480-pixel progressive scan video feature to provide
brilliant and sharp, flicker-free output to the video display.
Th e E S 6 0 2 8 p e r f o r m s a u di o / v i d e o s t r e a m d a ta
processing, and TV encoding, and includes four video
DACs, Macrovision  copy protection, DVD system
navigation, system control and housekeeping functions.
• Single-chip DVD processor based on ESS proprietary
The Vibratto DVD processor is built on the ESS proprietary
dual CPU Programmable Multimedia Processor (PMP)
core consisting of 32-bit RISC and 64-bit DSP processors
and offers the best DVD feature set. The processing units
enable simultaneous parallel execution of system
commands and data processing to perform specialized
encoding and decoding tasks in the device architecture.
The RISC processor, and its associated hardware,
perform bit stream parsing, control audio data output,
transfer video and audio data to the vector engine and
service system control and housekeeping functions. The
vector engine (DSP), and associated hardware, perform
audio and video micro-code processing required by A/V
standards, such as Dolby® Digital, DTS  surround,
MPEG, and JPEG imaging. These processing tasks
include audio processing, video motion compensation and
estimation, loop filtering, discrete cosine transforms (DCT)
and inverse DCT, quantization, and inverse quantization.
dual CPU PMP core.
• Integrated NTSC/PAL encoder.
• Progressive scan video output for flicker-free video
display.
•
•
•
•
•
•
Four integrated 10-bit video DACs.
DVD-Video, VCD 1.1, 2.0, and SVCD.
5.1 channel audio outputs.
Interface for ATAPI devices and A/V DVD loaders.
Interface for CF, MS, and SM memory cards.
Direct interface of 8-/16-bit SDRAM up to 128-Mb
capacity.
• Direct interface for up to 4 banks of 8-/16-bit EPROM or
Flash EPROM for up to 16-MB capacity.
• Macrovision 7.1 for NTSC/PAL interlaced video.
• Macrovision AGC 1.03-compliant for 480p progressive
scan video.
• Composite video, S-video, YUV and RGB outputs.
• 8-bit CCIR 601 YUV 4:2:2 output.
• On-Screen Display (OSD) controller with 3-bit blending
provides display with 256 colors in 8 degrees of
transparency.
The Vibratto DVD processor supports both parallel and
serial DVD loader interfaces, industry standard I2S audio
data input and output, EPROM and SDRAM access, and
audio/video data buffering. The Vibratto also supports
both letterbox and pan-and-scan displays, sub-picture
overlay, and On-Screen Display (OSD).
• Subpicture Unit (SPU) decoder supports karaoke lyric,
A new feature found with the Vibratto DVD solution is the
ESS Music Slideshow™, which allows a user to do
voiceovers while viewing JPEG images, Kodak®
PictureCD, and Fujicolor® CD images. In addition, the
Vibratto DVD solution offers support for SACD, Karaoke
CD+G, MP3, HDCD, CD-DA, and Windows Media Audio
(WMA) decoding and playback.
High-Definition Compatible Digital (HDCD) decoding.
The ES6028 Vibratto DVD processor is available in 208pin Plastic Quad Flat Pack (PQFP) device package.
ESS Technology, Inc.
subtitles, and EIA-608 compliant Line 21 Captioning.
• Dolby Digital (AC-3), Dolby Pro Logic, and Dolby Pro
Logic II.
•
•
•
•
•
•
•
•
DTS surround.
S/PDIF digital audio output.
SRS TruSurround®.
Windows Media Audio.
MP3.
CD-DA.
Karaoke.
SAM0462-031704
1
VEE
LA4
LA5
LA6
LA7
LA8
LA9
VSS
VCC
LA10
LA11
LA12
LA13
LA14
LA15
LA16
VSS
VEE
LA17
LA18
LA19
LA20
LA21
RESET#
TDMDX/RSEL
VSS
VEE
TDMDR
TDMCLK
TDMFS
TDMTSC#
TWS/SEL_PLL2
TSD0/SEL_PLL0
VSS
VCC
TSD1/SEL_PLL1
TSD2
NC
MCLK
TBCK
SPDIF/PLL3
NC
VSS
VCC
RSD
RWS
RBCK
NC
XIN
XOUT
AVEE
AVSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
VEE
HA2/AUX4[4]
VEE
I2CDATA/AUX0
I2C_CLK/AUX1
AUX2/IOW#
VSS
VEE
AUX3/IOR#
AUX4
AUX5
AUX6
AUX7
LOE#
VSS
VCC
LCS0#
LCS1#
LCS2#
LCS3#
VSS
LD0
LD1
LD2
LD3
LD4
VEE
VSS
LD5
LD6
LD7
LD8
LD9
LD10
LD11
VSS
VEE
LD12
LD13
LD14
LD15
LWRLL#
LWRHL#
VSS
VEE
CAMIN0
CAMIN1
LA0
LA1
LA2
LA3
VSS
2
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
VSS
HA1/AUX4[3]
HA0/AUX4[2]
HCS3FX#/AUX3[6]
HCS1FX#/AUX3[7]
HIOCS16#/CAMCLK/AUX3[4]
HRD#/DCI_ACK#/AUX4[6]
HWR#/DCI_CLK/AUX4[5]
VEE
VSS
HIORDY/AUX3[3]
HRST#/AUX3[5]
HIRQ/DCI_ERR#/AUX4[7]
HRRQ#/AUX4[0]
HWRQ#/DCI_REQ#/AUX4[1]
HD15/AUX2[7]/IR
HD14/AUX2[6]
VCC
VSS
HD13/AUX2[5]/SP
HD12/AUX2[4]/C2PO
HD11/AUX2[3]//IRQ
HD10/AUX2[2]
HD9/AUX2[1]
HD8/DCI_FDS#/AUX2[0]/VFD_CLK
HD7/DCI7/AUX1[7]/VFD_DIN
VEE
VSS
HD6/DCI6/AUX1[6]/VFD_DOUT
HD5/DCI5/AUX1[5]
HD4/DCI4/AUX1[4]
HD3/DCI3/AUX1[3]
HD2/DCI2/AUX1[2]
HD1/DCI1/AUX1[1]
HD0/DCI0/AUX1[0]
VCC
VSS
HSYNC#/CAMIN7/AUX3[0]
VSYNC#/CAMIN6/AUX3[1]
PCLKQSCN/CAMIN5/AUX3[2]
PCLK2XSCN/CAMIN4
YUV7/CAMIN3
YUV6/VDAC
YUV5/YDAC
ADVSS
ADVEE
YUV4/RSET
YUV3/COMP
YUV2/CDAC
YUV1/VREF
YUV0/CAMIN2/UDAC
DCLK
ES6028 PRODUCT BRIEF
ES6028 PINOUT DIAGRAM
ES6028 PINOUT DIAGRAM
The device pinout for the ES6028 is shown in Figure 1.
SAM0462-031704
ES6028
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
VEE
VSS
DSCK
DQM
DCS0#
VEE
VSS
DCS1#
DB15
DB14
DB13
DB12
VEE
VSS
DB11
DB10
DB9
DB8
DB7
DB6
VSS
VCC
DB5
DB4
DB3
DB2
DB1
DB0
VSS
VEE
DMBS1
DMBS0
DRAS#
DWE#
DOE#/DSCK_EN
DCAS#
VEE
VSS
DMA11
DMA10
DMA9
DMA8
DMA7
DMA6
VSS
VEE
DMA5
DMA4
DMA3
DMA2
DMA1
DMA0
Figure 1 ES6028 Device Pinout
ESS Technology, Inc.
ES6028 PRODUCT BRIEF
ES6028 PIN DESCRIPTION
ES6028 PIN DESCRIPTION
Table 1 lists the pin descriptions for the ES6028.
Table 1
ES6028 Pin Description
Name
Pin Numbers
I/O
1,18, 27, 59, 68, 75,
92, 99, 104, 130,
148, 157, 159, 164,
183, 193, 201
P
I/O power supply.
2-7, 10-16, 19-23,
204-207
O
RISC port address bus.
VSS
8, 17, 26, 34, 43,
60, 67, 76, 84, 91,
98, 103, 120, 129,
138, 147, 156, 163,
171, 177, 184, 192,
200, 208
G
Ground.
VCC
9, 35, 44, 83, 121,
139, 172
P
Core power supply.
24
I
Reset input, active-low.
O
TDM transmit data output.
I
LCS3 ROM Boot Data Width Select. Strapped to VCC or ground via 4.7-kΩ
resistor; read only during reset.
VEE
LA[21:0]
RESET#
TDMDX
RSEL
Definition
RSEL
25
Selection
0
16-bit ROM
1
8-bit ROM
TDMDR
28
I
TDM receive data input.
TDMCLK
29
I
TDM clock input.
TDMFS
30
I
TDM frame sync input.
TDMTSC#
31
O
TDM output enable.
O
Audio transmit frame sync output.
I
System and DSCK output clock frequency selection is made at the rising edge of
RESET#. The matrix below lists the available clock frequencies and their
respective PLL bit settings. Strapped to VCC or ground via 4.7-kΩ resistor; read
only during reset.
TWS
SEL_PLL2
ESS Technology, Inc.
32
SEL_PLL2
SEL_PLL1
SEL_PLL0 Clock Type
0
0
0
DCLK x 4.25
0
0
1
Reserved
0
1
0
Bypass mode
0
1
1
DCLK x 3.75
1
0
0
DCLK x 4.5
1
0
1
Reserved
1
1
0
DCLK x 3.5
1
1
1
DCLK x 4
SAM0462-031704
3
ES6028 PRODUCT BRIEF
ES6028 PIN DESCRIPTION
Table 1
ES6028 Pin Description (Continued)
Name
Pin Numbers
I/O
Definition
O
Audio transmit serial data output 0.
I
Refer to the description and matrix for SEL_PLL2 pin 32.
O
Audio transmit serial data output 1.
I
Refer to the description and matrix for SEL_PLL2 pin 32.
37
O
Audio transmit serial data output 2.
38, 42, 48
—
No connect pins. Leave open.
MCLK
39
I/O
Audio master clock for audio DAC.
TBCK
40
I/O
Audio transmit bit clock. TBCK is an input during reset and subsequently is
programmed as an output via the AUDIOXMT register (addr 0x2000D00Ch, bit 4).
O
S/PDIF output.
I
Clock source select. Strapped to VCC or ground via 4.7-kΩ resistor; read only
during reset.
TSD0
33
SEL_PLL0
TSD1
36
SEL_PLL1
TSD2
NC
SPDIF
SEL_PLL3
SEL_PLL3
41
Clock Source
0
Crystal oscillator
1
DCLK input
RSD
45
I
Audio receive serial data.
RWS
46
I
Audio receive frame sync.
RBCK
47
I
Audio receive bit clock.
XIN
49
I
27-MHz crystal input.
XOUT
50
O
27-MHz crystal output.
AVEE
51
P
Analog power for PLL.
AVSS
52
G
Analog ground for PLL.
53-58, 61-66
O
DRAM address bus.
69
O
DRAM column address strobe.
O
DRAM output enable.
O
DRAM clock enable.
DMA[11:0]
DCAS#
DOE#
70
DSCK_EN
DWE#
71
O
DRAM write enable.
DRAS#
72
O
DRAM row address strobe.
DMBS0
73
O
SDRAM bank select 0.
DMBS1
74
O
SDRAM bank select 1.
DB[15:0]
77-82, 85-90, 93-96
I/O
DRAM data bus.
97,100
O
SDRAM chip select.
DQM
101
O
Data input/output mask.
DSCK
102
O
Output clock to SDRAM.
DCS[1:0]#
4
SAM0462-031704
ESS Technology, Inc.
ES6028 PRODUCT BRIEF
ES6028 PIN DESCRIPTION
Table 1
ES6028 Pin Description (Continued)
Name
Pin Numbers
I/O
DCLK
105
I
Clock input to PLL.
YUV0
O
YUV pixel 0 output data.
CAMIN2
I
Camera input 2.
O
Video DAC output.
UDAC
106
Definition
Pin
114
113
108
106
Value
DAC V
DAC Y
DAC C
DAC U
0
CVBS1
Y
C
N/A
1
CVBS1
Y
C
CVBS2
2
N/A
Y
C
N/A
3
CVBS1
N/A
N/A
CVBS2
4
CVBS1
N/A
N/A
N/A
5
CVBS1
Y
Pb
Pr
6
N/A
Y
Pb
Pr
7
SYNC
G
B
R
8
CHROMA
Y
Pb
Pr
9
CVBS1
G
B
R
10
CVBS1
G
R
B
11
SYNC
G
R
B
12
N/A
Y
Pr
Pb
13
CVBS1
Y
Pr
Pb
Y: Luma component for YUV and Y/C processing.
C: Chrominance signal for Y/C processing.
U: Chrominance component signal for YUV mode.
V: Chrominance component signal for YUV mode.
YUV1
O
YUV pixel 1output data.
I
Internal voltage reference to video DAC. Bypass to ground with 0.1-µF capacitor.
O
YUV pixel 2 output data.
O
Video DAC output. Refer to description and matrix for UDAC pin 106.
O
YUV pixel 3 output data.
I
Compensation input. Bypass to ADVEE with 0.1-µF capacitor.
O
YUV pixel 4 output data.
I
DAC current adjustment resistor input.
107
VREF
YUV2
108
CDAC
YUV3
109
COMP
YUV4
110
RSET
ADVEE
111
P
Analog power for video DAC.
ADVSS
112
G
Analog ground for video DAC.
ESS Technology, Inc.
SAM0462-031704
5
ES6028 PRODUCT BRIEF
ES6028 PIN DESCRIPTION
Table 1
ES6028 Pin Description (Continued)
Name
Pin Numbers
YUV5
I/O
Definition
O
YUV pixel 5 output data.
O
Video DAC output. Refer to description and matrix for UDAC pin 106.
O
YUV pixel 6 output data.
O
Video DAC output. Refer to description and matrix for UDAC pin 106.
O
YUV pixel 7 output data.
I
Camera YUV 3.
113
YDAC
YUV6
114
VDAC
YUV7
115
CAMIN3
PCLK2XSCN
I/O
27-MHz video output pixel clock.
116
CAMIN4
I
Camera YUV 4.
PCLKQSCN
O
13.5-MHz video output pixel clock.
I
Camera YUV 5.
CAMIN5
117
AUX3[2]
I/O
Aux3 data I/O.
VSYNC#
I/O
Vertical sync, active-low.
CAMIN6
118
I
Camera YUV 6.
AUX3[1]
I/O
Aux3 data I/O.
HSYNC#
I/O
Horizontal sync, active-low.
CAMIN7
119
I
Camera YUV 7.
AUX3[0]
I/O
Aux3 data I/O.
HD[5:0]
I/O
Host data bus lines 5:0.
I/O
DVD channel data I/O.
AUX1[5:0]
I/O
Aux1 data I/O.
HD6
I/O
Host data bus line 6.
I/O
DVD channel data I/O.
I/O
Aux1 data I/O.
DCI[5:0]
122-127
DCI6
128
AUX1[6]
VFD_DOUT
I
HD7
VFD data output.
I/O
Host data bus line 7.
I/O
DVD channel data I/O.
AUX1[7]
I/O
Aux1 data I/O.
VFD_DIN
I
VFD data input.
DCI7
131
HD8
DCI_FDS#
I/O
Host data bus line 8.
I/O
DVD input sector start.
I/O
Aux2 data I/O.
132
AUX2[0]
VFD_CLK
I
HD9
VFD clock input.
I/O
Host data bus line 9.
I/O
Aux2 data I/O.
133
AUX2[1]
6
SAM0462-031704
ESS Technology, Inc.
ES6028 PRODUCT BRIEF
ES6028 PIN DESCRIPTION
Table 1
ES6028 Pin Description (Continued)
Name
Pin Numbers
I/O
Definition
I/O
Host data bus line 10.
AUX2[2]
I/O
Aux2 data I/O.
HD11
I/O
Host data bus line 11.
I/O
Aux2 data I/O.
IRQ
O
IRQ.
HD12
I/O
Host data bus line 12.
I/O
Aux2 data I/O.
HD10
134
AUX2[3]
AUX2[4]
135
136
C2PO
I
HD13
I/O
Host data bus line 13.
I/O
Aux2 data I/O.
AUX2[5]
137
SP
I
HD14
C2PO error correction flag from CD-ROM.
16550 UART serial port input.
I/O
Host data bus line 14.
AUX2[6]
I/O
Aux2 data I/O.
HD15
I/O
Host data bus line 15.
I/O
Aux2 data I/O.
140
AUX2[7]
141
IR
I
IR remote control input.
HWRQ#
O
Host write request.
O
DVD control interface request.
I/O
Aux4 data I/O.
O
Host read request.
AUX4[0]
I/O
Aux4 data I/O.
HIRQ
I/O
Host interrupt.
I/O
DVD channel data error.
I/O
Aux4 data I/O.
O
Host reset.
I/O
Aux3 data I/O.
I
Host I/O ready.
AUX3[3]
I/O
Aux3 data I/O.
HWR#
I/O
Host write.
I/O
DVD channel data clock.
AUX4[5]
I/O
Aux4 data I/O.
HRD#
O
Host read.
O
DVD channel data valid.
I/O
Aux4 data I/O.
DCI_REQ#
142
AUX4[1]
HRRQ#
143
DCI_ERR#
144
AUX4[7]
HRST#
145
AUX3[5]
HIORDY
146
DCI_CLK
DCI_ACK#
AUX4[6]
ESS Technology, Inc.
149
150
SAM0462-031704
7
ES6028 PRODUCT BRIEF
ES6028 PIN DESCRIPTION
Table 1
ES6028 Pin Description (Continued)
Name
Pin Numbers
HIOCS16#
CAMCLK
151
AUX3[4]
I/O
Definition
I
Device 16-bit data transfer.
I
Camera port pixel clock input.
I/O
Aux3 data I/O.
O
Host select 1.
I/O
Aux3 data I/O.
O
Host select 3.
I/O
Aux3 data I/O.
I/O
Host address bus.
I/O
Aux4 data I/Os.
I/O
Auxiliary port 0 (open collector).
I/O
I2C data I/O.
I/O
Auxiliary port 1 (open collector).
I/O
I2C clock I/O.
I/O
Auxiliary port.
O
I/O Write strobe (LCS1).
I/O
Auxiliary port.
O
I/O Read strobe (LCS1).
166-169
I/O
Auxiliary ports.
170
O
RISC port output enable.
173-176
O
RISC port chip select.
LD[15:0]
178-182, 185-191,
194-197
I/O
RISC port data bus.
LWRLL#
198
O
RISC port low-byte write enable.
LWRHL#
199
O
RISC port high-byte write enable.
CAMIN0
202
I
Camera YUV 0.
CAMIN1
203
I
Camera YUV 1.
HCS1FX#
152
AUX3[7]
HCS3FX#
153
AUX3[6]
HA[2:0]
154, 155, 158
AUX4[4:2]
AUX0
160
I2CDATA
AUX1
161
I2C_CLK
AUX2
162
IOW#
AUX3
165
IOR#
AUX7-4
LOE#
LCS[3:0]#
8
SAM0462-031704
ESS Technology, Inc.
ES6028 PRODUCT BRIEF
SYSTEM BLOCK DIAGRAM
SYSTEM BLOCK DIAGRAM
A sample system block diagram for the ES6028 Vibratto DVD
player board design is shown in Figure 2.
Video
TV Display
ROM/Flash
Audio
SDRAM
4/16 MB
EEPROM
DVD Drive
ES6028
Vibratto
Audio
DAC
S/PDIF
Speakers
A/V Receiver
Audio
Audio ADC
VFD
Driver
Microphone In
VFD Panel
IR Remote
Figure 2 ES6028 Vibratto System Block Diagram
ESS Technology, Inc.
SAM0462-031704
9
ES6028 PRODUCT BRIEF
ORDERING INFORMATION
ORDERING INFORMATION
Part Number
Description
Package
ES6028F
Vibratto 5.1-channel DVD, DTS, Progressive Scan and TV Encoder
208-pin PQFP
The letter F at the end of the part number identifies the package type PQFP.
Other Vibratto DVD Processors
Part Number
Description
Package
ES6008F
Vibratto 2-channel DVD and TV Encoder
208-pin PQFP
ES6018F
Vibratto 5.1-channel DVD, DTS and TV Encoder
208-pin PQFP
ES6038F
Vibratto 5.1-channel DVD, DTS, Progressive Scan, DVD-Audio and TV Encoder
208-pin PQFP
The letter F at the end of the part number identifies the package type PQFP.
ESS Technology, Inc.
48401 Fremont Blvd.
Fremont, CA 94538
Tel: (510) 492-1088
Fax: (510) 492-1898
10
http://www.esstech.com
No part of this publication may be reproduced, stored in a retrieval
system, transmitted, or translated in any form or by any means,
electronic, mechanical, manual, optical, or otherwise, without the prior
written permission of ESS Technology, Inc.
MPEG is the Moving Picture Experts Group of the ISO/IEC. References
to MPEG in this document refer to the ISO/IEC JTC1 SC29 committee
draft ISO 11172 dated January 9, 1992.
ESS Technology, Inc. makes no representations or warranties
regarding the content of this document.
Dolby is a trademark of Dolby Laboratories, Inc.
All specifications are subject to change without prior notice.
Trusurround, Trusurround XT, SRS, and (o) symbol are trademarks of
SRS Labs, Inc.
ESS Technology, Inc. assumes no responsibility for any errors
contained herein.
All other trademarks are trademarks of their respective companies and
are used for identification purposes only.
VideoDrive and Vibratto are trademarks of ESS Technology, Inc.
U.S. patents pending.
© 2004 ESS Technology, Inc.
SAM0462-031704