ETC ES6425

ES6425
Digital Media Processor 2
Product Brief
ESS Technology, Inc.
DESCRIPTION
FEATURES
The ES6425 Digital Media Processor 2 (DMP2) is a high
performance single-chip audio/video decoder for a wide
series of applications such as networked or nonnetworked/flash memory media players. This second
generation of Digital Media Processor has an enhanced
performance engine to decode MPEG-4 video at D1
resolution with state-of-the-art progressive scan
NTSC/PAL video encoder for brilliant and sharp, flickerfree output to the video display.
• Single-chip digital audio and video decoder and
At the heart of the ES6425 is the ESS proprietary
Programmable Multimedia Processor core consisting of
32-bit RISC and 64-bit DSP processors that enable
simultaneous parallel execution of system commands and
specialized multimedia decoding tasks. The ES6425
includes a memory controller which interfaces to 8-bit or
16-bit DRAM with up to 128-Mb capacity.
The ES6425 performs video processing to provide highresolution display of MPEG-1, MPEG-2, and MPEG-4
videos and JPEG photos. The integrated NTSC/PAL TVencoder provides composite, S-video, and YUV outputs.
The ES6425 includes an On-Screen-Display (OSD)
controller to provide a user friendly setup menu to enable
or modify the various audio decoding and video display
features. A CCIR656/601 digital video output port is also
present.
The ES6425 also performs audio processing for Wave,
MP3, AAC, Dolby Digital, and WMA playback along with
a 7-band graphic equalizer. The ES6425 has a multichannel audio serial port compliant to I 2 S format for
interfacing to an external audio DAC and ADC. An S/PDIF
output port is also integrated for transmitting digital audio
streams.
A 16-bit host interface present in the ES6425 connects to
many different storage solutions including Compact
Flash, Smart Media, xD-Picture Card, and IDE hard
drives. Similarly, a serial interface is built-in to interface to
SD  , xD  , MultiMediaCard  , and Memory Stick 
devices.
The ES6425 is available in an industry-standard 208-pin
Plastic Quad Flat Pack (PQFP) device package.
ESS Technology, Inc.
processor.
• MPEG-4 Advanced Simple Profile* at full screen D1 video
playback (playability is dependent on memory card
bandwidth).
• MPEG-2 video playback (playability is dependent on
memory card bandwidth).
•
•
•
•
•
•
•
•
•
•
•
MPEG-1 video playback.
Motion JPEG playback.
JPEG photo playback.
Progressive JPEG photo playback.
MP3 music playback.
WMA music playback (Microsoft license required).
Dolby Digital decode (ES6425FDF only)
AAC audio decode and playback.
ESS Music Slideshow.
S/PDIF digital audio output.
Integrated NTSC/PAL encoder with pixel adaptive deinterlacer and five 10-bit 54 MHz video DACs.
• High-quality progressive scan video output for flicker-free
video display.
• Simultaneous Composite, S-Video, and YUV outputs.
• CCIR656/601 YUV 4:2:2 output.
• On-Screen-Display controller with 3-bit blending to
provide 256 colors display.
• Integrated I2S serial port for up to 5.1 channel audio
output and stereo input.
• Direct interface for IDE devices and flash memory cards
including CF, MS, MS Pro, SD, xD, MMC, and SM.
• DRAM memory controller with interface to 8-bit or 16-bit
SDRAM for up to 16 MB of memory.
• 16-bit SRAM interface for connecting to boot EPROM or
flash memory.
• Lead-free leads using 98%-Sn/2%-Cu or 98%-Sn/2%-Bi.
SAM0529-091305
1
VEE
LA4
LA5
LA6
LA7
LA8
LA9
VSS
VCC
LA10
LA11
LA12
LA13
LA14
LA15
LA16
VSS
VEE
LA17
LA18
LA19
LA20
LA21
RESET#
TDMDX/RSEL
VSS
VEE
TDMDR
TDMCLK
TDMFS
TDMTSC#
TWS/SEL_PLL2
TSD0/SEL_PLL0
VSS
VCC
TSD1/SEL_PLL1
TSD2
NC
MCLK
TBCK
SPDIF/SEL_PLL3
NC
VSS
VCC
RSD
RWS
RBCK
CAMIN3
XIN
XOUT
AVEE
AVSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
VSS
HA1/AUX4[3]
HA0/AUX4[2]
HCS3FX3#/AUX3[6]
HCS1FX#/AUX3[7]
HIOCS16#/AUX3[4]
HRD#/AUX4[6]
HWR#/AUX4[5]
VEE
VSS
HIORDY/AUX3[3]
HRST#/AUX3[5]
HIRQ/AUX4[7]
HRRQ#/AUX4[0]/CAMIN2
HWRQ#/AUX4[1]
HD15/AUX2[7]/IR
HD14/AUX2[6]
VCC
VSS
HD13/AUX2[5]
HD12/AUX2[4]
HD11/AUX2[3]
HD10/AUX2[2]
HD9/AUX2[1]
HD8/AUX2[0]/VFD_CLK
HD7/AUX1[7]/VFD_DIN
VEE
VSS
HD6/AUX1[6]/VFD_DOUT
HD5/AUX1[5]
HD4/AUX1[4]
HD3/AUX1[3]
HD2/AUX1[2]
HD1/AUX1[1]
HD0/AUX1[0]
VCC
VSS
HSYNC#/AUX3[0]/CAMIN7
VSYNC#/AUX3[1]/CAMIN6
PCLKQSCN/AUX3[2]/CAMIN5
PCLK2XSCN/CAMIN4
YUV7/PIXOUT7
YUV6/VDAC/PIXOUT6
YUV5/YDAC/PIXOUT5
ADVSS
ADVEE
YUV4/RSET/PIXOUT4
YUV3/COMP/PIXOUT3
YUV2/CDAC/PIXOUT2
YUV1/VREF/PIXOUT1
YUV0/UDAC/PIXOUT0
DCLK
ES6425 PRODUCT BRIEF
ES6425 PINOUT DIAGRAM
ES6425 PINOUT DIAGRAM
The device pinout for the ES6425 is shown in Figure 1. The
pound symbol (#) denotes an active-low signal.
VEE
HA2/AUX4[4]
VEE
I2CDATA/AUX0
I2C_CLK/AUX1
IOW#/AUX2
VSS
VEE
IORD#/AUX3
AUX4
AUX5
AUX6
AUX7
LOE#
VSS
VCC
LCS0#/PIXOUT_CLK
LCS1#
LCS2#
LCS3#
VSS
LD0
LD1
LD2
LD3
LD4
VEE
VSS
LD5
LD6
LD7
LD8
LD9
LD10
LD11
VSS
VEE
LD12
LD13
LD14
LD15
LWRLL#
LWRHL#
VSS
VEE
CAMIN0
CAMIN1
LA0
LA1
LA2
LA3
VSS
2
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
SAM0529-091305
ES6425
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
VEE
VSS
DSCK
DQM
DCS0#
VEE
VSS
DCS1#
DB15
DB14
DB13
DB12
VEE
VSS
DB11
DB10
DB9
DB8
DB7
DB6
VSS
VCC
DB5
DB4
DB3
DB2
DB1
DB0
VSS
VEE
DMBS1
DMBS0
DRAS#
DWE#
DOE#/DSCK_EN
DCAS#
VEE
VSS
DMA11
DMA10
DMA9
DMA8
DMA7
DMA6
VSS
VEE
DMA5
DMA4
DMA3
DMA2
DMA1
DMA0
Figure 1 ES6425 Device Pinout
Note: (*) MPEG-4 Advanced Simple Profile without hardware Q-PEL and Global Motion Compensation (GMC).
ESS Technology, Inc.
ES6425 PRODUCT BRIEF
ES6425 PIN DESCRIPTION
ES6425 PIN DESCRIPTION
Table 1 lists the pin descriptions for the ES6425. The
pound symbol (#) denotes an active-low signal.
Table 1
ES6425 Pin Description
Name
Pin Numbers
I/O
1,18, 27, 59, 68, 75,
92, 99, 104, 130,
148, 157, 159, 164,
183, 193, 201
P
I/O power supply.
2-7, 10-16, 19-23,
204-207
O
RISC port address bus.
VSS
8, 17, 26, 34, 43,
60, 67, 76, 84, 91,
98, 103, 120, 129,
138, 147, 156, 163,
171, 177, 184, 192,
200, 208
G
Ground.
VCC
9, 35, 44, 83, 121,
139, 172
I
Core power supply.
VEE
LA[21:0]
RESET#
24
TDMDX
RSEL
Definition
I
Reset input (active-low); (5V tolerant input).
O
TDM transmit data.
I
LCS3 ROM Boot Data Width Select. Strapped to VCC or ground via 4.7-kΩ
resistor; read during reset.
25
RSEL
Selection
0
16-bit ROM
1
8-bit ROM
TDMDR
28
I
TDM receive data; (5V tolerant input).
TDMCLK
29
I
TDM clock; (5V tolerant input).
TDMFS
30
I
TDM frame sync; (5V tolerant input).
TDMTSC#
31
TWS
O
TDM output enable (active-low).
O
Audio transmit frame sync.
System and DSCK output clock frequency selection is made at the rising edge of
RESET#. The matrix below lists the available clock frequencies and their
respective PLL bit settings. Pull up to VCC via 4.7-kΩ resistor for proper
operation; read during reset.
SEL_PLL2
TSD0
SEL_PLL0
ESS Technology, Inc.
32
33
I
SEL_PLL2
SEL_PLL1
SEL_PLL0
Clock Type
0
0
0
DCLK x 4.5
0
0
1
DCLK x 5.0
0
1
0
Bypass mode
0
1
1
DCLK x 4.0
1
0
0
DCLK x 4.25
1
0
1
DCLK x 4.75
1
1
0
DCLK x 5.5
1
1
1
DCLK x 6.0
O
Audio transmit serial data output 0.
I
Pull up to VCC via 4.7-kΩ resistor for proper operation; read during reset.
SAM0529-091305
3
ES6425 PRODUCT BRIEF
ES6425 PIN DESCRIPTION
Table 1
ES6425 Pin Description (Continued)
Name
TSD1
SEL_PLL1
Pin Numbers
36
I/O
Definition
O
Audio transmit serial data output 1.
I
Pull up to VCC via 4.7-kΩ resistor for proper operation; read during reset.
TSD2
37
O
Audio transmit serial data output 2. This pin must be pulled down to VSS via a
4.7-kΩ resistor for proper operation.
MCLK
39
I/O
Audio master clock for audio DAC.
TBCK
40
I/O
Audio transmit bit clock. TBCK is an input during reset and subsequently is
programmed as an output via the AUDIOXMT register (addr 0x2000D00Ch, bit 4).
O
S/PDIF output.
I
Pull down to ground via 4.7-kΩ resistor for proper operation; read during reset.
SPDIF
SEL_PLL3
NC
41
38, 42
—
RSD
45
I
Audio receive serial data; (5V tolerant input).
RWS
46
I
Audio receive frame sync; (5V tolerant input).
RBCK
47
I
Audio receive bit clock; (5V tolerant input).
CAMIN3
48
I
Camera and YUV input 3.
XIN
49
I
27-MHz crystal input.
XOUT
50
O
27-MHz crystal output.
AVEE
51
P
Analog power for PLL.
AVSS
DMA[11:0]
DCAS#
DOE#
DSCK_EN
No connect.
52
G
Analog ground for PLL.
53-58, 61-66
O
DRAM address bus.
69
O
DRAM column address strobe (active-low).
O
DRAM output enable (active-low).
70
O
DRAM clock enable.
DWE#
71
O
DRAM write enable (active-low).
DRAS#
72
O
DRAM row address strobe (active-low).
DMBS0
73
O
SDRAM bank select 0.
DMBS1
74
O
SDRAM bank select 1.
DB[15:0]
77-82, 85-90, 93-96
I/O
DRAM data bus.
97,100
O
SDRAM chip select (active-low).
DQM
101
O
Data input/output mask.
DSCK
102
O
Output clock to SDRAM.
DCLK
105
I
Clock input to PLL; (5V tolerant input).
DCS[1:0]#
4
SAM0529-091305
ESS Technology, Inc.
ES6425 PRODUCT BRIEF
ES6425 PIN DESCRIPTION
Table 1
ES6425 Pin Description (Continued)
Name
UDAC
Pin Numbers
I/O
Definition
O
Video DAC output:
106
Value
DAC V
(pin 114)
DAC Y
(pin 113)
DAC C
(pin 108)
DAC U
(pin 106)
0
CVBS1
1
CVBS1
Y
N/A
C
Y
CVBS2
C
2
N/A
Y
N/A
C
3
CVBS1
N/A
CVBS2
N/A
4
CVBS1
N/A
N/A
N/A
5
CVBS1
Y
Pr
Pb
6
N/A
Y
Pr
Pb
7
SYNC
G
R
B
8
CHROMA
Y
Pr
Pb
9
CVBS1
G
R
B
10
CVBS1
G
B
R
11
SYNC
G
B
R
12
N/A
Y
Pb
Pr
13
CVBS1
Y
Pb
Pr
Y: Luma component for YUV and Y/C processing.
C: Chrominance signal for Y/C processing.
U: Chrominance component signal for YUV mode.
V: Chrominance component signal for YUV mode.
YUV0
O
YUV pixel 0 output data.
PIXOUT0
O
CCIR656 output pixel 0.
VREF
I
Internal voltage reference to DAC. Bypass to ground with 0.1-µF capacitor.
O
YUV pixel 1 output data.
YUV1
107
PIXOUT1
O
CCIR656 output pixel 1.
CDAC
O
Chrominance signal for Y/C processing display.
O
YUV pixel 2 output data.
O
CCIR656 output pixel 2.
YUV2
108
PIXOUT2
COMP
I
Compensation input. Bypass to ADVEE with 0.1-µF capacitor.
O
YUV pixel 3 output data.
PIXOUT3
O
CCIR656 output pixel 3.
RSET
I
DAC current adjustment resistor input.
O
YUV pixel 4 output data.
O
CCIR656 output pixel 4.
YUV3
YUV4
109
110
PIXOUT4
ADVEE
111
P
Analog power.
ADVSS
112
G
Analog ground for video DAC.
O
Luma component for Y/C processing display.
O
YUV pixel 5 output data.
PIXOUT5
O
CCIR656 output pixel 5.
VDAC
O
Video DAC output. Refer to description and matrix for UDAC pin 106.
O
YUV pixel 6 output data.
O
CCIR656 output pixel 6.
YDAC
YUV5
YUV6
PIXOUT6
ESS Technology, Inc.
113
114
SAM0529-091305
5
ES6425 PRODUCT BRIEF
ES6425 PIN DESCRIPTION
Table 1
ES6425 Pin Description (Continued)
Name
Pin Numbers
YUV7
115
PIXOUT7
PCLK2XSCN
CAMIN4
116
PCLKQSCN
AUX3[2]
117
I/O
Definition
O
YUV pixel 7 output data.
O
CCIR656 output pixel 7.
I/O
27-MHz video pixel clock.
I
Camera and YUV input 4.
O
13.5-MHz video output pixel clock.
I/O
Aux3 data I/O; (5V tolerant input).
CAMIN5
I
VSYNC#
I/O
AUX3[1]
118
I/O
Camera and YUV input 5
Vertical sync (active-low); (5V tolerant input).
Aux3 data I/O; (5V tolerant input).
CAMIN6
I
HSYNC#
I/O
Horizontal sync (active-low); (5V tolerant input).
I/O
Aux3 data I/O; (5V tolerant input).
AUX3[0]
119
Camera and YUV input 6.
CAMIN7
I
HD[5:0]
I/O
Host data bus; (5V tolerant input).
I/O
Aux1 data I/O; (5V tolerant input).
I/O
Host data bus; (5V tolerant input).
AUX1[5:0]
122-127
HD6
AUX1[6]
I/O
Aux1 data I/O; (5V tolerant input).
VFD_DOUT
O
VFD data output.
HD7
I/O
Host data bus; (5V tolerant input).
I/O
Aux1 data I/O; (5V tolerant input).
AUX1[7]
128
Camera and YUV input 7.
131
VFD_DIN
I
HD8
AUX2[0]
132
VFD_CLK
HD9
AUX2[1]
HD10
AUX2[2]
HD11
AUX2[3]
HD12
AUX2[4]
HD13
AUX2[5]
HD14
AUX2[6]
134
135
136
137
140
HD15
AUX2[7]
141
IR
HWRQ#
AUX4[1]
6
Host data bus; (5V tolerant input).
I/O
Aux2 data I/O; (5V tolerant input).
I
133
142
SAM0529-091305
VFD data input.
I/O
VFD clock.
I/O
Host data bus; (5V tolerant input).
I/O
Aux2 data I/O; (5V tolerant input).
I/O
Host data bus; (5V tolerant input).
I/O
Aux2 data I/O; (5V tolerant input).
I/O
Host data bus; (5V tolerant input).
I/O
Aux2 data I/O; (5V tolerant input).
I/O
Host data bus; (5V tolerant input).
I/O
Aux2 data I/O; (5V tolerant input).
I/O
Host data bus; (5V tolerant input).
I/O
Aux2 data I/O; (5V tolerant input).
I/O
Host data bus; (5V tolerant input).
I/O
Aux2 data I/O; (5V tolerant input).
I/O
Host data bus; (5V tolerant input).
I/O
Aux2 data I/O 7; (5V tolerant input).
I
IR remote control; (5V tolerant input).
O
Host write request (active-low).
I/O
Aux4 data I/O 1; (5V tolerant input).
ESS Technology, Inc.
ES6425 PRODUCT BRIEF
ES6425 PIN DESCRIPTION
Table 1
ES6425 Pin Description (Continued)
Name
Pin Numbers
HRRQ#
AUX4[0]
143
I/O
Definition
O
Host read request (active-low).
I/O
Aux4 data I/O 0; (5V tolerant input).
CAMIN2
I
Camera and YUV input 2.
HIRQ
O
Host interrupt.
I/O
Aux4 data I/O 7; (5V tolerant input).
O
Host reset (active-low).
144
AUX4[7]
HRST#
145
AUX3[5]
HIORDY
146
AUX3[3]
HWR#
149
AUX4[5]
HRD#
150
AUX4[6]
HIOCS16#
I/O
I
I/O
Aux3 data I/O 3; (5V tolerant input).
O
Host write (active-low).
I/O
Aux4 data I/O 5; (5V tolerant input).
O
Host read (active-low).
I/O
Aux4 data I/O 6; (5V tolerant input).
I
AUX3[4]
151
CAMCLK
HCS1FX#
152
AUX3[7]
HCS3FX#
153
AUX3[6]
HA[2:0]
154, 155, 158
AUX4[4:2]
AUX0
160
I2CDATA
AUX1
161
I2C_CLK
IOW#
162
AUX2
IOR#
165
AUX3
AUX4-7
LOE#
LCS0#
LCS[3:1]#
I/O
Device 16 bit data transfer (active-low).
Aux3 data I/O 4; (5V tolerant input).
I
Camera and YUV port pixel clock.
O
Host select 1 (active-low).
I/O
Aux3 data I/O 7; (5V tolerant input).
O
Host select 3 (active-low).
I/O
Aux3 data I/O 6; (5V tolerant input).
I/O
Host address bus.
I/O
Aux4 data I/Os 2, 3, and 4; (5V tolerant input).
I/O
Auxiliary port 0 (open collector); (5V tolerant input).
I/O
I2C data I/O; (5V tolerant input).
I/O
Auxiliary port 1 (open collector); (5V tolerant input).
I/O
I2C clock I/O; (5V tolerant input).
O
I/O write strobe (LCS1) (active-low).
I/O
Auxiliary port 2; (5V tolerant input).
O
I/O read strobe (LCS1) (active-low).
I/O
Auxiliary port 3; (5V tolerant input).
166-169
I/O
Auxiliary ports 4-7; (5V tolerant input).
170
O
RISC port output enable (active-low).
O
RISC port chip select 0 (active-low).
O
CCIR656 output pixel clock.
173
PIXOUT_CLK
Aux3 data I/O 5; (5V tolerant input).
Host I/O ready.
174-176
O
RISC port chip select [3:1] (active-low).
LD[15:0]
178-182, 185-191,
194-197
I/O
RISC port data bus; (5V tolerant input).
LWRLL#
198
O
RISC port low-byte write enable (active-low).
LWRHL#
199
O
RISC port high-byte write enable (active-low).
CAMIN0
202
I
Camera and YUV input 0.
CAMIN1
203
I
Camera and YUV input 1.
ESS Technology, Inc.
SAM0529-091305
7
ES6425 PRODUCT BRIEF
SYSTEM BLOCK DIAGRAM
SYSTEM BLOCK DIAGRAM
A sample system block diagram for the ES6425 board design is
shown in Figure 2.
Video
ROM/Flash
(1 MB)
ADC
SDRAM
(4/16 MB)
ES6425
DMP2
Audio
Audio
DAC
Speakers
S/PDIF
A/V Receiver
EEPROM
IR Remote
IDE HDD
Memory Cards
Figure 2 ES645 System Block Diagram
ORDERING INFORMATION
Part Number
Description
Package
ES6425FF
Digital Media Processor 2 with lead-free leads.
208-pin PQFP
ES6425FDF
Digital Media Processor 2 with Dolby Digital support and lead-free leads.
208-pin PQFP
The letter F at the end of the part number identifies the package type PQFP.
The second letter F at the end of the part number indicates lead-free leads with the device.
No part of this publication may be reproduced, stored in a retrieval
system, transmitted, or translated in any form or by any means,
electronic, mechanical, manual, optical, or otherwise, without the prior
written permission of ESS Technology, Inc.
ESS Technology, Inc.
48401 Fremont Blvd.
Fremont, CA 94538
Tel: (510) 492-1088
Fax: (510) 492-1898
8
http://www.esstech.com
ESS Technology, Inc. makes no representations or warranties
regarding the content of this document.
All specifications are subject to change without prior notice.
ESS Technology, Inc. assumes no responsibility for any errors
contained herein.
U.S. patents pending.
© 2005 ESS Technology, Inc.
MPEG is the Moving Picture Experts Group of the ISO/IEC. References
to MPEG in this document refer to the ISO/IEC JTC1 SC29 committee
draft ISO 11172 dated January 9, 1992.
Vibratto, SmartBright, SmartLogo, SmartColor, and Music Slideshow
are trademarks of ESS Technology, Inc.
Dolby is a trademark of Dolby Laboratories, Inc.
Trusurround, Trusurround XT, SRS, and (o) symbol are trademarks of
SRS Labs., Inc.
All other trademarks are trademarks of their respective companies and
are used for identification purposes only.
SAM0529-091305