MCS7840 USB-2.0 to Four Serial Ports Features • USB-2.0 Device Controller • On-Chip USB-2.0 PHY • On-Chip Voltage Regulators • Four 16c450/16c550 compatible UARTs • Supports SIR IrDA Mode on any/all ports • Supports RS-232, RS-485 and RS-422 Serial Ports • 5, 6, 7 & 8-bit Serial Data support • Hardware and Software Flow Control • Serial Port speeds from 50 bps to 6 Mbps • Custom BAUD Rates supported through external clock and/or by programming the internal PLL • On-Chip 512-Byte FIFOs for upstream and downstream data transfers for each Serial Port • Supports Remote Wakeup and Power Management features • Serial Port Transceiver Shut-Down support • Two-Wire I2C Interface for EEPROM • EEPROM read/write through USB • iSerial feature support with EEPROM • One Bi-directional multi-function GPIO • On-Chip buffers for Serial Port signals to operate without external Transceivers over short cable lengths • Bus-Powered Device Applications • Serial Attached Devices • Modems, Serial Mouse, Generic Serial Devices • Serial-Port Server • Data Acquisition System • POS Terminal & Industrial PC Application Note • AN-7840 Evaluation Board • MCS7840-EVB Package • 64-pin LQFP Package Driver Support • Windows (98SE / ME / 2000 / XP / 2003 Server) • Linux Kernel 2.6.5 and above • MAC 10.2 & above • Windows CE5.0 • Windows Vista Utility Support • Windows based EEPROM Tool • Mass Production Utility General Description The MCS7840 is a USB-2.0 to Quad-Serial Port device. It has been developed to connect a wide range of standard serial devices to a USB host. The MCS7840 has a USB Device Controller connected to four (4) individual UARTs. Support for the following serial communication programs is included: HyperTerminal, PComm, Windows direct connection, Windows dial-up connection through modem, Networking over IrDA and Windows direct connection over IrDA, Minicom. Ordering Information Commercial Grade (0 °C to +70 °C) MCS7840CV 64-LQFP RoHS MosChip Semiconductor ♦ 3335 Kifer Rd, Santa Clara, CA 95051 ♦ Tel (408) 737-7141 ♦ Fax (408) 737-7708 MCS7840 USB-2.0 to Four Serial Ports Block Diagram SCL SDA Interrupt-In Block 2 I C EEPROM Controller Wake-Up Block DTR Serial Port x4 RTS TXD Tx Buffer DP Bulk In FIFOs DM XTAL OUT RXD USB-2.0 PHY USB-2.0 Device Controller Rx Buffer Bridge DCD CTS RI Bulk Out FIFOs XTAL IN DSR VSPEC_CMD_ Processor Clock Recovery Resets BAUD Clock Generator x4 Ext_Clock Page 2 PLL Rev. 1.2 MCS7840 USB-2.0 to Four Serial Ports 49 GNDK 50 EXT_CLOCK 51 Vcc3IO 52 RI_2_N 53 DSR_2_N 54 DCD_2_N 55 CTS_2_N 56 TXD_3 57 DTR_3_N 58 RTS_3_N 59 RXD_3 60 RI_3_N 61 DSR_3_N 62 DCD_3_N 63 CTS_3_N 64 VccK Pin-Out Diagram GNDK 1 48 RXD_2 USB_XSCI 2 47 RTS_2_N USB_XSCO 3 46 DTR_2_N VccA 4 45 TXD_2 GNDA 5 44 EE_SDA USB_RREF 6 43 EE_SCL USB_DM 7 42 RESET USB_DP 8 41 GPIO VccA 9 MCS7840CV 40 VCC3IO 39 VccK GNDA 10 38 GND18A_PLL VccK 11 37 Vcc18A_PLL TEST_MODE 12 36 REG02_V18 TXD_4 13 DTR_4_N 14 35 GND5A RTS_4_N 15 34 VCC5A RXD_4 16 Rev. 1.2 SHTD_1_N 32 CTS_1_N 31 DCD_1_N 30 DSR_1_N 29 Vcc3IO 28 GNDK 27 VccK 26 RI_1_N 25 RXD_1 24 RTS_1_N 23 DTR_1_N 22 TXD_1 21 CTS_4_N 20 DCD_4_N 19 DSR_4_N 18 RI_4_N 17 33 REG06_VCC33 Page 3 MCS7840 USB-2.0 to Four Serial Ports Pin Assignments Pin Name Type Functional Description 1 GNDK Power 2 USB_XSCI Input 3 USB_XSCO Output Crystal Oscillator Output 4 VccA Power Power Pin (A3V3) 5 GNDA Power Analog Ground 6 USB_RREF Input 7 USB_DM I/O USB D- Signal 8 USB_DP I/O USB D+ Signal 9 VccA Power Power Pin (A3V3) 10 GNDA Power Analog Ground 11 VccK Power Power Pin (1.8V) Core Ground Crystal Oscillator Input External Reference Resistor (12.1 KΩ, 1%) Connect resistor to Analog GND. 12 TEST_MODE Input Test Mode Pin, (active high). Default = Low (0) When TEST_MODE = 1, PLL, Core, and SCAN/BIST/ Memory BIST testing can be performed. Set TEST_MODE = 0 for normal operation. 13 TXD_4 Output Serial Port 4 Transmit Data out to transceiver or IrDA data out to IR LED 14 DTR_4_N Output Serial Port 4 Data Terminal Ready (in serial protocol), active low. 15 RTS_4_N Output Serial Port 4 Request To Send (in serial protocol), active low. 16 RXD_4 Input Serial Port 4 Serial Receive Data in from transceiver or IrDA data in from IrDA detector. 17 RI_4_N Input Serial Port 4 Ring Indicator, active low 18 DSR_4_N Input Serial Port 4 Data Set Ready (in serial protocol), active low 19 DCD_4_N Input Serial Port 4 Data Carrier Detect (in serial protocol), active low 20 CTS_4_N Input Serial Port 4 Clear To Send (in serial protocol), active low 21 TXD_1 Output Serial Port 1 Transmit Data out to transceiver, or IrDA data out to IR LED 22 DTR_1_N Output Serial Port 1 Data Terminal Ready (in serial protocol), active low. Page 4 Rev. 1.2 MCS7840 USB-2.0 to Four Serial Ports Rev. Pin Name Type 23 RTS_1_N Output 24 RXD_1 Input Serial Port 1 Serial Receive Data in from transceiver, or IrDA data in from IrDA detector. 25 RI_1_N Input Serial Port 1 Ring Indicator, active low. 26 VccK Power Power Pin (1.8V) 27 GNDK Power Core Ground 28 Vcc3IO Power Power Pin (D3V3) 29 DSR_1_N Input Serial Port 1 Data Set Ready (in serial protocol), active low 30 DCD_1_N Input Serial Port 1 Data Carrier Detect (in serial protocol), active low 31 CTS_1_N Input Serial Port 1 Clear To Send (in serial protocol), active low 32 SHTD_1_N Output Shut Down External Serial Transceiver during normal operation, active low by default, can be configured active high by using DCR setting. 33 REG06_VCC33 Power Power Pin (3.3V OUTPUT) 34 Vcc5A Power Power Pin (5V INPUT) 35 GND5A Power Ground Pin for 5V Input 36 REG02_V18 Power Power Pin (1.8V OUTPUT) 37 Vcc18A_PLL Power PLL Power (1.8V) 38 GND18A_PLL Power PLL Ground 39 VccK Power Power Pin (1.8V) 40 VCC3IO Power Power pin D3V3. 41 GPIO I/O 42 RESET I 43 EE_SCL I/O 2-Wire EEPROM Clock. Default = High (1) 44 EE_SDA I/O 2-Wire EEPROM Data in/out. Default = High (1) 45 TXD_2 Output Serial Port 2 Transmit Data out to transceiver, or IrDA data out to IR LED 46 DTR_2_N Output Serial Port 2 Data Terminal Ready (in serial protocol), active low. 1.2 Functional Description Serial Port 1 Request To Send (in serial protocol), active low. GPIO_MODE - Bidirectional GPIO bit. The direction (Input or Output) is controlled by the DCR for Serial Port #1. Power-On Reset signal (active high). Page 5 MCS7840 USB-2.0 to Four Serial Ports Pin Name Type 47 RTS_2_N Output 48 RXD_2 Input 49 GNDK Power Functional Description Serial Port 2 Request To Send (in serial protocol), active low. Serial Port 2 Serial Receive Data in from transceiver or IrDA data in from IrDA detector. Core Ground. Input Clock from external world. In normal operation mode, clock can be supplied to serial ports and used for custom BAUD Rate of user’s choice. In test mode, clock will be the test clock input from external world. 50 EXT_CLOCK Input 51 Vcc3IO Power 52 RI_2_N Input Serial Port 2 Ring Indicator, active low. 53 DSR_2_N Input Serial Port 2 Data Set Ready (in serial protocol), active low. 54 DCD_2_N Input Serial Port 2 Data Carrier Detect (in serial protocol), active low. 55 CTS_2_N Input Serial Port 2 Clear To Send (in serial protocol), active low. 56 TXD_3 Output Serial Port 3 Transmit Data out to transceiver, or IrDA data out to IR LED. 57 DTR_3_N Output Serial Port 3 Data Terminal Ready (in serial protocol), active low. 58 RTS_3_N Output Serial Port 3 Request To Send (in serial protocol), active low. 59 RXD_3 Input Serial Port 3 Serial Receive Data in from transceiver, or IrDA data in from IrDA detector. 60 RI_3_N Input Serial Port 3 Ring Indicator, active low. 61 DSR_3_N Input Serial Port 3 Data Set Ready (in serial protocol), active low. 62 DCD_3_N Input Serial Port 3 Data Carrier Detect (in serial protocol), active low. 63 CTS_3_N Input Serial Port 3 Clear To Send (in serial protocol), active low. 64 VccK Power Page 6 Power Pin (D3V3). Power Pin (1.8V) Rev. 1.2 MCS7840 USB-2.0 to Four Serial Ports Functional Block Descriptions Internal Regulators Interrupt-In Block An internal DC-DC Regulator is provided to convert 5V to 1.8V for Core Logic. An additional regulator is provided to convert the 5V input to 3.3V for I/O functions. These regulators eliminate the need for external voltage sources. The Interrupt-In controller block gives the status of the serial port interrupt registers to the USB-2.0 Device Controller. The USB host controller periodically polls the interrupt endpoint and reads the status of the interrupts. Wakeup Block USB-2.0 PHY This is the physical layer of the USB interface. The USB-2.0 PHY communicates with the USB-2.0 Device Controller logic through a UTMI interface to send/receive data on the USB bus. USB-2.0 Device Controller The USB-2.0 Device Controller interfaces to the internal bridge and communicates with the serial ports through the bridge logic. The device controller logic is connected to a physical layer USB-2.0 PHY which provides the USB bus interface for the chip. The device controller responds to standard as well as vendor specific requests from USB-2.0 and USB-1.1 Hosts. Bridge The bridge logic controls traffic between the USB-2.0 Device Controller and the Serial Port Controllers. The bridge logic has synchronous RAM memories with pingpong FIFO control logic to buffer data in either direction (Bulk-In and Bulk-Out) and send it to the other side without loss. Control logic prevents overflow or underflow conditions in the memory. The Wakeup block is used for remote wakeup control. The USB host can suspend operation of the device. The remote wakeup block checks for activity on the serial port pins, and if information is available, it issues a remote wakeup request to the USB-2.0 Device Controller. The Device Controller in turn requests a remote wakeup by the external host. The host issues the “Resume Signaling” command to the device, which then resumes normal operation. I2C EEPROM Controller The I2C EEPROM Controller interfaces to an external EEPROM and retrieves information necessary for serial port settings, Product-IDs, Vendor-IDs and other control information. The EEPROM controller logic communicates with the USB-2.0 Device Controller block which uses the information from the external EEPROM. Clock Generation and Resets The Clock Generation logic is used to generate the clocks for the various BAUD rates supported by the device. The Resets block has logic for synchronous de-assertion and asynchronous assertion of Resets in the respective clock domains to various blocks. UART / Serial Port Controllers The Serial Port Controllers are linked to the bridge and send/receive data from the bridge interface. Each serial port controller has register logic controlling BAUD rates (50 bps – 6 Mbps), stop-bits, and parity bit settings. Each serial port has synchronous RAM memories acting as transmit and receive FIFOs to buffer outgoing and incoming data. This block has registers for interrupts, line status, and line control features which can be accessed by software. The Serial Port Controllers can interface to external RS-232 / RS-422 / RS-485 transceivers. Vendor Specific Command Processor The bridge logic interfaces to a vendor specific command processor block containing commands/register settings (BAUD settings etc.) which are specific to this device. Rev. 1.2 BAUD Clock Generators The BAUD Clock Generator block generates clocks for each of the Serial Port Controllers depending on the BAUD settings from the host. A source clock is generated from the Clock Recovery block which is further divided or used as is by the BAUD Clock Generator logic depending on the BAUD settings. PLL Clock Generator The PLL generates a master clock which the other blocks use to generate the various BAUD rates. The PLL supports a wide range of clock inputs to support industrial standard serial port bit rates, as well as custom BAUD rates. Page 7 MCS7840 USB-2.0 to Four Serial Ports UART Functional Description Overview The UARTs are high performance serial ports that comply with the 16c550 specification. All UARTs are similar in operation and function, and are described in this section. The function of a single UART is described below. Operation Modes The UARTs are backward compatible with 16c450 and 16c550 devices. The operation of the port depends upon the mode settings, which are described throughout the rest of this section. The modes, conditions and corresponding FIFO depth are tabulated below. UART Mode FIFO Size FCR[0] 450 1 0 550 16 1 450 Mode After the hardware reset, bit-0 of the FIFO Control Register (FCR) is cleared, and the UART is compatible with the 16c450 mode of operation. 550 Mode After the hardware reset, writing a 1 to FCR[0] will increase the FIFO size to 16, providing compatibility with 16c550 devices. The transmitter and receiver FIFOs (referred to as the “Transmitter Holding Register” and “Receiver Holding Register” respectively) have a depth of one. In 16c550 mode, the device has the following features: • RTS/CTS hardware flow control or DSR/DTR hardware flow control • Infrared IrDA format transmit & receive mode • Deeper (16-Byte) FIFOs This mode of operation is known as “Byte Mode”. Page 8 Rev. 1.2 MCS7840 USB-2.0 to Four Serial Ports UART Register-Set and Register Descriptions The UART has 10 registers, but only three address lines to access those registers. The mapping of the registers is dependent upon the Line Control Register (LCR). LCR[7] enables the Divider Latch Registers (DLL & DLM). The following table gives the various UART registers and their offsets. Register Offset R/W Bit-7 Name Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 THR 0 W Data to be transmitted ( Transmitter Holding Register) RHR 0 R Data to be received (Receiver Holding Register) Sleep Mode IER 1 R/W Reserved FCR 2 W RHR Trigger Level Reserved ISR 2 R FIFOs Enabled Reserved LCR 3 R/W DLE MCR 4 R/W LSR 5 MSR SPR Tx Break Modem Int Mask Rx Stat Int Mask Tx Rdy Int Mask Rx Rdy Int Mask Reserved Flush THR Flush RHR FIFO Enable Interrupt Pending Interrupt Priority Force Parity Odd/Even Parity DTR – DSR/ DCD Flow Control RTS/CTS Flow Control Loop R Data Tx Error Empty THR Empty Rx Break Framing Error 6 R DCD DSR CTS ΔDCD 7 R/W RI Bit-0 Parity Enable Stop Bits Unused Data Length RTS DTR Parity Error Overrun Error Rx Rdy Teri ΔDSR ΔCTS Scratch Pad Register Additional standard registers - these are accessed when LCR[7] = 1 Rev. DLL 0 R/W Divisor Latch bits[7:0] DLM 1 R/W Divisor Latch bits[15:8] 1.2 Page 9 MCS7840 USB-2.0 to Four Serial Ports Transmitter Holding Register & Receiver Holding Register (THR & RHR): Data is written into the bottom of the THR queue & read from the top of the RHR queue completely asynchronously to the operation of the transmitter & receiver. The size of the FIFOs is dependent upon the setting of the FCR register. Data written to the THR when it is full, is lost. Data read from the RHR when it is empty, is invalid. The empty and full status of the FIFOs is indicated in the Line Status Register. Register: THR Description: Data to be transmitted Offset: 0 Permissions: Write Only Access Condition: LCR[7] = 0 Default Value: (unknown) – based on memory Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0] Bit[2] Bit[1] Bit[0] Data to be transmitted Register: RHR Description: Data to be received Offset: 0 Permissions: Read Only Access Condition: LCR[7] = 0 Default Value: (unknown) – based on memory Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Data to be received Page 10 Rev. 1.2 MCS7840 USB-2.0 to Four Serial Ports Interrupt Enable Register (IER): Serial channel interrupts are enabled using the Interrupt Enable Register (IER). Register: IER Description: Interrupt Enable Register Offset: 1 Permissions: Read/Write Access Condition: LCR[7] = 0 Default Value: 0x0C Bit[7] Bit[6] Bit[5] Reserved Rev. 1.2 Bit[4] Bit[3] Bit[2] Bit[1] Bit[0] Sleep Mode Modem Int Mask Rx Stat Int Mask Tx Rdy Int Mask Rx Rdy Int Mask Bit Description Operation 0 Rx Rdy Interrupt Mask Logic 0: Disable the Receiver Ready Interrupt Logic 1: Enable the Receiver Ready Interrupt 1 Tx Rdy Interrupt Mask Logic 0: Disable the Transmitter Ready Interrupt Logic 1: Enable the Transmitter Ready Interrupt 2 Rx Stat Interrupt Mask Logic 0: Disable the Receiver Status Interrupt (Normal Mode) Logic 1: Enable the Receiver Status Interrupt (Normal Mode) 3 Modem Interrupt Mask Logic 0: Disable the Modem Status Interrupt Logic 1: Enable the Modem Status Interrupt 4 Sleep Mode [7:5] Reserved Logic 0: Disable Sleep Mode Logic 1: Enable Sleep Mode where by the internal clock of the channel is switched OFF Reserved Page 11 MCS7840 USB-2.0 to Four Serial Ports FIFO Control Register (FCR): The FCR controls the UART behavior in various modes. Register: FCR Description: FIFO Control Register Offset: 2 Permissions: Write Access Condition: Default Value: 0x00 Bit[7] Bit[6] Bit[5] RHR Trigger Level Bit[4] Reserved Bit Description 0 Enable FIFO Mode Bit[3] Bit[2] Bit[1] Bit[0] Reserved Flush THR Flush RHR Enable FIFOs Operation Logic 0: Byte Mode Logic 1: FIFO Mode 1 Flush RHR Logic 0: No change Logic 1: Flushes the contents of RHR, This is operative only in FIFO mode. The RHR is automatically flushed whenever changing between Byte Mode and FIFO Mode. The bit will return to zero after clearing the FIFO. 2 Flush THR Logic 0: No change Logic 1: Flushes the content of the THR, in the same manner as FCR[1] does the RHR 3 Reserved Reserved [5:4] Reserved Reserved [7:6] RHR Trigger Level See Table Below In 550 Mode, the receiver FIFO trigger levels are defined by FCR[7:6]. The interrupt trigger level & flow control trigger level where appropriate are defined by L2 in the table. FCR[7:6] 550 Mode (FIFO = 16) L1 L2 2’b00 1 1 L1 defines a lower flow control trigger level. The two trigger levels used together introduce a hysteresis element into the hardware RTS/CTS flow control. 2’b01 1 4 2’b10 1 8 In Byte Mode (450 Mode) trigger levels are all set to 1. 2’b11 1 14 Page 12 Rev. 1.2 MCS7840 USB-2.0 to Four Serial Ports Interrupt Status Register (ISR): The source of the highest priority pending interrupt is indicated by the contents of the Interrupt Status Register. There are five sources of interrupts and four levels of priority (1 is the highest) as tabulated below: Register: ISR Description: Interrupt Status Register Offset: 2 Permissions: Read Access Condition: Default Value: 0x00 Bit[7] Bit[6] Bit[5] FIFOs Enabled Interrupt Source and Priority Table Bit[4] Interrupt Priority (Enhanced Mode) Bit[3] Bit[2] Bit[1] Bit[0] Interrupt Priority (All Modes) Interrupt Pending Priority Level Interrupt Source ISR[5:0] - No interrupt pending 6’b000001 1 Receiver Status Error or address bit detected in 9-bit mode 6’b000110 2a Receiver Data Available 6’b000100 2b Receiver Time-Out 6’b001100 3 Transmitter THR Empty 6’b000010 4 Modem Status Change 6’b000000 Note: ISR[0] indicates whether any interrupt is pending Rev. 1.2 Page 13 MCS7840 USB-2.0 to Four Serial Ports Line Control Register (LCR): The LCR specifies the data format that is common to both transmitter and receiver. Register: LCR Description: Line Control Register Offset: 3 Permissions: Read/Write Access Condition: Default Value: 0x00 Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] DLE TX Break Force Parity Odd/Even Parity Parity Enable LCR[1:0] Data Length of serial characters. LCR[2] Number of Stop-Bits per serial character. LCR[5:3] Parity Type The selected parity type will be generated during transmission and checked by the receiver, which may produce a parity error as a result. In 9-bit mode parity is disabled and LCR[5:3] are ignored. LCR[6] LCR[7] Page 14 Transmission Break Logic 0: Transmission Break Disabled. Logic 1: Forces the transmitter data output SOUT low to alert the communications channel, or sends zeroes in IrDA mode. Divisor Latch Enable Logic 0: Accesses to DLL and DLM registers disabled. Logic 1: Accesses to DLL and DLM registers enabled. Bit[2] Bit[1] Bit[0] Number of Stop-Bits Data Length LCR[1:0] Data Length 2’b00 5 bits 2’b01 6 bits 2’b10 7 bits 2’b11 8 bits LCR[2] Data Length Number of Stop-Bits 0 5, 6, 7, 8 1 1 5 1.5 1 6, 7, 8 2 LCR[5:3] Parity Type 3’bxx0 No Parity 3’b001 Odd Parity 3’b011 Even Parity 3’b101 Parity bit forced to 1 3’b111 Parity bit forced to 0 Rev. 1.2 MCS7840 USB-2.0 to Four Serial Ports Line Status Register (LSR): This register provides the status of the data transfer to CPU. Register: LSR Description: Line Status Register Offset: 5 Permissions: Read Access Condition: Default Value: Rev. 1.2 0x00 Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0] Data Error Tx Empty THR Empty Rx Break Framing Error Parity Error Overrun Error Rx Rdy Bit Description 0 RHR Data Available Operation Logic 0: RHR is empty Logic 1: RHR is not empty. Data is available to be read 1 RHR Overrun Logic 0: No overrun error Logic 1: Data was received when the RHR was full, An overrun has occurred. The error is flagged when the data would normally have been transferred to the RHR. 2 Received Data Parity Error Logic 0: No parity error in normal mode or 9th bit received data is “0” in 9-bit mode. Logic 1: Data has been received that did not have correct parity 3 Received Data Framing Error Logic 0: No framing error Logic 1: Data has been received with an invalid stop-bit. 4 Receiver Break Error Logic 0: No receiver break error Logic 1: The receiver received a break error 5 THR Empty 6 Transmitter & THR Empty 7 Receiver Data Error Logic 0: Transmitter FIFO is not empty Logic 1: Transmitter FIFO is empty Logic 0: The transmitter is not idle Logic 1: THR is empty & the transmitter has completed the character in the shift register and is in the idle mode Logic 0: Either there is no receiver data error in the FIFO or it was cleared by an earlier read of LSR Logic 1: At least one parity error, framing error or break indication is present in the FIFO. Page 15 MCS7840 USB-2.0 to Four Serial Ports Modem Control Register (MCR): This register controls the UART’s flow control and self diagnostic features. Register: MCR Description: Modem Control Register Offset: 4 Permissions: Read/Write Access Condition: Default Value: 0x00 550 Mode Bit[7] Bit[6] DTR-DSR/DCD Flow Control Page 16 Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0] CTS/RTS Flow Control Internal Loop Back Enable Reserved Reserved RTS DTR Bit Description Operation 0 DTR Logic 0: Forces DTR# output to inactive (high) Logic 1: Forces DTR# output to active (low) 1 RTS Logic 0: Forces RTS# output to inactive (high) Logic 1: Forces RTS# output to active (low) 2 Reserved Reserved 3 Reserved Reserved 4 Loop-Back Mode Logic 0: Normal operating mode Logic 1: Enable local Loop-Back Mode 5 CTS/RTS Flow Control Logic 0: CTS/RTS flow control disabled in 550 mode Logic 1: CTS/RTS flow control enabled in 550 mode 6 DTR/DSR Flow Control Logic 0: DTR/DSR flow control disabled in 550 mode Logic 1: DTR/DSR flow control enabled in 550 mode 7 DCD Flow Control Logic 0: DCD flow control disabled in 550 mode Logic 1: DCD flow control enabled in 550 mode Rev. 1.2 MCS7840 USB-2.0 to Four Serial Ports Modem Status Register (MSR): This register provides the status of the modem control lines to CPU. Register: MSR Description: Modem Status Register Offset: 6 Permissions: Read Access Condition: Default Value: Rev. 1.2 0x00 Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0] DCD RI DSR CTS ΔDCD Teri ΔDSR ΔCTS Bit Description Operation 0 Delta CTS Logic 0: Logic 1: No change in the CTS signal Indicates that the CTS input has changed since the last time the MSR was read 1 Delta DSR Logic 0: Logic 1: No change in the DSR signal Indicates that the DSR input has changed since the last time the MSR was read 2 Trailing Edge of RI Logic 0: Logic 1: No change in the RI signal Indicates that the RI input has changed from low to high since the last time the MSR was read 3 Delta DCD Logic 0: Logic 1: No change in the DCD signal Indicates that the DCD input has changed since the last time the MSR was read 4 CTS Logic 0: Logic 1: CTS# line is 1 CTS# line is 0 5 DSR Logic 0: Logic 1: DSR# line is 1 DSR# line is 0 6 RI Logic 0: Logic 1: RI# line is 1 RI# line is 0 7 DCD Logic 0: Logic 1: DCD# line is 1 DCD# line is 0 Page 17 MCS7840 USB-2.0 to Four Serial Ports Scratch Pad Register (SPR): The scratch pad register does not influence operation of the UART in RS-232 mode in any way, and is used for temporary data storage. When using RS-422/485 Mode, bit[6] and bit[7] of the Scratch Pad Register are used for mode setting and DTR active level settings. Register: SPR Description: Scratch Pad Register Offset: 7 Permissions: Read/Write Access Condition: Default Value: Bit[7] 0x00 Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0] Scratch Pad Register Data Page 18 Rev. 1.2 MCS7840 USB-2.0 to Four Serial Ports Divisor Latch Registers (DLL & DLM): The Divisor Latch Registers are used to program the BAUD Rate divisor. This is a value between 1 and 65535 by which the input clock is divided in order to generate serial BAUD rates. After the hardware reset, the BAUD Rate used by the transmitter & receiver is given by: BAUD Rate = Input Clock / (16 * Divisor) where divisor is given by (256 * DLM) + DLL. More flexible BAUD rate generation options are also available. Register: DLL Description: Divisor Latch (Least Significant Byte) Offset: 0 Permissions: Read/Write Access Condition: LCR[7] = 1 Default Value: 0x01 Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0] Bit[1] Bit[0] Least Significant Byte of divisor latch Register: DLM Description: Divisor Latch (Most Significant Byte) Offset: 1 Permissions: Read/Write Access Condition: LCR[7] = 1 Default Value: 0x00 Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Most Significant Byte of divisor latch Rev. 1.2 Page 19 MCS7840 USB-2.0 to Four Serial Ports RS-422 / RS-485 Mode Support Two additional modes of serial port operation are supported, these are: • RS-422 Mode – Full Duplex Serial Port for industrial applications • RS-485 Mode – Half Duplex Serial Port for industrial applications RS-485 The RS-485 mode can be set using the Scratch Pad Register bit[6] and bit[7] for each serial port. This mode is a half duplex mode and the external transceiver is controlled for transmission or reception using the enable signal. Scratch Pad Scratch Pad Bit[7] Bit[6] 0 1 RS-422 This is the full duplex mode. This mode will work without the use of the DTR signal for external transceiver control. Operation Summary X RS-485 Mode Disabled 0 RS-485 Mode Enabled, DTR High = Rx DTR Low = Tx RS-485 Mode Enabled DTR Low = Rx DTR High = Tx 1 Page 20 1 This is the default selection when RS485 mode is selected through driver property sheets. Rev. 1.2 MCS7840 USB-2.0 to Four Serial Ports Configuration Options Four serial ports can be configured for operation. To program and access the serial ports via software, endpoint numbers have been assigned so that serial ports can be configured from the USB side. Endpoint Type Function Size (Bytes) (USB-1.1 / USB-2.0) 0 Control Endpoint Default Functionality 8 / 64 1 Bulk-In Serial Port – 1 64 / 512 2 Bulk-Out Serial Port – 1 64 / 512 3 Bulk-In Serial Port – 2 64 / 512 4 Bulk-Out Serial Port – 2 64 / 512 5 Bulk-In Serial Port – 3 64 / 512 6 Bulk-Out Serial Port – 3 64 / 512 7 Bulk-In Serial Port – 4 64 / 512 8 Bulk-Out Serial Port – 4 64 / 512 9 Interrupt Status Endpoint * Controlled by DCR1 bit-6 5 or 13 * Serial Port Set/Get Commands Vendor commands are the vendor specific USB setup commands. The purpose of the vendor commands is to set/get the contents of the application registers. The following table provides information on the various vendor specific commands. Windex [7:0] is the register index from where data is to be read. Brequest specifies whether to read or write. • 0x0E = write to the application register • 0x0D = read from the application register Wvalue specifies the application number and data to be written (ww = data). • 0x01ww is the application number for Serial Port-1 • 0x02ww is the application number for Serial Port-2 • 0x03ww is the application number for Serial Port-3 • 0x04ww is the application number for Serial Port-4 • 0x09ww is the application number for EEPROM Write/Read • 0x00ww is the application number provided for accessing the Control Registers which control the UARTs. It is possible to enable higher BAUD rates, and features like auto hardware flow control using the Control Registers Note: “N” in Wvalue and Register Name columns indicate the corresponding serial port number. Windex is the offset of the register to read/write. Wlength is the length of the data to read/write. Rev. 1.2 Page 21 MCS7840 USB-2.0 to Four Serial Ports Get Application Vendor Specific Command (Serial Port -N) Set Application Vendor Specific Command (Serial Port -N) Page 22 bmrequestType Brequest Wvalue Windex Wlength Register Name 0xC0 0x0D 0x0N00 0x0000 0x0001 SPN_RHR 0xC0 0x0D 0x0N00 0x0001 0x0001 SPN_IER 0xC0 0x0D 0x0N00 0x0002 0x0001 SPN_IIR 0xC0 0x0D 0x0N00 0x0003 0x0001 SPN_LCR 0xC0 0x0D 0x0N00 0x0004 0x0001 SPN_MCR 0xC0 0x0D 0x0N00 0x0005 0x0001 SPN_LSR 0xC0 0x0D 0x0N00 0x0006 0x0001 SPN_MSR 0xC0 0x0D 0x0N00 0x0007 0x0001 SPN_SPR 0xC0 0x0D 0x0N00 0x0000 0x0001 SPN_DLL 0xC0 0x0D 0x0N00 0x0001 0x0001 SPN_DLM bmrequestType Brequest Wvalue Windex Wlength Register Name 0x40 0x0E 0x0Nww 0x0000 0x0001 SPN_THR 0x40 0x0E 0x0Nww 0x0001 0x0001 SPN_IER 0x40 0x0E 0x0Nww 0x0002 0x0001 SPN_FCR 0x40 0x0E 0x0Nww 0x0003 0x0001 SPN_LCR 0x40 0x0E 0x0Nww 0x0004 0x0001 SPN_MCR 0x40 0x0E 0x0Nww 0x0005 0x0001 SPN_LSR 0x40 0x0E 0x0Nww 0x0006 0x0001 SPN_MSR 0x40 0x0E 0x0Nww 0x0007 0x0001 SPN_SPR 0x40 0x0E 0x0Nww 0x0000 0x0001 SPN_DLL 0x40 0x0E 0x0Nww 0x0001 0x0001 SPN_DLM Rev. 1.2 MCS7840 USB-2.0 to Four Serial Ports USB Device Descriptors Device Descriptor Location Data BLength 0 8’h12 BDescriptorType 1 8’h01 BcdUSB 2 8’h00 BcdUSB 3 8’h02 BDeviceClass 4 8’hFF BDeviceSubClass 5 8’h00 BDeviceProtocol 6 8’hFF bMaxPacketSize0 7 8’h40 IdVendor 8 8’h10 IdVendor 9 8’h97 IdProduct 10 8’h40 IdProduct 11 8’h78 BcdDevice 12 8’h01 BcdDevice 13 8’h00 iManufacturer 14 8’h00 / 02 * iProduct 15 8’h00 / 03 * iSerialNumber 16 8’h00 / 01 * BNumConfigurations 17 8’h01 * Values returned Without / With the Serial EEPROM present. Rev. 1.2 Page 23 MCS7840 USB-2.0 to Four Serial Ports USB Configuration Descriptors USB Interface Descriptors Page 24 Configuration Descriptor Index Data BLength 0 8’h09 BDescriptorType 1 8’h02 WtotalLength(L) 2 8’h51 WtotalLength(M) 3 8’h00 BNumInterfaces 4 8’h01 BConfigurationValue 5 8’h01 IConfiguration 6 8’h00 BmAttributes 7 8’hA0 BMaxPower 8 8’h32 (100 mA) Configuration Descriptor Index Data BLength 0 8’h09 BDescriptorType 1 8’h04 BInterfaceNumber 2 8’h00 BAlternateSetting 3 8’h00 BNumEndpoints 4 8’h09 BInterfaceClass 5 8’hFF BInterfaceSubClass 6 8’h00 BInterfaceProtocol 7 8’hFF IInterface 8 8’h00 Rev. 1.2 MCS7840 USB-2.0 to Four Serial Ports Endpoint-1 Serial Port 1 Bulk-In Endpoint-2 Serial Port 1 Bulk-Out Endpoint-3 Serial Port 2 Bulk-In Endpoint-4 Serial Port 2 Bulk-Out Configuration Descriptor bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize(L) wMaxPacketSize(M) bInterval Index 0 1 2 3 4 5 6 Data 8’h07 8’h05 8’h81 8’h02 8’h40/8’h00 * 8’h00/8’h02 * 8’hFF Configuration Descriptor bLength bDescriptorType bEndpointAddress bmAttributes WmaxPacketSize(L) WmaxPacketSize(M) bInterval Index 0 1 2 3 4 5 6 Data 8’h07 8’h05 8’h02 8’h02 8’h40/8’h00 * 8’h00/8’h02 * 8’hFF Configuration Descriptor bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize(L) wMaxPacketSize(M) bInterval Index 0 1 2 3 4 5 6 Data 8’h07 8’h05 8’h83 8’h02 8’h40/8’h00 * 8’h00/8’h02 * 8’hFF Configuration Descriptor bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize(L) wMaxPacketSize(M) bInterval Index 0 1 2 3 4 5 6 Data 8’h07 8’h05 8’h04 8’h02 8’h40/8’h00 * 8’h00/8’h02 * 8’hFF * Values for Full Speed & High Speed USB Rev. 1.2 Page 25 MCS7840 USB-2.0 to Four Serial Ports Endpoint-5 Serial Port 3 Bulk-In Endpoint-6 Serial Port 3 Bulk-Out Endpoint-7 Serial Port 4 Bulk-In Endpoint-8 Serial Port 4 Bulk-Out Configuration Descriptor bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize(L) wMaxPacketSize(M) bInterval Index 0 1 2 3 4 5 6 Data 8’h07 8’h05 8’h85 8’h02 8’h40/8’h00 * 8’h00/8’h02 * 8’hFF Configuration Descriptor bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize(L) wMaxPacketSize(M) bInterval Index 0 1 2 3 4 5 6 Data 8’h07 8’h05 8’h06 8’h02 8’h40/8’h00 * 8’h00/8’h02 * 8’hFF Configuration Descriptor bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize(L) wMaxPacketSize(M) bInterval Index 0 1 2 3 4 5 6 Data 8’h07 8’h05 8’h87 8’h02 8’h40/8’h00 * 8’h00/8’h02 * 8’hFF Configuration Descriptor bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize(L) wMaxPacketSize(M) bInterval Index 0 1 2 3 4 5 6 Data 8’h07 8’h05 8’h08 8’h02 8’h40/8’h00 * 8’h00/8’h02 * 8’hFF * Values for Full Speed & High Speed USB Page 26 Rev. 1.2 MCS7840 USB-2.0 to Four Serial Ports Endpoint-9 Interrupt Endpoint Configuration Descriptor Index Data bLength 0 8’h07 bDescriptorType 1 8’h05 bEndpointAddress 2 8’h89 bmAttributes 3 8’h03 wMaxPacketSize(L) 4 8’h0A wMaxPacketSize(M) 5 8’h00 bInterval Rev. 1.2 * 8’h01 / 8’h05 (default FS/HS) * programmable using intr_pg_fs , intr_pg_hs 6 Page 27 MCS7840 USB-2.0 to Four Serial Ports EEPROM Content Layout Page 28 Bytes # of Bytes Name Description [1:0] 2 EE Check EEPROM Present Check value = 0x9710 [3:2] 2 VID Vendor ID = 0x9710 [5:4] 2 PID Product ID = 0x7840 [7:6] 2 RN Release Number in BCD format = 0x0001 8 1 SER1_DCR0 Device Configuration Registers (SER1_DCR0) 9 1 SER1_DCR1 Device Configuration Registers (SER1_DCR1) 10 1 SER1_DCR2 Device Configuration Registers (SER1_DCR2) 11 1 SER2_DCR0 Device Configuration Registers (SER2_DCR0) 12 1 SER2_DCR1 Device Configuration Registers (SER2_DCR1) 13 1 SER2_DCR2 Device Configuration Registers (SER2_DCR2) 14 1 SER3_DCR0 Device Configuration Registers (SER3_DCR0) 15 1 SER3_DCR1 Device Configuration Registers (SER3_DCR1) 16 1 SER3_DCR2 Device Configuration Registers (SER3_DCR2) 17 1 SER4_DCR0 Device Configuration Registers (SER4_DCR0) 18 1 SER4_DCR1 Device Configuration Registers (SER4_DCR1) 19 1 SER4_DCR2 Device Configuration Registers (SER4_DCR2) 20 1 intr_pg_fs Binterval value for Full Speed 21 1 intr_pg_hs Binterval value for High Speed [23:22] 2 Language ID Language ID in HEX Format (0x0409 default) [71:24] 48 Manufacture ID “MosChip Semiconductor” in UNICODE [113:72] 42 Product Name “USB-Serial Controller” in UNICODE [129:114] 16 Serial Number “X7X6X5X4X3X2X1X0” in UNICODE Rev. 1.2 MCS7840 USB-2.0 to Four Serial Ports EEPROM Contents for MCS7840 (Example Contents) EE_Check, VID, PID, RN, SER1_DRC0, SER1_DRC1, SER1_DRC2, SER2_DRC0, SER2_DRC1, SER2_DRC2, SER3_DRC0, SER3_DRC1, SER3_DRC2, SER4_DRC0, SER4_DRC1, SER4_DRC2, INTR_PG_FS, INTR_PG_HS, Language ID, Manufacture ID, M o s C h i p 4D 6F 73 43 68 69 70 S e m i c o n d u c t o r 20 53 65 6D 69 63 6F 6E 64 75 63 74 6F 72 Product Name, U S B - S e r i a l 55 53 42 2D 53 65 72 69 61 6C C o n t r o l l e r 20 43 6F 6E 74 72 6F 6C 6C 65 72 Serial Number Rev. 1.2 Location HEX ASCII 0 10 1 97 2 10 3 97 4 40 5 78 6 01 7 00 8 01 9 85 10 24 11 01 12 80 13 24 14 01 15 80 16 24 17 01 18 80 19 24 20 01 21 05 22 09 23 04 24 4D M 25 00 26 6F o 27 00 28 73 s 29 00 30 43 C 31 00 32 68 h 33 00 34 69 i 35 00 36 70 p 37 00 38 20 Space 39 00 40 53 S 41 00 42 65 e 43 00 Location HEX ASCII 44 6D m 45 00 46 69 i 47 00 48 63 c 49 00 50 6F o 51 00 52 6E n 53 00 54 64 d 55 00 56 75 u 57 00 58 63 c 59 00 60 74 t 61 00 62 6F o 63 00 64 72 r 65 00 66 20 Space 67 00 68 20 Space 69 00 70 20 Space 71 00 72 55 U 73 00 74 53 S 75 00 76 42 B 77 00 78 2D 79 00 80 53 S 81 00 82 65 e 83 00 84 72 r 85 00 86 69 i 87 00 Location HEX 88 61 89 00 90 6C 91 00 92 20 93 00 94 43 95 00 96 6F 97 00 98 6E 99 00 100 74 101 00 102 72 103 00 104 6F 105 00 106 6C 107 00 108 6C 109 00 110 65 111 00 112 72 113 00 114 4D 115 00 116 6F 117 00 118 73 119 00 120 43 121 00 122 68 123 00 124 69 125 00 126 70 127 00 128 20 129 00 ASCII a l Space C o n t r o l l e r M o s C h i p Space Page 29 MCS7840 USB-2.0 to Four Serial Ports Device Configuration Bit Fields and Descriptions Bytes 4, 5, 6 and 22-30 form twenty-four 8-bit DCR Registers. These Bytes are read from the EEPROM, and loaded into the Global Device Configuration Registers after Power-On Reset. They can be programmed by software using the following application number and register indexes as shown in the table. EEPROM Location DCR Bit DCR Name Application Number Register Index Default Value 8 SER1_DCR[7:0] SER1_DCR0 0 4 0x01 9 SER1_DCR[15:8] SER1_DCR1 0 5 0x85 10 SER1_DCR[23:16] SER1_DCR2 0 6 0x24 11 SER2_DCR[7:0] SER2_DCR0 0 22 0x01 12 SER2_DCR[15:8] SER2_DCR1 0 23 0x84 13 SER2_DCR[23:16] SER2_DCR2 0 24 0x24 14 SER3_DCR[7:0] SER3_DCR0 0 25 0x01 15 SER3_DCR[15:8] SER3_DCR1 0 26 0x84 16 SER3_DCR[23:16] SER3_DCR2 0 27 0x24 17 SER4_DCR[7:0] SER4_DCR0 0 28 0x01 18 SER4_DCR[15:8] SER4_DCR1 0 29 0x84 19 SER4_DCR[23:16] SER4_DCR2 0 30 0x24 The following tables describe the function of each bit in the DCR registers. There are three DCR registers for each Serial Port (IrDA). In the absence of an EEPROM, the default values are taken from the Device Configuration Registers. Page 30 Rev. 1.2 MCS7840 USB-2.0 to Four Serial Ports Serial Port 1 – Device Configuration Register 0 Bit[7] Reserved DCR0 Bit Bit[6] IrDA_ Mode Bit[5] Bit[4] RTS_ CM Name Bit[3] Bit[2] GPIO_ Mode Definition Bit[1] Reserved Bit[0] RS_ SDM Default Value RS-232 / RS-422 / RS-485 Transceiver Shut-Down Mode: 0 RS_ SDM 0: Do not shut down the transceiver Even when USB SUSPEND is engaged 1: 1 Reserved [3:2] GPIO_ Mode [5:4] 6 7 Rev. 1.2 RTS_ CM IrDA_ Mode Reserved Shut down the transceiver when USB SUSPEND is engaged Reserved 00: GPIO = Input 1 0 00 10: GPIO = Output RTSM RTS Control Method: 00: RTS is controlled by Control Bit Map. Signal is active low; 01: RTS is controlled by Control Bit Map. Signal is active high; 10: Drive RTS active when Downstream Data Buffer is NOT EMPTY; Otherwise Drive RTS inactive. 11: Drive RTS inactive when Downstream Data Buffer is NOT EMPTY; Otherwise Drive RTS active. RS-232 / RS-422 / RS-485 Serial Port Mode. IrDA Mode. Reserved 00 0: 1: 0 0 Page 31 MCS7840 USB-2.0 to Four Serial Ports Serial Port 1 – Device Configuration Register 1 Bit[7] Bit[6] Reserved Interrupt IN Endpoint Status DCR1 Bit Name Bit[5] PLL_ Power-Down Bypass Control Bit[4] Bit[3] RW_ INHB Bit[2] Tx_I_ PMG Bit[1] Bit[0] GPIO_I_ PMG Definition Default Value These two bits set the output current of the GPIO lines: [1:0] GPIO_I_ PMG [3:2] Tx_I_ PMG 4 RW_ INHB 5 6 7 Page 32 PLL_ Power-Down Bypass Control Interrupt IN Endpoint Status Reserved 00: 01: 10: 11: 6 mA 8 mA (Default) 10 mA 12 mA These two bits set the output current of Serial output signals TxD, DTR_n and RTS_n: 01 00: 01: 10: 11: 6 mA 8 mA (Default) 10 mA 12 mA RW_INH Remote Wake Inhibit: 01 0: 1: Enable the USB Remote Wakeup function Inhibit the USB Remote Wakeup function 0: 1: Enables PLL Power-Down Disables PLL Power-Down 0: 1: Interrupt Endpoint returns 5 Bytes of data. Interrupt Endpoint returns 5 Bytes + 8 Bytes of the Bulk-In/Out memory controller status Reserved 0 0 0 1 Rev. 1.2 MCS7840 USB-2.0 to Four Serial Ports Serial Port 1 – Device Configuration Register 2 Bit[7] SHDN_ POL Bit[6] Bit[5] RWU_ Mode Reserved DCR2 Bit Name 0 EWU_ CTS 1 EWU_ DCD 2 EWU_ RI 3 EWU_ DSR 4 EWU_ Rx 5 RWU_ Mode Bit[4] EWU_ Rx Bit[3] EWU_ DSR Bit[2] EWU_ RI Definition Bit[1] EWU_ DCD Bit[0] EWU_ CTS Default Value Enable Wake Up Trigger on CTS: 0: 1: Disabled Enable Wake Up Trigger on CTS State Changes. Enable Wake Up Trigger on DCD: 0: 1: Disabled Enable Wake Up Trigger on DCD State Changes. Enable Wake Up Trigger on RI: 0: 1: Disabled Enable Wake Up Trigger on RI State Changes. Enable Wake Up Trigger on DSR: 0: 1: Disabled Enable Wake Up Trigger on DSR State Changes. Enable Wake Up Trigger on RXD: 0: 1: Disabled Enable Wake Up Trigger on RXD State Changes. Remote Wakeup Mode: 0: Engages Remote Wakeup, The device issues Disconnect Signal. 0 1 0 0 1 1: 6 Reserved 7 SHDN_ POL Engages Remote Wakeup, The device issues Resume Signal. Reserved SHDN Polarity: 0 0: Pin 12 Active Low Shut-Down Signal. 1: Pin 12 Active High Shut-Down Signal. 0 0 Note: Wake up defined above can work only when DCR0[6] = 0 and DCR1[4] = 0. Rev. 1.2 Page 33 MCS7840 USB-2.0 to Four Serial Ports Serial Port (2, 3, & 4) – Device Configuration Register 0 The Configuration Registers for these three Serial Ports are all identical. They are very similar to Serial Port 1, but have a few less configuration options. Bit[7] Reserved DCR0 Bit Bit[6] IrDA_ Mode Bit[5] Bit[4] RTS_ CM Name Bit[3] Bit[2] Reserved Definition Bit[1] Reserved Bit[0] RS_ SDM Default Value RS-232 / RS-422 / RS-485 Transceiver Shut-Down Mode: 0 1 [3:2] [5:4] 6 7 Page 34 RS_ SDM 0: Do not shut down the transceiver Even when USB SUSPEND is engaged 1: Shut down the transceiver when USB SUSPEND is engaged Reserved Reserved RTSM RTS Control Method: Reserved Reserved RTS_ CM IrDA_ Mode Reserved 00: RTS is controlled by Control Bit Map. Signal is active low; 01: RTS is controlled by Control Bit Map. Signal is active high; 10: Drive RTS active when Downstream Data Buffer is NOT EMPTY; Otherwise Drive RTS inactive. 11: Drive RTS inactive when Downstream Data Buffer is NOT EMPTY; Otherwise Drive RTS active. RS-232 / RS-422 / RS-485 Serial Port Mode. IrDA Mode. Reserved 1 0 00 00 0: 1: 0 0 Rev. 1.2 MCS7840 USB-2.0 to Four Serial Ports Serial Port (2, 3, & 4) – Device Configuration Register 1 The Configuration Registers for these three Serial Ports are all identical. They are very similar to Serial Port 1, but have a few less configuration options. Bit[7] Reserved DCR1 Bit [1:0] Rev. 1.2 Bit[6] Bit[5] Reserved Reserved Bit[4] RW_ INHB Bit[3] Bit[2] Tx_I_ PMG Name Definition Reserved Reserved These two bits set the output current of Serial output signals TxD, DTR_n and RTS_n: [3:2] Tx_I_ PMG 4 RW_ INHB 5 6 7 Reserved Reserved Reserved 00: 01: 10: 11: 6 mA 8 mA (Default) 10 mA 12 mA RW_INH Remote Wake Inhibit: 0: 1: Enable the USB Remote Wakeup function Inhibit the USB Remote Wakeup function Reserved Reserved Reserved Bit[1] Bit[0] Reserved Default Value 00 01 0 0 0 1 Page 35 MCS7840 USB-2.0 to Four Serial Ports Serial Port (2, 3, & 4) – Device Configuration Register 2 The Configuration Registers for these three Serial Ports are all identical. They are very similar to Serial Port 1, but have a few less configuration options. Bit[7] Bit[6] Reserved Reserved DCR2 Bit Name 0 EWU_ CTS 1 EWU_ DCD 2 EWU_ RI 3 EWU_ DSR 4 EWU_ Rx 5 RWU_ Mode Bit[5] RWU_ Mode Bit[4] EWU_ Rx Bit[3] EWU_ DSR Bit[2] EWU_ RI Definition Bit[1] EWU_ DCD Bit[0] EWU_ CTS Default Value Enable Wake Up Trigger on CTS: Disabled Enable Wake Up Trigger on CTS State Changes. Enable Wake Up Trigger on DCD: 0: 1: Disabled Enable Wake Up Trigger on DCD State Changes. Enable Wake Up Trigger on RI: 0: 1: Disabled Enable Wake Up Trigger on RI State Changes. Enable Wake Up Trigger on DSR: 0: 1: Disabled Enable Wake Up Trigger on DSR State Changes. Enable Wake Up Trigger on RXD: 0: 1: Disabled Enable Wake Up Trigger on RXD State Changes. Remote Wakeup Mode: 0: Engages Remote Wakeup, The device issues Disconnect Signal. 1 engages remote wakeup, the Device issues resume signal. Reserved Reserved 0 0 1: 6 7 Reserved Reserved 0 0: 1: 0 1 0 0 Note: Wake up defined above can work only when DCR0[6] = 0 and DCR1[4] = 0. Page 36 Rev. 1.2 MCS7840 USB-2.0 to Four Serial Ports Electrical Specifications Absolute Maximum Ratings: Core Power Supply (VccK) -0.3 to 2.16 V Power Supply of 3.3V I/O (Vcc3I0) -0.3 to 4.0 V Input Voltage of 3.3V I/O (Vin3 ) -0.3 to 4.0 V Input Voltage of 5V Tolerant I/O (Vin5) -0.3 to 5.8 V Operating Temperature 0 to +70 °C Storage Temperature -40 to +150 °C ESD HBM (MIL-STD 883E Method 3015-7 Class 2) 2000 V ESD MM (JEDEC EIA/JESD22 A115-A) 200 V CDM (JEDEC/JESD22 C101-A) 500 V Latch-up (JESD No. 78, March 1997) 200 mA, 1.5 x VCC Junction Temperature (Tj) 115 °C Thermal Resistance of Junction to Ambient (Still Air) 65 °C/W Operating Conditions: Symbol Parameter Min Typ Max Units Vcc5A 5V Power Supply Input 4.5 5.0 5.5 V VccK Core Power Supply 1.62 1.8 1.98 V Vcc3IO Power Supply of 3.3V I/O 2.97 3.3 3.63 V REG02_V18 1.8V Regulator Output 1.71 1.8 1.89 V IREG02_V18 1.8V Regulator Current 70 mA REG06_VCC33 3.3V Regulator Output 3.46 V IREG06_VCC33 3.3V Regulator Current 250 mA I5V Operating current of 5V when 3.3V and 1.8V internal regulators are used. No serial load. 70 mA I3.3V Operating current of 3.3V. No serial load. 45 mA I1.8V Operating current of 1.8V. No serial load. 25 mA Rev. 1.2 3.14 3.3 Page 37 MCS7840 USB-2.0 to Four Serial Ports DC Characteristics of 3.3V I/O Cells Symbol Parameter Condition Min Typ Max Units VccK Core Power Supply Core Area 1.62 1.8 1.98 V Vcc3IO Power Supply 3.3V I/O 2.97 3.3 3.63 V ViL Input Low Voltage LVTTL 0.8 V ViH Input High Voltage LVTTL Vt Switching Threshold LVTTL VtVt+ Schmitt Trigger Threshold Voltage LVTTL VoL Output Low Voltage IoL= 2 to 24mA VoH Output High Voltage IoH= -2 to -24mA 2.0 V 1.5 0.8 1.1 1.6 V 2.0 0.4 2.4 V V V DC Characteristics of 5V Tolerant I/O Cells Symbol Parameter Condition Min Typ Max Units 5V Power Supply 5V I/O 4.5 5.0 5.5 V Input Low Voltage LVTTL 0.8 V Vcc5A ViL ViH Input High Voltage LVTTL Vt Switching Threshold LVTTL VtVt+ Schmitt Trigger Threshold Voltage LVTTL VoH Output Low Voltage IoL= 2 to 24 mA VoH Output High Voltage IoH= -2 to -24 mA Page 38 2.0 V 1.5 0.8 1.1 1.6 V 2.0 0.4 2.4 V V V Rev. 1.2 MCS7840 USB-2.0 to Four Serial Ports HE E 64 49 1 48 16 33 17 32 D HD e b A2 A1 c L MIN Millimeters TYP MAX A1 0.05 0.15 A2 1.35 1.45 b 0.17 0.27 c 0.09 0.20 Symbol 64-Pin “CV” LQFP Package Dimensions Rev. 1.2 e 0.50 L 0.45 0.75 HD 11.75 12.25 D 9.90 10.10 HE 11.75 12.25 E 9.90 10.10 Page 39 MCS7840 USB-2.0 to Four Serial Ports IMPORTANT NOTICE MosChip Semiconductor Technology, LTD products are not authorized for use as critical components in life support devices or systems. Life support devices are applications that may involve potential risks of death, personal injury or severe property or environmental damages. These critical components are semiconductor products whose failure to perform can be reasonably expected to cause the failure of the life support systems or device, or to adversely impact its effectiveness or safety. The use of MosChip Semiconductor Technology LTD’s products in such devices or systems is done so fully at the customer risk and liability. As in all designs and applications it is recommended that the customer apply sufficient safeguards and guard bands in both the design and operating parameters. MosChip Semiconductor Technology LTD assumes no liability for customer’s applications assistance or for any customer’s product design(s) that use MosChip Semiconductor Technology, LTD’s products. MosChip Semiconductor Technology, LTD warrants the performance of its products to the current specifications in effect at the time of sale per MosChip Semiconductor Technology, LTD standard limited warranty. MosChip Semiconductor Technology, LTD imposes testing and quality control processes that it deems necessary to support this warranty. The customer should be aware that not all parameters are 100% tested for each device. Sufficient testing is done to ensure product reliability in accordance with MosChip Semiconductor Technology LTD’s warranty. MosChip Semiconductor Technology, LTD believes the information in this document to be accurate and reliable but assumes no responsibility for any errors or omissions that may have occurred in its generation or printing. The information contained herein is subject to change without notice and no responsibility is assumed by MosChip Semiconductor Technology, LTD to update or keep current the information contained in this document, nor for its use or for infringement of patent or other rights of third parties. MosChip Semiconductor Technology, LTD does not warrant or represent that any license, either expressed or implied, is granted to the user. Page 40 Rev. 1.2 MCS7840 USB-2.0 to Four Serial Ports Revision History Revision Changes Date 0.9 Preliminary Release 30-May-2006 0.91 Corrected MaxPacketSize values (FS/HS) 01-Jun-2006 0.92 Corrected Wlength field in “Set Application Vendor Specific Command” 05-Jun-2006 1.0 Removed Preliminary Notice. Made change to reflect one GPIO port instead of two. Added Driver Support entries on page 1. Made bits 2 and 1 of the MCR register reserved. Made bit 5 of the Mode register reserved. Replaced Raid_reg1 with Rx_sampling_reg1 throughout document. Modified product ID value in EEPROM Content Layout table. Made bit 1 of Device Configuration register 0 reserved and added note. Modified description of bit 1 of Device Configuration register 0. Made bit 6 of Device Configuration register 0 reserved and added note. 28-Aug-2006 1.1 Clarified Linux Kernel support in Features Deleted Windows CE5.0 and Vista release dates 16-Sept-2006 1.2 Updated Absolute Maximum Rating table Deleted Leakage Current table Updated Operating Conditions table Updated 3.3V DC Characteristics table Updated 5V DC Characteristics table Removed dimensions in Inches from Package Dimensions table Removed ‘Confidential’ notice from all pages 6-August-2007 Rev. 1.2 Page 41