ICS932S422C Integrated Circuit Systems, Inc. PCIe Gen 2 main Clock for Intel-based Servers Recommended Application: PCIe Gen 2 & FBD compliant CK410B/CK410B+ clock for Intel-based servers Output Features: • 5 - 0.7V current-mode differential CPU pairs • 4 - 0.7V current-mode differential SRC pair • 4 - PCI (33MHz) • 3 - PCICLK_F, (33MHz) free-running • 1 - 48MHz • 2 - REF, 14.318MHz Features/Benefits: • Supports spread spectrum modulation, 0 to -0.5% down spread • Uses external 14.318MHz crystal and external load capacitors for low ppm synthesis error • • • CPU clocks independent of SRC/PCI clocks D2/D3 SMBus address Compliant with PCIe Gen II phase noise specifications Key Specifications: • CPU cycle-cycle jitter: < 50ps • SRC cycle-cycle jitter: < 125ps • PCI cycle-cycle jitter: < 500ps • CPU output skew: < 100ps • SRC output skew: < 250ps • ± 300ppm frequency accuracy on all outputs except 48MHz • ± 100ppm frequency accuracy on 48MHz Functionality 0 0 0 0 1 1 1 1 1 2 FSLB FSLA 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CPU MHz 266.67 133.33 200.00 166.67 333.33 100.00 400.00 SRC MHz 100.00 100.00 100.00 100.00 100.00 100.00 100.00 PCI MHz 33.33 33.33 33.33 33.33 33.33 33.33 33.33 Reserved REF MHz 14.318 14.318 14.318 14.318 14.318 14.318 14.318 USB MHz 48.000 48.000 48.000 48.000 48.000 48.000 48.000 1. FSLB and FSLC are three-level inputs. Please see VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2.FSLA is a low-threshold input. Please see the VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. VDDPCI GNDPCI PCICLK0 PCICLK1 PCICLK2 PCICLK3 GNDPCI VDDPCI PCICLK_F0 PCICLK_F1 PCICLK_F2 VDD48 48MHz GND48 VDDSRC NC Vtt_PwrGd#/PD SRCCLKC1 SRCCLKT1 GNDSRC SRCCLKT2 SRCCLKC2 SRCCLKC3 SRCCLKT3 VDDSRC SRCCLKT4 SRCCLKC4 VDDSRC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ICS932S422 1 FSLC Pin Configuration 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 FSLC/TEST_SEL REF0 REF1 VDDREF X1 X2 GNDREF FSLB/TEST_MODE FSLA VDDCPU CPUCLKT0 CPUCLKC0 VDDCPU CPUCLKT1 CPUCLKC1 GNDCPU CPUCLKT2 CPUCLKC2 VDDCPU CPUCLKT3 CPUCLKC3 VDDA GNDA IREF CPUCLKT4 CPUCLKC4 SDATA SCLK 56-pin SSOP & TSSOP 1412A—12/10/07 Integrated Circuit Systems, Inc. ICS932S422C Pin Description Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN NAME VDDPCI GNDPCI PCICLK0 PCICLK1 PCICLK2 PCICLK3 GNDPCI VDDPCI PCICLK_F0 PCICLK_F1 PCICLK_F2 VDD48 48MHz GND48 VDDSRC NC 17 Vtt_PwrGd#/PD 18 19 20 21 22 23 24 25 26 27 28 SRCCLKC1 SRCCLKT1 GNDSRC SRCCLKT2 SRCCLKC2 SRCCLKC3 SRCCLKT3 VDDSRC SRCCLKT4 SRCCLKC4 VDDSRC PIN TYPE PWR PWR OUT OUT OUT OUT PWR PWR OUT OUT OUT PWR OUT PWR PWR N/A IN OUT OUT PWR OUT OUT OUT OUT PWR OUT OUT PWR DESCRIPTION Power supply for PCI clocks, nominal 3.3V Ground pin for the PCI outputs PCI clock output. PCI clock output. PCI clock output. PCI clock output. Ground pin for the PCI outputs Power supply for PCI clocks, nominal 3.3V Free running PCI clock not affected by PCI_STOP# . Free running PCI clock not affected by PCI_STOP# . Free running PCI clock not affected by PCI_STOP# . Power pin for the 48MHz output.3.3V 48MHz clock output. Ground pin for the 48MHz outputs Supply for SRC clocks, 3.3V nominal No Connection. Vtt_PwrGd# is an active low input used to determine when latched inputs are ready to be sampled. PD is an asynchronous active high input pin used to put the device into a low power state. The internal clocks, PLLs and the crystal oscillator are stopped. Complement clock of differential push-pull SRC clock pair. True clock of differential SRC clock pair. Ground pin for the SRC outputs True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. Complement clock of differential SRC clock pair. True clock of differential SRC clock pair. Supply for SRC clocks, 3.3V nominal True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. Supply for SRC clocks, 3.3V nominal 1412A—12/10/07 2 Integrated Circuit Systems, Inc. ICS932S422C Pin Description (Continued) Pin # 29 30 SCLK SDATA Type IN I/O 31 CPUCLKC4 OUT 32 CPUCLKT4 OUT 33 IREF OUT 34 35 GNDA VDDA PWR PWR 36 CPUCLKC3 OUT 37 CPUCLKT3 OUT 38 VDDCPU PWR 39 CPUCLKC2 OUT 40 CPUCLKT2 OUT 41 GNDCPU PWR 42 CPUCLKC1 OUT 43 CPUCLKT1 OUT 44 VDDCPU PWR 45 CPUCLKC0 OUT 46 CPUCLKT0 OUT 47 VDDCPU PWR 48 FSLA IN 49 FSLB/TEST_MODE IN 50 51 52 53 54 55 GNDREF X2 X1 VDDREF REF1 REF0 56 PIN NAME FSLC/TEST_SEL PWR OUT IN PWR OUT OUT IN Pin Description Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 3.3V tolerant. Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin for the PLL core. 3.3V power for the PLL core. Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Ground pin for the CPU outputs Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table. Ground pin for the REF outputs. Crystal output, Nominally 14.318MHz Crystal input, Nominally 14.318MHz. Ref, XTAL power supply, nominal 3.3V 14.318 MHz reference clock. 14.318 MHz reference clock. 3.3V tolerant input for CPU frequency selection. Low voltage threshold inputs, see input electrical characteristics for Vil_FS and Vih_FS values. TEST_Sel: 3-level latched input to enable test mode. Refer to Test Clarification Table 1412A—12/10/07 3 Integrated Circuit Systems, Inc. ICS932S422C General Description The ICS932S422C is a main clock synthesizer for CK410-generation Intel server platforms. The ICS932S422C is driven with a 14.318MHz crystal. It generates 5 CPU output pairs up to 400MHz and PCI-Express clocks at 100 or 200 MHz. The 48 MHz USB clock is an exact 48.000 MHz clock. Block Diagram REF(1:0) X1 X2 48MHz XTAL OSC. FIXED PLL DIVIDER CPU PLL DIVIDERS SRC/PCI PLL DIVIDERS CPUCLK(4:0) SRCCLK(3:0) PCICLK(3:0), PCICLK_F(2:0) FS(C:A) TEST_SEL TEST_MODE VTT_PWRGD#/PD SDATA SCLK CONTROL LOGIC IREF Power Groups Pin Number VDD GND 53 50 1,8 2,7 15,25,28 20 35 34 12 14 47,44,38 41 Description Xtal, Ref PCICLK outputs SRCCLK outputs Master clock, CPU Analog 48MHz, PLL_48 CPUCLK clocks 1412A—12/10/07 4 Integrated Circuit Systems, Inc. ICS932S422C Single-ended Output Terminations ICS932S422 Zo Rs CL=5pF Test Load SEPP Output Buffer (Single Ended Push Pull) Zo Rs CL=5pF Zo Rs CL=5pF SEPP Output Buffer (Single Ended Push Pull) The singled-ended outputs of the ICS 932S422 default to a drive strength of 2 loads. The REF clocks can be turned down to 1-load strength via the SMBus. Suggested termination resistors are as follows for transmission lines with Zo = 50 ohms: Single-ended outputs at 2-load strength (Power up default for all single-ended outputs) Driving 1 load, Rs = 33 ohms Driving 2 loads, Rs = 7.5 ohms Single-ended outputs at 1-load strength (REF clock only) Driving 1 load, Rs = 22 ohms 1412A—12/10/07 5 Integrated Circuit Systems, Inc. ICS932S422C Absolute Maximum Rating PARAMETER SYMBOL CONDITIONS 3.3V Core Supply Voltage 3.3V Logic Input Supply Voltage Storage Temperature VDD_A - VDD_In - Ts Ambient Operating Temp Tambient Case Temperature Tcase - Input ESD protection HBM ESD prot - 1Guaranteed MIN TYP MAX UNITS Notes VDD + 0.5V V 1 GND - 0.5 VDD + 0.5V V 1 - -65 150 °C 1 - 0 70 °C 1 115 °C 1 V 1 2000 by design and characterization, not 100% tested in production. Electrical Characteristics - Input/Supply/Common Output Parameters PARAMETER SYMBOL CONDITIONS* MIN MAX UNITS Notes Input High Voltage VIH 3.3 V +/-5% 2 VDD + 0.3 V 1 Input Low Voltage VIL 3.3 V +/-5% VSS - 0.3 0.8 V 1 Input High Current IIH VIN = VDD -5 5 uA 1 IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 uA 1 IIL2 VIN = 0 V; Inputs with pull-up resistors -200 uA 1 VIH_FS 3.3 V +/-5% 0.7 VDD + 0.3 V 1 VSS - 0.3 0.35 V 1 Input Low Current TYP Low Threshold InputHigh Voltage Low Threshold InputLow Voltage Operating Supply Current VIL_FS 3.3 V +/-5% IDD3.3OP Full Active, CL = Full load; 350 mA 1 Operating Current IDD3.3OP all outputs driven 400 mA 1 Powerdown Current IDD3.3PD all diff pairs driven 70 mA 1 all differential pairs tri-stated 12 mA 1 VDD = 3.3 V 14.31818 MHz 2 7 nH 1 Logic Inputs 5 pF 1 Output pin capacitance 6 pF 1 5 pF 1 1.8 ms 1 33 kHz 1 300 us 1 5 ns 1 5 ns 1 Input Frequency Fi Pin Inductance Lpin CIN Input Capacitance COUT CINX Tfall_PD X1 & X2 pins From VDD Power-Up or de-assertion of PD to 1st clock Triangular Modulation CPU output enable after PD de-assertion PD fall time of Trise_PD PD rise time of Clk Stabilization TSTAB Modulation Frequency Tdrive_PD SMBus Voltage VDD Low-level Output Voltage VOL Current sinking at IPULLUP VOL = 0.4 V SCLK/SDATA TRI2C Clock/Data Rise Time SCLK/SDATA TFI2C Clock/Data Fall Time *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% 30 2.7 @ IPULLUP 5.5 V 1 0.4 V 1 mA 1 1000 ns 1 300 ns 1 4 (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) 1 Guaranteed by design and characterization, not 100% tested in production. 2 Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. 1412A—12/10/07 6 Integrated Circuit Systems, Inc. ICS932S422C Electrical Characteristics - CPU 0.7V Current Mode Differential Pair PARAMETER SYMBOL CONDITIONS* MIN Current Source Output Impedance Zo VO = V x 3000 Voltage High VHigh 850 mV 1,3 VLow Statistical measurement on single ended signal 660 Voltage Low -150 150 mV 1,3 Measurement on single ended signal using absolute value. -300 Max Voltage Vovs Min Voltage Vuds Crossing Voltage (abs) Vx(abs) Crossing Voltage (var) d-Vx Variation of crossing over all edges Long Accuracy ppm see Tperiod min-max values Average period Absolute min period Tperiod Tabsmin TYP 1150 UNITS NOTES Ω 1 mV 1 mV 1 550 mV 1 140 mV 1 -300 300 ppm 1,2 400MHz nominal 2.4993 2.5008 ns 2 400MHz spread 2.4993 2.5133 ns 2 333.33MHz nominal 2.9991 3.0009 ns 2 333.33MHz spread 2.9991 3.016 ns 2 266.66MHz nominal 3.7489 3.7511 ns 2 266.66MHz spread 3.7489 3.77 ns 2 200MHz nominal 4.9985 5.0015 ns 2 200MHz spread 4.9985 5.0266 ns 2 250 166.66MHz nominal 5.9982 6.0018 ns 2 166.66MHz spread 5.9982 6.0320 ns 2 133.33MHz nominal 7.4978 7.5023 ns 2 133.33MHz spread 7.4978 7.5400 ns 2 100.00MHz nominal 9.9970 10.0030 ns 2 100.00MHz spread 9.9970 10.0533 ns 2 400MHz nominal/spread 2.4143 ns 1,2 333.33MHz nominal/spread 2.9141 ns 1,2 266.66MHz nominal/spread 3.6639 ns 1,2 200MHz nominal/spread 4.8735 ns 1,2 166.66MHz nominal/spread 5.8732 ns 1,2 133.33MHz nominal/spread 7.3728 ns 1,2 100.00MHz nominal/spread 9.8720 ns 1,2 1 Rise Time tr VOL = 0.175V, VOH = 0.525V 175 525 ps Fall Time tf VOH = 0.525V VOL = 0.175V 175 525 ps 1 Rise Time Variation d-tr VOL = 0.175V, VOH = 0.525V 125 ps 1 Fall Time Variation d-tf VOH = 0.525V VOL = 0.175V 125 ps 1 Duty Cycle dt3 Measurement from differential wavefrom 55 % 1 Skew tsk3 CPU(4:0), VT = 50% 100 ps 1 50 ps 1 45 Measurement from differential wavefrom, tjcyc-cyc Jitter, Cycle to cycle (CPU(4:0)) *TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω 1 Guaranteed by design and characterization, not 100% tested in production. 2 MAX All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz 3 IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω. 1412A—12/10/07 7 Integrated Circuit Systems, Inc. ICS932S422C Electrical Characteristics - SRC/SATA 0.7V Current Mode Differential Pair PARAMETER SYMBOL CONDITIONS* MIN TYP MAX Current Source Output Impedance Zo VO = V x 3000 Voltage High VHigh 850 mV 1,3 VLow Statistical measurement on single ended signal 660 Voltage Low -150 150 mV 1,3 Measurement on single ended signal using absolute value. -300 1150 UNITS Notes Ω 1 Max Voltage Vovs Min Voltage Vuds Crossing Voltage (abs) Vx(abs) Crossing Voltage (var) d-Vx Variation of crossing over all edges Long Accuracy ppm see Tperiod min-max values -300 Average period Tperiod 100.00MHz nominal 9.9970 10.0030 ns 2 100.00MHz spread 9.9970 10.0533 ns 2 Absolute min period Tabsmin 100.00MHz nominal/spread 9.8720 ns 1,2 Rise Time tr VOL = 0.175V, VOH = 0.525V 175 525 ps 1 Fall Time tf VOH = 0.525V VOL = 0.175V 175 525 ps 1 Rise Time Variation d-tr VOL = 0.175V, VOH = 0.525V 125 ps 1 Fall Time Variation d-tf VOH = 0.525V VOL = 0.175V 125 ps 1 Duty Cycle dt3 Measurement from differential wavefrom 55 % 1 Skew tsk3 VT = 50% 250 ps 1 Jitter, Cycle to cycle tjcyc-cyc Measurement from differential wavefrom 125 ps 1 MAX UNITS NOTES 55 Ω 1 V 1 250 45 mV 1 mV 1 550 mV 1 140 mV 1 300 ppm 1,2 *TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz 3 IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω. Electrical Characteristics - PCICLK/PCICLK_F PARAMETER SYMBOL CONDITIONS* MIN Output Impedance RDSP VO = VDD*(0.5) 12 Output High Voltage VOH IOH = -1 mA 2.4 Output Low Voltage VOL Output High Current IOH IOL = 1 mA 0.55 V OH @MIN = 1.0 V -33 VOH@MAX = 3.135 V VOL @ MIN = 1.95 V -33 30 V 1 mA 1 mA 1 mA 1 Output Low Current IOL 38 mA 1 Rise Time tr VOL = 0.4 V, VOH = 2.4 V 0.5 2 ns 1 Fall Time tf VOH = 2.4 V, VOL = 0.4 V 0.5 2 ns 1 Duty Cycle dt1 VT = 1.5 V 45 55 % 1 Group Skew tskew VT = 1.5 V 250 ps 1 Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 500 ps 1 VOL @ MAX = 0.4 V *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs = 22Ω (unless otherwise specified) 1 Guaranteed by design and characterization, not 100% tested in production. 3 TYP Spread Spectrum is off 1412A—12/10/07 8 Integrated Circuit Systems, Inc. ICS932S422C Electrical Characteristics - USB48MHz PARAMETER SYMBOL CONDITIONS* MIN MAX UNITS NOTES Long Accuracy ppm see Tperiod min-max values -100 100 ppm 1,2 Clock period Tperiod 48.00MHz output nominal 20.8313 20.8354 ns 2 Output Impedance RDSP VO = VDD*(0.5) 12 55 Ω 1 Output High Voltage VOH IOH = -1 mA 2.4 V 1 Output Low Voltage VOL Output High Current TYP IOL = 1 mA 0.55 V OH @MIN = 1.0 V IOH -29 VOH@MAX = 3.135 V VOL @ MIN = 1.95 V -33 29 V 1 mA 1 mA 1 mA 1 Output Low Current IOL 27 mA 1 Rise Time tr_USB VOL = 0.4 V, VOH = 2.4 V 1 2 ns 1 Fall Time tf_USB VOH = 2.4 V, VOL = 0.4 V 1 2 ns 1 Duty Cycle dt1 VT = 1.5 V 45 55 % 1 Group Skew tskew VT = 1.5 V 250 ps 1 Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 500 ps 1 VOL @ MAX = 0.4 V *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs = 22Ω 1 Guaranteed by design and characterization, not 100% tested in production. Electrical Characteristics - REF-14.318MHz PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes Long Accuracy ppm see Tperiod min-max values -300 300 ppm 1,2 Clock period Tperiod 14.318MHz output nominal 69.8270 69.8550 ns 2 Output High Voltage VOH IOH = -1 mA 2.4 V 1 Output Low Voltage VOL Output High Current TYP IOL = 1 mA 0.4 V OH @MIN = 1.0 V IOH -33 VOH@MAX = 3.135 V VOL @ MIN = 1.95 V -33 30 V 1 mA 1 mA 1 mA 1 Output Low Current IOL 38 mA 1 Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V 0.5 2 ns 1 Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V 0.5 2 ns 1 Skew tsk1 VT = 1.5 V 500 ps 1 Duty Cycle dt1 VT = 1.5 V Jitter tjcyc-cyc VT = 1.5 V VOL @ MAX = 0.4 V 45 55 % 1 1000 ps 1 Max Units Notes 86 ps (p-p) 1,2 3 ps (RMS) 1,2 3.1 ps (RMS) 1,2 FBD1 3.2/4G 11MHz to 33MHz 3 ps (RMS) 1,2 FBD1 4.8G 11MHz to 33MHz 2.5 ps (RMS) 1,2 *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs = 22Ω (Rs is used in USB48MHz test only) 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz Electrical Characteristics - Differential Jitter Parameters PARAMETER Symbol Conditions tjphasePLL PCIe Gen 1 PCIe Gen 2 10kHz < f < 1.5MHz PCIe Gen 2 1.5MHz < f < Nyquist (50MHz) tjphaseLo tjphaseHigh Jitter, Phase t jphFBD1_3.2 G t jphFBD1_4.0 G Min *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% 1 2 Guaranteed by design and characterization, not 100% tested in production. See http://www.pcisig.com for compelte specs 1412A—12/10/07 9 TYP Integrated Circuit Systems, Inc. ICS932S422C General SMBus serial interface information for the ICS932S422C How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • • • • • • • • Index Block Read Operation Index Block Write Operation Controller (Host) starT bit T Slave Address D2(H) WR WRite Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Controller (Host) T starT bit Slave Address D2(H) WR WRite ICS (Slave/Receiver) ICS (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address D3(H) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Byte N + X - 1 N P 1412A—12/10/07 10 Not acknowledge stoP bit Integrated Circuit Systems, Inc. ICS932S422C SMBus Table: SRC Output Byte 0 Pin # NA Bit 7 NA Bit 6 NA Bit 5 26,27 Bit 4 23,24 Bit 3 21,22 Bit 2 18,19 Bit 1 32,31 Bit 0 Enable Register Name SRCCLK7 Enable SRCCLK6 Enable SRCCLK5 Enable SRCCLK4 Enable SRCCLK3 Enable SRCCLK2 Enable SRCCLK1 Enable CPUCLK4 Control Function Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable SMBus Table: CPU, REF and 48 MHz Output Enable Register Pin # Name Control Function Byte 1 REF1 Enable Output Enable Bit 7 54 REF0 Enable Output Enable 55 Bit 6 36,37 CPUCLK3 Output Enable Bit 5 39,40 CPUCLK2 Output Enable Bit 4 RESERVED Bit 3 CPUCLK1 Output Enable 42,43 Bit 2 CPUCLK0 Output Enable 45,46 Bit 1 Spread Spectrum Spread Off/On Bit 0 CPU, SRC, PCI Enable SMBus Table: Byte 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PCI and PCICLK_F Output Enable Register Pin # Name Control Function PCICLK3 Output Enable 6 PCICLK2 Output Enable 5 4 PCICLK1 Output Enable PCICLK0 Output Enable 3 PCICLK_F2 Enable Output Enable 11 PCICLK_F1 Enable Output Enable 10 PCICLK_F0 Enable Output Enable 9 48MHz Enable Output Enable 13 SMBus Table: PCICLK_F Byte 3 Pin # 11 Bit 7 10 Bit 6 9 Bit 5 26,27 Bit 4 23,24 Bit 3 21,22 Bit 2 18,19 Bit 1 Bit 0 Type RW RW RW RW RW RW RW RW 0 Disable-Hi-Z Disable-Hi-Z Disable-Hi-Z Disable-Hi-Z Disable-Hi-Z Disable-Hi-Z Disable-Hi-Z Disable-Hi-Z 1 Enable Enable Enable Enable Enable Enable Enable Enable PWD 1 1 1 1 1 1 1 1 Type 0 RW Disable-Low RW Disable-Low RW Disable-Hi-Z RW Disable-Hi-Z 1 Enable Enable Enable Enable RW RW Disable-Hi-Z Disable-Hi-Z Enable Enable PWD 1 1 1 1 0 1 1 RW Spread Off Spread On 0 Type RW RW RW RW RW RW RW RW 0 Disable-Low Disable-Low Disable-Low Disable-Low Disable-Low Disable-Low Disable-Low Disable-Low 1 Enable Enable Enable Enable Enable Enable Enable Enable PWD 1 1 1 1 1 1 1 1 Type RW RW RW RW RW RW RW 0 Free-Running Free-Running Free-Running Free-Running Free-Running Free-Running Free-Running 1 Stoppable Stoppable Stoppable Stoppable Stoppable Stoppable Stoppable PWD 1 1 1 1 1 1 1 0 and SRC Stop Control Register Name PCICLK_F2 Stop En PCICLK_F1 Stop En PCICLK_F0 Stop En SRCCLK4 Stop En SRCCLK3 Stop En SRCCLK2 Stop En SRCCLK1 Stop En Control Function Free-Running Control, Default: not affected by PCI/SRC_STOP (Byte 4, bit 5) RESERVED 1412A—12/10/07 11 Integrated Circuit Systems, Inc. ICS932S422C SMBus Table: CPU and SRC Stop and Power Down Mode Drive Control Register Byte 4 Pin # Name Control Function Type Drive Mode in PD CPUCLK3 PD Drive RW 36,37 Bit 7 Drive Mode in PD CPUCLK2 PD Drive RW 39,40 Bit 6 Drive mode in PD CPUCLK1 PD Drive RW 42,43 Bit 5 Drive mode in PD 45,46 CPUCLK0 PD Drive RW Bit 4 RESERVED Bit 3 RESERVED Bit 2 RESERVED Bit 1 RESERVED Bit 0 0 Driven Driven Driven Driven 1 Hi-Z Hi-Z Hi-Z Hi-Z PWD 0 0 0 0 0 0 0 0 Type RW RW RW 0 Driven Driven Driven 1 Hi-Z Hi-Z Hi-Z PWD 0 0 0 0 0 0 0 0 Control Function Test Mode Selection Test Mode RESERVED 1X or 2X Stop non-free running PC and SRC clocks. Type RW RW 0 Hi-Z Disable 1 REF/N Enable RW 1X 2X PWD 0 0 0 1 RW Stop Run 1 FS_C FS_C readback R FS_B FS_B readback R FS_A FS_A readback R Control Function Type R R R R R R R R SMBus Table: Output and Spread Spectrum Control Register Byte 5 Pin # Name Control Function Drive Mode in PD CPUCLK4 PD Drive Bit 7 32,31 Driven in STOP SRC Stop Drive Mode SRC Bit 6 Driven in PD SRC PD Drive Mode SRC Bit 5 RESERVED Bit 4 RESERVED Bit 3 RESERVED Bit 2 RESERVED Bit 1 RESERVED Bit 0 SMBus Table: Device ID Register Byte 6 Pin # Name Test Mode Selection Bit 7 Test Clock Mode Entry Bit 6 Bit 5 REF Drive Strength 54,55 Bit 4 Bit 3 PCI, SRC Bit 2 Bit 1 Bit 0 SMBus Table: Byte 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - PCI_STOP Control Vendor & Revision ID Register Pin # Name RID3 RID2 RID1 RID0 VID3 VID2 VID1 VID0 REVISION ID VENDOR ID 1412A—12/10/07 12 Latch See 932S422 Functionality Table Latch Latch 0 - 1 - PWD 0 0 1 0 0 0 0 1 Integrated Circuit Systems, Inc. SMBus Table: Byte Count Register Byte 8 Pin # Name BC7 Bit 7 BC6 Bit 6 BC5 Bit 5 BC4 Bit 4 BC3 Bit 3 BC2 Bit 2 BC1 Bit 1 BC0 Bit 0 SMBus Table: Device ID Register Byte 9 Pin # Name DID7 Bit 7 DID6 Bit 6 DID5 Bit 5 DID4 Bit 4 DID3 Bit 3 DID2 Bit 2 DID1 Bit 1 DID0 Bit 0 ICS932S422C Control Function Type 0 1 PWD RW 0 RW 0 Writing to this register will RW 0 configure how many bytes will Byte Count Programming RW 0 be read back, default is 8 b(7:0) RW 1 bytes. RW 0 (0 to 7) RW 0 RW 0 Control Function Device ID (0C hex) SMBus Table: M/N Programming & Control Register Byte 10 Pin # Name Control Function CPU and SRC M/N_EN Bit 7 M/N Programming RESERVED Bit 6 Spread Spectrum CPU Spread Off/On Bit 5 Enable Spread Spectrum SRC Spread Off/On Bit 4 Enable Set SRC = 96 MHz and SRC Alternate PCI = 32 MHz SRC, PCI Frequency (96% of Bit 3 Only active if Nominal) Byte 10, bit 2 = 1 CPU Alternate Set alternate CPU Frequency (96% of frequency: CPU Nominal) Only active if Bit 2 166 MHz to 160 MHz latched frequency is 333 MHz to 320 MHz 166 MHz or 333 MHz. 1X or 2X REF1 Drive Strength 54 Bit 1 1X or 2X 55 REF0 Drive Strength Bit 0 1412A—12/10/07 13 Type R R R R R R R R 0 - 1 - PWD 0 0 0 0 1 1 0 0 Type 0 1 PWD RW Disable Enable 0 0 RW Spread Off Spread On 0 RW Spread Off Spread On 0 RW Normal Alternate Frequency 0 RW Normal Alternate Frequency 0 RW RW See REF Drive Strength Functionality Table 1 1 Integrated Circuit Systems, Inc. ICS932S422C SMBus Table: Byte 11 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CPU Frequency Control Register Pin # Name Control Function Type 0 1 PWD CPU N Div8 N Divider Prog bit 8 RW The decimal representation of X CPU N Div9 N Divider Prog bit 9 RW M and N Divider in Byte 11 and X CPU M Div5 RW 12 will configure the CPU VCO X CPU M Div4 RW X frequency. Default at power up = latch-in or Byte 0 Rom CPU M Div3 X M Divider Programming RW table. VCO Frequency = bit (5:0) CPU M Div2 RW X 14.318 x [NDiv(9:0)+8] / CPU M Div1 RW X [MDiv(5:0)+2] CPU M Div0 RW X SMBus Table: Byte 12 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CPU Frequency Control Register Pin # Name Control Function Type 0 1 PWD CPU N Div7 RW The decimal representation of X CPU N Div6 RW M and N Divider in Byte 11 and X CPU N Div5 RW 12 will configure the CPU VCO X N Divider Programming frequency. Default at power CPU N Div4 RW X Byte12 bit(7:0) and up = latch-in or Byte 0 Rom CPU N Div3 RW X Byte11 bit(7:6) table. VCO Frequency = CPU N Div2 RW X 14.318 x [NDiv(9:0)+8] / CPU N Div1 RW X [MDiv(5:0)+2] CPU N Div0 RW X SMBus Table: CPU Spread Spectrum Control Register Byte 13 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 SMBus Table: Byte 14 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # - Name CPU SSP7 CPU SSP6 CPU SSP5 CPU SSP4 CPU SSP3 CPU SSP2 CPU SSP1 CPU SSP0 Control Function Spread Spectrum Programming bit(7:0) Type 0 1 RW RW RW These Spread Spectrum bits in RW Byte 13 and 14 will program RW the spread pecentage of CPU RW RW RW PWD X X X X X X X X CPU Spread Spectrum Control Register Pin # Name Control Function Type 0 1 PWD 0 Reserved CPU SSP14 RW X CPU SSP13 RW X CPU SSP12 RW These Spread Spectrum bits in X Spread Spectrum CPU SSP11 RW X Byte 13 and 14 will program Programming bit(14:8) CPU SSP10 RW the spread pecentage of CPU X CPU SSP9 RW X CPU SSP8 RW X 1412A—12/10/07 14 Integrated Circuit Systems, Inc. ICS932S422C SMBus Table: Byte 15 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SRC Frequency Control Register Pin # Name Control Function Type 0 1 PWD SRC N Div8 N Divider Prog bit 8 RW The decimal representation of X SRC N Div9 N Divider Prog bit 9 RW M and N Divider in Byte 15 and X SRC M Div5 RW 16 will configure the SRC VCO X SRC M Div4 RW X frequency. Default at power up = latch-in or Byte 0 Rom SRC M Div3 X M Divider Programming RW table. VCO Frequency = bits SRC M Div2 RW X 14.318 x [NDiv(9:0)+8] / SRC M Div1 RW X [MDiv(5:0)+2] SRC M Div0 RW X SMBus Table: Byte 16 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SRC Frequency Control Register Pin # Name Control Function Type 0 1 PWD SRC N Div7 RW The decimal representation of X SRC N Div6 RW M and N Divider in Byte 15 and X SRC N Div5 RW 16 will configure the SRC VCO X N Divider Programming RW frequency. Default at power SRC N Div4 X b(7:0) up = latch-in or Byte 0 Rom SRC N Div3 RW X table. VCO Frequency = SRC N Div2 RW X 14.318 x [NDiv(9:0)+8] / SRC N Div1 RW X [MDiv(5:0)+2] SRC N Div0 RW X SMBus Table: Byte 17 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SRC Spread Spectrum Control Register Pin # Name Control Function SRC SSP7 SRC SSP6 SRC SSP5 SRC SSP4 Spread Spectrum Programming b(7:0) SRC SSP3 SRC SSP2 SRC SSP1 SRC SSP0 Type 0 1 PWD RW X RW X RW X These Spread Spectrum bits in RW X Byte 17 and 18 will program RW X the spread pecentage of SRC RW X RW X RW X SMBus Table: Byte 18 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SRC Spread Spectrum Control Register Pin # Name Control Function Reserved Reserved SRC SSP14 SRC SSP13 SRC SSP12 Spread Spectrum SRC SSP11 Programming b(14:8) SRC SSP10 SRC SSP9 SRC SSP8 Type 0 1 PWD R 0 RW X RW X RW These Spread Spectrum bits in X RW Byte 17 and 18 will program X RW the spread pecentage of SRC X RW X RW X 1412A—12/10/07 15 Integrated Circuit Systems, Inc. ICS932S422C SMBus Table: Byte 19 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CPU Programmable Output Divider Register Pin # Name Control Function CPUDiv3 CPU Divider Ratio CPUDiv2 Programming Bits CPUDiv1 CPUDiv0 RESERVED RESERVED RESERVED RESERVED SMBus Table: Byte 20 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SRC and PCI Programmable Output Divider Register Pin # Name Control Function PCIDiv3 PCI Divider Ratio PCIDiv2 Programming Bits PCIDiv1 PCIDiv0 SRC_Div3 SRC_ Divider Ratio SRC_Div2 Programming Bits SRC_Div1 SRC_Div0 SMBusTable: Test Byte Register Byte 21 Test Function Test ICS ONLY TEST Bit 7 ICS ONLY TEST Bit 6 ICS ONLY TEST Bit 5 ICS ONLY TEST Bit 4 ICS ONLY TEST Bit 3 ICS ONLY TEST Bit 2 ICS ONLY TEST Bit 1 ICS ONLY TEST Bit 0 Note: Do NOT write to Bit 21. Erratic device operation will result! 1412A—12/10/07 16 Type RW RW RW RW Type RW RW RW RW RW RW RW RW Type RW RW RW RW RW RW RW RW 0 1 See CPU, SRC and PCI Divider Ratios Table 0 1 See CPU, SRC and PCI Divider Ratios Table See CPU, SRC and PCI Divider Ratios Table Test Result Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PWD X X X X X X X X PWD X X X X X X X X PWD 0 0 0 0 0 0 0 0 Integrated Circuit Systems, Inc. ICS932S422C PD, Power Down PD is an asynchronous active high input used to shut off all clocks cleanly prior to system power down. When PD is asserted, all clocks will be driven low before turning off the VCO. All clocks will start without glitches when PD is PD CPU CPU # SRC SRC# PCIF/PCI USB REF Note 1 Normal Normal Normal Normal 33MHz 48MHz 14.318MHz 1 0 Iref * 2 or Float Float Iref * 2 or Float Float Low Low Low 1 Notes: 1. Refer to SMBus Byte 4 for additional information. PD Assertion PD should be sampled low by 2 consecutive CPU# rising edges before stopping clocks. All single ended clocks will be held low on their next high to low transition. All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven. When the drive mode corresponding to the CPU or SRC clock of interest is set to '0' the true clock will be driven high at 2 x Iref and the complementary clock will be tristated. If the control register is programmed to '1' both clocks will be tristated. See SMBus Byte 4 for additional information. PD CPU, 133MHz CPU#, 133MHz SRC, 100MHz SRC#, 100MHz USB, 48MHz PCI, 33MHz REF, 14.31818 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CPU, SRC and PCI Divider Ratios Div(3:0) Divider 0000 2 0001 3 0010 5 0011 15 0100 4 0101 6 0110 10 0111 30 1000 8 1001 12 1010 20 1011 60 1100 16 1101 24 1110 40 1111 120 REF Drive Strength Functionality Byte6, Byte 10, Byte 10, bit 4 bit 1 bit 0 REF1 0 X X 1x 1 0 0 1x 1 0 1 1x 1 1 0 2x 1 1 1 2x 1412A—12/10/07 17 REF0 1x 1x 2x 1x 2x Integrated Circuit Systems, Inc. ICS932S422C PD De-assertion The time from the de-assertion of PD or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive mode control bit for PD tristate is programmed to '1' the stopped differential pair must first be driven high to a minimum of 200mV in less than 300µs of PD deassertion. Tstable <1.8mS PWRDWN# CPU, 133MHz CPU#, 133MHz SRC, 100MHz SRC# 100MHz USB, 48MHz PCI, 33MHz REF, 14.31818 Tdrive_PwrDwn# <300µS, >200mV Test Clarification Table HW Comments SW 0 1 1 1 X 0 0 1 TEST ENTRY BIT B6b6 0 X X X 1 1 X 1 REF/N 0 X 1 0 HI-Z 0 X 1 1 REF/N FSLC/TES FSLB/TES T_SEL T_MODE HW PIN HW PIN Power-up w/ TEST_SEL = 1 to enter test mode Cycle power to disable test mode FSLC./TEST_SEL -->3-level latched input If power-up w/ V>2.0V (-0.3V) then use TEST_SEL If power-up w/ V<2.0V (-0.3V) then use FSLC FSLB/TEST_MODE -->low Vth input TEST_MODE is a real time input. If TEST_SEL HW pin is 0 during power-up, test mode can be invoked through B6b6. If test mode is invoked by B6b6, only B6b7 is used to select HI-Z or REF/N FSLB/TEST_Mode pin is not used. Cycle power to disable test mode, one shot control B6b6: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION) B6b7: 1= REF/N, Default = 0 (HI-Z) 1412A—12/10/07 18 REF/N or HI-Z B6b7 OUTPUT X NORMAL 0 HI-Z 1 REF/N 0 REF/N Integrated Circuit Systems, Inc. ICS932S422C c N 56-Lead, 300 mil Body, 25 mil, SSOP SYMBOL L E1 INDEX AREA A A1 b c D E E1 e h L N a E 1 2 α h x 45° D A In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° VARIATIONS A1 N -C- e In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0° 8° SEATING PLANE b 56 D mm. MIN 18.31 D (inch) MAX 18.55 Reference Doc.: JEDEC Publication 95, MO-118 .10 (.004) C 10-0034 Ordering Information ICS932S422CFLF-T Example: ICS XXXX C F LF- T Designation for tape and reel packaging Annealed Lead Free (optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 1412A—12/10/07 19 MIN .720 MAX .730 Integrated Circuit Systems, Inc. ICS932S422C c N L E1 INDEX AREA E 1 2 a D 56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS D 8.10 BASIC 0.319 BASIC E E1 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N a 0° 8° 0° 8° aaa -0.10 -.004 VARIATIONS A A2 N 56 A1 Ref erence Doc.: JEDEC Publicat ion 95, M O-153 -Ce D mm. MIN MAX 13.90 14.10 10-0039 SEATING PLANE b aaa C Ordering Information ICS932S422CGLF-T Example: ICS XXXX C G LF- T Designation for tape and reel packaging Annealed Lead Free (optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 1412A—12/10/07 20 D (inch) MIN .547 MAX .555 Integrated Circuit Systems, Inc. ICS932S422C Revision History Rev. A Issue Date Description 12/10/07 Initial Release Page # - 1412A—12/10/07 21