ICS9DB104 Integrated Circuit Systems, Inc. Four Output Differential Buffer for PCI-Express Output Features: • 4 - 0.7V current-mode differential output pairs • Supports zero delay buffer mode and fanout mode • Bandwidth programming available Key Specifications: • Outputs cycle-cycle jitter: < 50ps • Outputs skew: < 50ps • +/- 300ppm frequency accuracy on output clocks Features/Benefits: • Supports tight ppm accuracy clocks for Serial-ATA • Spread spectrum modulation tolerant, 0 to -0.5% down spread and +/- 0.25% center spread • Supports undriven differential output pair in PD# and SRC_STOP# for power management. 0767C—07/19/04 Pin Configuration VDD SRC_IN SRC_IN# GND VDD DIF_1 DIF_1# OE_1 DIF_2 DIF_2# VDD BYPASS#/PLL SCLK SDATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ICS9DB104 Recommended Application: DB400 Intel Yellow Cover part with PCI-Express support. 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDDA GNDA IREF GND VDD DIF_6 DIF_6# OE_6 DIF_5 DIF_5# VDD HIGH_BW# SRC_STOP# PD# 28-pin SSOP & TSSOP ICS9DB104 Integrated Circuit Systems, Inc. Pin Description PIN # PIN NAME PIN TYPE 1 2 3 4 5 6 7 VDD SRC_IN SRC_IN# GND VDD DIF_1 DIF_1# PWR IN IN PWR PWR OUT OUT 8 OE_1 9 10 11 DIF_2 DIF_2# VDD 12 BYPASS#/PLL IN 13 14 SCLK SDATA IN I/O 15 PD# IN 16 SRC_STOP# IN 17 HIGH_BW# IN 18 19 20 VDD DIF_5# DIF_5 21 OE_6 22 23 24 25 DIF_6# DIF_6 VDD GND OUT OUT PWR PWR 26 IREF OUT 27 28 GNDA VDDA PWR PWR IN OUT OUT PWR PWR OUT OUT IN DESCRIPTION Power supply, nominal 3.3V 0.7 V Differential SRC TRUE input 0.7 V Differential SRC COMPLEMENTARY input Ground pin. Power supply, nominal 3.3V 0.7V differential true clock outputs 0.7V differential complement clock outputs Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs 0.7V differential true clock outputs 0.7V differential complement clock outputs Power supply, nominal 3.3V Input to select Bypass(fan-out) or PLL (ZDB) mode 0 = Bypass mode, 1= PLL mode Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 5V tolerant. Asynchronous active low input pin used to power down the device. The internal clocks are disabled and the VCO and the crystal are stopped. Active low input to stop diff outputs. 3.3V input for selecting PLL Band Width 0 = High, 1= Low Power supply, nominal 3.3V 0.7V differential complement clock outputs 0.7V differential true clock outputs Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs 0.7V differential complement clock outputs 0.7V differential true clock outputs Power supply, nominal 3.3V Ground pin. This pin establishes the reference current for the differential currentmode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin for the PLL core. 3.3V power for the PLL core. 0767C—07/19/04 2 ICS9DB104 Integrated Circuit Systems, Inc. General Description ICS9DB104 follows the Intel DB400 Differential Buffer Specification. This buffer provides four SRC clocks for PCI-Express, next generation I/O devices. ICS9DB104 is driven by a differential input pair from a CK409/CK410 main clock generator, such as the ICS952601 or ICS954101. ICS9DB104 can run at speeds up to 200MHz. It provides ouputs meeting tight cycle-to-cycle jitter (50ps) and output-to-output skew (50ps) requirements. Block Diagram 2 OE1, OE6 SPREAD COMPATIBLE PLL SRC_IN SRC_IN# HIGH_BW# SRC_STOP# PD# BYPASS#/PLL SDATA SCLK STOP LOGIC 4 DIF(1,2,5,6) CONTROL LOGIC IREF Power Groups Pin Number VDD GND 1 4 5,11,18,24 4,25 28 27 28 27 Description SRC_IN/SRC_IN# DIF Outputs IREF Analog VDD & GND for PLL core 0767C—07/19/04 3 ICS9DB104 Integrated Circuit Systems, Inc. Absolute Max Symbol VDD_A VDD_In VIL VIH Ts Tambient Tcase ESD prot Parameter 3.3V Core Supply Voltage 3.3V Logic Supply Voltage Input Low Voltage Input High Voltage Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection human body model Min Max 4.6 4.6 GND-0.5 VDD+0.5V 150 70 115 -65 0 2000 Units V V V V ° C °C °C V Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Input High Voltage Input Low Voltage Input High Current SYMBOL VIH VIL IIH IIL1 Input Low Current IIL2 CONDITIONS MIN TYP 3.3 V +/-5% 2 GND - 0.3 3.3 V +/-5% VIN = VDD -5 VIN = 0 V; Inputs with no pull-up -5 resistors VIN = 0 V; Inputs with pull-up -200 resistors MAX UNITS NOTES VDD + 0.3 V 0.8 V 5 uA uA uA Operating Supply Current IDD3.3OP Full Active, CL = Full load; 200 mA Powerdown Current IDD3.3PD all diff pairs driven all differential pairs tri-stated 40 12 mA mA Input Frequency3 Fi VDD = 3.3 V 220 MHz 3 7 5 6 nH pF pF 1 1 1 4 MHz 1 2 MHz 1 1 ms 1,2 33 kHz 1 10 ns 1,3 300 us 1,3 5 ns 1 5 ns 2 Pin Inductance 1 80 100/133 166/200 Lpin CIN COUT Logic Inputs 1.5 1 Input Capacitance Output pin capacitance PLL Bandwidth when PLL_BW=0 PLL Bandwidth BW PLL Bandwidth when PLL_BW=1 From VDD Power-Up and after 1,2 TSTAB input clock stabilization or deClk Stabilization assertion of PD# to 1st clock Triangular Modulation 30 Modulation Frequency DIF output enable after Tdrive_SRC_STOP# SRC_Stop# de-assertion DIF output enable after Tdrive_PD# PD# de-assertion Fall time of PD# and Tfall SRC_STOP# Rise time of PD# and Trise SRC_STOP# 1 Guaranteed by design and characterization, not 100% tested in production. 2 See timing diagrams for timing requirements. 3 Time from deassertion until outputs are >200 mV 0767C—07/19/04 4 ICS9DB104 Integrated Circuit Systems, Inc. Electrical Characteristics - DIF 0.7V Current Mode Differential Pair TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω PARAMETER Current Source Output Impedance SYMBOL CONDITIONS MIN Zo VO = Vx 3000 Voltage High VHigh Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. 660 1 Voltage Low VLow Max Voltage Min Voltage Crossing Voltage (abs) Vovs Vuds Vcross(abs) Crossing Voltage (var) d-Vcross Long Accuracy ppm Average period Tperiod Absolute min period Tabsmin Rise Time Fall Time Rise Time Variation Fall Time Variation tr tf d-tr d-tf Variation of crossing over all edges see Tperiod min-max values 200MHz nominal 200MHz spread 166.66MHz nominal 166.66MHz spread 133.33MHz nominal 133.33MHz spread 100.00MHz nominal 100.00MHz spread 200MHz nominal 166.66MHz nominal/spread 133.33MHz nominal/spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V TYP MAX UNITS NOTES Ω 1 850 1,3 mV -150 150 1150 -300 250 4.9985 4.9985 5.9982 5.9982 7.4978 7.4978 9.9970 9.9970 4.8735 5.8732 7.3728 9.8720 175 175 1,3 550 mV 1 1 1 140 mV 1 0 5.0015 5.0266 6.0018 6.0320 7.5023 5.4000 10.0030 10.0533 ppm ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps 1,2 2 2 2 2 2 2 2 2 1,2 1,2 1,2 1,2 1 1 1 1 700 700 125 125 mV Measurement from differential 45 55 % wavefrom VT = 50% tsk3 50 ps Skew PLL mode, 50 ps Measurement from differential tjcyc-cyc Jitter, Cycle to cycle wavefrom BYPASS mode as additive jitter 50 ps 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that the input clock complies with CK409/CK410 accuracy requirements 3 IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω. Duty Cycle dt3 0767C—07/19/04 5 1 1 1 1 ICS9DB104 Integrated Circuit Systems, Inc. General SMBus serial interface information for the ICS9DB104 How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address DC (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • • • • • • • • Index Block Read Operation Index Block Write Operation Controller (Host) starT bit T Slave Address DC(H) WR WRite Controller (host) will send start bit. Controller (host) sends the write address DC (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address DD (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Controller (Host) T starT bit Slave Address DC(H) WR WRite ICS (Slave/Receiver) ICS (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address DD(H) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Byte N + X - 1 N P 0767C—07/19/04 6 Not acknowledge stoP bit ICS9DB104 Integrated Circuit Systems, Inc. SMBus Table: Frequency Select Register, READ/WRITE ADDRESS (DC/DD) Control Byte 0 Pin # Name Type 0 1 PWD Function PD# drive mode RW driven Hi-Z 0 Bit 7 SRC_Stop# drive RW driven Hi-Z 0 Bit 6 RW X Reserved Reserved Bit 5 RW X Reserved Reserved Bit 4 RW X Reserved Reserved Bit 3 1 RW High BW Low BW PLL_BW# adjust Bit 2 BYPASS#/PLL RW fan-out ZDB 1 Bit 1 RW div /2 x1 1 SRC_DIV# Bit 0 SMBus Table: Output Control Register Pin # Byte 1 Name Control Function Bit 7 - Bit 6 23,22 DIF_6 Bit 5 20,19 DIF_5 Bit 4 - Reserved Bit 3 - Reserved Bit 2 9,10 DIF_2 Bit 1 6,7 DIF_1 Bit 0 - Reserved Output Control Output Control Output Control Output Control Reserved Type RW 0 1 User should write '0' to minimize power PWD 1 RW Disable Enable 1 RW Disable Enable 1 User should write '0' to minimize power User should write '0' RW to minimize power RW 1 1 RW Disable Enable 1 RW Disable Enable 1 RW User should write '0' to minimize power 1 SMBus Table: Output Control Register Pin # Byte 2 Bit 7 - Bit 6 23,22 Bit 5 20,19 Bit 4 Bit 3 - Bit 2 9,10 Bit 1 6,7 Bit 0 - Control Function Reserved Output DIF_6 Control Output DIF_5 Control Reserved Reserved Output DIF_2 Control Output DIF_1 Control Reserved Name Type RW 0 1 Reserved PWD 0 RW Free-run Stoppable 0 RW Free-run Stoppable 0 RW RW 0 0 Reserved Reserved RW Free-run Stoppable 0 RW Free-run Stoppable 0 RW 0 0767C—07/19/04 7 Reserved ICS9DB104 Integrated Circuit Systems, Inc. SMBus Table: Output Control Register Byte 3 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Name Type 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RW RW RW RW RW RW RW RW SMBus Table: Vendor & Revision ID Register Control Byte 4 Pin # Name Type Function RID3 R Bit 7 REVISION RID2 R Bit 6 ID RID1 R Bit 5 RID0 R Bit 4 VID3 R Bit 3 VENDOR VID2 R Bit 2 ID VID1 R Bit 1 VID0 R Bit 0 1 PWD X X X X X X X X 0 1 PWD - - X X X X 0 0 0 1 0 1 PWD SMBus Table: DEVICE ID Byte 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # - Control Function Device ID 7 (MSB) Device ID 6 Device ID 5 Device ID 4 Device ID 3 Device ID 2 Device ID 1 Device ID 0 Name Type Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RW RW RW RW RW RW RW RW 0 0 0 0 1 0 0 0 SMBus Table: Byte Count Register Byte 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # - Name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Control Type Function RW Writing to RW this register RW configures RW how many RW bytes will RW be read RW back. RW 0767C—07/19/04 8 0 1 PWD - - 0 0 0 0 0 1 0 1 ICS9DB104 Integrated Circuit Systems, Inc. PD# The PD# pin cleanly shuts off all clocks and places the device into a power saving mode. PD# must be asserted before shutting off the input clock or power to insure an orderly shutdown. PD is asynchronous active-low input for both powering down the device and powering up the device. When PD# is asserted, all clocks will be driven high, or tri-stated (depending on the PD# drive mode and Output control bits) before the PLL is shut down. PD# Assertion When PD# is sampled low by two consecutive rising edges of DIF#, all DIF outputs must be held High, or tri-stated (depending on the PD# drive mode and Output control bits) on the next High-Low transition of the DIF# outputs. When the PD# drive mode bit is set to ‘0’, all clock outputs will be held with DIF driven High with 2 x IREF and DIF# tri-stated. If the PD# drive mode bit is set to ‘1’, both DIF and DIF# are tri-stated. PWRDWN# DIF DIF# PD# De-assertion Power-up latency is less than 1 ms. This is the time from de-assertion of the PD# pin, or VDD reaching 3.3V, or the time from valid SRC_IN clocks until the time that stable clocks are output from the device (PLL Locked). If the PD# drive mode bit is set to ‘1’, all the DIF outputs must driven to a voltage of >200 mV within 300 ms of PD# de-assertion. Tstable <1mS PWRDWN# DIF DIF# Tdrive_PwrDwn# <300uS, >200mV 0767C—07/19/04 9 ICS9DB104 Integrated Circuit Systems, Inc. SRC_STOP# The SRC_STOP# signal is an active-low asynchronous input that cleanly stops and starts the DIF outputs. A valid clock must be present on SRC_IN for this input to work properly. The SRC_STOP# signal is de-bounced and must remain stable for two consecutive rising edges of DIF# to be recognized as a valid assertion or de-assertion. SRC_STOP# - Assertion (transition from '1' to '0') Asserting SRC_STOP# causes all DIF outputs to stop after their next transition (if the control register settings allow the output to stop). When the SRC_STOP# drive bit is ‘0’, the final state of all stopped DIF outputs is DIF = High and DIF# = Low. There is no change in output drive current. DIF is driven with 6xIREF. DIF# is not driven, but pulled low by the termination. When the SRC_STOP# drive bit is ‘1’, the final state of all DIF output pins is Low. Both DIF and DIF# are not driven. SRC_STOP# - De-assertion (transition from '0' to '1') All stopped differential outputs resume normal operation in a glitch-free manner. The de-assertion latency to active outputs is 2-6 DIF clock periods, with all DIF outputs resuming simultaneously. If the SRC_STOP# drive control bit is ‘1’ (tri-state), all stopped DIF outputs must be driven High (>200 mV) within 10 ns of de-assertion. SRC_STOP_1 (SRC_Stop = Driven, PD = Driven) 1mS SRC_Stop# PWRDWN# DIF (Free Running) DIF# (Free Running) DIF (Stoppable) DIF# (Stoppable) SRC_STOP_2 (SRC_Stop =Tristate, PD = Driven) 1mS SRC_Stop# PWRDWN# DIF (Free Running) DIF# (Free Running) DIF (Stoppable) DIF# (Stoppable) 0767C—07/19/04 10 ICS9DB104 Integrated Circuit Systems, Inc. SRC_STOP_3 (SRC_Stop = Driven, PD = Tristate) 1mS SRC_Stop# PWRDWN# DIF (Free Running) DIF# (Free Running) DIF (Stoppable) DIF# (Stoppable) SRC_STOP_4 (SRC_Stop = Tristate, PD = Tristate) 1mS SRC_Stop# PWRDWN# DIF (Free Running) DIF# (Free Running) DIF (Stoppable) DIF# (Stoppable) 0767C—07/19/04 11 ICS9DB104 Integrated Circuit Systems, Inc. c N L E1 INDEX AREA E 1 2 α D A A2 A1 209 mil SSOP In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -2.00 -.079 A1 0.05 -.002 -A2 1.65 1.85 .065 .073 b 0.22 0.38 .009 .015 c 0.09 0.25 .0035 .010 SEE VARIATIONS SEE VARIATIONS D E 7.40 8.20 .291 .323 E1 5.00 5.60 .197 .220 0.65 BASIC 0.0256 BASIC e L 0.55 0.95 .022 .037 SEE VARIATIONS SEE VARIATIONS N α 0° 8° 0° 8° VARIATIONS -Ce SEATING PLANE b .10 (.004) C N 28 D mm. MIN 9.90 D (inch) MAX 10.50 MIN .390 Reference Doc.: JEDEC Publication 95, MO-150 10-0033 Ordering Information ICS9DB104yFLFT Example: ICS XXXX y F LF T Designation for tape and reel packaging Lead Free (optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 0767C—07/19/04 12 MAX .413 ICS9DB104 Integrated Circuit Systems, Inc. 4.40 mm. Body, 0.65 mm. Pitch TSSOP c N (173 mil) L E1 INDEX AREA SYMBOL A A1 A2 b c D E E1 e L N a aaa E 1 2 α D A A2 N 28 -Cb In Inches COMMON DIMENSIONS MIN MAX -.047 .002 .006 .032 .041 .007 .012 .0035 .008 SEE VARIATIONS 0.252 BASIC .169 .177 0.0256 BASIC .018 .030 SEE VARIATIONS 0° 8° -.004 VARIATIONS A1 e (25.6 mil) In Millimeters COMMON DIMENSIONS MIN MAX -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 SEE VARIATIONS 6.40 BASIC 4.30 4.50 0.65 BASIC 0.45 0.75 SEE VARIATIONS 0° 8° -0.10 SEATING PLANE aaa C D mm. MIN 9.60 D (inch) MAX 9.80 MIN .378 Reference Doc.: JEDEC Publication 95, MO-153 10-0035 Ordering Information ICS9DB104yGLFT Example: ICS XXXX y G LF T Designation for tape and reel packaging Lead Free (optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 0767C—07/19/04 13 MAX .386