IC63LV1024 Document Title 128K x 8 Hight Speed SRAM with 3.3V Central Power Revision History Revision No History Draft Date 0A 0B Initial Draft Add B (36-pin TF-BGA 6x8mm) and H (32-pin TSOP-1 8x13.4mm) package type To correct the TYPO error Obsolete "H" type September 12,2001 June 20,2002 0C 0D Remark October 16,2003 April 16,2004 The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. Integrated Circuit Solution Inc. AHSR025-0D 04/16/2004 1 IC63LV1024 128K x 8 HIGH-SPEED CMOS STATIC RAM 3.3V REVOLUTIONARY PINOUT FEATURES • High-speed access times: 8, 10, 12 and 15 ns • High-performance, low-power CMOS process • Multiple center power and ground pins for greater noise immunity • Easy memory expansion with CE and OE options • CE power-down • Fully static operation: no clock or refresh required • TTL compatible inputs and outputs • Single 3.3V power supply • Packages available: – 32-pin 300mil SOJ – 32-pin 400mil SOJ – 32-pin 400mil TSOP-2 – 36-pin TF-BGA (6mmx8mm) DESCRIPTION The ICSI IC63LV1024 is a very high-speed, low power, 131, 072-word by 8-bit CMOS static RAM in revolutionary pinout. The IC63LV1024 is fabricated using ICSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 250 µW (typical) with CMOS input levels. The IS63LV1024 operates from a single 3.3V power supply and all inputs are TTL-compatible. The IS63LV1024 is available in 32-pin 300mil SOJ, 400mil SOJ, 400mil TSOP-2 and 36-pin TF-BGA (6mmx8mm). FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 128K X 8 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VCC GND I/O0-I/O7 CE OE CONTROL CIRCUIT WE ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. 2 Integrated Circuit Solution Inc. AHSR025-0D 04/16/2004 IC63LV1024 PIN CONFIGURATION PIN CONFIGURATION 32-Pin SOJ 32-Pin TSOP-2 A0 1 32 A16 A1 2 31 A15 A2 3 30 A14 A3 4 29 A13 CE 5 28 OE I/O0 6 27 I/O7 I/O1 7 26 I/O6 Vcc 8 25 GND GND 9 24 Vcc I/O2 10 23 I/O5 I/O3 11 22 I/O4 WE 12 21 A12 A4 13 20 A11 A5 14 19 A10 A6 15 18 A9 A7 16 17 A8 A0 A1 A2 A3 CE I/O0 I/O1 Vcc GND I/O2 I/O3 WE A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE I/O7 I/O6 GND Vcc I/O5 I/O4 A12 A11 A10 A9 A8 PIN CONFIGURATION 36-Pin TF-BGA (TOP View) (6mm x 8mm) 1 2 3 4 5 6 A A0 A1 NC A3 A6 A8 B I/O4 A2 WE A4 A7 I/O0 C I/O5 NC A5 D GND Vcc E Vcc GND F I/O6 G I/O7 H A9 I/O1 NC NC OE CE A16 A15 I/O3 A10 A11 A12 A13 A14 Integrated Circuit Solution Inc. AHSR025-0D 04/16/2004 I/O2 3 IC63LV1024 PIN DESCRIPTIONS TRUTH TABLE WE A0-A16 Address Inputs Mode CE Chip Enable Input OE Output Enable Input WE Write Enable Input I/O1-I/O8 Bidirectional Ports Not Selected (Power-down) Output Disabled Read Write Vcc Power GND Ground CE OE X H X High-Z ISB1, ISB2 H H L L L L H L X High-Z DOUT DIN ICC1, ICC2 ICC1, ICC2 ICC1, ICC2 I/O Operation Vcc Current ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TBIAS TSTG PT Parameter Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation Value –0.5 to Vcc + 0.5 –55 to +125 –65 to +150 1.0 Unit V °C °C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 4 Integrated Circuit Solution Inc. AHSR025-0D 04/16/2004 IC63LV1024 OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 3.3V ± 0.3V 3.3V ± 0.3V DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 — V VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA — 0.4 V VIH Input HIGH Voltage 2.2 VCC + 0.3 V VIL Input LOW Voltage(1) –0.3 0.8 V ILI Input Leakage GND ≤ VIN ≤ VCC Com. Ind. –2 –5 2 5 µA ILO Output Leakage GND ≤ VOUT ≤ VCC, Outputs Disabled Com. Ind. –2 –5 2 5 µA Notes: 1. VIL = –3.0V for pulse width less than 10 ns. 2. The Vcc operating range for 8 ns is 3.3V +10%, -5%. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Test Conditions Min. -8 ns Max. -10 ns Min. Max. -12 ns Min. Max. -15 ns Min. Max. Unit ICC1 Vcc Operating Supply Current VCC = Max., CE = VIL IOUT = 0 mA, f = Max. Com. Ind. — — 160 170 — — 150 160 — — 140 150 — — 130 140 mA ISB1 TTL Standby Current (TTL Inputs) VCC = Max., VIN = VIH or VIL CE ≥ VIH, f = 0 Com. Ind. — — 30 40 — — 30 40 — — 30 40 — — 30 40 mA ISB2 CMOS Standby Current (CMOS Inputs) VCC = Max., CE ≤ VCC – 0.2V, VIN ≥ VCC – 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. — — 10 15 — — 10 15 — — 10 15 — — 10 15 mA Notes: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. CAPACITANCE(1,2) Symbol Parameter CIN Input Capacitance CI/O Input/Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V. Integrated Circuit Solution Inc. AHSR025-0D 04/16/2004 5 IC63LV1024 READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol -8 ns Min. Max. Parameter -10 ns Min. Max. -12 ns Min. Max. -15 ns Min. Max. Unit tRC Read Cycle Time 8 — 10 — 12 — 15 — ns tAA Address Access Time — 8 — 10 — 12 — 15 ns tOHA Output Hold Time 3 — 3 — 3 — 3 — ns tACE CE Access Time — 8 — 10 — 12 — 15 ns tDOE OE Access Time — 4 — 5 — 6 — 7 ns tLZOE(2) OE to Low-Z Output 0 — 0 — 0 — 0 — ns tHZOE(2) OE to High-Z Output 0 4 0 5 0 6 0 7 ns tLZCE CE to Low-Z Output 3 — 3 — 3 — 3 — ns CE to High-Z Output 0 4 0 5 0 6 0 7 ns (2) tHZCE (2) Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Levels Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1a and 1b Notes: 1. The Vcc operating range for 8 ns is 3.3V +10%, -5%. AC TEST LOADS 317 Ω ZOUT = 50 Ω 3.3V OUTPUT 50 Ω VT = 1.5V Figure 1a. 6 OUTPUT 351 Ω 5 pF Including jig and scope Figure 1b. Integrated Circuit Solution Inc. AHSR025-0D 04/16/2004 IC63LV1024 AC WAVEFORMS READ CYCLE NO. 1(1,2) t RC ADDRESS t AA t OHA t OHA DOUT DATA VALID PREVIOUS DATA VALID READ1.eps READ CYCLE NO. 2(1,3) t RC ADDRESS t AA t OHA OE t HZOE t DOE t LZOE CE t ACE t HZCE t LZCE DOUT HIGH-Z DATA VALID CE_RD2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions. Integrated Circuit Solution Inc. AHSR025-0D 04/16/2004 7 IC63LV1024 WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) Symbol -8 ns Min. Max. Parameter -10 ns Min. Max. -12 ns Min. Max. -15 ns Min. Max. Unit tWC Write Cycle Time 8 — 10 — 12 — 15 — ns tSCE CE to Write End 7 — 8 — 9 — 10 — ns tAW Address Setup Time to Write End 7 — 8 — 9 — 10 — ns tHA Address Hold from Write End 0 — 0 — 0 — 0 — ns tSA Address Setup Time 0 — 0 — 0 — 0 — ns tPWE(4) WE Pulse Width 7 — 8 — 9 — 10 — ns tSD Data Setup to Write End 4.5 — 6 — 6 — 7 — ns tHD Data Hold from Write End 0 — 0 — 0 — 0 — ns tHZWE(2) WE LOW to High-Z Output 0 4 0 5 0 6 0 7 ns tLZWE(2) WE HIGH to Low-Z Output 0 — 0 — 0 — 0 — ns Notes: 1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 4. Tested with OE HIGH. AC WAVEFORMS WRITE CYCLE NO. 1 (WE Controlled)(1,2) t WC VALID ADDRESS ADDRESS t SA t SCE t HA CE t AW t PWE1 t PWE2 WE t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID CE_WR1.eps 8 Integrated Circuit Solution Inc. AHSR025-0D 04/16/2004 IC63LV1024 WRITE CYCLE NO. 2 (CE Controlled)(1,2) t WC ADDRESS VALID ADDRESS t HA OE CE LOW t AW t PWE1 WE t SA DOUT t HZWE t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN CE_WR2.eps WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) t WC ADDRESS VALID ADDRESS OE LOW CE LOW t HA t AW t PWE2 WE t SA DOUT DATA UNDEFINED t HZWE t LZWE HIGH-Z t SD DIN t HD DATAIN VALID CE_WR3.eps Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE ≥ VIH. Integrated Circuit Solution Inc. AHSR025-0D 04/16/2004 9 IC63LV1024 ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed(ns) Order Part No. Package 8 8 8 8 IC63LV1024-8B IC63LV1024-8T IC63LV1024-8J IC63LV1024-8K 10 10 10 10 ORDERING INFORMATION Industrial Range: –40°C to +85°C Speed(ns) OrderPartNo. Package 6*8mm TF-BGA 400mil T SOP-2 300mil SOJ 400mil SOJ 8 8 8 8 IC63LV1024-8BI IC63LV1024-8TI IC63LV1024-8JI IC63LV1024-8KI 6*8mm TF-BGA 400mil T SOP-2 300mil SOJ 400mil SOJ IC63LV1024-10B IC63LV1024-10T IC63LV1024-10J IC63LV1024-10K 6*8mm TF-BGA 400mil T SOP-2 300mil SOJ 400mil SOJ 10 10 10 10 IC63LV1024-10BI IC63LV1024-10TI IC63LV1024-10JI IC63LV1024-10KI 6*8mm TF-BGA 400mil T SOP-2 300mil SOJ 400mil SOJ 12 12 12 12 IC63LV1024-12B IC63LV1024-12T IC63LV1024-12J IC63LV1024-12K 6*8mm TF-BGA 400mil T SOP-2 300mil SOJ 400mil SOJ 12 12 12 12 IC63LV1024-12BI IC63LV1024-12TI IC63LV1024-12JI IC63LV1024-12KI 6*8mm TF-BGA 400mil T SOP-2 300mil SOJ 400mil SOJ 15 15 15 15 IC63LV1024-15B IC63LV1024-15T IC63LV1024-15J IC63LV1024-15K 6*8mm TF-BGA 400mil T SOP-2 300mil SOJ 400mil SOJ 15 15 15 15 IC63LV1024-15BI IC63LV1024-15TI IC63LV1024-15JI IC63LV1024-15KI 6*8mm TF-BGA 400mil T SOP-2 300mil SOJ 400mil SOJ Integrated Circuit Solution Inc. HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw 10 Integrated Circuit Solution Inc. AHSR025-0D 04/16/2004