IS61C3216 IS61C3216 32K x 16 HIGH-SPEED CMOS STATIC RAM FEATURES • High-speed access time: 10, 12, 15, and 20 ns • CMOS low power operation — 450 mW (typical) operating — 250 µW (typical) standby • TTL compatible interface levels • Single 5V ± 10% power supply • I/O compatible with 3.3V device • Fully static operation: no clock or refresh required • Three state outputs • Industrial temperature available • Available in 44-pin 400mil SOJ package and 44-pin TSOP-2 DESCRIPTION The ICSI IS61C3216 is a high-speed, 512K static RAM 1 organized as 32,768 words by 16 bits. It is fabricated using ICSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields fast access times with low power consumption. 2 When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. 3 Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. 4 5 The IS61C3216 is packaged in the JEDEC standard 44-pin 400mil SOJ and 44-pin 400mil TSOP-2. 6 FUNCTIONAL BLOCK DIAGRAM 7 A0-A14 DECODER 32K x 16 MEMORY ARRAY 8 VCC 9 GND I/O0-I/O7 Lower Byte I/O DATA CIRCUIT I/O8-I/O15 Upper Byte COLUMN I/O 10 CE OE WE 11 CONTROL CIRCUIT UB LB 12 ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. Integrated Circuit Solution Inc. SR008-0B 1 IS61C3216 PIN CONFIGURATIONS 44-Pin TSOP-2 44-Pin SOJ NC 1 44 A0 A14 2 43 A1 A13 3 42 A2 A12 4 41 OE A11 5 40 UB CE 6 39 LB I/O0 7 38 I/O15 I/O1 8 37 I/O14 I/O2 9 36 I/O13 I/O3 10 35 I/O12 Vcc 11 34 GND GND 12 33 Vcc I/O4 13 32 I/O11 I/O5 14 31 I/O10 I/O6 15 30 I/O9 I/O7 16 29 I/O8 WE 17 28 NC A10 18 27 A3 A9 19 26 A4 A8 20 25 A5 A7 21 24 A6 NC 22 23 NC NC A14 A13 A12 A11 CE I/O0 I/O1 I/O2 I/O3 Vcc GND I/O4 I/O5 I/O6 I/O7 WE A10 A9 A8 A7 NC 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A0 A1 A2 OE UB LB I/O15 I/O14 I/O13 I/O12 GND Vcc I/O11 I/O10 I/O9 I/O8 NC A3 A4 A5 A6 NC PIN DESCRIPTIONS A0-A14 Address Inputs LB Lower-byte Control (I/O0-I/O7) I/O0-I/O15 Data Inputs/Outputs UB Upper-byte Control (I/O8-I/O15) CE Chip Enable Input NC No Connection OE Output Enable Input Vcc Power WE Write Enable Input GND Ground TRUTH TABLE Mode Not Selected Output Disabled Read Write 2 WE CE OE LB UB I/O0-I/O7 I/O8-I/O15 Vcc Current X H X H H H L L L H L L L L L L L L X H X L L L X X X X X H L H L L H L X X H H L L H L L High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN ISB1, ISB2 ICC ICC ICC Integrated Circuit Solution Inc. SR008-0B IS61C3216 ABSOLUTE MAXIMUM RATINGS(1) Symbol VCC VTERM TSTG PT IOUT Parameter Supply Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature Power Dissipation DC Output Current (LOW) Value –0.5 to +7.0 –0.5 to +7.0 –65 to +150 1.5 20 Unit V V °C W mA Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE Range Commercial Ambient Temperature 0°C to +70°C Industrial Speed -10, -12 -15, -20 -12 -15, -20 –40°C to +85°C 4 5 Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 — V VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA — 0.4 V VIH Input HIGH Voltage 2.2 VCC + 0.5 V –0.5 0.8 V Voltage(1) VIL Input LOW ILI Input Leakage GND < VIN < VCC –2 2 µA ILO Output Leakage GND < VOUT < VCC, Outputs Disabled –2 2 µA 6 7 Notes: 1. VIL (min.) = –3.0V for pulse width less than 10 ns. 8 POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -10 -12 Min. Max. Min. Max. -15 Min. Max. 9 -20 Min. Max. Unit Symbol Parameter Test Conditions ICC Vcc Dynamic Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX Com. Ind. — — 300 — — — 270 300 — — 250 270 — — 230 250 mA ISB1 TTL Standby Current (TTL Inputs) VCC = Max., VIN = VIH or VIL CE > VIH , f = 0 Com. Ind. — — 40 — — — 40 45 — — 40 45 — — 40 45 mA ISB2 CMOS Standby Current (CMOS Inputs) VCC = Max., CE > VCC – 0.2V, VIN > VCC – 0.2V, or VIN < 0.2V, f = 0 Com. Ind. — — 5 — — — 5 10 — — 5 10 — — 5 10 mA 10 11 12 Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. SR008-0B 2 3 VCC 5V ± 5% 5V ± 10% 5V ± 5% 5V ± 10% DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Integrated Circuit Solution Inc. 1 3 IS61C3216 CAPACITANCE(1) Symbol Parameter CIN Input Capacitance COUT Input/Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 8 pF Note: 1. Tested initially and after any design or process changes that may affect these parameters. READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol -10 Min. Max. Parameter -12 Min. Max. -15 Min. Max. -20 Min. Max. Unit tRC Read Cycle Time 10 — 12 — 15 — 20 — ns tAA Address Access Time — 10 — 12 — 15 — 20 ns tOHA Output Hold Time 3 — 3 — 3 — 3 — ns tACE CE Access Time — 10 — 12 — 15 — 20 ns OE Access Time — 5 — 5 — 7 — 8 ns OE to High-Z Output 0 5 0 6 0 7 — 8 ns tLZOE(2) OE to Low-Z Output 0 — 0 — 0 — 0 — ns tHZCE(2 CE to High-Z Output 0 5 0 6 0 7 0 8 ns CE to Low-Z Output 4 — 4 — 4 — 4 — ns tBA LB, UB Access Time — 5 — 6 — 7 — 8 ns tHZB LB, UB to High-Z Output 0 5 0 6 0 7 — 8 ns tLZB LB, UB to Low-Z Output 5 — 5 — 5 — 5 — ns tDOE tHZOE tLZCE (2) (2) Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1a and 1b AC TEST LOADS 480 Ω 5V OUTPUT OUTPUT 30 pF Including jig and scope Figure 1a. 4 480 Ω 5V 255 Ω 5 pF Including jig and scope 255 Ω Figure 1b. Integrated Circuit Solution Inc. SR008-0B IS61C3216 AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL) 1 tRC ADDRESS 2 tAA tOHA tOHA DOUT 3 DATA VALID PREVIOUS DATA VALID 4 READ CYCLE NO. 2(1,3) 5 tRC ADDRESS tAA tOHA 6 OE tHZOE tDOE 7 tLZOE CE tACE tHZCE tLZCE 8 LB, UB tBA DOUT HIGH-Z tHZB tLZB DATA VALID 9 Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = VIL. 3. Address is valid prior to or coincident with CE LOW transition. 10 11 12 Integrated Circuit Solution Inc. SR008-0B 5 IS61C3216 WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) Symbol Parameter -10 Min. Max. -12 Min. Max. -15 Min. Max. -20 Min. Max. Unit tWC Write Cycle Time 10 — 12 — 15 — 20 — ns tSCE CE to Write End 9 — 10 — 11 — 12 — ns tAW Address Setup Time to Write End 9 — 10 — 11 — 12 — ns tHA Address Hold from Write End 1 — 1 — 1 — 1 — ns tSA Address Setup Time 0 — 0 — 0 — 0 — ns tPWB LB, UB Valid to End of Write 9 — 10 — 11 — 12 — ns tPWE WE Pulse Width 7 — 8 — 10 — 11 — ns tSD Data Setup to Write End 5 — 6 — 7 — 8 — ns tHD Data Hold from Write End 0 — 0 — 0 — 0 — ns (2) tHZWE WE LOW to High-Z Output — 5 — 6 — 7 — 8 ns tLZWE(2) WE HIGH to Low-Z Output 1 — 1 — 1 — 1 — ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 6 Integrated Circuit Solution Inc. SR008-0B IS61C3216 AC WAVEFORMS WRITE CYCLE NO. 1 (WE WE Controlled)(1,2) 1 tWC 2 ADDRESS tHA tSCE 3 CE tPWB LB, UB 4 tAW tPWE WE 5 tSA WRITE (1) tSD 6 tHD DIN tHZWE DOUT HIGH-Z tLZWE UNDEFINED HIGH-Z 7 UNDEFINED 8 Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CE) [ (LB) = (UB) ] (WE). 9 10 11 12 Integrated Circuit Solution Inc. SR008-0B 7 IS61C3216 ORDERING INFORMATION Commercial Range: 0°C to +70°C ORDERING INFORMATION Industrial Range: –40°C to +85°C Speed (ns) Order Part No. Speed (ns) Order Part No. Package Package 10 IS61C3216-10T IS61C3216-10K 400mil TSOP-2 400mil SOJ 12 IS61C3216-12TI IS61C3216-12KI 400mil TSOP-2 400mil SOJ 12 IS61C3216-12T IS61C3216-12K 400mil TSOP-2 400mil SOJ 15 IS61C3216-15TI IS61C3216-15KI 400mil TSOP-2 400mil SOJ 15 IS61C3216-15T IS61C3216-15K 400mil TSOP-2 400mil SOJ 20 IS61C3216-20TI IS61C3216-20KI 400mil TSOP-2 400mil SOJ 20 IS61C3216-20T IS61C3216-20K 400mil TSOP-2 400mil SOJ Integrated Circuit Solution Inc. HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw 8 Integrated Circuit Solution Inc. SR008-0B