ISSI IS45S16100C1

ISSI
IS45S16100C1
512K Words x 16 Bits x 2 Banks (16-MBIT)
SYNCHRONOUS DYNAMIC RAM
FEATURES
• Clock frequency: 143 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Two banks can be operated simultaneously and
independently
• Dual internal bank controlled by A11
(bank select)
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and
precharge command
• Byte controlled by LDQM and UDQM
• Automotive Temperature Range
Option A: 0oC to +70oC
Option A1: -40oC to +85oC
• Packages: 400-mil 50-pin TSOP-II, 60-ball
fBGA
• Lead-free package option
®
JANUARY 2006
DESCRIPTION
ISSI’s 16Mb Synchronous DRAM IS45S16100C1 is
organized as a 524,288-word x 16-bit x 2-bank for
improved performance. The synchronous DRAMs
achieve high-speed data transfer using pipeline
architecture. All inputs and outputs signals refer to the
rising edge of the clock input.
PIN CONFIGURATIONS
50-Pin TSOP (Type II)
VDD
1
50
GND
DQ0
2
49
DQ15
DQ1
3
48
IDQ14
GNDQ
4
47
GNDQ
DQ2
5
46
DQ13
DQ3
6
45
DQ12
VDDQ
7
44
VDDQ
DQ4
8
43
DQ11
DQ5
9
42
DQ10
GNDQ
10
41
GNDQ
DQ6
11
40
DQ9
DQ7
12
39
DQ8
VDDQ
13
38
VDDQ
LDQM
14
37
NC
WE
15
36
UDQM
CAS
16
35
CLK
RAS
17
34
CKE
CS
18
33
NC
A11
19
32
A9
A10
20
31
A8
A0
21
30
A7
A1
22
29
A6
A2
23
28
A5
A3
24
27
A4
VDD
25
26
GND
PIN DESCRIPTIONS
A0-A11
Address Input
CAS
Column Address Strobe Command
A0-A10
Row Address Input
WE
Write Enable
A11
Bank Select Address
LDQM
Lower Bye, Input/Output Mask
A0-A7
Column Address Input
UDQM
Upper Bye, Input/Output Mask
DQ0 to DQ15
Data DQ
VDD
Power
CLK
System Clock Input
GND
Ground
CKE
Clock Enable
VDDQ
Power Supply for DQ Pin
CS
Chip Select
GNDQ
Ground for DQ Pin
RAS
Row Address Strobe Command
NC
No Connection
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
1
ISSI
IS45S16100C1
®
PIN CONFIGURATION
PACKAGE CODE: B 60 BALL FBGA (Top View) (10.1 mm x 6.4 mm Body, 0.65 mm Ball Pitch)
1 2 3 4 5 6 7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
VSS DQ15
DQ0
VDD
DQ14 VSSQ
VDDQ DQ1
DQ13 VDDQ
VSSQ DQ2
DQ12 DQ11
DQ4
DQ3
DQ10 VSSQ
VDDQ DQ5
DQ9 VDDQ
VSSQ DQ6
DQ8
NC
NC
DQ7
NC
NC
NC
NC
LDQM
WE
NC UDQM
NC
CLK
RAS
CAS
CKE
NC
NC
CS
A11
A9
NC
NC
A8
A7
A0
A10
A6
A5
A2
A1
VSS
A4
A3
VDD
PIN DESCRIPTIONS
2
A0-A10
Row Address Input
WE
Write Enable
A0-A7
Column Address Input
LDQM, UDQM
x16 Input/Output Mask
A11
Bank Select Address
VDD
Power
DQ0 to DQ15
Data I/O
Vss
Ground
CLK
System Clock Input
VDDQ
Power Supply for I/O Pin
CKE
Clock Enable
VssQ
Ground for I/O Pin
CS
Chip Select
NC
No Connection
RAS
Row Address Strobe Command
CAS
Column Address Strobe Command
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Rev. C
01/03/06
ISSI
IS45S16100C1
®
PIN FUNCTIONS
Pin No.
Symbol
Type
Function (In Detail)
20 to 24
27 to 32
A0-A10
Input Pin
A0 to A10 are address inputs. A0-A10 are used as row address inputs during active
command input and A0-A7 as column address inputs during read or write command
input. A10 is also used to determine the precharge mode during other commands. If
A10 is LOW during precharge command, the bank selected by A11 is precharged,
but if A10 is HIGH, both banks will be precharged.
When A10 is HIGH in read or write command cycle, the precharge starts
automatically after the burst access.
These signals become part of the OP CODE during mode register set command
input.
19
A11
Input Pin
A11 is the bank selection signal. When A11 is LOW, bank 0 is selected and when
high, bank 1 is selected. This signal becomes part of the OP CODE during mode
register set command input.
16
CAS
Input Pin
CAS, in conjunction with the RAS and WE, forms the device command. See the
“Command Truth Table” item for details on device commands.
34
CKE
Input Pin
The CKE input determines whether the CLK input is enabled within the device. When
is CKE HIGH, the next rising edge of the CLK signal will be valid, and when LOW,
invalid. When CKE is LOW, the device will be in either the power-down mode, the
clock suspend mode, or the self refresh mode. The CKE is an asynchronous input.
35
CLK
Input Pin
CLK is the master clock input for this device. Except for CKE, all inputs to this device
are acquired in synchronization with the rising edge of this pin.
18
CS
Input Pin
The CS input determines whether command input is enabled within the device.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The
device remains in the previous state when CS is HIGH.
2, 3, 5, 6, 8, 9, 11
12, 39, 40, 42, 43,
45, 46, 48, 49
DQ0 to
DQ15
DQ Pin
DQ0 to DQ15 are DQ pins. DQ through these pins can be controlled in byte units
using the LDQM and UDQM pins.
14, 36
LDQM,
UDQM
Input Pin
LDQM and UDQM control the lower and upper bytes of the DQ buffers. In read
mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW,
the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go
to the HIGH impedance state when LDQM/UDQM is HIGH. This function
corresponds to OE in conventional DRAMs. In write mode, LDQM and UDQM control
the input buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is
enabled, and data can be written to the device. When LDQM or UDQM is HIGH, input
data is masked and cannot be written to the device.
17
RAS
Input Pin
RAS, in conjunction with CAS and WE, forms the device command. See the
“Command Truth Table” item for details on device commands.
15
WE
Input Pin
WE, in conjunction with RAS and CAS, forms the device command. See the
“Command Truth Table” item for details on device commands.
7, 13, 38, 44
VDDQ
Power Supply Pin
VDDQ is the output buffer power supply.
1, 25
VDD
Power Supply Pin
VDD is the device internal power supply.
4, 10, 41, 47
GNDQ
Power Supply Pin
GNDQ is the output buffer ground.
26, 50
GND
Power Supply Pin
GND is the device internal ground.
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Rev. C
01/03/06
3
ISSI
IS45S16100C1
®
CLK
CKE
CS
RAS
CAS
WE
A11
COMMAND
DECODER
&
CLOCK
GENERATOR
MODE
REGISTER
11
ROW
ADDRESS
BUFFER
11
ROW DECODER
FUNCTIONAL BLOCK DIAGRAM
MEMORY CELL
ARRAY
2048
BANK 0
DQM
11
REFRESH
CONTROLLER
11
ROW
ADDRESS
LATCH
MULTIPLEXER
REFRESH
COUNTER
11
COLUMN
ADDRESS BUFFER
SELF
ROW
ADDRESS
BUFFER
11
ROW DECODER
8
REFRESH
CONTROLLER
BURST COUNTER
COLUMN
ADDRESS LATCH
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DATA IN
BUFFER
SENSE AMP I/O GATE
256
16
16
DQ 0-15
COLUMN DECODER
8
256
DATA OUT
BUFFER
SENSE AMP I/O GATE
16
2048
MEMORY CELL
ARRAY
16
VDD/VDDQ
GND/GNDQ
BANK 1
S16BLK.eps
4
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Rev. C
01/03/06
ISSI
IS45S16100C1
®
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Parameters
Rating
VDD MAX
Maximum Supply Voltage
–1.0 to +4.6 V
VDDQ MAX
Maximum Supply Voltage for Output Buffer
–1.0 to +4.6 V
VIN
Input Voltage
–1.0 to +4.6 V
VOUT
Output Voltage
–1.0 to +4.6 V
PD MAX
Allowable Power Dissipation
1
W
ICS
Output Shorted Current
50
mA
TOPR
Operating Temperature
0 to +70
-40 to +85
°C
°C
TSTG
Storage Temperature
A
A1
Unit
–55 to +150 °C
DC RECOMMENDED OPERATING CONDITIONS(2) (A: TA = 0°C to +70°C, A1: TA = -40°C to +85°C)
Symbol
VDD, VDDQ
VIH
VIL
Parameter
Supply Voltage
Input High Voltage(3)
Input Low Voltage(4)
Min.
3.0
2.0
-0.3
Typ.
3.3
—
—
Max.
3.6
VDD + 0.3
+0.8
Unit
V
V
V
CAPACITANCE CHARACTERISTICS(1,2) (At TA = 0 to +25°C, VDD = VDDQ = 3.3 ± 0.3V, f = 1 MHz)
Symbol
CIN1
CIN2
CI/O
Parameter
Input Capacitance: A0-A11
Input Capacitance: (CLK, CKE, CS, RAS, CAS, WE, LDQM, UDQM)
Data Input/Output Capacitance: DQ0-DQ15
Typ.
—
—
—
Max.
4
4
5
Unit
pF
pF
pF
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. All voltages are referenced to GND.
3. VIH (max) = VDDQ + 2.0V with a pulse width ≤ 3 ns.
4. VIL (min) = VDDQ - 2.0V with a pulse width ≤ 3 ns.
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Rev. C
01/03/06
5
ISSI
IS45S16100C1
®
DC ELECTRICAL CHARACTERISTICS (Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter
IIL
Input Leakage Current
ICC2P
Test Condition
0V ≤ VIN ≤ VDD, with pins other than
the tested pin at 0V
Output Leakage Current
Output is disabled, 0V ≤ VOUT ≤ VDD
Output High Voltage Level IOUT = –2 mA
Output Low Voltage Level IOUT = +2 mA
Operating Current(1,2)
One Bank Operation, CAS latency = 3
Burst Length=1
tRC ≥ tRC (min.)
IOUT = 0mA
Precharge Standby Current CKE ≤ VIL (MAX)
tCK = tCK (MIN)
ICC2PS
(In Power-Down Mode)
tCK = ∞
ICC3N
ICC3NS
Active Standby Current
CKE ≥ VIH (MIN)
(In Non Power-Down Mode) tCK = ∞
tCK = tCK (MIN)
ICC4
Operating Current
(In Burst Mode)(1)
CAS latency = 3
IOL
VOH
VOL
ICC1
tCK = tCK (MIN)
IOUT = 0mA
CAS latency = 2
ICC5
Auto-Refresh Current
tRC = tRC (MIN)
CAS latency = 3
CAS latency = 2
ICC6
Self-Refresh Current
CKE ≤ 0.2V
Speed
Min.
–5
Max.
5
Unit
µA
5
—
0.4
140
160
µA
V
V
mA
mA
3
4
2
3
40
30
30
130
150
130
150
70
90
70
90
1
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
A
A1
-7
-7
–5
2.4
—
—
—
A
A1
A
A1
—
—
—
—
—
—
—
-7
-7
-7
-7
-7
-7
-7
-7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
A
A1
A
A1
A
A1
A
A1
A
A1
Notes:
1. These are the values at the minimum cycle time. Since the currents are transient, these values decrease as the cycle time
increases. Also note that a bypass capacitor of at least 0.01 µF should be inserted between VDD and GND for each
memory chip to suppress power supply voltage noise (voltage drops) due to these transient currents.
2. Icc1 and Icc4 depend on the output load. The maximum values for Icc1 and Icc4 are obtained with the output open state.
6
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Rev. C
01/03/06
ISSI
IS45S16100C1
®
AC CHARACTERISTICS(1,2,3)
-7
Symbol Parameter
Min.
Max.
Units
tCK3
tCK2
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
7
8
—
—
ns
ns
tAC3
tAC2
Access Time From CLK(4)
CAS Latency = 3
CAS Latency = 2
—
—
5.5
6
ns
ns
tCHI
CLK HIGH Level Width
2.5
—
ns
tCL
CLK LOW Level Width
2.5
—
ns
tOH3
tOH2
Output Data Hold Time
2.0
2.5
—
—
ns
ns
tLZ
Output LOW Impedance Time
0
—
ns
tHZ3
tHZ2
tDS
Output HIGH Impedance Time(5)
Input Data Setup Time
—
—
2
5.5
6
—
ns
ns
ns
tDH
Input Data Hold Time
1
—
ns
tAS
Address Setup Time
2
—
ns
tAH
Address Hold Time
1
—
ns
tCKS
CKE Setup Time
2
—
ns
tCKH
CKE Hold Time
1
—
ns
tCKA
CKE to CLK Recovery Delay Time
1CLK+3
—
ns
tCS
Command Setup Time (CS, RAS, CAS, WE, DQM)
2
—
ns
tCH
Command Hold Time (CS, RAS, CAS, WE, DQM)
1
—
ns
tRC
Command Period (REF to REF / ACT to ACT)
63
—
ns
tRAS
Command Period (ACT to PRE)
42
100,000
ns
tRP
Command Period (PRE to ACT)
20
—
ns
tRCD
Active Command To Read / Write Command Delay Time
16
—
ns
tRRD
Command Period (ACT [0] to ACT[1])
14
—
ns
tDPL3
Input Data To Precharge
Command Delay time
CAS Latency = 3
1CLK
—
ns
tDPL2
CAS Latency = 2
1CLK
—
ns
tDAL3
1CLK+tRP
—
ns
tDAL2
Input Data To Active / Refresh
CAS Latency = 3
Command Delay time (During Auto-Precharge)
CAS Latency = 2
1CLK+tRP
—
ns
tT
Transition Time
1
10
ns
tREF
Refresh Cycle Time (4096)
—
64
ms
CAS Latency = 3
CAS Latency = 2
CAS Latency = 3
CAS Latency = 2
Notes:
1. When power is first applied, memory operation should be started 100 µs after VDD and VDDQ reach their stipulated voltages. Also note that the
power-on
sequence must be executed before starting memory operation.
2. Measured with tT = 1 ns.
3. The reference level is 1.4 V when measuring input signal timing. Rise and fall times are measured between VIH (min.) and VIL (max.).
4. Access time is measured at 1.4V with the load shown in the figure below.
5. The time tHZ (max.) is defined as the time required for the output voltage to transition by ± 200 mV from VOH (min.) or VOL (max.) when the
output is in the high impedance state.
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Rev. C
01/03/06
7
ISSI
IS45S16100C1
®
OPERATING FREQUENCY / LATENCY RELATIONSHIPS
SYMBOL
PARAMETER
-7
UNITS
—
Clock Cycle Time
7
ns
—
Operating Frequency
143
MHz
tCAC
CAS Latency
3
cycle
tRCD
Active Command To Read/Write Command Delay Time
3
cycle
tRAC
RAS Latency (tRCD + tCAC)
6
cycle
tRC
Command Period (REF to REF / ACT to ACT)
9
cycle
tRAS
Command Period (ACT to PRE)
6
cycle
tRP
Command Period (PRE to ACT)
3
cycle
tRRD
Command Period (ACT[0] to ACT [1])
3
cycle
tCCD
Column Command Delay Time
(READ, READA, WRIT, WRITA)
1
cycle
tDPL
Input Data To Precharge Command Delay Time
1
cycle
tDAL
Input Data To Active/Refresh Command Delay Time
(During Auto-Precharge)
4
cycle
tRBD
Burst Stop Command To Output in HIGH-Z Delay Time
(Read)
3
cycle
tWBD
Burst Stop Command To Input in Invalid Delay Time
(Write)
0
cycle
tRQL
Precharge Command To Output in HIGH-Z Delay Time
(Read)
3
cycle
tWDL
Precharge Command To Input in Invalid Delay Time
(Write)
0
cycle
tPQL
Last Output To Auto-Precharge Start Time (Read)
–1
cycle
tQMD
DQM To Output Delay Time (Read)
2
cycle
tDMD
DQM To Input Delay Time (Write)
0
cycle
tMCD
Mode Register Set To Command Delay Time
2
cycle
AC TEST CONDITIONS (Input/Output Reference Level: 1.4V)
Output Load
Input
tCHI
tCK
tCL
50 Ω
2.8V
CLK
1.4V
0.0V
tCS
+1.4V
I/O
tCH
2.8V
INPUT 1.4V
0.0V
OUTPUT
8
50 pF
tAC
tOH
1.4V
1.4V
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Rev. C
01/03/06
ISSI
IS45S16100C1
®
COMMANDS
Active Command
Read Command
CLK
CLK
CKE
HIGH
CKE
CS
CS
RAS
RAS
CAS
CAS
WE
WE
A0-A9
ROW
A0-A9
A10
ROW
A10
HIGH
COLUMN (1)
AUTO PRECHARGE
NO PRECHARGE
BANK 1
A11
BANK 1
A11
BANK 0
Write Command
BANK 0
Precharge Command
CLK
CLK
CKE HIGH
CKE HIGH
CS
CS
RAS
RAS
CAS
CAS
WE
WE
A0-A9
COLUMN(1)
A0-A9
BANK 0 AND BANK 1
AUTO PRECHARGE
A10
A10
NO PRECHARGE
BANK 0 OR BANK 1
BANK 1
BANK 1
A11
A11
BANK 0
BANK 0
Don't Care
Notes:
1. A8-A9 = Don’t Care.
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Rev. C
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9
ISSI
IS45S16100C1
®
COMMANDS (cont.)
No-Operation Command
Device Deselect Command
CLK
CLK
CKE HIGH
CKE HIGH
CS
CS
RAS
RAS
CAS
CAS
WE
WE
A0-A9
A0-A9
A10
A10
A11
A11
Mode Register Set Command
CLK
CKE
Auto-Refresh Command
CLK
HIGH
CKE
CS
CS
RAS
RAS
CAS
CAS
WE
WE
A0-A9
OP-CODE
A0-A9
A10
OP-CODE
A10
A11
OP-CODE
A11
HIGH
Don't Care
10
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Rev. C
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ISSI
IS45S16100C1
®
COMMANDS (cont.)
Self-Refresh Command
Power Down Command
CLK
CLK
CKE
CKE
CS
CS
NOP
RAS
RAS
NOP
CAS
CAS
NOP
WE
WE
A0-A9
A0-A9
A10
A10
A11
A11
Clock Suspend Command
Burst Stop Command
CLK
CKE
BANK(S) ACTIVE
CKE
NOP
CS
RAS
NOP
RAS
CAS
NOP
CAS
NOP
HIGH
WE
A0-A9
A0-A9
A10
A10
A11
A11
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Rev. C
01/03/06
NOP
CLK
CS
WE
ALL BANKS IDLE
11
ISSI
IS45S16100C1
®
Mode Register Set Command
(CS, RAS, CAS, WE = LOW)
The IS45S16100C1 product incorporates a register that
defines the device operating mode. This command
functions as a data input pin that loads this register from
the pins A0 to A11. When power is first applied, the
stipulated power-on sequence should be executed and
then the IS45S16100C1 should be initialized by executing
a mode register set command.
Note that the mode register set command can be executed
only when both banks are in the idle state (i.e. deactivated).
Another command cannot be executed after a mode
register set command until after the passage of the period
tMCD, which is the period required for mode register set
command execution.
When the A10 pin is HIGH, this command functions as a
read with auto-precharge command. After the burst read
completes, the bank selected by pin A11 is precharged.
When the A10 pin is LOW, the bank selected by the A11 pin
remains in the activated state after the burst read completes.
Write Command
(CS, CAS, WE = LOW, RAS = HIGH)
When burst write mode has been selected with the mode
register set command, this command selects the bank
specified by the A11 pin and starts a burst write operation
at the start address specified by pins A0 to A9. This first
data must be input to the DQ pins in the cycle in which this
command.
The selected bank must be activated before executing this
command.
Active Command
(CS, RAS = LOW, CAS, WE= HIGH)
The IS45S16100C1 includes two banks of 4096 rows
each. This command selects one of the two banks
according to the A11 pin and activates the row selected
by the pins A0 to A10.
This command corresponds to the fall of the RAS signal
from HIGH to LOW in conventional DRAMs.
Precharge Command
When A10 pin is HIGH, this command functions as a write
with auto-precharge command. After the burst write
completes, the bank selected by pin A11 is precharged.
When the A10 pin is low, the bank selected by the A11 pin
remains in the activated state after the burst write completes.
After the input of the last burst write data, the application
must wait for the write recovery period (tDPL, tDAL) to elapse
according to CAS latency.
Auto-Refresh Command
(CS, RAS, WE = LOW, CAS = HIGH)
(CS, RAS, CAS = LOW, WE, CKE = HIGH)
This command starts precharging the bank selected by
pins A10 and A11. When A10 is HIGH, both banks are
precharged at the same time. When A10 is LOW, the bank
selected by A11 is precharged. After executing this
command, the next command for the selected bank(s) is
executed after passage of the period tRP, which is the
period required for bank precharging.
This command corresponds to the RAS signal from LOW
to HIGH in conventional DRAMs
This command executes the auto-refresh operation. The
row address and bank to be refreshed are automatically
generated during this operation.
Both banks must be placed in the idle state before executing
this command.
The stipulated period (tRC) is required for a single refresh
operation, and no other commands can be executed during
this period.
The device goes to the idle state after the internal refresh
operation completes.
Read Command
This command must be executed at least 4096 times every
128 ms.
(CS, CAS = LOW, RAS, WE = HIGH)
This command selects the bank specified by the A11 pin
and starts a burst read operation at the start address
specified by pins A0 to A9. Data is output following CAS
latency.
This command corresponds to CBR auto-refresh in
conventional DRAMs.
The selected bank must be activated before executing
this command.
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
ISSI
IS45S16100C1
®
Self-Refresh Command
Power-Down Command
(CS, RAS, CAS, CKE = LOW, WE = HIGH)
(CKE = LOW)
This command executes the self-refresh operation. The
row address to be refreshed, the bank, and the refresh
interval are generated automatically internally during this
operation. The self-refresh operation is started by dropping
the CKE pin from HIGH to LOW. The self-refresh operation
continues as long as the CKE pin remains LOW and there
is no need for external control of any other pins. The
self-refresh operation is terminated by raising the CKE pin
from LOW to HIGH. The next command cannot be executed
until the device internal recovery period (tRC) has elapsed.
After the self-refresh, since it is impossible to determine
the address of the last row to be refreshed, an auto-refresh
should immediately be performed for all addresses (4096
cycles).
When both banks are in the idle (inactive) state, or when
at least one of the banks is not in the idle (inactive) state,
this command can be used to suppress device power
dissipation by reducing device internal operations to the
absolute minimum. Power-down mode is started by dropping
the CKE pin from HIGH to LOW. Power-down mode
continues as long as the CKE pin is held low. All pins other
than the CKE pin are invalid and none of the other
commands can be executed in this mode. The powerdown operation is terminated by raising the CKE pin from
LOW to HIGH. The next command cannot be executed
until the recovery period (tCKA) has elapsed.
Both banks must be placed in the idle state before
executing this command.
Since this command differs from the self-refresh command
described above in that the refresh operation is not
performed automatically internally, the refresh operation
must be performed within the refresh period (tREF). Thus
the maximum time that power-down mode can be held is
just under the refresh cycle time.
Burst Stop Command
(CS, WE, = LOW, RAS, CAS = HIGH)
The command forcibly terminates burst read and write
operations. When this command is executed during a
burst read operation, data output stops after the CAS
latency period has elapsed.
No Operation
(CS, = LOW, RAS, CAS, WE = HIGH)
This command has no effect on the device.
Device Deselect Command
(CS = HIGH)
This command does not select the device for an object of
operation. In other words, it performs no operation with
respect to the device.
Clock Suspend
(CKE = LOW)
This command can be used to stop the device internal
clock temporarily during a read or write cycle. Clock
suspend mode is started by dropping the CKE pin from
HIGH to LOW. Clock suspend mode continues as long as
the CKE pin is held LOW. All input pins other than the CKE
pin are invalid and none of the other commands can be
executed in this mode. Also note that the device internal
state is maintained. Clock suspend mode is terminated by
raising the CKE pin from LOW to HIGH, at which point
device operation restarts. The next command cannot be
executed until the recovery period (tCKA) has elapsed.
Since this command differs from the self-refresh command
described above in that the refresh operation is not
performed automatically internally, the refresh operation
must be performed within the refresh period (tREF). Thus
the maximum time that clock suspend mode can be held
is just under the refresh cycle time.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
13
ISSI
IS45S16100C1
®
COMMAND TRUTH TABLE(1,2)
Symbol Command
MRS
Mode Register Set(3,4)
REF
Auto-Refresh(5)
SREF
Self-Refresh(5,6)
PRE
Precharge Selected Bank
PALL
Precharge Both Banks
ACT
Bank Activate(7)
WRIT
Write
WRITA
Write With Auto-Precharge(8)
READ
Read(8)
READA
Read With Auto-Precharge(8)
BST
Burst Stop(9)
NOP
No Operation
DESL
Device Deselect
SBY
Clock Suspend / Standby Mode
ENB
Data Write / Output Enable
MASK
Data Mask / Output Disable
CKE
n-1 n
H
X
H
H
H
L
H
X
H
X
H
X
H
X
H
X
H
X
H
X
H
X
H
X
H
X
L
X
H
X
H
X
CS RAS CAS
L
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
L
H
L
H
L
L
H
L
L
H
L
L
H
L
L
H
H
L
H
H
H
X
X
X
X
X
X
X
X
X
X
X
WE DQM
L
X
H
X
H
X
L
X
L
X
H
X
L
X
L
X
H
X
H
X
L
X
H
X
X
X
X
X
X
L
X
H
A11 A10 A9-A0 I/On
OP CODE
X
X
X
X
HIGH-Z
X
X
X
HIGH-Z
BS
L
X
X
X
H
X
X
BS Row Row
X
BS
L Column(18) X
BS
H Column(18) X
BS
L Column(18) X
BS
H Column(18) X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Active
X
X
X
HIGH-Z
DQM TRUTH TABLE(1,2)
CKE
Symbol
ENB
MASK
ENBU
ENBL
MASKU
MASKL
Command
Data Write / Output Enable
Data Mask / Output Disable
Upper Byte Data Write / Output Enable
Lower Byte Data Write / Output Enable
Upper Byte Data Mask / Output Disable
Lower Byte Data Mask / Output Disable
n-1
H
H
H
H
H
H
n
X
X
X
X
X
X
DQM
UPPER
LOWER
L
L
H
H
L
X
X
L
H
X
X
H
CKE TRUTH TABLE(1,2)
14
Symbol
SPND
—
—
REF
SELF
SELFX
Command
Start Clock Suspend Mode
Clock Suspend
Terminate Clock Suspend Mode
Auto-Refresh
Start Self-Refresh Mode
Terminate Self-Refresh Mode
Current State
Active
Other States
Clock Suspend
Idle
Idle
Self-Refresh
PDWN
Start Power-Down Mode
Idle
—
Terminate Power-Down Mode
Power-Down
CKE
n-1 n
H
L
L
L
L
H
H
H
H
L
L
H
L
H
H
L
H
L
L
H
CS RAS CAS
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
H
H
H
X
X
L
H
H
H
X
X
X
X
X
WE A11 A10 A9-A0
X
X
X
X
X
X
X
X
X
X
X
X
H
X
X
X
H
X
X
X
H
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
X
X
X
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
ISSI
IS45S16100C1
®
OPERATION COMMAND TABLE(1,2)
Current State Command
Idle
DESL
NOP
BST
READ / READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
Row Active
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
Read
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
Write
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
Read With
DESL
AutoNOP
Precharge
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
CS RAS CAS WE A11 A10 A9-A0
Operation
No Operation or Power-Down(12)
H
X
X
X
X
X
X
(12)
No Operation or Power-Down
L
H
H
H
X
X
X
No Operation or Power-Down
L
H
H
L
X
X
X
Illegal
L
H
L
H
V
V V(18)
Illegal
L
H
L
L
V
V V(18)
Row Active
L
L
H
H
V
V V(18)
No Operation
L
L
H
L
V
V
X
(13)
Auto-Refresh or Self-Refresh
L
L
L
H
X
X
X
Mode Register Set
L
L
L
L
OP CODE
No Operation
H
X
X
X
X
X
X
No Operation
L
H
H
H
X
X
X
No Operation
L
H
H
L
X
X
X
Read Start(17)
L
H
L
H
V
V V(18)
Write Start(17)
L
H
L
L
V
V V(18)
Illegal(10)
L
L
H
H
V
V V(18)
(15)
Precharge
L
L
H
L
V
V
X
Illegal
L
L
L
H
X
X
X
Illegal
L
L
L
L
OP CODE
Burst Read Continues, Row Active When Done
H
X
X
X
X
X
X
Burst Read Continues, Row Active When Done
L
H
H
H
X
X
X
Burst Interrupted, Row Active After Interrupt
L
H
H
L
X
X
X
(16)
Burst Interrupted, Read Restart After Interrupt
L
H
L
H
V
V V(18)
(11,16)
Burst Interrupted Write Start After Interrupt
L
H
L
L
V
V V(18)
(10)
Illegal
L
L
H
H
V
V V(18)
Burst Read Interrupted, Precharge After Interrupt
L
L
H
L
V
V
X
Illegal
L
L
L
H
X
X
X
Illegal
L
L
L
L
OP CODE
Burst Write Continues, Write Recovery When Done H
X
X
X
X
X
X
Burst Write Continues, Write Recovery When Done L
H
H
H
X
X
X
Burst Write Interrupted, Row Active After Interrupt
L
H
H
L
X
X
X
Burst Write Interrupted, Read Start After Interrupt(11,16) L
H
L
H
V
V V(18)
Burst Write Interrupted, Write Restart After Interrupt(16) L
H
L
L
V
V V(18)
Illegal(10)
L
L
H
H
V
V V(18)
Burst Write Interrupted, Precharge After Interrupt
L
L
H
L
V
V
X
Illegal
L
L
L
H
X
X
X
Illegal
L
L
L
L
OP CODE
Burst Read Continues, Precharge When Done
H
X
X
X
X
X
X
Burst Read Continues, Precharge When Done
L
H
H
H
X
X
X
Illegal
L
H
H
L
X
X
X
Illegal
L
H
L
H
V
V V(18)
Illegal
L
H
L
L
V
V V(18)
(10)
Illegal
L
L
H
H
V
V V(18)
(10)
Illegal
L
L
H
L
V
V
X
Illegal
L
L
L
H
X
X
X
Illegal
L
L
L
L
OP CODE
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
15
ISSI
IS45S16100C1
®
OPERATION COMMAND TABLE(1,2)
Current State Command
Write With
DESL
Auto-Precharge
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
Row Precharge DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
Immediately
DESL
Following
NOP
Row Active
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
Write
Recovery
16
CS RAS CAS WE A11 A10 A9-A0
Operation
Burst Write Continues, Write Recovery And Precharge
When Done
H
X
X
X
X
X
X
Burst Write Continues, Write Recovery And Precharge
L
H
H
H
X
X
X
Illegal
Illegal
Illegal
Illegal(10)
Illegal(10)
Illegal
Illegal
No Operation, Idle State After tRP Has Elapsed
No Operation, Idle State After tRP Has Elapsed
No Operation, Idle State After tRP Has Elapsed
Illegal(10)
Illegal(10)
Illegal(10)
No Operation, Idle State After tRP Has Elapsed(10)
Illegal
Illegal
No Operation, Row Active After tRCD Has Elapsed
No Operation, Row Active After tRCD Has Elapsed
No Operation, Row Active After tRCD Has Elapsed
Illegal(10)
Illegal(10)
Illegal(10,14)
Illegal(10)
Illegal
Illegal
L
L
L
L
L
L
L
H
L
H
H
H
L
L
L
L
X
H
H
L
L
H
H
L
L
X
H
L
H
L
H
L
H
L
X
H
X
V
V
V
V
X
X
X
V V(18)
V V(18)
V V(18)
V
X
X
X
OPCODE
X
X
X
X
X
X
L
H
H
L
X
X
V(18)
V(18)
V(18)
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
H
L
L
L
L
X
H
H
H
H
L
L
L
L
L
H
H
L
L
X
H
H
L
L
H
H
L
H
L
H
L
H
L
X
H
L
H
L
H
L
H
V
V
V
V
X
X
X
OP CODE
X
X
X
X
X
X
X
X
X
(18)
V
V V
V
V V(18)
V
V V(18)
V
V
X
X
X
X
L
No Operation, Row Active After tDPL Has ElapsedH
No Operation, Row Active After tDPL Has Elapsed L
L
X
H
L
X
H
L
X
H
X
X
BST
No Operation, Row Active After tDPL Has Elapsed L
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
Read Start
Write Restart
Illegal(10)
Illegal(10)
Illegal
Illegal
H
H
H
L
L
L
L
H
L
L
H
H
L
L
L
H
L
H
L
H
L
X
X
X
V
V V(18)
V
V V(18)
V
V V(18)
V
V
X
X
X
X
OP CODE
DESL
NOP
L
L
L
L
L
L
V
V
V
V
X
X
OP CODE
X
X
X
X
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
ISSI
IS45S16100C1
®
OPERATION COMMAND TABLE(1,2)
Current State
Write Recovery
With AutoPrecharge
Command
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
Refresh
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
Mode Register DESL
Set
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
Operation
No Operation, Idle State After tDAL Has Elapsed
No Operation, Idle State After tDAL Has Elapsed
No Operation, Idle State After tDAL Has Elapsed
Illegal(10)
Illegal(10)
Illegal(10)
Illegal(10)
Illegal
Illegal
No Operation, Idle State After tRP Has Elapsed
No Operation, Idle State After tRP Has Elapsed
No Operation, Idle State After tRP Has Elapsed
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
No Operation, Idle State After tMCD Has Elapsed
No Operation, Idle State After tMCD Has Elapsed
No Operation, Idle State After tMCD Has Elapsed
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
CS RAS CAS WE A11 A10 A9-A0
H
X
X
X
X
X
X
L
H
H
H
X
X
X
L
H
H
L
X
X
X
L
H
L
H
V
V V(18)
L
H
L
L
V
V V(18)
L
L
H
H
V
V V(18)
L
L
H
L
V
V
X
L
L
L
H
X
X
X
L
L
L
L
OP CODE
H
X
X
X
X
X
X
L
H
H
H
X
X
X
L
H
H
L
X
X
X
L
H
L
H
V
V V(18)
L
H
L
L
V
V V(18)
L
L
H
H
V
V V(18)
L
L
H
L
V
V
X
L
L
L
H
X
X
X
L
L
L
L
OP CODE
H
X
X
X
X
X
X
L
H
H
H
X
X
X
L
H
H
L
X
X
X
L
H
L
H
V
V V(18)
L
H
L
L
V
V V(18)
L
L
H
H
V
V V(18)
L
L
H
L
V
V
X
L
L
L
H
X
X
X
L
L
L
L
OP CODE
Notes:
1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input, V: Valid data input
2. All input signals are latched on the rising edge of the CLK signal.
3. Both banks must be placed in the inactive (idle) state in advance.
4. The state of the A0 to A11 pins is loaded into the mode register as an OP code.
5. The row address is generated automatically internally at this time. The DQ pin and the address pin data is ignored.
6. During a self-refresh operation, all pin data (states) other than CKE is ignored.
7. The selected bank must be placed in the inactive (idle) state in advance.
8. The selected bank must be placed in the active state in advance.
9. This command is valid only when the burst length set to full page.
10. This is possible depending on the state of the bank selected by the A11 pin.
11. Time to switch internal busses is required.
12. The IS45S16100C1 can be switched to power-down mode by dropping the CKE pin LOW when both banks in the idle
state. Input pins other than CKE are ignored at this time.
13. The IS45S16100C1 can be switched to self-refresh mode by dropping the CKE pin LOW when both banks in the idle state.
Input pins other than CKE are ignored at this time.
14. Possible if tRRD is satisfied.
15. Illegal if tRAS is not satisfied.
16. The conditions for burst interruption must be observed. Also note that the IS45S16100C1 will enter the precharged state
immediately after the burst operation completes if auto-precharge is selected.
17. Command input becomes possible after the period tRCD has elapsed. Also note that the IS45S16100C1 will enter the
precharged state immediately after the burst operation completes if auto-precharge is selected.
18. A8,A9 = don’t care.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
17
ISSI
IS45S16100C1
®
CKE RELATED COMMAND TRUTH TABLE(1)
Current State
Self-Refresh
Operation
Undefined
Self-Refresh Recovery(2)
Self-Refresh Recovery(2)
Illegal(2)
Illegal(2)
Self-Refresh
Self-Refresh Recovery Idle State After tRC Has Elapsed
Idle State After tRC Has Elapsed
Illegal
Illegal
Power-Down on the Next Cycle
Power-Down on the Next Cycle
Illegal
Illegal
Clock Suspend Termination on the Next Cycle (2)
Clock Suspend
Power-Down
Undefined
Power-Down Mode Termination, Idle After
That Termination(2)
Power-Down Mode
Both Banks Idle
No Operation
See the Operation Command Table
Bank Active Or Precharge
Auto-Refresh
Mode Register Set
See the Operation Command Table
See the Operation Command Table
See the Operation Command Table
Self-Refresh(3)
See the Operation Command Table
Power-Down Mode(3)
Other States
See the Operation Command Table
Clock Suspend on the Next Cycle(4)
Clock Suspend Termination on the Next Cycle
Clock Suspend Termination on the Next Cycle
CKE
n-1 n
H
X
L
H
L
H
L
H
L
H
L
L
H
H
H
H
H
H
H
H
H
L
H
L
H
L
H
L
L
H
L
L
H
X
L
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
L
L
L
H
H
H
H
H
L
L
L
L
L
X
H
L
H
L
C S RAS CAS W E A11 A10 A9-A0
X
X
X
X
X
X
X
H
X
X
X
X
X
X
L
H
H
X
X
X
X
L
H
L
X
X
X
X
L
L
X
X
X
X
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
L
H
H
X
X
X
X
L
H
L
X
X
X
X
L
L
X
X
X
X
X
H
X
X
X
X
X
X
L
H
H
X
X
X
X
L
H
L
X
X
X
X
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
L
L
L
H
L
L
L
L
X
X
X
X
X
X
X
H
L
L
L
X
H
L
L
L
X
X
X
X
X
X
X
X
H
L
L
X
X
H
L
L
X
X
X
X
X
X
X
X
X
H
L
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
OP CODE
X
X
X
X
X
X
X
X
X
X
X
X
OP CODE
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Notes:
1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input
2. The CLK pin and the other input are reactivated asynchronously by the transition of the CKE level from LOW to HIGH.
The minimum setup time (tCKA) required before all commands other than mode termination must be satisfied.
3. Both banks must be set to the inactive (idle) state in advance to switch to power-down mode or self-refresh mode.
4. The input must be command defined in the operation command table.
18
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Rev. C
01/03/06
ISSI
IS45S16100C1
®
TWO BANKS OPERATION COMMAND TRUTH TABLE(1,2)
Operation
DESL
NOP
BST
CS RAS CAS WE A11 A10 A9-A0
H
X
X
X
X
X
X
L
H
H
H
X
X
X
L
H
H
L
X
X
X
READ/READA
L
H
L
H
WRIT/WRITA
L
H
L
L
ACT
L
L
H
H
PRE/PALL
L
L
H
L
REF
MRS
L
L
L
L
L
L
H
L
H
H CA(3)
H
H CA(3)
H
L CA(3)
H
L CA(3)
L
H CA(3)
L
H CA(3)
L
L CA(3)
L
L CA(3)
H
H CA(3)
H
H CA(3)
H
L CA(3)
H
L CA(3)
L
H CA(3)
L
H CA(3)
L
L CA(3)
L
L CA(3)
H RA RA
L RA RA
X
H
X
X
H
X
H
L
X
H
L
X
L
L
X
L
L
X
X
X
X
OPCODE
Previous State
BANK 0BANK 1
Any
Any
Any
Any
R/W/A
I/A
I
I/A
I/A
R/W/A
I/A
I
I/A
R/W/A
R/W
A
I/A
R/W/A
R/W
A
R/W/A
I/A
A
R/W
R/W/A
I/A
A
R/W
I/A
R/W/A
R/W
A
I/A
R/W/A
R/W
A
R/W/A
I/A
A
R/W
R/W/A
I/A
A
R/W
Any
I
I
Any
R/W/A/I I/A
I/A R/W/A/I
I/A R/W/A/I
R/W/A/I I/A
R/W/A/I I/A
I/A R/W/A/I
I
I
I
I
Next State
BANK 0BANK 1
Any
Any
Any
Any
A
I/A
I
I/A
I/A
A
I/A
I
I/A
RP
A
RP
I/A
R
A
R
RP
I/A
RP
A
R
I/A
R
A
I/A
WP
A
WP
I/A
W
A
W
WP
I/A
WP
A
W
I/A
W
A
Any
A
A
Any
I
I
I
I
I/A
I
R/W/A/I
I
I
I/A
I
R/W/A/I
I
I
I
I
Notes:
1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input, RA: Row Address, CA: Column Address
2. The device state symbols are interpreted as follows:
I
Idle (inactive state)
A
Row Active State
R
Read
W
Write
RP Read With Auto-Precharge
WP Write With Auto-Precharge
Any Any State
3. CA: A8,A9 = don’t care.
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Rev. C
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19
ISSI
IS45S16100C1
®
SIMPLIFIED STATE TRANSITION DIAGRAM (One Bank Operation)
SELF
REFRESH
SREF entry
SREF exit
MRS
MODE
AUTO
REFRESH
REF
IDLE
REGISTER
SET
CKE_
CKE
IDLE
POWER
DOWN
ACT
ACTIVE
POWER
DOWN
CKE_
CKE
BANK
ACTIVE
BST
BST
READ
WRIT
WRIT
READ
WRITA
READA
READ
WRITE
READ
CKE_
CKE
CLOCK
SUSPEND
READA
WRITA
WRITA
CKE_
CKE
READA
WRITE WITH
AUTO
PRECHARGE
POWER ON
PRE
CKE
CLOCK
SUSPEND
CKE_
READ WITH
AUTO
PRECHARGE
PRE
PRE
POWER APPLIED
CKE_
WRIT
CKE
PRE
PRECHARGE
Automatic transition following the
completion of command execution.
Transition due to command input.
20
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Rev. C
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ISSI
IS45S16100C1
®
Device Initialization At Power-On
Burst Length
(Power-On Sequence)
When writing or reading, data can be input or output data
continuously. In these operations, an address is input only
once and that address is taken as the starting address
internally by the device. The device then automatically
generates the following address. The burst length field in
the mode register stipulates the number of data items input
or output in sequence. In the IS45S16100C1 product, a
burst length of 1, 2, 4, 8, or full page can be specified. See
the table on the next page for details on setting the mode
register.
As is the case with conventional DRAMs, the IS45S16100C1
product must be initialized by executing a stipulated poweron sequence after power is applied.
After power is applied and VDD and VDDQ reach their
stipulated voltages, set and hold the CKE and DQM pins
HIGH for 100 µs. Then, execute the precharge command to
precharge both bank. Next, execute the auto-refresh
command twice or more and define the device operation
mode by executing a mode register set command.
The mode register set command can be also set before
auto-refresh command.
Mode Register Settings
The mode register set command sets the mode register.
When this command is executed, pins A0 to A9, A10, and
A11 function as data input pins for setting the register, and
this data becomes the device internal OP code. This OP
code has four fields as listed in the table below.
Input Pin
A11, A10, A9, A8, A7
A6, A5, A4
A3
A2, A1, A0
Field
Mode Options
CAS Latency
Burst Type
Burst Length
Note that the mode register set command can be executed
only when both banks are in the idle (inactive) state. Wait
at least two cycles after executing a mode register set
command before executing the next command.
CAS Latency
Burst Type
The burst data order during a read or write operation is
stipulated by the burst type, which can be set by the mode
register set command. The IS45S16100C1 product supports
sequential mode and interleaved mode burst type settings.
See the table on the next page for details on setting the
mode register. See the “Burst Length and Column Address
Sequence” item for details on DQ data orders in these
modes.
Write Mode
Burst write or single write mode is selected by the OP code
(A11, A10, A9) of the mode register.
A burst write operation is enabled by setting the OP code
(A11, A10, A9) to (0,0,0). A burst write starts on the same
cycle as a write command set. The write start address is
specified by the column address and bank select address
at the write command set cycle.
A single write operation is enabled by setting OP code
(A11, A10, A9) to (0, 0,1). In a single write operation, data
is only written to the column address and bank select
address specified by the write command set cycle without
regard to the bust length setting.
During a read operation, the between the execution of the
read command and data output is stipulated as the CAS
latency. This period can be set using the mode register set
command. The optimal CAS latency is determined by the
clock frequency and device speed grade. See the “Operating
Frequency / Latency Relationships” item for details on the
relationship between the clock frequency and the CAS
latency. See the table on the next page for details on setting
the mode register.
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Rev. C
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21
ISSI
IS45S16100C1
®
MODE REGISTER
A11 A10 A9
WRITE MODE
A8
A7 A6
LT MODE
A5 A4
A3 A2
BT
BL
A1 A0
Address Bus (Ax)
Mode Register (Mx)
M2
Burst Length 0
0
0
0
1
1
1
1
Burst Type
M3
0
1
M6
Latency Mode 0
0
0
0
1
1
1
1
M11
0
0
M10
0
0
M9
1
0
M8
0
0
M7
0
0
M1
0
0
1
1
0
0
1
1
M0
0
1
0
1
0
1
0
1
Sequential Interleaved
1
1
2
2
4
4
8
8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Full Page
Reserved
Type
Sequential
Interleaved
M5
0
0
1
1
0
0
1
1
M4
0
1
0
1
0
1
0
1
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Write Mode
Burst Read & Single Write
Burst Read & Burst Write
Note: Other values for these bits are reserved.
22
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Rev. C
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ISSI
IS45S16100C1
®
BURST LENGTH AND COLUMN ADDRESS SEQUENCE
Burst Length
Column Address
A2 A1 A0
Address Sequence
Sequential
Interleaved
2
X
X
X
X
0
1
0-1
1-0
0-1
1-0
4
X
X
X
X
0
0
1
1
0
1
0
1
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
8
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Full Page
(256)
n
n
n
Cn, Cn+1, Cn+2
Cn+3, Cn+4.....
...Cn-1(Cn+255),
Cn(Cn+256).....
None
Notes:
1. The burst length in full page mode is 256.
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Rev. C
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23
ISSI
IS45S16100C1
®
BANK SELECT AND PRECHARGE ADDRESS ALLOCATION
Row
X0
X1
X2
X3
X4
X5
X6
X7
—
—
—
—
—
—
—
—
Row Address
Row Address
Row Address
Row Address
Row Address
Row Address
Row Address
Row Address
X8
—
Row Address
X9
X10
—
0
1
0
1
Row Address
Precharge of the Selected Bank (Precharge Command)
Row Address
Precharge of Both Banks (Precharge Command)
(Active Command)
Bank 0 Selected (Precharge and Active Command)
Bank 1 Selected (Precharge and Active Command)
—
—
—
—
—
—
—
—
—
—
0
1
0
1
Column Address
Column Address
Column Address
Column Address
Column Address
Column Address
Column Address
Column Address
Don’t Care
Don’t Care
Auto-Precharge - Disabled
Auto-Precharge - Enables
Bank 0 Selected (Read and Write Commands)
Bank 1 Selected (Read and Write Commands)
X11
Column
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
24
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Rev. C
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ISSI
IS45S16100C1
®
Burst Read
The read cycle is started by executing the read command.
The address provided during read command execution is
used as the starting address. First, the data corresponding
to this address is output in synchronization with the clock
signal after the CAS latency period. Next, data corresponding
to an address generated automatically by the device is
output in synchronization with the clock signal.
The output buffers go to the LOW impedance state CAS
latency minus one cycle after the read command, and go
to the HIGH impedance state automatically after the last
data is output. However, the case where the burst length
is a full page is an exception. In this case the output
buffers must be set to the high impedance state by
executing a burst stop command.
Note that upper byte and lower byte output data can be
masked independently under control of the signals applied
to the U/LDQM pins. The delay period (tQMD) is fixed at two,
regardless of the CAS latency setting, when this function
is used.
The selected bank must be set to the active state before
executing this command.
CLK
COMMAND
READ A0
tQMD=2
UDQM
LDQM
DQ8-DQ15
DOUT A0
DQ0-DQ 7
DOUT A0
READ (CA=A, BANK 0)
CAS latency = 3, burst length = 4
HI-Z
DOUT A1
DOUT A2
DOUT A3
HI-Z
HI-Z
DATA MASK (LOWER BYTE)
DATA MASK (UPPER BYTE)
Burst Write
The write cycle is started by executing the command. The
address provided during write command execution is used
as the starting address, and at the same time, data for this
address is input in synchronization with the clock signal.
a burst stop command. The latency for DQ pin data input
is zero, regardless of the CAS latency setting. However, a
wait period (write recovery: tDPL) after the last data input is
required for the device to complete the write operation.
Next, data is input in other in synchronization with the clock
signal. During this operation, data is written to address
generated automatically by the device. This cycle
terminates automatically after a number of clock cycles
determined by the stipulated burst length. However, the
case where the burst length is a full page is an exception.
In this case the write cycle must be terminated by executing
Note that the upper byte and lower byte input data can be
masked independently under control of the signals applied
to the U/LDQM pins. The delay period (tDMD) is fixed at zero,
regardless of the CAS latency setting, when this function
is used.
The selected bank must be set to the active state before
executing this command.
CLK
COMMAND
DQ
WRITE
DIN 0
DIN 1
DIN 2
DIN 3
BURST LENGTH
CAS latency = 2,3, burst length = 4
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25
ISSI
IS45S16100C1
®
Read With Auto-Precharge
The read with auto-precharge command first executes a
burst read operation and then puts the selected bank in the
precharged state automatically. After the precharge completes, the bank goes to the idle state. Thus this command
performs a read command and a precharge command in a
single operation.
During this operation, the delay period (tPQL) between the
last burst data output and the start of the precharge
operation differs depending on the CAS latency setting.
three, the precharge operation starts on two clock cycles
before the last burst data is output (tPQL = –2). Therefore,
the selected bank can be made active after a delay of tRP
from the start position of this precharge operation.
The selected bank must be set to the active state before
executing this command.
The auto-precharge function is invalid if the burst length is
set to full page.
When the CAS latency setting is two, the precharge
operation starts on one clock cycle before the last burst
data is output (tPQL = –1). When the CAS latency setting is
CAS Latency
tPQL
3
–2
2
–1
CLK
COMMAND
READA 0
ACT 0
tPQL
DQ
DOUT 0
READ WITH AUTO-PRECHARGE
(BANK 0)
DOUT 1
DOUT 2
PRECHARGE START
DOUT 3
tRP
CAS latency = 2, burstlength = 4
CLK
COMMAND
ACT 0
READA 0
tPQL
DQ
READ WITH AUTO-PRECHARGE
(BANK 0)
DOUT 0
PRECHARGE START
DOUT 1
DOUT 2
DOUT 3
tRP
CAS latency = 3, burstlength = 4
26
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Rev. C
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ISSI
IS45S16100C1
®
Write With Auto-Precharge
The write with auto-precharge command first executes a
burst write operation and then puts the selected bank in the
precharged state automatically. After the precharge
completes the bank goes to the idle state. Thus this
command performs a write command and a precharge
command in a single operation.
During this operation, the delay period (tDAL) between the
last burst data input and the completion of the precharge
operation differs depending on the CAS latency setting.
The delay (tDAL) is tRP plus one CLK period. That is, the
precharge operation starts one clock period after the last
burst data input.
Therefore, the selected bank can be made active after a
delay of tDAL.
The selected bank must be set to the active state before
executing this command.
The auto-precharge function is invalid if the burst length is
set to full page.
CAS Latency
tDAL
3
2
1CLK
+tRP
1CLK
+tRP
CLK
COMMAND
ACT 0
WRITE A0
PRECHARGE START
DQ
DIN 0
DIN 1
DIN 2
DIN 3
tRP
tDAL
WRITE WITH AUTO-PRECHARGE
(BANK 0)
CAS latency = 2, burstlength = 4
CLK
COMMAND
ACT 0
WRITE A0
PRECHARGE START
DQ
DIN 0
DIN 1
DIN 2
DIN 3
WRITE WITH AUTO-PRECHARGE
(BANK 0)
tRP
tDAL
CAS latency = 3, burstlength = 4
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Rev. C
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27
ISSI
IS45S16100C1
®
Interval Between Read Command
A new command can be executed while a read cycle is in
progress, i.e., before that cycle completes. When the
second read command is executed, after the CAS latency
has elapsed, data corresponding to the new read command
is output in place of the data due to the previous read
command.
The interval between two read command (tCCD) must be at
least one clock cycle.
The selected bank must be set to the active state before
executing this command.
CLK
COMMAND
READ A0
READ B0
DQ
DOUT A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
tCCD
READ (CA=A, BANK 0) READ (CA=B, BANK 0)
CAS latency = 2, burstlength = 4
Interval Between Write Command
A new command can be executed while a write cycle is in
progress, i.e., before that cycle completes. At the point the
second write command is executed, data corresponding to
the new write command can be input in place of the data
for the previous write command.
The interval between two write commands (tCCD) must be
at least one clock cycle.
The selected bank must be set to the active state before
executing this command.
CLK
tCCD
COMMAND
DQ
WRITE A0
WRITE B0
DIN A0
DIN B0
DIN B1
DIN B2
DIN B3
WRITE (CA=A, BANK 0) WRITE (CA=B, BANK 0)
CAS latency = 3, burstlength = 4
28
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Rev. C
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ISSI
IS45S16100C1
®
Interval Between Write and Read Commands
A new read command can be executed while a write cycle
is in progress, i.e., before that cycle completes. Data
corresponding to the new read command is output after the
CAS latency has elapsed from the point the new read
command was executed. The I/On pins must be placed in
the HIGH impedance state at least one cycle before data
is output during this operation.
The interval (tCCD) between command must be at least one
clock cycle.
The selected bank must be set to the active state before
executing this command.
CLK
tCCD
COMMAND
DQ
WRITE A0
READ B0
DIN A0
HI-Z
WRITE (CA=A, BANK 0)
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT B0
DOUT B1
DOUT B2
READ (CA=B, BANK 0)
CAS latency = 2, burstlength = 4
CLK
tCCD
COMMAND
DQ
WRITE A0
READ B0
DIN A0
WRITE (CA=A, BANK 0)
HI-Z
DOUT B3
READ (CA=B, BANK 0)
CAS latency = 3, burstlength = 4
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Rev. C
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29
ISSI
IS45S16100C1
®
Interval Between Read and Write Commands
A read command can be interrupted and a new write
command executed while the read cycle is in progress,
i.e., before that cycle completes. Data corresponding to
the new write command can be input at the point new
write command is executed. To prevent collision
between input and output data at the DQn pins during
this operation, the
output data must be masked using the U/LDQM pins. The
interval (tCCD) between these commands must be at least
one clock cycle.
The selected bank must be set to the active state before
executing this command.
CLK
tCCD
COMMAND
READ A0
WRITE B0
U/LDQM
DQ
HI-Z
DIN B0
READ (CA=A, BANK 0)
DIN B1
DIN B2
DIN B3
WRITE (CA=B, BANK 0)
CAS latency = 2, 3, burstlength = 4
30
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ISSI
IS45S16100C1
Precharge
Read Cycle Interruption
The precharge command sets the bank selected by pin A11
to the precharged state. This command can be executed at
a time tRAS following the execution of an active command to
the same bank. The selected bank goes to the idle state at
a time tRP following the execution of the precharge command,
and an active command can be executed again for that
bank.
Using the Precharge Command
®
A read cycle can be interrupted by the execution of the
precharge command before that cycle completes. The
delay time (tRQL) from the execution of the precharge
command to the completion of the burst output is the
clock cycle of CAS latency.
If pin A10 is low when this command is executed, the bank
selected by pin A11 will be precharged, and if pin A10 is
HIGH, both banks will be precharged at the same time. This
input to pin A11 is ignored in the latter case.
CAS Latency
tRQL
3
2
3
2
CLK
tRQL
COMMAND
READ A0
DQ
PRE 0
DOUT A0 DOUT A1 DOUT A2
READ (CA=A, BANK 0)
HI-Z
PRECHARGE (BANK 0)
CAS latency = 2, burstlength = 4
CLK
tRQL
COMMAND
READ A0
DQ
PRE 0
DOUT A0 DOUT A1 DOUT A2
READ (CA=A, BANK 0)
HI-Z
PRECHARGE (BANK 0)
CAS latency = 3, burstlength = 4
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31
ISSI
IS45S16100C1
®
Write Cycle Interruption Using the
Precharge Command
A write cycle can be interrupted by the execution of the
precharge command before that cycle completes. The
delay time (tWDL) from the precharge command to the point
where burst input is invalid, i.e., the point where input data
is no longer written to device internal memory is zero clock
cycles regardless of the CAS.
Inversely, to write all the burst data to the device, the
precharge command must be executed after the write
data recovery period (tDPL) has elapsed. Therefore, the
precharge command must be executed on one clock
cycle that follows the input of the last burst data item.
To inhibit invalid write, the DQM signal must be asserted
HIGH with the precharge command.
This precharge command and burst write command must
be of the same bank, otherwise it is not precharge interrupt
but only another bank precharge of dual bank operation.
CAS Latency
tWDL
3
0
2
0
tDPL
1
1
CLK
tWDL=0
COMMAND
PRE 0
WRITE A0
DQM
DQ
DIN A0
DIN A1
DIN A2
DIN A3
MASKED BY DQM
WRITE (CA=A, BANK 0)
PRECHARGE (BANK 0)
CAS latency = 2, burstlength = 4
CLK
tDPL
COMMAND
WRITE A0
DQ
DIN A0
PRE 0
DIN A1
WRITE (CA=A, BANK 0)
DIN A2
DIN A3
PRECHARGE (BANK 0)
CAS latency = 3, burstlength = 4
32
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Rev. C
01/03/06
ISSI
IS45S16100C1
®
Read Cycle (Full Page) Interruption Using
the Burst Stop Command
The IS45S16100C1 can output data continuously from the
burst start address (a) to location a+255 during a read cycle
in which the burst length is set to full page. The
IS45S16100C1 repeats the operation starting at the 256th
cycle with the data output returning to location (a) and
continuing with a+1, a+2, a+3, etc. A burst stop command
must be executed to terminate this cycle. A precharge
command must be executed within the ACT to PRE
command period (tRAS max.) following the burst stop
command.
After the period (tRBD) required for burst data output to
stop following the execution of the burst stop command
has elapsed, the outputs go to the HIGH impedance
state. This period (tRBD) is two clock cycle when the
CAS latency is two and three clock cycle when the CAS
latency is three.
CAS Latency
3
2
tRBD
3
2
CLK
tRBD
COMMAND
READ A0
DQ
BST
DOUT A0 DOUT A0
DOUT A1
DOUT A2
DOUT A3
HI-Z
BURST STOP
READ (CA=A, BANK 0)
CAS latency = 2, burstlength = 4
CLK
tRBD
COMMAND
BST
READ A0
DQ
DOUT A0 DOUT A0
READ (CA=A, BANK 0)
DOUT A1
DOUT A2
DOUT A3
HI-Z
BURST STOP
CAS latency = 3, burstlength = 4
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Rev. C
01/03/06
33
ISSI
IS45S16100C1
®
Write Cycle (Full Page) Interruption Using
the Burst Stop Command
must be executed within the ACT to PRE command
period (tRAS max.) following the burst stop command.
After the period (tWBD) required for burst data input to
stop following the execution of the burst stop command
has elapsed, the write cycle terminates. This period
(tWBD) is zero clock cycles, regardless of the CAS
latency.
The IS45S16100C1 can input data continuously from the
burst start address (a) to location a+255 during a write
cycle in which the burst length is set to full page. The
IS45S16100C1 repeats the operation starting at the
256th cycle with data input returning to location (a) and
continuing with a+1, a+2, a+3, etc. A burst stop
command must be executed to terminate this cycle. A
precharge command
CLK
tWBD=0
COMMAND
WRITE A0
BST
tRP
PRE 0
INVALID DATA
DQ
DIN A0
DIN A1
DIN A
DIN A1
DIN A2
READ (CA=A, BANK 0)
BURST STOP
PRECHARGE (BANK 0)
Don't Care
Burst Data Interruption Using the U/LDQM
Pins (Read Cycle)
Burst data output can be temporarily interrupted (masked)
during a read cycle using the U/LDQM pins. Regardless of
the CAS latency, two clock cycles (tQMD) after one of the U/
LDQM pins goes HIGH, the corresponding outputs go to the
HIGH impedance state. Subsequently, the outputs are
maintained in the high impedance state as long as that U/
LDQM pin remains HIGH. When the U/LDQM pin goes
LOW, output is resumed at a time tQMD later. This output
control operates independently on a byte basis with the
UDQM pin controlling upper byte output (pins
DQ8-DQ15) and the LDQM pin controlling lower byte output
(pins DQ0 to DQ7).
Since the U/LDQM pins control the device output buffers
only, the read cycle continues internally and, in particular,
incrementing of the internal burst counter continues.
CLK
COMMAND
READ A0
tQMD=2
UDQM
LDQM
DQ8-DQ15
DOUT A0
DQ0-DQ 7
DOUT A0
READ (CA=A, BANK 0)
HI-Z
DOUT A1
DOUT A2
DOUT A3
HI-Z
HI-Z
DATA MASK (LOWER BYTE)
DATA MASK (UPPER BYTE)
CAS latency = 2, burstlength = 4
34
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
ISSI
IS45S16100C1
®
Burst Data Interruption U/LDQM Pins (Write
Cycle)
Burst data input can be temporarily interrupted (muted )
during a write cycle using the U/LDQM pins. Regardless of
the CAS latency, as soon as one of the U/LDQM pins goes
HIGH, the corresponding externally applied input data will
no longer be written to the device internal circuits.
Subsequently, the corresponding input continues to be
muted as long as that U/LDQM pin remains HIGH.
that pin is dropped to LOW and data will be written to the
device. This input control operates independently on a byte
basis with the UDQM pin controlling upper byte input (pin
DQ8 to DQ15) and the LDQM pin controlling the lower byte
input (pins DQ0 to DQ7).
Since the U/LDQM pins control the device input buffers
only, the cycle continues internally and, in particular,
incrementing of the internal burst counter continues.
The IS45S16100C1 will revert to accepting input as soon
as
CLK
COMMAND
WRITE A0
UDQM
tDMD=0
LDQM
DQ8-DQ15
DIN A1
DQ0-DQ7
DIN A2
DIN A0
WRITE (CA=A, BANK 0)
DATA MASK (LOWER BYTE)
DATA MASK (UPPER BYTE)
DIN A3
DIN A3
Don't Care
CAS latency = 2, burstlength = 4
Burst Read and Single Write
The burst read and single write mode is set up using the
mode register set command. During this operation, the
burst read cycle operates normally, but the write cycle only
writes a single data item for each write cycle. The CAS
latency and DQM latency are the same as in normal mode.
CLK
COMMAND
DQ
WRITE A0
DIN A0
WRITE (CA=A, BANK 0)
CAS latency = 2, 3
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Rev. C
01/03/06
35
ISSI
IS45S16100C1
®
Bank Active Command Interval
When the selected bank is precharged, the period trp
has elapsed and the bank has entered the idle state, the
bank can be activated by executing the active
command. If the other bank is in the idle state at that
time, the active command can be executed for that bank
after the period tRRD has elapsed. At that point both
banks will be in the active state. When a bank active
command has been executed, a precharge command
must be executed for
that bank within the ACT to PRE command period (tRAS
max). Also note that a precharge command cannot be
executed for an active bank before tRAS (min) has elapsed.
After a bank active command has been executed and the
trcd period has elapsed, read write (including auto-precharge)
commands can be executed for that bank.
CLK
tRRD
COMMAND
ACT 0
ACT 1
BANK ACTIVE (BANK 0)
BANK ACTIVE (BANK 1)
CLK
tRCD
COMMAND
ACT 0
READ 0
BANK ACTIVE (BANK 0)
BANK ACTIVE (BANK 0)
CAS latency = 3
Clock Suspend
When the CKE pin is dropped from HIGH to LOW during a
read or write cycle, the IS45S16100C1 enters clock suspend
mode on the next CLK rising edge. This command reduces
the device power dissipation by stopping the device internal
clock. Clock suspend mode continues as long as the CKE
pin remains low. In this state, all inputs other than CKE pin
are invalid and no other commands can be executed. Also,
the device internal states are maintained. When the CKE
pin goes from LOW to HIGH clock suspend mode is
terminated on the next CLK rising edge and device operation
resumes.
The next command cannot be executed until the recovery
period (tCKA) has elapsed.
Since this command differs from the self-refresh command
described previously in that the refresh operation is not
performed automatically internally, the refresh operation
must be performed within the refresh period (tref). Thus the
maximum time that clock suspend mode can be held is just
under the refresh cycle time.
CLK
CKE
COMMAND
READ 0
DQ
DOUT 0
READ (BANK 0)
DOUT 1
DOUT 2
DOUT 3
CLOCK SUSPEND
CAS latency = 2, burstlength = 4
36
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
ISSI
IS45S16100C1
®
OPERATION TIMING EXAMPLE
Power-On Sequence, Mode Register Set Cycle
T0
T1
T2
T3
T10
T17
T18
T19
T20
CLK
tCHI
tCK
CKE HIGH
tCS
tCL
tCH
CS
tCS
tCH
tCS
tCH
tCS
tCH
RAS
CAS
WE
tAS
A0-A9
tAH
ROW
CODE
tAS
A10
tAS
tAH
tAH
CODE
BANK 0 & 1
tAS
A11
ROW
tAH
BANK 1
CODE
BANK 0
DQM HIGH
DQ
WAIT TIME
T=100 µs
<PALL>
tRC
tRP
<REF>
<REF>
tRAS
tRC
tMCD
tRC
<MRS>
<ACT>
Undefined
CAS latency = 2, 3
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Rev. C
01/03/06
Don't Care
37
ISSI
IS45S16100C1
®
Power-Down Mode Cycle
T0
T1
T2
T3
Tn
Tn+1
Tn+2
Tn+3
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
tCKH
tCKS
tCKA
CS
tCS
tCH
tCS
tCH
tCS
tCH
RAS
CAS
WE
tAS
tAH
ROW
A0-A9
tAS
A10
A11
tAH
BANK 0 & 1
ROW
BANK 0 OR 1
BANK 1
BANK 1
BANK 0
BANK 0
DQM
DQ
POWER DOWN MODE
tRP
<PRE>
<PALL>
<SBY>
EXIT
POWER DOWN MODE
tRAS
tRC
<ACT>
Undefined
CAS latency = 2, 3
38
Don't Care
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Rev. C
01/03/06
ISSI
IS45S16100C1
®
Auto-Refresh Cycle
T0
T1
T2
T3
Tl
Tm
Tn
Tn+1
CLK
tCKS
tCK
tCS
tCH
tCHI
tCL
CKE
CS
tCS
tCH
tCS
tCH
tCS
tCH
RAS
CAS
WE
ROW
A0-A9
tAS
A10
tAH
ROW
BANK 0 & 1
BANK 1
A11
BANK 0
DQM
DQ
tRC
tRP
<PALL>
<REF>
<REF>
tRAS
tRC
tRC
tRC
<REF>
<ACT>
Undefined
CAS latency = 2, 3
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Rev. C
01/03/06
Don't Care
39
ISSI
IS45S16100C1
®
Self-Refresh Cycle
T0
T1
T2
T3
Tm
Tm+1
Tm+2
Tn
CLK
tCKS
CKE
tCK
tCHI
tCL
tCKS
tCKS
tCKA
tCS
tCKA
tCH
CS
tCS
tCH
tCS
tCH
tCS
tCH
tAS
tAH
RAS
CAS
WE
A0-A9
A10
BANK 0 & 1
A11
DQM
DQ
tRP
<PALL>
SELF REFRESH MODE
<SELF>
EXIT
SELF
REFRESH
tRC
tRC
<REF>
Undefined
CAS latency = 2, 3
Don't Care
Note 1: A8,A9 = Don’t Care.
40
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Rev. C
01/03/06
ISSI
IS45S16100C1
®
Read Cycle
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
CS
tCS
tCH
tCS
tCH
tCS
tCH
tAS
tAH
RAS
CAS
WE
COLUMN m
ROW
A0-A9
tAS
ROW
BANK 0 AND 1
tAH
NO PRE
ROW
A10
tAH
tAS
A11
(1)
ROW
BANK 0 OR 1
BANK 1
BANK 1
BANK 1
BANK 1
BANK 0
tCS
BANK 0
tCH BANK 0
tQMD
BANK 0
DQM
tAC
tAC
tAC
tOH
DQ
DOUT m
tAC
tOH
tOH
tOH
DOUT m+1
DOUT m+2
DOUT m+3
tLZ
tCAC
tRCD
tHZ
tRAS
tRQL
tRCD
tRP
tRAS
tRC
tRC
<ACT>
<READ>
<PRE>
<PALL>
<ACT>
Undefined
CAS latency = 2, burstlength = 4
Don't Care
Note 1: A8,A9 = Don’t Care.
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Rev. C
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41
ISSI
IS45S16100C1
®
Read Cycle / Auto-Precharge
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
CS
tCS
tCH
tCS
tCH
tCS
tCH
tAS
tAH
RAS
CAS
WE
ROW
A0-A9
tAS
COLUMN m
ROW
AUTO PRE
ROW
BANK 1
BANK 1
tAH
ROW
A10
tAH
tAS
A11
(1)
BANK 1
BANK 0
tCS
BANK 0
BANK 0
tCH
tQMD
DQM
tAC
DQ
tAC
tAC
tAC
tOH
tOH
tOH
tOH
DOUT m
DOUT m+1
DOUT m+2
DOUT m+3
tLZ
tRCD
tCAC
tRAS
tHZ
tPQL
tRCD
tRP
tRAS
tRC
tRC
<ACT>
<READA>
<ACT>
Undefined
CAS latency = 2, burstlength = 4
Don't Care
Note 1: A8,A9 = Don’t Care.
42
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Rev. C
01/03/06
ISSI
IS45S16100C1
®
Read Cycle / Full Page
T0
T1
T2
T3
T4
T5
T6
T260
T261
T262
T263
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
CS
tCS
tCH
tCS
tCH
tCS
tCH
RAS
CAS
WE
tAS
tAH
tAS
tAH
ROW
A10
tAH
tAS
A11
(1)
COLUMN
ROW
A0-A9
BANK 0
tCS
NO PRE
BANK 0 OR 1
BANK 0
BANK 0
tCH
tQMD
DQM
tAC
tOH
DQ
tAC
tAC
DOUT 0m
tOH
DOUT 0m+1
tAC
tOH
DOUT 0m-1
tAC
tOH
tOH
DOUT 0m
DOUT 0m+1
tLZ
tRCD
tCAC
tHZ
tRBD
(BANK 0)
tRP
(BANK 0)
tRAS
tRC
(BANK 0)
<ACT 0>
<READ0>
<BST>
<PRE 0>
Undefined
CAS latency = 2, burstlength = full page
Don't Care
Note 1: A8,A9 = Don’t Care.
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Rev. C
01/03/06
43
ISSI
IS45S16100C1
®
Read Cycle / Ping-Pong Operation (Bank Switching)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
CS
tCS
tCH
tCS
tCH
tCS
tCH
RAS
CAS
WE
tAS
tAH
(1)
ROW
COLUMN
tAS
tAH
AUTO PRE
tAH
NO PRE
ROW
COLUMN
AUTO PRE
ROW
ROW
A10
tAS
A11
(1)
ROW
A0-A9
BANK 0
BANK 0
ROW
BANK 1
tCS
NO PRE
BANK 0 OR 1
BANK 1
BANK 0
BANK 0 OR 1
BANK 0
BANK 1
tCH
tQMD
DQM
tAC
tAC
tAC
tOH
DQ
DOUT 0m
DOUT 0m+1
tLZ
tRRD
(BANK 0 TO 1)
tRCD
(BANK 0)
tCAC
(BANK 1)
tOH
DOUT 1m+1
tLZ
tCAC
(BANK 1)
tRP
tRAS
(BANK 0)
tRC
(BANK 0)
<ACT 0>
DOUT 1m
tHZ
tRCD
(BANK 1)
tAC
tOH
tOH
(BANK 0)
tHZ
tRCD
(BANK 0)
tRAS
(BANK 0)
tRC
(BANK 0)
tRAS
(BANK 1)
tRC
(BANK 1)
<READ 0>
<READA 0>
<ACT1>
<READ 1>
<READA 1>
tRP
(BANK1)
<PRE 0>
<ACT 0>
<PRE 1>
Undefined
CAS latency = 2, burstlength = 2
Don't Care
Note 1: A8,A9 = Don’t Care.
44
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Rev. C
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ISSI
IS45S16100C1
®
Write Cycle
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
CS
tCS
tCH
tCS
tCH
tCS
tCH
tAS
tAH
RAS
CAS
WE
ROW
A0-A9
tAS
COLUMN m
ROW
BANK 0 AND 1
tAH
NO PRE
ROW
A10
tAH
tAS
A11
(1)
ROW
BANK 1
BANK 0 OR 1
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
BANK 1
BANK 0
tCS
tCH
DQM
tDS
tDH tDS
DIN m
DQ
tDH tDS
DIN m+1
tDH tDS
DIN m+2
tDH
DIN m+3
tDPL
tRCD
tRAS
tRCD
tRP
tRAS
tRC
<ACT>
tRC
<WRIT>
<PRE>
<PALL>
<ACT>
Undefined
CAS latency = 2, burstlength = 4
Don't Care
Note 1: A8,A9 = Don’t Care.
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Rev. C
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45
ISSI
IS45S16100C1
®
Write Cycle / Auto-Precharge
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
CS
tCS
tCH
tCS
tCH
tCS
tCH
tAS
tAH
RAS
CAS
WE
ROW
A0-A9
tAS
COLUMN m
ROW
AUTO PRE
ROW
BANK 1
BANK 1
tAH
ROW
A10
tAH
tAS
A11
(1)
BANK 1
BANK 0
BANK 0
tCS
BANK 0
tCH
DQM
tDS
tDH tDS
DIN m
DQ
tDH tDS
DIN m+1
tDH tDS
DIN m+2
tDH
DIN m+3
tDAL
tRCD
tRAS
tRCD
tRP
tRAS
tRC
<ACT>
tRC
<WRITA>
<ACT>
Undefined
CAS latency = 2, burstlength = 4
Don't Care
Note 1: A8,A9 = Don’t Care.
46
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Rev. C
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ISSI
IS45S16100C1
®
Write Cycle / Full Page
T0
T1
T2
T3
T4
T5
T258
T259
T260
T261
T262
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
CS
tCS
tCH
tCS
tCH
tCS
tCH
tAS
tAH
RAS
CAS
WE
COLUMN m
ROW
A0-A9
tAS
tAH
ROW
A10
tAH
tAS
A11
(1)
BANK 0
NO PRE
BANK 0 OR 1
BANK 0
BANK 0
tCH
tCS
DQM
tDS
DQ
tDH tDS
DIN 0m
tDH tDS
DIN 0m+1
tDH tDS
DIN 0m+2
tDH
DIN 0m-1
DIN 0m
tDPL
tRCD
tRAS
tRP
tRC
<ACT 0>
<WRIT0>
<BST>
<PRE 0>
Undefined
CAS latency = 2, burst length = full page
Don't Care
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
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47
ISSI
IS45S16100C1
®
Write Cycle / Ping-Pong Operation
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
CS
tCS
tCH
tCS
tCH
tCS
tCH
RAS
CAS
WE
tAS
tAH
A0-A9
(1)
ROW
COLUMN
tAS
tAH
AUTO PRE
tAH
NO PRE
ROW
COLUMN
AUTO PRE
ROW
A10
ROW
tAS
A11
(1)
ROW
BANK 0
BANK 0
ROW
BANK 1
NO PRE
BANK 0 OR 1
BANK 1
BANK 0
BANK 0
tCH
tCS
DQM
tDS
tDH tDS
DIN 0m
DQ
tRRD
(BANK 0 TO 1)
tRCD
(BANK 0)
DIN 0m+1
tDH tDS
DIN 0m+2
tDH tDS
DIN 0m+3
tDH tDS
DIN 1m
tDH tDS
DIN 1m+1
tDH tDS
DIN 1m+2
tDH
DIN 1m+3
tDPL
tDPL
tRCD
(BANK 1)
tRP
(BANK 0)
tRAS
(BANK 0)
tRC
(BANK 0)
<ACT 0>
tDH tDS
tRCD
(BANK 0)
tRAS
(BANK 0)
tRC
(BANK 0)
tRAS
(BANK 1)
tRC
(BANK 1)
<WRIT 0>
<WRITA 0>
<ACT 1>
<WRIT 1>
<WRITA 1>
<PRE 0>
<ACT 0>
Undefined
CAS latency = 2, burst length = 2
Don't Care
Note 1: A8,A9 = Don’t Care.
48
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Rev. C
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ISSI
IS45S16100C1
®
Read Cycle / Page Mode
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
CS
tCS
tCH
tCS
tCH
tCS
tCH
RAS
CAS
WE
tAS
tAH
tAS
tAH
tAS
A11
(1)
COLUMN n
COLUMN o
tAH
ROW
A10
(1)
(1)
COLUMN m
ROW
A0-A9
BANK 1
BANK 0
tCS
NO PRE
NO PRE
BANK 1
BANK 1
BANK 0
BANK 0
tQMD
AUTO PRE
BANK 0 AND 1
NO PRE
BANK 0 OR 1
BANK 1
BANK 1
BANK 0
BANK 0
tCH
DQM
tAC
tAC
tOH
DQ
tAC
tOH
DOUT m
DOUT m+1
tAC
tOH
DOUT n
tAC
tOH
DOUT n+1
tAC
tOH
DOUT o
tLZ
tRCD
tRAS
tRC
<ACT>
tHZ
tCAC
<READ>
tOH
DOUT o+1
tCAC
<READ>
tCAC
<READ>
<READA>
tRQL
tRP
<PRE>
<PALL>
Undefined
CAS latency = 2, burst length = 2
Don't Care
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
49
ISSI
IS45S16100C1
®
Read Cycle / Page Mode; Data Masking
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
CS
tCS
tCH
tCS
tCH
tCS
tCH
tAS
tAH
RAS
CAS
WE
tAS
(1)
(1)
COLUMN n
COLUMN o
tAH
ROW
A10
tAH
tAS
A11
(1)
COLUMN m
ROW
A0-A9
BANK 1
BANK 0
tCS
NO PRE
NO PRE
BANK 1
BANK 1
BANK 0
BANK 0
tQMD
NO PRE
AUTO PRE
BANK 0 AND 1
NO PRE
BANK 0 OR 1
BANK 1
BANK 1
BANK 0
BANK 0
tCH
tQMD
DQM
tAC
tAC
tAC
tOH
DQ
tOH
DOUT m
DOUT m+1
tLZ
tRCD
tRAS
tRC
<ACT>
tCAC
<READ>
tAC
tOH
DOUT n
<MASK>
tOH
tOH
DOUT o
DOUT o+1
tLZ
tHZ
tCAC
tAC
tHZ
tCAC
<READ, ENB>
<READA, ENB>
tRQL
tRP
<PRE>
<PALL>
Undefined
CAS latency = 2, burst length = 2
Don't Care
Note 1: A8,A9 = Don’t Care.
50
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
ISSI
IS45S16100C1
®
Write Cycle / Page Mode
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
CS
tCS
tCH
tCS
tCH
tCS
tCH
RAS
CAS
WE
tAS
tAH
A0-A9
tAS
(1)
(1)
COLUMN o
COLUMN n
tAH
ROW
A10
tAH
tAS
A11
(1)
COLUMN m
ROW
BANK 1
BANK 0
tCS
NO PRE
NO PRE
BANK 1
BANK 1
AUTO PRE
BANK 0 AND 1
NO PRE
BANK 0 OR 1
BANK 1
BANK 1
BANK 0
BANK 0
BANK 0
BANK 0
tCH
DQM
tDS
tDH tDS
DIN m
DQ
tDH tDS
DIN m+1
tDH tDS
DIN n
tDH tDS
DIN n+1
tDH tDS
tDH
DIN o
DIN o+1
tRCD
tRAS
tRC
<ACT>
tDPL
tRP
<WRIT>
<WRIT>
<WRIT>
<WRITA>
<PRE>
<PALL>
Undefined
CAS latency = 2, burst length = 2
Don't Care
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
51
ISSI
IS45S16100C1
®
Write Cycle / Page Mode; Data Masking
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
CS
tCS
tCH
tCS
tCH
tCS
tCH
RAS
CAS
WE
tAS
tAH
tAS
tAH
tAS
A11
COLUMN n
COLUMN o
tAH
ROW
A10
(1)
(1)
(1)
COLUMN m
ROW
A0-A9
BANK 1
BANK 0
tCS
AUTO PRE
BANK 0 AND 1
NO PRE
NO PRE
BANK 1
BANK 1
NO PRE
BANK 1OR 0
BANK 0
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
tCH
DQM
tDS
tDH tDS
DIN m
DQ
tDH tDS
DIN m+1
tDH
tDS
DIN n
tDH tDS
DIN o
tRCD
tRAS
tRC
<ACT>
tDH
DIN o+1
tDPL
tRP
<WRIT>
<WRIT>
<MASK>
<WRIT>
<WRITA>
<PRE>
<PALL>
Undefined
CAS latency = 2, burst length = 2
Don't Care
Note 1: A8,A9 = Don’t Care.
52
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
ISSI
IS45S16100C1
®
Read Cycle / Clock Suspend
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCKS
tCL
tCKH
CS
tCS
tCH
tCS
tCH
tCS
tCH
tAS
tAH
RAS
CAS
WE
tAS
ROW
BANK 0 AND 1
tAH
AUTO PRE
tAH
NO PRE
BANK 0 OR 1
BANK 1
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
ROW
ROW
A10
tAS
A11
(1)
COLUMN m
ROW
A0-A9
BANK 1
BANK 0
tCS
tCH
tQMD
DQM
tAC
tAC
tOH
DQ
tOH
DOUT m
DOUT m+1
tLZ
tRCD
tHZ
tCAC
tRAS
tRAS
tRP
tRC
<ACT 0>
tRC
<READ>
<READ A>
<SPND>
<SPND>
<PRE>
<PALL>
<ACT >
Undefined
CAS latency = 2, burst length = 2
Don't Care
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
53
ISSI
IS45S16100C1
®
Write Cycle / Clock Suspend
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL tCKS
tCKH
CS
tCS
tCH
tCS
tCH
tCS
tCH
tAS
tAH
RAS
CAS
WE
COLUMN m
ROW
A0-A9
tAS
ROW
BANK 0 AND 1
tAH
AUTO PRE
tAH
NO PRE
BANK 0 OR 1
BANK 1
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
ROW
ROW
A10
tAS
A11
(1)
BANK 1
BANK 0
tCS
tCH
DQM
tDS
tDH
DIN m
DQ
tDS
tDH
DIN m+1
tRCD
tDPL
tRAS
tRAS
tRP
tRC
<ACT>
tRC
<WRIT, SPND> <SPND>
<WRITA, SPND>
<PRE>
<PALL>
<ACT >
Undefined
CAS latency = 2, burst length = 2
Don't Care
Note 1: A8,A9 = Don’t Care.
54
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
ISSI
IS45S16100C1
®
Read Cycle / Precharge Termination
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
CS
tCS
tCH
tCS
tCH
tCS
tCH
RAS
CAS
WE
tAS
tAH
tAS
COLUMN n
ROW
AUTO PRE
tAH
ROW
ROW
A10
tAH
tAS
A11
(1)
(1)
COLUMN m
ROW
A0-A9
BANK 0
NO PRE
BANK 0 OR 1
BANK 0
BANK 0
tCS
BANK 1
BANK 0
tCH
tQMD
NO PRE
BANK 1
BANK 0
DQM
tAC
tAC
tOH
DQ
DOUT m
tAC
tOH
tHZ
tOH
DOUT m+1
DOUT m+2
tLZ
tRCD
tCAC
tRAS
tRQL
tRCD
tRP
tRAS
tRC
<ACT 0>
tCAC
tRC
<READ 0>
<PRE 0>
<ACT >
<READ>
<READA>
Undefined
CAS latency = 2, burst length = 4
Don't Care
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
55
ISSI
IS45S16100C1
®
Write Cycle / Precharge Termination
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
CS
tCS
tCH
tCS
tCH
tCS
tCH
RAS
CAS
WE
tAS
tAH
A0-A9
tAS
COLUMN n
ROW
AUTO PRE
tAH
ROW
ROW
A10
BANK 0 OR 1
NO PRE
tAH
tAS
A11
(1)
(1)
COLUMN m
ROW
BANK 0
BANK 0
BANK 1
NO PRE
BANK 0
BANK 0
BANK 0
tCS
tCH
tCS
tDH
tDS
tDH
BANK 1
tCH
tCS
DQM
tDH
tDS
tDS
DQ
DIN 0m
DIN 0m+1
tDH
tDS
DIN 0m+2
DIN 0n
tRCD
tRCD
tRAS
tRAS
tRP
tRC
<ACT 0>
tRC
<WRIT 0>
<PRE 0>
<ACT >
<WRIT>
<WRITA>
Undefined
CAS latency = 2, burst length = 4
Don't Care
Note 1: A8,A9 = Don’t Care.
56
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
ISSI
IS45S16100C1
®
Read Cycle / Byte Operation
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
CS
tCS
tCH
tCS
tCH
tCS
tCH
RAS
CAS
WE
tAS
tAH
tAS
ROW
AUTO PRE
tAH
BANK 0 AND 1
ROW
ROW
A10
tAH
tAS
A11
(1)
COLUMN m
ROW
A0-A9
BANK 1
BANK 0
tCS
NO PRE
BANK 0 OR 1
BANK 1
BANK 0
BANK 1
BANK 0
tCH
tQMD
BANK 1
BANK 0
UDQM
tQMD
tCS
tCH
LDQM
tAC
tLZ
DQ8-15
tAC
tHZ
tOH
tLZ
DOUT m+2
DOUT m
tAC
tLZ
tRCD
tCAC
tOH
DOUT m+3
tAC
tOH
DOUT m
DQ0-7
tAC
tOH
tOH
DOUT m+1
tQMD
tRQL
tRAS
tRCD
tRP
tRAS
tRC
tRC
<ACT>
<READ>
<READA>
<MASKU>
<ENBU, MASKL> <MASKL>
<PRE>
<PALL>
<ACT>
Undefined
CAS latency = 2, burst length = 4
Don't Care
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
57
ISSI
IS45S16100C1
®
Write Cycle / Byte Operation
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
CS
tCS
tCH
tCS
tCH
tCS
tCH
RAS
CAS
WE
tAS
tAH
tAS
ROW
AUTO PRE
tAH
BANK 0 AND 1
ROW
ROW
A10
tAH
tAS
A11
(1)
COLUMN m
ROW
A0-A9
BANK 1
BANK 0
tCS
NO PRE
BANK 0 OR 1
BANK 1
BANK 0
BANK 1
BANK 0
tCH
BANK 1
BANK 0
UDQM
tCS
tCH
tDS
tDS
tDH
LDQM
DQ8-15
DIN m
tDH
DIN m+1
DIN m+3
tDH
tDS
tDH
tDS
DIN m
DQ0-7
tDH
tDS
DIN m+3
tRCD
tDPL
tRCD
tRAS
tRP
tRAS
tRC
tRC
<ACT>
<WRIT>
<WRITA>
<MASKL>
<MASK>
<ENB>
<PRE>
<PALL>
<ACT>
Undefined
CAS latency = 2, burst length = 4
Don't Care
Note 1: A8,A9 = Don’t Care.
58
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
ISSI
IS45S16100C1
®
Read Cycle, Write Cycle / Burst Read, Single Write
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
CS
tCS
tCH
tCS
tCH
tCS
tCH
RAS
CAS
WE
tAS
tAH
tAS
(1)
COLUMN n
tAH
tAH
tAS
AUTO PRE
BANK 0 AND 1
NO PRE
BANK 0 OR 1
BANK 1
BANK 1
BANK 0
BANK 0
NO PRE
ROW
A10
A11
(1)
COLUMN m
ROW
A0-A9
BANK 1
BANK 1
BANK 0
tCS
BANK 0
tCH
tQMD
DQM
tAC
tOH
DQ
tAC
tAC
DOUT m
tDS
tOH
tOH
tOH
DOUT m+1
DOUT m+2
DOUT m+3
tLZ
tRCD
tAC
tDH
DIN n
tHZ
tCAC
tDPL
tRAS
tRP
tRC
<ACT>
<READ>
<WRIT>
<WRITA>
<PRE>
<PALL>
Undefined
CAS latency = 2, burst length = 4
Don't Care
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
59
ISSI
IS45S16100C1
®
Read Cycle
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
CS
tCS
tCH
tCS
tCH
tCS
tCH
RAS
CAS
WE
tAS
tAH
A0-A9
tAS
BANK 0 AND 1
NO PRE
tAH
tAS
A11
ROW
tAH
ROW
A10
(1)
COLUMN m
ROW
ROW
BANK 0 OR 1
BANK 1
BANK 1
BANK 1
BANK 1
BANK 0
BANK 0
tCS
tCH BANK 0
tQMD
BANK 0
DQM
tAC
tAC
tOH
DQ
DOUT m
tAC
tAC
tOH
tOH
tOH
DOUT m+1
DOUT m+2
DOUT m+3
tLZ
tRCD
tHZ
tCAC
tRAS
tRQL
tRCD
tRP
tRAS
tRC
tRC
<ACT>
<READ>
<PRE>
<PALL>
<ACT>
Undefined
CAS latency = 3, burst length = 4
Don't Care
Note 1: A8,A9 = Don’t Care.
60
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
ISSI
IS45S16100C1
®
Read Cycle / Auto-Precharge
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
CS
tCS
tCH
tCS
tCH
tCS
tCH
tAS
tAH
RAS
CAS
WE
tAS
tAH
ROW
AUTO PRE
ROW
ROW
A10
tAH
tAS
A11
COLUMN
ROW
A0-A9
(1)
BANK 1
BANK 1
BANK 1
BANK 0
BANK 0
tCS
BANK 0
tCH
tQMD
DQM
tAC
tAC
tOH
DQ
DOUT m
tAC
tAC
tOH
tOH
tOH
DOUT m+1
DOUT m+2
DOUT m+3
tLZ
tRCD
tCAC
tRAS
tHZ
tPQL
tRCD
tRP
tRAS
tRC
tRC
<ACT>
<READA>
<ACT>
Undefined
CAS latency = 3, burst length = 4
Don't Care
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
61
ISSI
IS45S16100C1
®
Read Cycle / Full Page
T0
T1
T2
T3
T4
T5
T6
T7
T8
T262
T263
T264
T265
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
CS
tCS
tCH
tCS
tCH
tCS
tCH
RAS
CAS
WE
tAS
tAH
tAS
tAH
NO PRE
ROW
A10
BANK 0 OR 1
tAH
tAS
A11
(1)
COLUMN
ROW
A0-A9
BANK 0
BANK 0
BANK 0
tCH
tCS
DQM
tAC
tAC
tOH
DQ
DOUT 0m
tAC
tOH
DOUT 0m+1
tAC
tOH
DOUT 0m-1
tAC
tOH
tOH
DOUT 0m
DOUT 0m+1
tLZ
tRCD
tCAC
(BANK 0)
tRAS
(BANK 0)
tRC
(BANK 0)
(BANK 0)
<ACT 0>
tHZ
tRBD
tRP
(BANK 0)
<READ0>
<BST>
<PRE 0>
Undefined
CAS latency = 3, burst length = full page
Don't Care
Note 1: A8,A9 = Don’t Care.
62
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
ISSI
IS45S16100C1
®
Read Cycle / Ping Pong Operation (Bank Switching)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
ROW
COLUMN
COLUMN
AUTO PRE
AUTO PRE
NO PRE
NO PRE
BANK 0 OR 1
BANK 0 OR 1
BANK 0
BANK 1
BANK 0
BANK1
T12
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
CS
tCS
tCH
tCS
tCH
tCS
tCH
RAS
CAS
WE
tAS
tAH
ROW
A0-A9
tAS
tAH
ROW
tAH
tAS
A11
ROW
ROW
ROW
A10
(1)
(1)
BANK 0
BANK 1
tCS
BANK 0
tCH
tQMD
DQM
tAC
tLZ
tAC
tOH
DQ
DOUT 0m
tRRD
(BANK 0 TO 1)
tRCD
(BANK 0)
DOUT 0m+1
tAC
tOH
tOH
DOUT 1m
DOUT 1m+1
tCAC
(BANK 1)
tRCD
(BANK 1)
tHZ
tCAC
tRQL
(BANK 0)
tRAS
(BANK 0)
tRC
(BANK 0)
tRCD
(BANK 0)
tRAS
(BANK 0)
(BANK 0)
tRP
(BANK 0)
tRC
(BANK 0)
tRAS
tRP
(BANK 1)
tRC
(BANK 1)
<ACT 0>
tAC
tOH
<ACT1>
<READ 0>
<READA 0>
<READ 1>
<READA 1>
(BANK1)
<PRE 0>
<PRE 1>
<ACT 0>
Undefined
CAS latency = 3, burst length = 2
Don't Care
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
63
ISSI
IS45S16100C1
®
Write Cycle
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
CS
tCS
tCH
tCS
tCH
tCS
tCH
RAS
CAS
WE
tAS
tAH
tAS
COLUMN
ROW
BANK 0 AND 1
tAH
NO PRE
ROW
A10
tAH
tAS
A11
(1)
ROW
A0-A9
ROW
BANK 1
BANK 0 OR 1
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
BANK 1
BANK 0
tCS
tCH
DQM
tDS
tDH tDS
DIN m
DQ
tDH tDS
DIN m+1
tDH tDS
DIN m+2
tDH
DIN m+3
tDPL
tRCD
tRAS
tRCD
tRP
tRAS
tRC
<ACT>
tRC
<WRIT>
<PRE>
<PALL>
<ACT>
Undefined
CAS latency = 3, burst length = 4
Don't Care
Note 1: A8,A9 = Don’t Care.
64
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
ISSI
IS45S16100C1
®
Write Cycle / Auto-Precharge
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
CS
tCS
tCH
tCS
tCH
tCS
tCH
RAS
CAS
WE
tAS
tAH
tAS
COLUMN
ROW
AUTO PRE
tAH
ROW
A10
ROW
tAH
tAS
A11
(1)
ROW
A0-A9
BANK 1
BANK 1
BANK 1
BANK 0
BANK 0
tCS
BANK 0
tCH
DQM
tDS
tDH tDS
DIN m
DQ
tDH tDS
DIN m+1
tDH tDS
DIN m+2
tDH
DIN m+3
tDAL
tRCD
tRAS
tRCD
tRP
tRAS
tRC
<ACT>
tRC
<WRITA>
<ACT>
Undefined
CAS latency = 3, burst length = 4
Don't Care
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
65
ISSI
IS45S16100C1
®
Write Cycle / Full Page
T0
T1
T2
T3
T4
T5
T6
T259
T260
T261
T262
T263
T264
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
CS
tCS
tCH
tCS
tCH
tCS
tCH
RAS
CAS
WE
tAS
tAH
tAS
tAH
NO PRE
ROW
A10
BANK 0 OR 1
tAH
tAS
A11
(1)
COLUMN
ROW
A0-A9
BANK 0
BANK 0
BANK 0
tCH
tCS
DQM
tDS
DQ
tDH tDS
DIN 0m
tDH tDS
DIN 0m+1
tDH tDS
DIN 0m+2
tDH
DIN 0m-1
DIN 0m
tDPL
tRCD
tRAS
tRP
tRC
<ACT 0>
<WRIT0>
<BST>
<PRE 0>
Undefined
CAS latency = 3, burst length = full page
Don't Care
Note 1: A8,A9 = Don’t Care.
66
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
ISSI
IS45S16100C1
®
Write Cycle / Ping-Pong Operation (Bank Switching)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T11
T10
T12
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
CS
tCS
tCH
tCS
tCH
tCS
tCH
RAS
CAS
WE
tAS
tAH
ROW
COLUMN
tAS
ROW
COLUMN
AUTO PRE
AUTO PRE
tAH
ROW
A10
ROW
ROW
NO PRE
tAH
tAS
A11
(1)
(1)
ROW
A0-A9
BANK 0
BANK 0
BANK 1
NO PRE
BANK 0 OR 1
BANK 1
BANK 0
BANK 1
BANK 0
tCH
tCS
DQM
tDS
tDH tDS
DIN 0m
DQ
tDH tDS
DIN 0m+1
tRRD
(BANK 0 TO 1)
tRCD
(BANK 0)
tDH tDS
DIN 0m+2
tDH tDS
DIN 0m+3
tDH tDS
DIN 1m
tDH tDS
DIN 1m+1
tDH tDS
DIN 1m+2
tDH
DIN 1m+3
tDPL
(BANK 0)
tDPL
tRCD
tRCD
(BANK 1)
tRP
tRAS
tRAS
(BANK 0)
(BANK 0)
tRC
(BANK 0)
tRC
tRAS
(BANK 1)
tRC
(BANK 1)
<ACT 0>
<WRIT 0>
<WRITA 0>
<ACT 1>
<WRIT 1>
<WRITA 1>
<PRE 0>
<ACT 0>
Undefined
CAS latency = 3, burst length = 4
Don't Care
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
67
ISSI
IS45S16100C1
®
Read Cycle / Page Mode
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
CS
tCS
tCH
tCS
tCH
tCS
tCH
RAS
CAS
WE
tAS
tAH
A0-A9
tAS
(1)
COLUMN o
NO PRE
tAH
tAS
A11
(1)
COLUMN n
tAH
ROW
A10
(1)
COLUMN m
ROW
BANK 1
BANK 0
BANK 0 AND 1
NO PRE
BANK 0 OR 1
BANK 1
BANK 0
BANK 1
BANK 0
NO PRE
BANK 1
BANK 1
BANK 0
AUTO PRE
tCS
tQMD
BANK 0
tCH
DQM
tAC
tLZ
tAC
tOH
DQ
DOUT m
tAC
tOH
DOUT m+1
tAC
tAC
tOH
tOH
DOUT n
DOUT n+1
DOUT o
tCAC
<ACT>
tCAC
<READ>
tOH
DOUT o+1
tHZ
tCAC
tRCD
tRAS
tRC
tAC
tOH
tRQL
tRP
<READ>
<READ>
<READA>
<PRE>
<PALL>
Undefined
CAS latency = 3, burst length = 2
Don't Care
Note 1: A8,A9 = Don’t Care.
68
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
ISSI
IS45S16100C1
®
Read Cycle / Page Mode; Data Masking
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T11
T10
T12
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
CS
tCS
tCH
tCS
tCH
tCS
tCH
RAS
CAS
WE
tAS
tAH
ROW
A0-A9
tAS
(1)
COLUMN o
NO PRE
AUTO PRE
BANK 0 AND 1
NO PRE
BANK 0 OR 1
BANK 1
BANK 0
NO PRE
tAH
tAS
A11
(1)
COLUMN n
tAH
ROW
A10
(1)
COLUMN m
BANK 1
BANK 0
BANK 1
BANK 1
BANK 1
BANK 0
BANK 0
BANK 0
tCS
tQMD
tCH
tQMD
DQM
tAC
tAC
tOH
tLZ
DQ
DOUT m
tCAC
tRCD
tRAS
tRC
<ACT>
tAC
tOH
tAC
tAC
tOH
DOUT m+1
DOUT n
tOH
DOUT o
DOUT o+1
tHZ
tCAC
tCAC
<READ>
tOH
tRQL
tRP
<READ>
<READ, MASK>
<READA, MASK>
<ENB>
<PRE>
<PALL>
Undefined
CAS latency = 3, burst length = 2
Don't Care
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
69
ISSI
IS45S16100C1
®
Write Cycle / Page Mode
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
CS
tCS
tCH
tCS
tCH
tCS
tCH
RAS
CAS
WE
tAS
tAH
ROW
A0-A9
tAS
(1)
(1)
COLUMN n
COLUMN o
tAH
ROW
A10
tAH
tAS
A11
(1)
COLUMN m
AUTO PRE
BANK 0 AND 1
NO PRE
NO PRE
BANK 1
BANK 1
NO PRE
BANK 0 OR 1
BANK 1
BANK 0
BANK 0
BANK 0
BANK 1
BANK 0
BANK 0
tCS
tCH
DQM
tDS
tDH tDS
DIN m
DQ
tDH tDS
DIN m+1
tDH
tDS
tDH tDS
DIN o
DIN n
tRCD
tRAS
tRC
<ACT>
tDH
DIN o+1
tDPL
tRP
<WRIT>
<WRIT>
<MASK>
<WRIT>
<WRITA>
<PRE>
<PALL>
Undefined
CAS latency = 3, burst length = 2
Don't Care
Note 1: A8,A9 = Don’t Care.
70
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
ISSI
IS45S16100C1
®
Write Cycle / Page Mode; Data Masking
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
CS
tCS
tCH
tCS
tCH
tCS
tCH
RAS
CAS
WE
tAS
tAH
ROW
A0-A9
tAS
(1)
(1)
COLUMN n
COLUMN o
tAH
NO PRE
ROW
A10
tAH
tAS
A11
(1)
COLUMN m
BANK 1
BANK 0
tCS
AUTO PRE
BANK 0 AND 1
NO PRE
BANK 1OR 0
NO PRE
BANK 1
BANK 1
BANK 0
BANK 0
BANK 1
BANK 0
tCH
BANK 1
BANK 0
DQM
tDS
tDH tDS
DIN m
DQ
tDH tDS
DIN m+1
tDH
tDS
DIN n
tDH tDS
DIN o
tRCD
tRAS
tRC
<ACT>
tDH
DIN o+1
tDPL
tRP
<WRIT>
<WRIT>
<MASK>
<WRIT>
<WRITA>
<PRE>
<PALL>
Undefined
CAS latency = 3, burst length = 2
Don't Care
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
71
ISSI
IS45S16100C1
®
Read Cycle / Clock Suspend
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCKS
tCL
tCKH
CS
tCS
tCH
tCS
tCH
tCS
tCH
tAS
tAH
RAS
CAS
WE
tAS
tAH
AUTO PRE
BANK 0 AND 1
tAH
NO PRE
BANK 0 OR 1
BANK 1
BANK 0
BANK 1
ROW
A10
tAS
A11
(1)
COLUMN m
ROW
A0-A9
BANK 1
BANK 0
tCS
BANK 0
tCH
tQMD
DQM
tAC
tAC
tOH
DQ
tOH
DOUT m
DOUT m+1
tLZ
tRCD
tHZ
tCAC
tRAS
tRP
tRC
<ACT>
<READ>
<READ A>
<SPND>
<SPND>
<PRE>
<PALL>
Undefined
CAS latency = 3, burst length = 2
Don't Care
Note 1: A8,A9 = Don’t Care.
72
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
ISSI
IS45S16100C1
®
Write Cycle / Clock Suspend
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
tCKS
tCKH
CS
tCS
tCH
tCS
tCH
tCS
tCH
tAS
tAH
RAS
CAS
WE
tAS
ROW
BANK 0 AND 1
tAH
AUTO PRE
tAH
NO PRE
BANK 0 OR 1
BANK 1
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
ROW
ROW
A10
tAS
A11
(1)
COLUMN m
ROW
A0-A9
BANK 1
BANK 0
tCS
tCH
DQM
tDS
tDH
DIN m
DQ
tRCD
tDS
tDH
DIN m+1
tDPL
tRAS
tRAS
tRP
tRC
<ACT>
tRC
<WRIT, SPND> <SPND>
<WRITA, SPND>
<PRE>
<PALL>
<ACT >
Undefined
CAS latency = 3, burst length = 2
Don't Care
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
73
ISSI
IS45S16100C1
®
Read Cycle / Precharge Termination
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
CS
tCS
tCH
tCS
tCH
tCS
tCH
RAS
CAS
WE
tAS
tAH
tAS
ROW
tAH
ROW
ROW
A10
tAH
tAS
A11
(1)
COLUMN m
ROW
A0-A9
BANK 0
NO PRE
BANK 0 OR 1
BANK 0
BANK 0
tCS
BANK 1
BANK 0
tCH
tQMD
DQM
tAC
tAC
tOH
DQ
DOUT m
tAC
tOH
tHZ
tOH
DOUT m+1
DOUT m+2
tLZ
tRCD
tCAC
tRAS
tRQL
tRCD
tRP
tRAS
tRC
<ACT 0>
tRP
<READ 0>
<PRE 0>
<ACT>
Undefined
CAS latency = 3, burst length = 2
Don't Care
Note 1: A8,A9 = Don’t Care.
74
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
ISSI
IS45S16100C1
®
Write Cycle / Precharge Termination
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
CS
tCS
tCH
tCS
tCH
tCS
tCH
tAS
tAH
RAS
CAS
WE
tAS
ROW
tAH
ROW
ROW
A10
tAH
tAS
A11
(1)
COLUMN m
ROW
A0-A9
BANK 0
NO PRE
BANK 0 OR 1
BANK 0
BANK 0
tCS
tCS
tCH
BANK 1
BANK 0
tCH
DQM
tDH
tDS
tDS
DQ
DIN 0m
tDH
tDS
DIN 0m+1
tDH
DIN 0m+2
tRCD
tRCD
tRAS
tRAS
tRP
tRC
<ACT 0>
tRP
<WRIT 0>
<PRE 0>
<ACT >
Undefined
CAS latency = 3, burst length = 4
Don't Care
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
75
ISSI
IS45S16100C1
®
Read Cycle / Byte Operation
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
CS
tCS
tCH
tCS
tCH
tCS
tCH
RAS
CAS
WE
tAS
tAH
tAS
ROW
tAH
AUTO PRE
BANK 0 AND 1
tAH
NO PRE
BANK 0 OR 1
ROW
ROW
A10
tAS
A11
(1)
COLUMN m
ROW
A0-A9
BANK 1
BANK 1
BANK 0
BANK 0
BANK 1
BANK 1
tCS
tQMD
tCS
tQMD
BANK 0
tCH
BANK 0
UDQM
tCH
LDQM
tAC
tLZ
DQ8-15
tAC
tHZ
tOH
tAC
tLZ
DOUT m+2
DOUT m
tAC
tLZ
DQ0-7
tRCD
tCAC
tAC
tHZ
tOH
DOUT m+3
tHZ
tOH
tOH
DOUT m
DOUT m+1
tQMD
tRAS
tRQL
tRCD
tRP
tRAS
tRP
tRC
<ACT>
<READ>
<READA>
<MASKU>
<ENBU, MASKL> <MASKL>
<PRE>
<PALL>
<ACT>
Undefined
CAS latency = 3, burst length = 4
Don't Care
Note 1: A8,A9 = Don’t Care.
76
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
ISSI
IS45S16100C1
®
Write Cycle / Byte Operation
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
CS
tCS
tCH
tCS
tCH
tCS
tCH
RAS
CAS
WE
tAS
tAH
A0-A9
tAS
tAH
ROW
AUTO PRE
BANK 0 AND 1
NO PRE
BANK 0 OR 1
BANK 1
BANK 0
BANK 1
ROW
ROW
A10
tAH
tAS
A11
(1)
COLUMN m
ROW
BANK 1
BANK 0
tCS
BANK 0
tCH
BANK 1
BANK 0
UDQM
tCS
tCH
tDS
tDS
tDH
LDQM
DQ8-15
DIN m
tDH
DIN m+1
DIN m+3
tDH
tDS
tDH
tDS
DIN m
DQ0-7
tDH
tDS
DIN m+3
tRCD
tDPL
tRCD
tRAS
tRP
tRAS
tRP
tRC
<ACT>
<WRIT>
<WRITA>
<MASKL>
<MASK>
<ENB>
<PRE>
<PALL>
<ACT>
Undefined
CAS latency = 3, burst length = 4
Don't Care
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
77
ISSI
IS45S16100C1
®
Read Cycle, Write Cycle / Burst Read, Single Write
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T11
T10
T12
CLK
tCKS
tCK
tCS
tCKA
tCH
CKE
tCHI
tCL
CS
tCS
tCH
tCS
tCH
tCS
tCH
RAS
CAS
WE
tAS
tAH
A0-A9
tAS
AUTO PRE
BANK 0 AND 1
NO PRE
BANK 0 OR 1
BANK 1
BANK 1
NO PRE
tAH
tAS
A11
COLUMN n
tAH
ROW
A10
(1)
(1)
COLUMN m
ROW
BANK 1
BANK 1
BANK 0
BANK 0
tCS
BANK 0
tQMD
tCH
BANK 0
DQM
tAC
DQ
tLZ
tRC
tAC
tDS
tOH
tOH
DOUT m
DOUT m+1
tDH
DIN n
tHZ
tCAC
tDPL
tRAS
tRP
tRC
<ACT>
<READ>
<WRIT>
<WRITA>
<PRE>
<PALL>
Undefined
CAS latency = 3, burst length = 2
Don't Care
Note 1: A8,A9 = Don’t Care.
78
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
ISSI
IS45S16100C1
®
ORDERING INFORMATION
Automotive Range: 0°°C to +70°°C
Frequency
143MHz
143MHz
Speed (ns)
7
7
Order Part No.
IS45S16100C1-7TLA
IS45S16100C1-7BLA
Package
400-mil TSOP II, Lead-free
60-ball fBGA, Lead-free
Order Part No.
IS45S16100C1-7TA1
IS45S16100C1-7TLA1
IS45S16100C1-7BLA1
Package
400-mil TSOP II
400-mil TSOP II, Lead-free
60-ball fBGA, Lead-free
Automotive Range: -40°°C to +85°°C
Frequency
143MHz
143MHz
143MHz
Speed (ns)
7
7
7
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/03/06
79
ISSI
PACKAGING INFORMATION
®
Mini Ball Grid Array
Package Code: B (60-Ball)
ø 0.40 + +/-0.05 (60X)
7 6 5 4 3 2 1
1 2 3 4 5 6 7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
e
D
D1
e
E1
E
A1
A
Notes:
1. Controlling dimensions are in millimeters.
2. 0.65 mm Ball Pitch
SEATING PLANE
mBGA - 10.1mm x 6.4mm
MILLIMETERS
Sym. Min.
No.
Leads
A
Min. Typ.
Max.
60
—
A1
0.23
D
10.00
D1
Typ. Max.
INCHES
—
1.20
0.28
0.33
10.10 10.20
—
—
0.047
0.009 0.011 0.013
0.394 0.398
—
0.358
0.402
—
9.10
—
E
6.30
6.40
6.50
E1
—
3.90
—
—
0.154
—
e
—
0.65
—
—
0.026
—
0.248 0.252
—
0.256
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
02/16/06
ISSI
®
PACKAGING INFORMATION
Plastic TSOP
Package Code: T (Type II)
N
N/2+1
E1
1
Notes:
1. Controlling dimension: millimieters,
unless otherwise specified.
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions and
should be measured from the
bottom of the package.
4. Formed leads shall be planar with
respect to one another within
0.004 inches at the seating plane.
E
N/2
D
SEATING PLANE
A
ZD
.
b
e
Symbol
Ref. Std.
No. Leads
A
A1
b
C
D
E1
E
e
L
ZD
α
Millimeters
Min
Max
Inches
Min
Max
(N)
32
—
1.20
—
0.047
0.05 0.15
0.002 0.006
0.30 0.52
0.012 0.020
0.12 0.21
0.005 0.008
20.82 21.08
0.820 0.830
10.03 10.29
0.391 0.400
11.56 11.96
0.451 0.466
1.27 BSC
0.050 BSC
0.40 0.60
0.016 0.024
0.95 REF
0.037 REF
0°
5°
0°
5°
L
α
A1
Plastic TSOP (T - Type II)
Millimeters
Inches
Min
Max
Min Max
44
—
1.20
—
0.047
0.05 0.15
0.002 0.006
0.30 0.45
0.012 0.018
0.12 0.21
0.005 0.008
18.31 18.52
0.721 0.729
10.03 10.29
0.395 0.405
11.56 11.96
0.455 0.471
0.80 BSC
0.032 BSC
0.41 0.60
0.016 0.024
0.81 REF
0.032 REF
0°
5°
0°
5°
Millimeters
Min
Max
C
Inches
Min
Max
50
—
1.20
0.05 0.15
0.30 0.45
0.12 0.21
20.82 21.08
10.03 10.29
11.56 11.96
0.80 BSC
0.40 0.60
0.88 REF
0°
5°
—
0.047
0.002 0.006
0.012 0.018
0.005 0.008
0.820 0.830
0.395 0.405
0.455 0.471
0.031 BSC
0.016 0.024
0.035 REF
0°
5°
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
06/18/03