ISSI IS75V16F64GS16

ISSI
75V16F64GS16
®
64 Mbit FLASH MEMORY AND 16 Mbit PSEUDO SRAM
STACKED MULTI-CHIP PACKAGE (MCP)
PRELIMINARY INFORMATION
AUGUST 2002
MCP FEATURES
• Power supply voltage of 2.7 to 3.1 volt
• High performance:
- Flash access time as fast as 70 ns
• WP/ACC Input Pin
- At VIL, allows protection of “outermost” 2 × 8 Kbytes
on both ends of boot sectors, regardless of sector
protection/unprotection status
- At VIH, allows removal of boot sector protection
- At VACC, program time will be reduced by 40 %
- PSRAM access time as fast as 80 ns
• Package: 65-Ball FBGA
• Operating Temperature: –30°C to +85°C
• Embedded EraseTM Algorithms
FLASH MEMORY FEATURES
• 0.16 µm Process Technology
• Simultaneous Read/Write Operations (Dual Bank)
• FlexBankTM architecture
•
•
•
•
- Bank A : 8 Mbit ( 8 KB x 8 and 64 KB x 15)
- Bank B : 24 Mbit (64 KB x 48)
- Bank C : 24 Mbit (64 KB x 48)
- Bank D : 8 Mbit ( 8 KB x 8 and 64 KB x 15)
- Two virtual Banks are chosen from the combination
of four physical banks (Refer to "Example of Virtual
Banks Combination Table" and Simultaneous
Operation Table" in FLEXIBLE SECTOR-ERASE
ARCHITECTURE on FLASH MEMORY)
- Host system can program or erase in one bank, and
then read immediately and simultaneously from the
other bank with zero latency between read and write
operations.
- Read-while-erase
- Read-while-program
Single 3.0 V Read, Program, and Erase
- Minimized system level power requirements
Minimum 100,000 Program/Erase Cycles
Sector Erase Architecture
- Sixteen 4 Kword and one hundred twenty-six 32
Kword sectors in word
- Any combination of sectors can be concurrently
erased
- Supports full chip erase
Hidden ROM (Hi-ROM) Region
- 256 byte of Hi-ROM, accessible through a new "HIROM Enable" command sequence
- Factory serialized and protected to provide a secure
electronic serial number (ESN)
•
•
•
•
•
•
•
- Automatically preprograms and erases the chip
or any sector
Embedded ProgramTM Algorithms
- Automatically writes and verifies data at specified
address
Data Polling and Toggle Bit Feature for Detection of
Program or Erase Cycle Completion
Ready/Busy Output (RY/BY)
- Hardware method for detection of program or
erase cycle completion
Automatic Sleep Mode
- When addresses remain stable, the device
automatically switches itself to low power mode.
Low VCCf Write Inhibit ≤ 2.5 V
Program Suspend/Resume
- Suspends the program operation to allow a read
in another byte
Erase Suspend/Resume
- Suspends the erase operation to allow a read
data and/or program in another sector within the
same device
PSRAM FEATURES
• Power Dissipation:
•
•
•
- Operating
: 20 mA Max
- Standby
: 70 µA Max
- Power Down : 10 µA Max
Power down Control by CE2r
Byte Write Control : LB (DQ7-DQ0), UB (DQ15-DQ8)
4 words Address Access Capability
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products. FlexBankTM is a trademark
of Fujitsu Limited, Japan. Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
1
ISSI
75V16F64GS16
®
PIN CONFIGURATION (64 Mb Flash and 16 Mb PSRAM)
PACKAGE CODE: D 65 BALL FBGA (Top View) (9.00 mm x 9.00 mm Body, 0.8 mm Ball Pitch)
A
B
C
D
E
F
G
H
J
K
10
NC
NC
9
NC
NC
A15
A21
NC
A16
Vccf
GND
A11
A12
A13
A14
NC
DQ15
DQ7
DQ14
A8
A19
A9
A10
DQ6
DQ13
DQ12
DQ5
WE
CE2r
A20
DQ4
Vccr
NC
DQ3
Vccf
DQ11
8
7
6
5
WP/ACC RESET RY/BY
4
LB
UB
A18
A17
DQ1
DQ9
DQ10
DQ2
A7
A6
A5
A4
GND
OE
DQ0
DQ8
A3
A2
A0
CEf
CE1r
Common
3
Flash Only
2
NC
A1
NC
PSRAM Only
1
NC
NC
NC
PIN DESCRIPTIONS
2
A0-A19
Address Inputs, Common
LB
Lower-byte Control, PSRAM
A20-A21
Address Inputs, Flash
UB
Upper-byte Control, PSRAM
DQ0-DQ15 Data Inputs/Outputs, Common
WP/ACC
Write Protect/Acceleration, Flash
RESET
RY/BY
Ready/Busy Output
CE1r,CE2r Chip Enable, PSRAM
NC
No Internal Connection
RY/BY
Ready/Busy Output, Flash Open Drain Output
Vccf
Device Power Supply, Flash
CEf
Chip Enable, Flash
GND
Device Ground, Common
OE
Output Enable, Common
Vccr
Device Power, PSRAM
WE
Write Enable, Common
Hardware Reset Pin/Acceleration, Flash
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
ISSI
75V16F64GS16
®
MCP BLOCK DIAGRAM
Vccf GND
A21-A0
A21-A0
WP/ACC
RESET
CEf
RY/BY
64-MBIT
Flash Memory
DQ15-DQ0
DQ15-DQ0
VCCr GND
A19-A0
LB
UB
WE
OE
CE1r
CE2r
DQ15-DQ0
16-MBIT
Static PSRAM
LOGIC SYMBOL
22
A21-A0
CEf
CE1r
RY/BY
CE2r
OE
WE
x16
WP/ACC DQ15-DQ0
RESET
UB
LB
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
3
ISSI
75V16F64GS16
®
FLASH MEMORY BLOCK DIAGRAM
OE
Y-Decoder
Upper Bank Address
A21-A0
Upper Bank
Latches and
Control Logic
VCC
GND
DQ15-DQ0
A21-A0
A21-A0
X-Decoder
RESET
STATE
CONTROL
&
COMMAND
REGISTER
WE
CE
WP/ACC
DQ15-DQ0
Status
Control
DQ15-DQ0
X-Decoder
A21-A0
Lower Bank
Latches and
Control Logic
Lower Bank Address
Y-Decoder
DQ15-DQ0
A21-A0
OE
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
ISSI
75V16F64GS16
®
DEVICE BUS OPERATIONS
OPERATION(1,2)
CE
CEf CE1
CE1r CE2r
Full Standby
Output Disable(3)
Read from Flash(4)
Write to Flash
Read from PSRAM(5)
Write to PSRAM
Temporary
Sector
Group Unprotection(6)
Flash Hardware
Reset
Boot Block
Sector Write
Protection
PSRAM Power Down(8)
OE
WE
LB
LBs
UB
UBs
DQ7-DQ0 DQ15-DQ8 RESET WP
WP/ACC(7)
X
X
X
X
X
X
L
H
L
X
X
X
X
X
X
L
L
H
High-Z
High-Z
High-Z
DOUT
DIN
DOUT
DIN
High-Z
DIN
High-Z
High-Z
High-Z
DOUT
DIN
DOUT
DIN
DIN
High-Z
H
H
H
H
H
H
X
X
X
X
X
X
H
X
H
H
L
L
L
H
H
L
H
H
H
L
H
X
X
X
X
H
X
H
H
L
H
L
X
H
H
H
L
H
H
L
H
H
L
X
X
X
X
X
X
X
X
X
VID
X
X
H
H
X
X
X
X
High-Z
High-Z
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
L
X
X
X
X
X
X
X
X
Legend : L = VIL, H = VIH, X = VIL or VIH. See “DC CHARACTERISTICS” for voltage levels.
Notes:
1. Other operations not indicated in this table are prohibited.
2. Do not apply CEf = VIL, CE1r = VIL and CE2r = VIH all at once.
3. PSRAM Output Disable condition should not be kept longer than 1 ms.
4. WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
5. PSRAM Byte control at Read operation is not supported.
6. Also used for the extended sector group protections.
7. Protects “outermost” 2 ´ 8 Kbytes (4 words) on both ends of the boot block sectors.
8. Power Down mode can be entered from Standby state and all DQ pins are in High-Z state.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
5
ISSI
75V16F64GS16
®
FLEXIBLE SECTOR-ERASE ARCHITECTURE ON FLASH MEMORY
Bank
Sector
Bank
Sector
Type
Address K-Word Address
Type
Address K-Word Address
BankA
SA0
4
000000h
BankB
SA36
32
0E8000h
BankA
SA1
4
001000h
BankB
SA37
32
0F0000h
BankA
SA2
4
002000h
BankB
SA38
32
0F8000h
BankA
SA3
4
003000h
BankB
SA39
32
100000h
BankA
SA4
4
004000h
BankB
SA40
32
108000h
BankA
SA5
4
005000h
BankB
SA41
32
110000h
BankA
SA6
4
006000h
BankB
SA42
32
118000h
BankA
SA7
4
007000h
BankB
SA43
32
120000h
BankA
SA8
32
008000h
BankB
SA44
32
128000h
BankA
SA9
32
010000h
BankB
SA45
32
130000h
BankA
SA10
32
018000h
BankB
SA46
32
138000h
BankA
SA11
32
020000h
BankB
SA47
32
140000h
BankA
SA12
32
028000h
BankB
SA48
32
148000h
BankA
SA13
32
030000h
BankB
SA49
32
150000h
BankA
SA14
32
038000h
BankB
SA50
32
158000h
BankA
SA15
32
040000h
BankB
SA51
32
160000h
BankA
SA16
32
048000h
BankB
SA52
32
168000h
BankA
SA17
32
050000h
BankB
SA53
32
170000h
BankA
SA18
32
058000h
BankB
SA54
32
178000h
BankA
SA19
32
060000h
BankB
SA55
32
180000h
BankA
SA20
32
068000h
BankB
SA56
32
188000h
BankA
SA21
32
070000h
BankB
SA57
32
190000h
BankA
SA22
32
078000h
BankB
SA58
32
198000h
BankB
SA23
32
080000h
BankB
SA59
32
1A0000h
BankB
SA24
32
088000h
BankB
SA60
32
1A8000h
BankB
SA25
32
090000h
BankB
SA61
32
1B0000h
BankB
SA26
32
098000h
BankB
SA62
32
1B8000h
BankB
SA27
32
0A0000h
BankB
SA63
32
1C0000h
BankB
SA28
32
0A8000h
BankB
SA64
32
1C8000h
BankB
SA29
32
0B0000h
BankB
SA65
32
1D0000h
BankB
SA30
32
0B8000h
BankB
SA66
32
1D8000h
BankB
SA31
32
0C0000h
BankB
SA67
32
1E0000h
BankB
SA32
32
0C8000h
BankB
SA68
32
1E8000h
BankB
SA33
32
0D0000h
BankB
SA69
32
1F0000h
BankB
SA34
32
0D8000h
BankB
SA70
32
1F8000h
BankB
SA35
32
0E0000h
BankC
SA71
32
200000h
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
ISSI
75V16F64GS16
®
FLEXIBLE SECTOR-ERASE ARCHITECTURE ON FLASH MEMORY (Continued)
Bank
Sector
Bank
Sector
Type
Address K-Word Address
Type
Address K-Word Address
BankC
SA72
32
208000h
BankC
SA107
32
320000h
BankC
SA73
32
210000h
BankC
SA108
32
328000h
BankC
SA74
32
218000h
BankC
SA109
32
330000h
BankC
SA75
32
220000h
BankC
SA110
32
338000h
BankC
SA76
32
228000h
BankC
SA111
32
340000h
BankC
SA77
32
230000h
BankC
SA112
32
348000h
BankC
SA78
32
238000h
BankC
SA113
32
350000h
BankC
SA79
32
240000h
BankC
SA114
32
358000h
BankC
SA80
32
248000h
BankC
SA115
32
360000h
BankC
SA81
32
250000h
BankC
SA116
32
368000h
BankC
SA82
32
258000h
BankC
SA117
32
370000h
BankC
SA83
32
260000h
BankC
SA118
32
378000h
BankC
SA84
32
268000h
BankD
SA119
32
380000h
BankC
SA85
32
270000h
BankD
SA120
32
388000h
BankC
SA86
32
278000h
BankD
SA121
32
390000h
BankC
SA87
32
280000h
BankD
SA122
32
398000h
BankC
SA88
32
288000h
BankD
SA123
32
3A0000h
BankC
SA89
32
290000h
BankD
SA124
32
3A8000h
BankC
SA90
32
298000h
BankD
SA125
32
3B0000h
BankC
SA91
32
2A0000h
BankD
SA126
32
3B8000h
BankC
SA92
32
2A8000h
BankD
SA127
32
3C0000h
BankC
SA93
32
2B0000h
BankD
SA128
32
3C8000h
BankC
SA94
32
2B8000h
BankD
SA129
32
3D0000h
BankC
SA95
32
2C0000h
BankD
SA130
32
3D8000h
BankC
SA96
32
2C8000h
BankD
SA131
32
3E0000h
BankC
SA97
32
2D0000h
BankD
SA132
32
3E8000h
BankC
SA98
32
2D8000h
BankD
SA133
32
3F0000h
BankC
SA99
32
2E0000h
BankD
SA134
4
3F8000h
BankC
SA100
32
2E8000h
BankD
SA135
4
3F9000h
BankC
SA101
32
2F0000h
BankD
SA136
4
3FA000h
BankC
SA102
32
2F8000h
BankD
SA137
4
3FB000h
BankC
SA103
32
300000h
BankD
SA138
4
3FC000h
BankC
SA104
32
308000h
BankD
SA139
4
3FD000h
BankC
SA105
32
310000h
BankD
SA140
4
3FE000h
BankC
SA106
32
318000h
BankD
SA141
4
3FF000h
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
7
ISSI
75V16F64GS16
®
FLEXBANK TM ARCHITECTURE TABLE
Bank 1
Bank Split
Bank 2
Volume
Combination
Volume
Combination
1
8 Mbit
Bank A
56 Mbit
Bank B, C, D
2
24 Mbit
Bank B
40 Mbit
Bank A, C, D
3
24 Mbit
Bank C
40 Mbit
Bank A, B, D
4
8 Mbit
Bank D
56 Mbit
Bank A, B, C
EXAMPLE OF VIRTUAL BANKS COMBINATION TABLE
Bank 1
Bank Split Volume
1
8 Mbit
Bank 2
Combination
Sector Size
Volume
Combination
Sector Size
Bank A
8x4 Kword
56 Mbit
Bank B, C, D
8x4 Kword
15x32 Kword
2
16 Mbit
Bank A,D
16x4 Kword
111x32 Kword
48 Mbit
Bank B,C
96x32 Kword
40 Mbit
Bank A, C, D
16x4 Kword
30x32 Kword
3
24 Mbit
Bank B
48x32 Kword
78x32 Kword
4
32 Mbit
Bank A,B
8x4 Kword
63x32 Kword
32 Mbit
Bank C,D
8x4 Kword
63x32 Kword
Notes:
1) When multiple sector erase over several banks is operated, the system cannot read out of the bank to which a sector being
erased belongs. For example, if erasing is taking place at both Bank A and Bank B, neither Bank A nor Bank B is read out. They
would output the sequence flag once they were selected. Meanwhile the system would get to read from either Bank C or Bank D.
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
ISSI
75V16F64GS16
®
SIMULTANEOUS OPERATION TABLE
Case
Bank 1 Status
Bank 2 Status
1
Read Mode
Read Mode
2
Read Mode
Autoselect Mode
3
Read Mode
Program Mode
4
Read Mode
Erase Mode (1)
5
Autoselect Mode
Read Mode
6
Program Mode
Read Mode
7
Note:
Erase Mode
(1)
Read Mode
1) By writing erase suspend command on the bank address of sector being erased, the erase operation gets suspended so that it
enables reading from or programming the remaining sectors.
2) Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. Actually, the Bank consists of 4 banks,
Bank A, Bank B, Bank C and Bank D. Bank Address (BA) means to specify each of the Banks.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
9
ISSI
75V16F64GS16
®
SECTOR ADDRESS TABLE
Bank Address
Sector Address
Address Range
Bank
Sector
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Word Mode
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
000000h to 000FFFh
001000h to 001FFFh
002000h to 002FFFh
003000h to 003FFFh
004000h to 004FFFh
005000h to 005FFFh
006000h to 006FFFh
007000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 067FFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
0
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
ISSI
75V16F64GS16
®
SECTOR ADDRESS TABLE (Continued)
Bank Address
Sector Address
Address Range
Bank
Sector
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Word Mode
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
0F8000h to 0FFFFFh
100000h to 107FFFh
108000h to 10FFFFh
110000h to 117FFFh
118000h to 11FFFFh
120000h to 127FFFh
128000h to 12FFFFh
130000h to 137FFFh
138000h to 13FFFFh
140000h to 147FFFh
148000h to 14FFFFh
150000h to 157FFFh
158000h to 15FFFFh
160000h to 167FFFh
168000h to 16FFFFh
170000h to 177FFFh
178000h to 17FFFFh
180000h to 187FFFh
188000h to 18FFFFh
190000h to 197FFFh
198000h to 19FFFFh
1A0000h to 1A7FFFh
1A8000h to 1AFFFFh
1B0000h to 1B7FFFh
1B8000h to 1BFFFFh
1C0000h to 1C7FFFh
1C8000h to 1CFFFFh
1D0000h to 1D7FFFh
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
11
ISSI
75V16F64GS16
®
SECTOR ADDRESS TABLE (Continued)
Bank Address
Sector Address
Address Range
Bank
Sector
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Word Mode
Bank B
Bank B
Bank B
Bank B
Bank B
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1D8000h to 1DFFFFh
1E0000h to 1E7FFFh
1E8000h to 1EFFFFh
1F0000h to 1F7FFFh
1F8000h to 1FFFFFh
200000h to 207FFFh
208000h to 20FFFFh
210000h to 217FFFh
218000h to 21FFFFh
220000h to 227FFFh
228000h to 22FFFFh
230000h to 237FFFh
238000h to 23FFFFh
240000h to 247FFFh
248000h to 24FFFFh
250000h to 257FFFh
258000h to 25FFFFh
260000h to 267FFFh
268000h to 26FFFFh
270000h to 277FFFh
278000h to 27FFFFh
280000h to 287FFFh
288000h to 28FFFFh
290000h to 297FFFh
298000h to 29FFFFh
2A0000h to 2A7FFFh
2A8000h to 2AFFFFh
2B0000h to 2B7FFFh
2B8000h to 2BFFFFh
2C0000h to 2C7FFFh
2C8000h to 2CFFFFh
2D0000h to 2D7FFFh
2D8000h to 2DFFFFh
2E0000h to 2E7FFFh
12
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
ISSI
75V16F64GS16
®
SECTOR ADDRESS TABLE (Continued)
Bank Address
Sector Address
Address Range
Bank
Sector
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Word Mode
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
SA135
SA136
SA137
SA138
SA139
SA140
SA141
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2E8000h to 2EFFFFh
2F0000h to 2F7FFFh
2F8000h to 2FFFFFh
300000h to 307FFFh
308000h to 30FFFFh
310000h to 317FFFh
318000h to 31FFFFh
320000h to 327FFFh
328000h to 32FFFFh
330000h to 337FFFh
338000h to 33FFFFh
340000h to 347FFFh
348000h to 34FFFFh
350000h to 357FFFh
358000h to 35FFFFh
360000h to 367FFFh
368000h to 36FFFFh
370000h to 377FFFh
378000h to 37FFFFh
380000h to 387FFFh
388000h to 38FFFFh
390000h to 397FFFh
398000h to 39FFFFh
3A0000h to 3A7FFFh
3A8000h to 3AFFFFh
3B0000h to 3B7FFFh
3B8000h to 3BFFFFh
3C0000h to 3C7FFFh
3C8000h to 3CFFFFh
3D0000h to 3D7FFFh
3D8000h to 3DFFFFh
3E0000h to 3E7FFFh
3E8000h to 3EFFFFh
3F0000h to 3F7FFFh
3F8000h to 3F8FFFh
3F9000h to 3F9FFFh
3FA000h to 3FAFFFh
3FB000h to 3FBFFFh
3FC000h to 3FCFFFh
3FD000h to 3FDFFFh
3FE000h to 3FEFFFh
3FF000h to 3FFFFFh
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
0
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
13
ISSI
75V16F64GS16
®
SECTOR ADDRESS GROUP TABLE
Sector
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Sectors
SGA0
SGA1
SGA2
SGA3
SGA4
SGA5
SGA6
SGA7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SGA8
0
0
0
0
0
SGA9
SGA10
SGA11
SGA12
SGA13
SGA14
SGA15
SGA16
SGA17
SGA18
SGA19
SGA20
SGA21
SGA22
SGA23
SGA24
SGA25
SGA26
SGA27
SGA28
SGA29
SGA30
SGA31
SGA32
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
14
0
0
0
0
0
0
0
0
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
X
X
X
SA8 to SA10
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA11 to SA14
SA15 to SA18
SA19 to SA22
SA23 to SA26
SA27 to SA30
SA31 to SA34
SA35 to SA38
SA39 to SA42
SA43 to SA46
SA47 to SA50
SA51 to SA54
SA55 to SA58
SA59 to SA62
SA63 to SA66
SA67 to SA70
SA71 to SA74
SA75 to SA78
SA79 to SA82
SA83 to SA86
SA87 to SA90
SA91 to SA94
SA95 to SA98
SA99 to SA102
SA103 to SA106
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
ISSI
75V16F64GS16
®
SECTOR ADDRESS GROUP TABLE (Continued)
Sector
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Sectors
SGA33
SGA34
SGA35
SGA36
SGA37
SGA38
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
1
1
0
0
1
1
0
1
0
1
0
SGA39
1
1
1
1
1
SGA40
SGA41
SGA42
SGA43
SGA44
SGA45
SGA46
SGA47
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
X
X
X
X
0
0
1
1
1
1
1
1
1
1
1
X
X
X
X
X
X
0
1
0
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA107 to SA110
SA111 to SA114
SA115 to SA118
SA119 to SA122
SA123 to SA126
SA127 to SA130
X
X
X
SA131 to SA133
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SA134
SA135
SA136
SA137
SA138
SA139
SA140
SA141
FLASH MEMORY AUTOSELECT CODES TABLE
Type
A21 to A12
A6
A3
A2
A1
A0
Code (HEX)
Manufacture's Code
BA
L
L
L
L
L
04h
Device Code
BA
L
L
L
L
H
227Eh
Extended Device
BA
L
H
H
H
L
2202h
BA
L
H
H
H
H
2201h
L
L
L
H
L
01h(1)
(2)
Code
Sector Group
Protection
Sector Group
Address
Legend: L = VIL, H = VIH. See “n DC CHARACTERISTICS” for voltage levels.
Notes:
1. Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.
2. A read cycle at address (BA) 01h outputs device code. When 227Eh was output, this indicates that there will require two
additional codes, called Extended Device Codes. Therefore the system may continue reading out these Extended Device Codes
at the address of (BA) 0Eh, as well as at (BA) 0Fh.
.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
15
ISSI
75V16F64GS16
®
FLASH MEMORY COMMAND DEFINITIONS
First Bus
Cycle
Second Bus
Write Cycle
Bus
Write
Cycle
Req'd
Addr.
Data
Addr.
Data
(1)
1
XXXh
F0h
—
—
Read / Reset (1)
3
555h
AAh
2AAh
55h
Autoselect
3
555h
AAh
2AAh
Program
4
555h
B0h
2AAh
Program Suspend
1
BA
30h
—
Program Resume
1
BA
AAh
Chip Erase
6
555h
Command
Sequence
Read / Reset
AAh
Third Bus
Write Cycle
Fourth Bus
Read/Write
Data
Addr.
Data
—
—
—
555h
F0h
RA
55h
(BA)
555h
90h
55h
555h
—
—
2AAh
Fifth Bus
Cycle
Data
Addr.
Data
—
—
—
—
RD
—
—
—
—
—
—
—
—
—
—
A0h
PA
PD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
55h
555h
80h
555h
AAh
2AAh
55h
555h
10h
—
—
—
—
—
Addr.
—
—
Addr.
Sixth Bus
Cycle
—
B0h
2AAh
55h
555h
80h
555h
AAh
2AAh
BA
B0h
—
—
—
—
—
—
1
BA
30h
—
—
—
—
—
—
Extended Sector
Group Protection
4
XXXh
60h
SPA
60h
SPA
40h
SPA
SD
—
—
—
—
Set to Fast
Mode (2)
3
555h
AAh
2AAh
55h
555h
20h
—
—
—
—
—
—
(2)
2
XXXh
A0h
PA
PD
—
—
—
—
—
—
—
Reset from Flash
Mode (2)
2
BA
90h
XXXh
(6)
F0H
—
—
—
—
—
—
—
1
(BA)
55h
98h
—
—
—
—
—
—
3
555h
AAh
2AAh
55h
555h
88h
—
—
—
—
4
555h
AAh
2AAh
55h
555h
A0h
(HRA)
PA
PD
—
—
—
—
4
555h
AAh
2AAh
55h
90h
XXXh
00h
—
—
—
—
Sector Erase
6
555h
Erase Suspend
1
Erase Resume
(3)
Flash Program
Query
(4)
Hi-ROM
Entry
Hi-ROM
Program
Hi-ROM
Exit (5)
(5)
(HRBA)
555h
55h
SA
30h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Notes:
1. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
2. This command is valid during Fast Mode.
3. This command is valid while RESET = VID
4. The valid address is A6 to A0.
5. This command is valid during Hi-ROM mode.
6. The data “00h” is also acceptable.
16
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PRELIMINARY INFORMATION Rev. 00A
08/01/02
ISSI
75V16F64GS16
®
FLASH MEMORY COMMAND DEFINITIONS (Continued)
Notes:
Address bits A21 to A11 = X = “H” or “L” for all
address commands except or Program Address (PA),
Sector Address (SA) , and Bank Address (BA) , and
Sector Group Address (SPA) .
Bus operations are defined in "DEVICE BUS
OPERATIONS”.
RA = Address of the memory location to be read
PA = Address of the memory location to be
programmed
Addresses are latched on the falling edge of the write
pulse.
SA = Address of the sector to be erased. The
combination of A21, A20, A19, A18, A17, A16, A15,
A14, A13, and A12 will uniquely select any sector.
BA = Bank Address (A21, A20, A19)
RD = Data read from location RA during read
operation.
PD = Data to be programmed at location PA. Data is
latched on the rising edge of write pulse.
SPA = Sector group address to be protected.
Set sector group address and (A6, A3, A2, A1, A0) =
(0, 0, 0, 1, 0).
SD = Sector group protection verify data. Output 01h at
protected sector group addresses and output 00h at
unprotected sector group addresses.
HRA = Address of the Hi-ROM area : 000000h to
00007Fh
HRBA = Bank Address of the Hi-ROM area (A21 = A20
= A19 = VIL)
The system should generate the following address
patterns : 555h or 2AAh to addresses A10 to A0
Both Read/Reset commands are functionally
equivalent, resetting the device to the read mode.
Command combinations not described in “Flash
Memory Command Definitions” are illegal.
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PRELIMINARY INFORMATION Rev. 00A
08/01/02
17
ISSI
75V16F64GS16
®
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Tstg
TA
Parameter
Storage Temperature
Ambient Temperature with Power Applied
Min.
–55
–30
Max.
+125
+85
Unit
°C
°C
VIN
Voltage with Respect to Ground All Pins(1,2)
–0.3
VCCf + 0.3
V
(1,2)
VOUT
VCCf
Voltage with Respect to Ground All Pins
–0.3
VCCr + 0.3
V
(1)
–0.2
+3.6
V
(1,3)
-0.2
+3.6
V
-0.5
+13.0
V
–0.5
+10.5
V
VCCf Supply
VCCr
VCCr Supply
VIN
RESET
VACC
WP/ACC(1,4)
(1,3)
Notes:
1. Voltage is defined on the basis of GND = GND = 0 V.
2. Minimum DC voltage on input or I/O pins is -0.3 V. During voltage transitions, input or I/O pins may undershoot
GND to -1.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf + 0.3 V or VCCr + 0.3 V.
During voltage transitions, input or I/O pins may overshoot to VCCf + 1.0 V or VCCr + 1.0 V for periods of up to 5 ns.
3. Minimum DC input voltage on RESET pin is -0.5 V. During voltage transitions, RESET pin may undershoot GND
to -2.0 V for periods of up to 20 ns.
Voltage difference between input and supply voltage (VIN-VCCf or VCCr) does not exceed 9.0 V.
Maximum DC input voltage on RESET pin is +13.0 V that may overshoot to +14.0 V for periods of up to 20 ns.
4. Minimum DC input voltage on WP/ACC pin is -0.5 V. During voltage transitions, WP/ACC pin may undershoot
GND to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may
overshoot to +10.5 V for periods of up to 20 ns, when VCCf is applied.
5. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS
Rating
Symbol
TA
VCCf
VCCr
Parameter
Ambient Temperature
VCCf Supply Voltages
VCCr Supply Voltages
Min.
–30
–2.7
–2.7
Max.
+85
+3.1
+3.1
Unit
°C
V
V
Note:
Voltage is defined on the basis of GND = GND = 0 V.
18
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PRELIMINARY INFORMATION Rev. 00A
08/01/02
ISSI
75V16F64GS16
®
DC CHARACTERISTICS
Symbol
ILI
ILO
ILIT
ICC1f
Parameter
Input Leakage
Output Leakage
RESET Inputs
Leakage Current
FLASH Vcc (1)
Active Current (Read)
Test Conditions
VIN=GND to VCCf, VCCr
VOUT=GND to VCCf, VCCr
VCCf=VCCf max.,
RESET = 12.5V
CEf=VIL, OE=VIH
tCycle = 5Mhz
tCycle = 1Mhz
ICC2f
ICC3f
ICC4f
ICC5f
IACC
ICC1r
ISB1f
ISB2f
ISB3f
ISBr
ISB1r
ISB2r
FLASH Vcc Active
CEf=VIL,
Current(Program/Erase) OE=VIH
FLASH Vcc Active(5)
CEf=VIL,
Current
OE=VIH
(Read-While-Program)
FLASH Vcc Active(5)
CEf=VIL,
Current
OE=VIH
(Read-While-Erase)
FLASH Vcc Active
CEf=VIL,
Current
OE=VIH
(Erase-Suspend-Program)
WP/ACC Acceleration
VCCf = Vcc max,
Program Current
WP/ACC = VACC max
PSRAM Vcc Active
VCCr = Vccr max,
trc / twc = min
Current
CE1r=VIL, CE2r=VIH,
VIN=VIH or VIL,
trc / twc = 1 µs
IOUT=0 mA
FLASH Vcc
VCCf = Vccf max, CEf= VCCf + 0.3V,
Standby Current
RESET = VCCf + 0.3V,
WP/ACC = VCCf + 0.3V
FLASH Vcc
VCCf = Vccf max, RESET= GND + 0.3V,
Standby Current
WP/ACC = VCCf + 0.3V
(RESET)
FLASH Vcc(3)
VCCf = Vcc max., CEf, = GND + 0.3V,
Current
RESET = VCCf + 0.3V,
(Automatic Sleep Mode) WP/ACC = VCCf + 0.3V,
VIN = VCCf + 0.3V OR GND + 0.3V
PSRAM Vcc Standby
VCCr = Vccr max, CE1r = CE2R = VIN,
Current
VIN=VIH or VIL,
IOUT=0 mA
PSRAM Vcc Standby
VCCr = Vccr max, CE1r ≥ VCCr -0.2V,
Current
CE2r ≥ VCCr -0.2V,
VIN ≤ 0.2 V or VIN ≥ VCCr -0.2V
IOUT=0 mA
PSRAM Vcc Standby
VCCr = Vccr max, CE1r ≥ VCCr -0.2V,
Current(6)
CE2r ≥ VCCr -0.2V,
VIN Cycle time = tRC min, IOUT = 0 mA
(2)
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PRELIMINARY INFORMATION Rev. 00A
08/01/02
Min.
-1.0
-1.0
—
Typ.
—
—
—
Max.
+1.0
+1.0
35
Unit
µA
µA
µA
—
—
18
mA
—
—
—
—
4
35
mA
mA
—
—
53
mA
—
—
53
mA
—
—
40
mA
—
—
20
mA
—
15
20
mA
—
2.5
3.0
mA
—
1
5
µA
—
1
5
µA
—
1
5
µA
—
0.5
1
mA
—
—
70
µA
—
—
5
mA
19
ISSI
75V16F64GS16
®
DC CHARACTERISTICS (Continued)
Symbol Parameter
IPDr
PSRAM VCC Power
Down Current
VIL
VIH
VIH
VID
VACC
VOL
VOH
VOL
VOH
VLKO
Test Conditions
VCCr = VCCr max.,
VIN ≥ VCCf - 0.2 V OR VIN ≤ 0.2 V
CE2r ≤ 0.2 V, IOUT = 0 mA
Input Low Level
Input High Level (Flash)
Input High Level (PSRAM)
Voltage for Autoselect
and Sector Protection
(RESET)(4)
Voltage for WP/ACC
Sector Protection/Unprotection
and Program Acceleration (4)
Output Low Level
VCCr = VCCr min., VCCS=VCCS min.
(PSRAM)
IOL = 1.0 mA
Output High Level
VCCr = VCCr min., VCCS=VCCS min.
(PSRAM)
IOH = -0.5 mA
Output Low Level
VCCf = VCCf min., VCCS=VCCS min.
(Flash)
IOL = 4.0 mA
Output High Level
VCCf = VCCf min., VCCS=VCCS min.
(Flash)
IOH = -0.1 mA
Flash Low Vccf
Lock-Out Voltage
Min.
—
Max.
10
Unit
µA
-0.3
2.0
2.2
11.5
0.5
VCCf + 0.3
VCCr + 0.3
12.5
V
V
V
V
8.5
9.5
V
—
0.4
V
2.2
—
V
—
0.45
V
VCCf - 0.4
—
V
2.3
2.5
V
Notes:
1. ICC current listed includes both the DC operating current and the frequency dependent component.
2. ICC active while Embedded Algorithm (program or erase) is in progress.
3. Automatic sleep mode enables the low power mode when address remains stable for 150 ns.
4. Applicable for only VCCf applying.
5. Embedded Algorithm (program or erase) is in progress. (@5 MHz)
6. ISB2 r depends on VIN cycle time. Please refer to “APPENDIX A”.
.
20
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PRELIMINARY INFORMATION Rev. 00A
08/01/02
ISSI
75V16F64GS16
®
AC CHARACTERISTICS - CE TIMING
Parameter
Symbol
Condition
tCCR
—
0
—
ns
CEf Hold Time
tCHOLD
—
3
—
ns
CE1r High to WE Invalid time for
Standby Entry
tCHWX
—
20
—
ns
CEf Recover Time
Min Max
Unit
TIMING DIAGRAM FOR ALTERNATING PSRAM TO FLASH
CEf
tCCR
tCCR
CE1r
WE
tCHWX
tCCR
tCHOLD
tCCR
CE2r
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PRELIMINARY INFORMATION Rev. 00A
08/01/02
21
ISSI
75V16F64GS16
®
FLASH READ ONLY OPERATIONS CHARACTERISTICS
JEDEC
Symbol
Standard
Symbol
Read Cycle Time
tAVAV
tRC
Address to Output Delay
tAVQV
tACC
Chip Enable to Output Delay
tELQV
tCE
Output Enable to Output Delay
tGLQV
Chip Enable to Output High-Z
Parameter
Condition
Min Max
Unit
70
—
ns
CEf = VIL, OE = VIL
—
70
ns
OE = VIL
—
70
ns
tOE
—
30
ns
tEHQZ
tDF
—
25
ns
Output Enable to Output High-Z
tGHQZ
tDF
—
25
ns
Output Hold Time From Addresses,
CEf or OE, Whichever Occures First
tAXQX
tOH
0
—
ns
—
tREADY
—
20
µs
RESET Pin Low to Read Mode
Test Conditions:
Output Load : 1 TTL gate and 30 pF
Input rise and fall times : 5 ns
Input pulse levels : 0.0 V or VCCf
Timing measurement reference level
Input : VCCf/2
Output : VCCf/2
22
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PRELIMINARY INFORMATION Rev. 00A
08/01/02
ISSI
75V16F64GS16
®
FLASH READ CYCLE
tRC
Address
Address Stable
tACC
CEf
tDF
tOE
OE
tOEH
WE
DQ
tCE
High-Z
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PRELIMINARY INFORMATION Rev. 00A
08/01/02
High-Z
Output valid
23
ISSI
75V16F64GS16
®
FLASH HARDWARE RESET / READ OPERATION TIMING DIAGRAM
tRC
Address
Address Stable
tACC
CEf
tRH
tRP
tRH
tCE
RESET
tOH
DQ
24
High-Z
Output valid
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PRELIMINARY INFORMATION Rev. 00A
08/01/02
ISSI
75V16F64GS16
®
WRITE/ERASE/PROGRAM OPERATIONS
JEDEC
Symbol
Standard
Symbol
Min
Typ
Max
Unit
Write Cycle Time
tAVAV
tWC
70
tAVWL
tAS
0
—
tASO
12
—
—
—
ns
Address Setup Time
—
—
—
tWLAX
tAH
45
tAHT
0
—
—
ns
—
—
—
Data Setup Time
tDVWH
tDS
30
tWHDX
tDH
0
—
—
tOEH
0
tOEH
10
—
—
—
—
ns
Data Hold Time
—
—
—
—
—
—
tCEPH
20
20
Read Recover Time Before Write (OE to CE)
tGHWL
tGHWL
0
Read Recover Time Before Write (OE to WE)
tGHEL
tGHEL
0
WE Setup Time (CEf to WE)
tELWL
tWS
0
CE Setup Time (WE to CE)
tWLEL
tCS
0
WE Hold Time (CE to WE)
tWHEH
tWH
0
CE Hold Time (WE to CE)
tEHWH
tCH
0
Write Pulse Width
tWLWH
tWPH
35
CEf Pulse Width
tELEH
tCP
35
Write Pulse Width High
tWHWL
tWPH
25
CE Pulse Width High
tEHEL
tCPH
25
tWHWH1
tWHWH1
tWHWH2
tWHWH2
—
—
—
—
—
—
—
tVCS
50
tVIDR
500
tVACCR
500
tVLHT
4
tWPP
100
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
tOEPH
—
—
—
—
—
—
—
—
—
—
—
—
Parameter
Address Setup Time to OE Low
During Toggle Bit Polling
Address Hold Time
Address Hold Time from CE or
OE High During Toggle Bit Polling
Output Enable Hold Time Read
Output Enable Hold Time
Toggle and Data Polling
CE High During Toggle Bit Polling
OE High During Toggle Bit Polling
Programming Operation
Sector Erase Operation
(1)
VCC Setup Time
Rise Time to VID (2)
Rise Time to VID
(3)
Voltage Transition Time (2)
Write Pulse width (2)
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PRELIMINARY INFORMATION Rev. 00A
08/01/02
10
0.2
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
s
µs
ns
ns
µs
µs
25
ISSI
75V16F64GS16
®
WRITE/ERASE/PROGRAM OPERATIONS (Continued)
Parameter
OE Setup Time to WE Active
(2)
CE Setup Time to WE Active (2)
Recover Time from RY/BY
RESET Pulse Width
RESET High Level Period Before Read
Program/Erase Valid to RY/BY Delay
Delay Time from Embedded Output Enable
Erase Time-Out Time
Erase Suspend Transition Time
JEDEC
Symbol
Standard
Symbol
Min
Typ
Max
Unit
—
—
—
—
—
—
—
—
—
tOESP
4
4
tRB
0
tRP
500
tRH
200
—
—
—
—
—
µs
tCSP
tBUSY
90
ns
tEOE
—
—
70
ns
tTOW
50
—
µs
tSPD
—
—
—
—
—
—
—
—
—
—
20
µs
µs
ns
ns
ns
Notes:
1. Does not include preprogramming time.
2. For Sector Group Protection operation.
3. For Accelerated Program operation.
26
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PRELIMINARY INFORMATION Rev. 00A
08/01/02
ISSI
75V16F64GS16
®
FLASH WRITE CYCLE
(WE CONTROL)
Data Polling
3rd Bus Cycle
tAS
tWC
PA
PA
555h
Address
tRC
tAH
CEf
tCH
tCS
tCE
OE
tGHWL
tWP
tWPH
tDS
tDH
tWHWH1
tOE
WE
DQ
A0h
tDF
PD
DQ7
Dout
tOH
Dout
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles out of four bus cycle sequence.
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PRELIMINARY INFORMATION Rev. 00A
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27
ISSI
75V16F64GS16
®
FLASH WRITE CYCLE
(CEf CONTROL)
Data Polling
3rd Bus Cycle
555h
Address
tWC
WE
tWS
OE
tGHEL
PA
PA
tAS
tAH
tWH
tCP
tCPH
tDS
tDH
tWHWH1
CEf
DQ
PD
AOh
DQ7
Dout
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles out of four bus cycle sequence.
28
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PRELIMINARY INFORMATION Rev. 00A
08/01/02
ISSI
75V16F64GS16
®
FLASH AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS
555h
Address
2AAh
tAS
tWC
555h
555h
2AAh
SA(1)
tAH
CEf
tCH
tSC
OE
tWP
tWPH
tGHWL
WE
tDS
tDH
DQ
AAh
30h for Sector Erase
55h
80h
AAh
55h
10h/
30h
tVCS
Vccf
Notes:
1. SA is the sector address for Sector Erase. Address = 555h for Chip Erase.
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PRELIMINARY INFORMATION Rev. 00A
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29
ISSI
75V16F64GS16
®
FLASH AC WAVEFORMS
FOR DATA POLLING DURING EMBEDDED ALGORITHM OPERATIONS
CEf
tCH
OE
tDF
tOE
tOEH
WE
tCE
(1)
DQ
DQ7
Data In
DQ7 =
Valid Data
High - Z
tWHWH1 or 2
DQ0/DQ6
Data In
DQ0 to DQ6 = Output Flag
tBUSY
DQ0 to DQ6
Valid Data
High - Z
tEOE
RY/BY
Notes:
1. DQ7 = Valid Data (the device has completed the Embedded operation.)
30
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PRELIMINARY INFORMATION Rev. 00A
08/01/02
ISSI
75V16F64GS16
®
FLASH AC WAVEFORMS
FOR TOGGLE BIT DURING EMBEDDED ALGORITHM OPERATIONS
ADDRESS
tAHT tASO
CEf
tAHT tAS
tCEPH
WE
tOEH
tOEH
tOEPH
OE
tDH
DQ6/DQ2
Data
(1)
tOE
tCE
Toggle
Data
Toggle
Data
Toggle
Data
Toggle
Data
Output
Valid
tBUSY
RY/BY
Notes:
1. DQ6 stops toggling (the device has completed the Embedded operation).
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PRELIMINARY INFORMATION Rev. 00A
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31
ISSI
75V16F64GS16
®
FLASH BACK-to-BACK READ/WRITE TIMING DIAGRAM
ADDRESS
Read
tRC
Command
tWC
Read
tRC
Command
tWC
Read
tRC
Read
tRC
BA1
BA2
(555h)
BA1
BA2
(PA)
BA1
BA2
(PA)
tAS
tACC
tAH
tAS
tCE
tAHT
CEf
tCEPH
tOE
OE
tGHWL
tWP
tDF
tOEH
WE
tDS
DQ
Valid
Output
Valid
Input
(A0h)
tDH
tDF
Valid
Output
Valid
Input
Valid
Output
Status
(PD)
Note:
1. This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2. BA1: Address of Bank 1;
BA2: Address of Bank 2.
32
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PRELIMINARY INFORMATION Rev. 00A
08/01/02
ISSI
75V16F64GS16
®
BY TIMING DIAGRAM DURING WRITE/ERASE OPERATIONS
FLASH RY/BY
CEf
The rising edge of the last write pulse
WE
Entire programming
or erase operations
RY/BY
tBUSY
BY TIMING DIAGRAM
FLASH RESET, RY/BY
WE
RESET
tRB
tRP
RY/BY
tREADY
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PRELIMINARY INFORMATION Rev. 00A
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33
ISSI
75V16F64GS16
®
FLASH EXTENDED SECTOR GROUP PROTECTION
tVCS
Vccf
tVLHT
RESET
tWC
tWC
tVIDR
SPAX
SPAX
Address
SPAY
A6, A3
A2, A0
A1
CEf
OE
tWP
TIME-OUT
WE
Data
60h
60h
01h
40h
60h
tOE
Notes:
1. SPAX : Sector Group Address to be protected, SPAY : Next Group Sector Address to be protected,
TIME-OUT: Time-Out window = 250 µs (Min)
34
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PRELIMINARY INFORMATION Rev. 00A
08/01/02
ISSI
75V16F64GS16
®
PSRAM READ OPERATIONS
Parameter
Symbol
Value
Min.
Max.
Unit
tRC
90
—
ns
tCE
80
ns
45
ns
tAA
—
—
—
80
ns
tOH
5
ns
tCLZ
5
tOLZ
0
—
—
—
CE1r High to Output High-Z
tCHZ
ns
tOHZ
—
—
30
(2)
25
ns
tASC
-5
ns
tASO
45
tASO(ABS)
10
—
—
—
Read Cycle Time
(1,3)
Chip Enable Access Time
Output Enable Access Time
(1)
tOE
Chip Enable Access Time(1,4)
(1)
Output Data Hold Time
(2)
CE1r Low to Output Low-Z
OE Low to Output Low-Z(2)
(2)
OE High to Output High-Z
Address Setup Time to CE1r Low(5)
(3,6)
Address Setup Time to OE
Address Setup Time to OE
(7)
Address Invalid Time(4)
ns
ns
ns
ns
tAX
—
5
ns
(4)
tCLAH
90
ns
(4,8)
tOLAH
45
CE1r High to Address Hold Time
tCHAH
-5
OE High to Address Hold Time
CE1r Low to Address Hold Time
tOHAH
-5
—
—
—
—
(4,6,8,9)
tCLOL
45
1000
ns
(8)
tOLCH
45
ns
CE1r High Pulse Width
tCP
20
—
—
OE High Pulse Width(6,8,9)
tOP
45
1000
ns
tOP(ABS)
20
—
ns
OE Low to Address Hold Time
CE1r Low to OE Low DelayTime
OE Low to CE1r High DelayTime
OE High Pulse Width
(7)
ns
ns
ns
ns
Notes:
1. The output load is 30 pF.
2. The output load is 5 pF.
3. The tCE is applicable if OE is brought to Low before CE1r goes Low and is also applicable if actual value of both
or either tASO or tCLOL is shorter than specified value.
4. Applicable only to A0 and A1 when both CE1r and OE are kept at Low for the address access.
5. Applicable if OE is brought to Low before CE1r goes Low.
6. The tASO, tCLOL (Min) and top (Min) are reference values when the access time is determined by tOE.
If actual value of each parameter is shorter than specified minimum value, tOE becomes longer by the amount
of subtracting actual value from specified minimum value.
For example, if actual tASO, tASO (actual) , is shorter than specified minimum value, tASO (Min) , during OE control
access (i.e., CE1r stays Low) , the tOE becomes tOE (Max) + tASO (Min) - tASO (actual) .
7. The tASO[ABS] and tOP[ABS] are the absolute minimum values during OE control access.
8. If actual value of either tCLOL or tOP is shorter than specified minimum value, both tOLAH and tOLCH become tRC (Min)
- tCLOL (actual) or tRC (Min) - tOP (actual) .
9. Maximum value is applicable if CE1r is kept at Low.
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PRELIMINARY INFORMATION Rev. 00A
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35
ISSI
75V16F64GS16
®
PSRAM WRTE OPERATIONS
Parameter
Symbol
Write Cycle Time(1)
Value
Min.
Max.
Unit
tWC
90
—
ns
tAS
0
—
ns
Address Setup Timev
tAH
45
—
ns
CE1r Write Setup Time
tCS
0
1000
ns
CE1r Write Hold Time
tCH
0
1000
ns
WE Setup Time
tWS
0
—
ns
WE Hold Time
tWH
0
—
ns
LB adnd UB Setup Time
tBS
0
—
ns
LB adnd UB Hold Time
tBH
-5
—
ns
OE Setup Time(3)
tOES
0
1000
ns
OE Hold Time
tOEH
45
1000
ns
OE Hold Time
tOEH(ABS)
20
—
ns
OE High to CE1r Low Setup Time(6)
tOHCL
-3
—
ns
OE High to Address Hold Time
tOHAH
-5
—
ns
CE1r Write Pulse Width
tCW
60
—
ns
WE Write Pulse Width
tWP
60
—
ns
CE1r Write Recovery Time(1,9)
tWRC
15
—
ns
WE Write Recovery Time(1,3,9)
tWR
15
1000
ns
Data Setup Time
tDS
20
—
ns
Data Hold Time
tDH
0
—
ns
CE1r High Pulse Width(9)
tCD
20
—
ns
Address Setup Time
(2)
(3,4)
(5)
(1,8)
(1,8)
(7)
Notes:
1. Minimum value must be equal or greater than the sum of actual tCW (or tWP) and tWRC (or tWR) .
2. New write address is valid from either CE1r or WE that is brought to High.
3. Maximum value is applicable if CE1r is kept at Low and both WE and OE are kept at High.
4. The tOEH is specified from end of tWC (Min) , and is a reference value when access time is determined by tOE.
If actual value is shorter than specified minimum value, tOE becomes longer by the amount of subtracting actual
value from specified minimum value.
5. The tOEH[ABS] is the absolute minimum value if write cycle is terminated by WE and CE1r stay Low.
6. tOHCL (Min) must be satisfied if read operation is not performed prior to write operation.
In case OE is disabled after tOHCL (Min) , WE Low must be asserted after tRC (Min) from CE1r Low.
In other words, read operation is initiated if tOHCL (Min) is not satisfied.
7. Applicable if CE1r stays Low after read operation.
8. tCW and tWP are applicable if write operation is initiated by CE1r and WE, respectively.
9. tWRC and tWR are applicable if write operation is terminated by CE1r and WE, respectively.
The tWR (Min) can be ignored if CE1r is brought to High together or after WE is brought to High.
In such a case, the tCP (Min) must be satisfied.
36
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PRELIMINARY INFORMATION Rev. 00A
08/01/02
ISSI
75V16F64GS16
®
PSRAM POWER DOWN PARAMETER
Parameter
Symbol
Value
Min.
Max.
CE2r Low Setup Time for Power down Entry
tCSP
10
CE2r Low Setup Time after Power down Entry
tC2LP
100
CE1r High Hold Time Following CE2r High after Power down Exit
tCHH
350
CE1r High Setup Time Following CE2r High after Power down Exit
tCHS
10
—
—
—
—
Unit
ns
ns
µs
ns
PSRAM OTHER TIMING PARAMETERS
Parameter
Symbol
Value
Min.
Max.
CE1r High to OE Invalid for Standby Entry
tCHOX
20
CE1r High to WE Invalid for Standby Entry(1)
CE2r Low Hold Time after Power-up
tCHWX
20
(2)
tC2LH
50
(3)
tC2HL
50
tCHH
350
—
—
—
—
—
tT
1
25
CE2r High Hold Time after Power-up
CE1r High Hold Time Following CE2r High after Power-up(2)
(4)
Input Transition Time
Unit
ns
ns
µs
ns
µs
µs
Notes:
1. Unintended data may be written into any address location if tCHWX is not satisfied.
2. Must satisfy tCHH (Min) after tC2LH (Min) .
3. Requires Power Down mode entry and exit after tC2HL.
4. Input Transition Time (tT) at AC testing is 5 ns as shown below. If actual tT is longer than 5 ns,
it may violate some timing parameters of AC specification.
PSRAM AC TEST CONDITIONS
Parameter
Input HIgh Level
Input Low Level
Input Timing Measurement Level
Input Transition Time
Symbol
Conditon
Value
Unit
VIH
VCCr = 2.7V to 3.1V
2.3
V
VIL
VREF
tT
VCCr = 2.7V to 3.1V
VCCr = 2.7V to 3.1V
Between VIL and VIH
0.4
1.3
5
V
V
ns
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PRELIMINARY INFORMATION Rev. 00A
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37
ISSI
75V16F64GS16
®
PSRAM READ TIMING
(OE Control Access)
tRC
tRC
Address
Address Valid
Address Valid
tASO
tCE
tOHAH
tOHAH
CE1r
tCLOL
tOLCH
tOP
tOE
tOE
OE
tOHZ
tASO
tOH
DQ
(Input)
tOHZ
tOH
tOLZ
tOLZ
Note: CE2r and WE must be High during read cycle.
Valid Data Input
Valid Data Input
PSRAM READ TIMING
(CE1r Control Access)
tRC
tRC
Address
Address Valid
tASC
Address Valid
tASC
tCE
tCE
tcHAH
tOHAH
CE1r
tCP
tCHZ
tCHZ
OE
tOH
tCLZ
tCLZ
tOH
DQ
(Input)
Valid Data Input
Valid Data Input
Note: CE2r and WE must be High during read cycle.
38
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PRELIMINARY INFORMATION Rev. 00A
08/01/02
ISSI
75V16F64GS16
®
PSRAM READ TIMING
(Address Access after OE Control Access)
tRC
tRC
Address
(A19-A2)
Address Valid
Address
(A1, A0)
Address Valid (No change)
Address Valid
tASO
Address Valid
tAA
tOLAH
tOHAH
tAX
CE1r
tOE
tOHZ
OE
tOH
tOLZ
tOH
DQ
(Input)
Valid Data Input
Valid Data Input
Note: CE2r and WE must be High during read cycle.
PSRAM READ TIMING
(Address Access after CE1r Control Access)
tRC
tRC
Address
(A19-A2)
Address Valid
Address
(A1, A0)
Address Valid (No change)
Address Valid
tASC
Address Valid
tAA
tCLAH
tAX
tCHAH
CE1r
tCE
tCHZ
OE
tCLZ
tOH
tOH
DQ
(Input)
Valid Data Input
Valid Data Input
Note: CE2r and WE must be High during read cycle.
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PRELIMINARY INFORMATION Rev. 00A
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39
ISSI
75V16F64GS16
®
PSRAM WRITE TIMING
(CE1r Control)
tWC
Address
Address Valid
tAH
tAS
CE1r
tAS
tWRC
tCW
tWS
tWH
tWS
tBH
tBS
WE
tBS
UB, LB
tOHCL
OE
tDS
tDH
DQ
(Input)
Note: CE2r must be High during write cycle.
Valid Data Input
PSRAM WRITE TIMING
(WE Control, Single Write Operation)
tWC
Address
Address Valid
tAH
tOHAH
tAS
tAS
tCH
CE1r
tCP
tOHCL
tCS
tWP
tWR
WE
tBS
tBH
UB, LB
tOES
OE
tOHz
tDS
tDH
DQ
(Input)
Valid Data Input
Note: CE2r must be High during write cycle.
40
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PRELIMINARY INFORMATION Rev. 00A
08/01/02
ISSI
75V16F64GS16
®
PSRAM WRITE TIMING
(WE Control, Continuous Write Operation)
tWC
Address
Address Valid
tAH
tOHAH
tAS
tAS
CE1r
tWP
tCS
tOHCL
tWR
WE
tBS
tBS
tBH
UB, LB
tOES
OE
tDS
tOHz
tDH
DQ
(Input)
Valid Data Input
Note: CE2r must be High during write cycle.
PSRAM READ / WRITE TIMING
(CE1r Control)
tWC
Address
Read Address
Write Address
tCHAH
tAS
tASC
tAH
CE1r
tCP
tWH
tWS
tCW
tWH
tWRC
tWS
WE
tBS
tBH
UB, LB
tCLOL
tOHCL
OE
tCHZ
tOH
tDS
tDH
tOLz
tOLz
DQ
(Input)
Read Data Output
Valid Data Input
Note: Write address is valid from either CE1r or WE of last falling edge.
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41
ISSI
75V16F64GS16
®
PSRAM READ / WRITE TIMING
(CE1r Control)
tRC
Address
Write Address
Read Address
CE1r
tAS
tASC
tWRC
tCHAH
tWRC (Min)
tWH
tCP
tWH
tWS
tWS
WE
tBH
tCE
tBS
UB, LB
tOEH
tOHCL
OE
tCHZ
tOH
tCLz
tOH
DQ
Read Data Output
Write Data Input
Note: CE2r must be High during write cycle.
PSRAM READ / WRITE TIMING
(READ = OE Control, WRITE = WE Control)
tWC
Address
Read Address
Write Address
tAS
tASO
tAH
tOHAH
CE1r
Low
tWR
tWP
WE
tBH
tBS
UB, LB
tOEH
tOES
OE
tOHZ
tOH
tDS
tDH
tOLz
DQ
Read Data Output
Write Data Input
Note: CE1r can be tied to Low for WE and OE controlled operation. When CE1r is tied to Low, output is
exclusively controlled by OE.
42
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PRELIMINARY INFORMATION Rev. 00A
08/01/02
ISSI
75V16F64GS16
®
PSRAM READ / WRITE TIMING
(READ = OE Control, WRITE = WE Control)
tRC
Address
Read Address
Write Address
tASO
CE1r
tOHAH
tAS
Low
tWR
WE
tBH
tBS
UB, LB
tOEH
tOE
tOES
OE
tOHZ
tDH
tOH
tOLZ
DQ
Write Data Input
Read Data Output
Note: CE1r can be tied to Low for WE and OE controlled operation. When CE1r is tied to Low, output
is exclusively controlled OE.
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PRELIMINARY INFORMATION Rev. 00A
08/01/02
43
ISSI
75V16F64GS16
®
PSRAM POWER DOWN TIMING
CE1r
tCHS
CE2r
tCHH
tC2LP
tCSP
High - Z
DQ
Power Down Entry
Power Down Mode
Power Down Exit
PSRAM STANDBY ENTRY TIMING AFTER READ WRITE
CE1r
tCHOX
tCHWX
OE
WE
Active (Read)
Standby
Active (Write)
Standby
Note: Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes tRC (min) period from either last address transition of A0 and A1, or CE1r Low to High transition.
44
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PRELIMINARY INFORMATION Rev. 00A
08/01/02
ISSI
75V16F64GS16
®
PSRAM POWER UP TIMING 1
CE1r
tCHS
tCHH
tC2LH
CE2r
Vccr Min
Vccr
0V
Note: It is recommended CE2r to be kept at Low during Vccr power-up. The tC2LH specifies after Vccr reaches
specified minimum level.
PSRAM POWER UP TIMING 2
CE1r
tCHS
tCSP
tC2HL
tC2LP
tCHH
CE2r
tC2HL
Vccr Min
Vccr
0V
Note: The tC2LH specifies from CE2r Low to High transition after Vccr reaches specified minimum level. CE1r must
be brought to High prior to or together with CE2r Low to High transition.
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PRELIMINARY INFORMATION Rev. 00A
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45
ISSI
75V16F64GS16
®
FLASH ERASE AND PROGRAMMING PERFORMANCE
Min.
Max.
Typ.(1)
Unit
Sector Erase Time
—
0.2
1.0
s
Excludes programming time
prior to erasure
Word Programming Time
—
6.0
60
µs
Excludes system-level
overhead
Chip Programming Time
—
—
200
s
Excludes system-level
overhead
100,00
—
—
cycle
Parameter
Erase/Program Cycle
Remarks
Note:
1. Test conditions TA = +25 °C, VCC = 2.9V, Data = Checker
46
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PRELIMINARY INFORMATION Rev. 00A
08/01/02
ISSI
75V16F64GS16
®
PSRAM DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
Parameter
Conditions
Min.
Max.
Unit
VDR
Vccr Data Retention Supply Voltage
CE1r = CE2r ≥ VCCr -0.2V OR,
CE1r = CE2r = VIH
2.1
3.1
V
IDR
Vccr Data Retention Supply Current
2.3 V ≤ VCCr ≤ 2.7 V,≥
VIN = VIH (1) or VIL
CE1r = CE2r = VIH (1),
IOUT = 0 MA
—
1
mA
IDR1
Vccr Data Retention Supply Current
2.3 V ≤VCCr ≤ 2.7 V,≥
VIN ≤ 0.2 V or VIN ≥ VCCr -2.0 V,
CE1r = CE2r ≥ VCCr -0.2 V
IOUT = 0 MA
—
70
µA
tDRS
Data Retention SetupTime
2.7 V ≤ VCCr ≤ 3.1 V,≥
At Data Retention Entry
0
—
ns
tDRR
Data Retention RecoveryTime
2.7 V ≤ VCCr ≤ 3.1 V,≥
After Data Retention
90
—
ns
∆V/∆t
VCCR Voltage Transition Time
—
0.5
—
V/µs
Note:
1. 2.0 V ≤ VIN ≤ VCCr + 0.3
PSRAM DATA RETENTION TIMING
tDRS
3.1V
2.7V
tDRR
∆V/∆t
Vccr
∆V/∆t
2.3V
CE2r
CE1r
CE1r = CE2r >Vccr - 0.2V or
VIH(1) Min
4.0V
GND
Data Retention Mode
Data bus must be in High-Z at data retention entry
Note:
1. 2.0 V ≤ VIH ≤ VCCr + 0.3 V
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PRELIMINARY INFORMATION Rev. 00A
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47
ISSI
75V16F64GS16
®
PSRAM DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
Parameter
Conditions
CIN
Input Capacitance
VIN
COUT
Output Capacitance
CIN2
Control Pin Capacitance
CIN3
WP/ACC Pin Capacitance
=0V
VOUT = 0 V
VIN = 0 V
VIN = 0 V
Min.
Max.
Unit
11
14
pF
12
16
pF
14
16
pF
21.5
26
pF
Notes:
1. Test conditions TA = +25 °C, f = 1.0 MHz
HANDLING OF PACKAGE:
Please handle this package carefully since the sides of package created with acute angles.
CAUTION:
1) The high voltage (VID) cannot be applied to address pins and control pins except RESET. Exception is when
autoselect and sector group protection function are used. Then the high voltage (VID) can be applied to RESET.
2) Without the high voltage (VID) , sector group protection can be achieved by using “Extended Sector Group
Protection” command.
ISB2r VS VIN Cycle Time
ISB2r vs. VIN Cycle Time (VCCr = 3.0 V)
2.5
ISB2r (mA)
2.0
: RT = 25 °C
: LT = -30 °C
: HT = 85 °C
1.5
1.0
0.5
0.0
0
200
400
600
800
1000
VIN Cycle Time (ns)
48
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PRELIMINARY INFORMATION Rev. 00A
08/01/02
ISSI
75V16F64GS16
®
BALL GRID ARRAY – 65-Ball FBGA
PACKAGE CODE: D - 9.0 mm x 9.0 mm Body, 0.8 mm Ball Pitch
ø 0.45 + 0.10/−0.05 (65X)
K J H G F E D C B A
A B C D E F G H J K
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
2
1
e
D
D1
e
E1
E
A1
A
SEATING PLANE
Symbol
Min.
Typ.
Max.
Units
A
1.09
1.19
1.34
mm
A1
0.29
0.39
0.49
mm
D
8.90
9.00
9.10
mm
D1
—
7.20
—
mm
E
8.90
9.00
9.10
mm
E1
—
7.20
—
mm
e
—
0.80
—
mm
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PRELIMINARY INFORMATION Rev. 00A
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49
ISSI
75V16F64GS16
®
ORDERING INFORMATION
Industrial Range: -30ºC to +85ºC
Order Part No.
IS75V16F64GS16-7080DI
50
SRAM
Data
Boot
Bus Section
16
PC
Flash Bank
Organization
PC
Flash
PSRAM
Speed(ns) Speed(ns)
70
80
Package
65-ball FBGA
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08/01/02