TM SPANSION MCP Data Sheet September 2003 TM This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a SPANSION revisions will occur when appropriate, and changes will be noted in a revision summary. TM product. Future routine Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about SPANSION solutions. TM memory FUJITSU SEMICONDUCTOR DATA SHEET DS05-50304-3E Stacked MCP (Multi-Chip Package) FLASH MEMORY & FCRAM CMOS 64 M ( × 16) FLASH MEMORY & 16 M ( × 16) Mobile FCRAMTM MB84VD23381FJ-80 ■ FEATURES • Power Supply Voltage of 2.7 V to 3.1 V • High Performance 70 ns maximum access time (Flash) 80 ns maximum access time (FCRAM) • Operating Temperature −30 °C to +85 °C • Package 65-ball FBGA (Continued) ■ PRODUCT LINEUP Flash Memory FCRAM VCCf* = 2.7 V to 3.1 V VCCr* = 2.7 V to 3.1 V Max Address Access Time (ns) 70 80 Max CE Access Time (ns) 70 80 Max OE Access Time (ns) 30 40 Power Supply Voltage ( V ) *: Both VCCf and VCCr must be the same level when either part is being accessed. ■ PACKAGE 65-ball plastic FBGA (BGA-65P-M01) MB84VD23381FJ-80 (Continued) 1. FLASH MEMORY • 0.17 µm Process Technology • Simultaneous Read/Write Operations (Dual Bank) • FlexBankTM*1 Bank A : 8 Mbit (8 KB × 8 and 64 KB × 15) Bank B : 24 Mbit (64 KB × 48) Bank C : 24 Mbit (64 KB × 48) Bank D : 8 Mbit (8 KB × 8 and 64 KB × 15) Two virtual Banks are chosen from the combination of four physical banks Host system can program or erase in one bank, and then read immediately and simultaneously from the other bank with zero latency between read and write operations. Read-while-erase Read-while-program • Single 3.0 V Read, Program, and Erase Minimized system level power requirements • Minimum 100,000 Program/Erase Cycles • Sector Erase Architecture Sixteen 4 Kword and one hundred twenty-six 32 Kword sectors in word. Any combination of sectors can be concurrently erased. It also supports full chip erase. • HiddenROM Region 256 byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) • WP/ACC Input Pin At VIL, allows protection of “outermost” 2 × 8 Kbytes on both ends of boot sectors, regardless of sector protection/ unprotection status At VIH, allows removal of boot sector protection At VACC, increases program performance • Embedded EraseTM*2 Algorithms Automatically preprograms and erases the chip or any sector • Embedded ProgramTM*2 Algorithms Automatically writes and verifies data at specified address • Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion • Ready/Busy Output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic Sleep Mode When addresses remain stable, the device automatically switches itself to low power mode. • Low VCCf Write Inhibit ≤ 2.5 V • Program Suspend/Resume Suspends the program operation to allow a read in another byte • Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device • Please Refer to “MBM29DL64DF” Datasheet in Detailed Function (Continued) 2 MB84VD23381FJ-80 (Continued) 2. FCRAMTM*3 • Power Dissipation Operating : 20 mA Max Standby : 70 µA Max Power Down : 10 µA Max • Power Down Control by CE2r • Byte Write Control : LB (DQ7 to DQ0) , UB (DQ15 to DQ8) • 4 words Address Access Capability. *1: FlexBankTM is a trademark of Fujitsu Limited, Japan. *2: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. *3: FCRAMTM is a trademark of Fujitsu Limited, Japan. 3 MB84VD23381FJ-80 ■ PIN ASSIGNMENT FBGA (TOP VIEW) Marking Side A10 K10 N.C. N.C. A9 C9 D9 E9 F9 G9 H9 K9 N.C. A15 A21 N.C. A16 Vccf Vss N.C. B8 C8 D8 E8 F8 G8 H8 J8 A11 A12 A13 A14 N.C. DQ15 DQ7 DQ14 B7 C7 D7 E7 F7 G7 H7 J7 A8 A19 A9 A10 DQ6 DQ13 DQ12 DQ5 B6 C6 D6 G6 H6 J6 WE CE2r A20 DQ4 Vccr N.C. B5 C5 D5 G5 H5 J5 WP/ACC RESET RY/BY DQ3 Vccf DQ11 B4 C4 D4 E4 F4 G4 H4 J4 LB UB A18 A17 DQ1 DQ9 DQ10 DQ2 B3 C3 D3 E3 F3 G3 H3 J3 A7 A6 A5 A4 VSS OE DQ0 DQ8 A2 C2 D2 E2 F2 G2 H2 K2 N.C. A3 A2 A1 A0 CEf CE1r N.C. A1 B1 K1 N.C. N.C. N.C. (BGA-65P-M01) 4 MB84VD23381FJ-80 ■ PIN DESCRIPTION Pin Name Function Input/Output A19 to A0 Address Inputs (Common) I A21, A20 Address Inputs (Flash) I DQ15 to DQ0 CEf Data Inputs/Outputs (Common) I/O Chip Enable (Flash) I CE1r Chip Enable (FCRAM) I CE2r Chip Enable (FCRAM) I OE Output Enable (Common) I WE Write Enable (Common) I Ready/Busy Outputs (Flash) Open Drain Output O UB Upper Byte Control (FCRAM) I LB Lower Byte Control (FCRAM) I Hardware Reset Pin/Sector Protection Unlock (Flash) I Write Protect/Acceleration (Flash) I RY/BY RESET WP/ACC N.C. No Internal Connection VSS Device Ground (Common) Power VCCf Device Power Supply (Flash) Power VCCr Device Power Supply (FCRAM) Power ■ BLOCK DIAGRAM VCCf VSS A21 to A0 RY/BY A21 to A0 WP/ACC 64 M bit Flash Memory RESET CEf DQ15 to DQ0 DQ15 to DQ0 VCCr VSS A19 to A0 LB UB WE OE CE1r CE2r 16 M bit FCRAM DQ15 to DQ0 5 MB84VD23381FJ-80 ■ DEVICE BUS OPERATIONS User Bus Operations CEf CE1r CE2r OE WE Operation *1, *2 Full Standby Output Disable *3 Read from Flash *4 Write to Flash 5 Read from FCRAM * Write to FCRAM LB UB DQ7 to DQ0 DQ15 to DQ8 RESET WP/ACC*7 H H H X X X X High-Z High-Z H L X H H X X High-Z High-Z L H X H H X X High-Z High-Z L H X L H X X DOUT L H X H L X X H L H L H X H L H H L H X H X DOUT H X DIN DIN H X X DOUT DOUT H X L L DIN DIN H L High-Z DIN H X L H DIN High-Z Temporary Sector Group Unprotection *6 X X X X X X X X X VID X Flash Hardware Reset X H H X X X X High-Z High-Z L X Boot Block Sector Write Protection X X X X X X X X X X L FCRAM Power Down*8 X X L X X X X X X X X Legend : L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels. *1: Other operations except for this indicated table are prohibited. *2: Do not apply CEf = VIL, CE1r = VIL and CE2r = VIH all at once. *3: FCRAM Output Disable condition should not be kept longer than 1 µs. *4: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *5: FCRAM Byte control at Read operation is not supported. *6: It is also used for the extended sector group protections. *7: Protect “outermost” 2 × 8 Kbytes (4 words) on both ends of the boot block sectors. *8: Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. 6 MB84VD23381FJ-80 ■ ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Min Max Tstg −55 +125 °C TA −30 +85 °C VIN −0.3 VCCf + 0.3 V VOUT −0.3 VCCr + 0.3 V VCCf Supply *1 VCCf −0.2 +3.6 V 1 VCCr −0.2 +3.6 V RESET * VIN −0.5 +13.0 V WP/ACC *3 VIN −0.5 +10.5 V Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All pins *1 VCCr Supply * 2 *1: Minimum DC voltage on input or I/O pins is –0.3 V. During voltage transitions, input or I/O pins may undershoot VSS to –1.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf+0.3 V or VCCr+0.3 V. During voltage transitions, input or I/O pins may overshoot to VCCf+1.0 V or VCCr+1.0 V for periods of up to 5 ns. *2: Minimum DC input voltage on RESET pin is –0.5 V. During voltage transitions, RESET pin may undershoot VSS to –2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN-VCCf or VCCr) does not exceed 9.0 V. Maximum DC input voltage on RESET pin is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns. *3: Minimum DC input voltage on WP/ACC pin is –0.5 V. During voltage transitions, WP/ACC pin may undershoot Vss to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may overshoot to +10.5 V for periods of up to 20 ns, when VCCf is applied. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Value Min Max Unit Ambient Temperature TA −30 +85 °C VCCf Supply Voltages VCCf +2.7 +3.1 V VCCr Supply Voltages VCCr +2.7 +3.1 V WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 7 MB84VD23381FJ-80 ■ ELECTRICAL CHARACTERISTICS 1. DC Characteristics*1,*2,*3 Parameter Symbol Test Conditions Value Min Typ Max Unit Input Leakage Current ILI VIN = VSS to VCCf, VCCr –1.0 — +1.0 µA Output Leakage Current ILO VOUT = VSS to VCCf, VCCr –1.0 — +1.0 µA RESET Inputs Leakage Current ILIT VCCf = VCCf Max, RESET = 12.5 V — — 35 µA Flash VCC Active Current (Read) *4 ICC1f CEf = VIL, OE = VIH tCYCLE = 5 MHz — — 18 mA tCYCLE = 1 MHz — — 4 mA Flash VCC Active Current (Program/Erase) *5 ICC2f CEf = VIL, OE = VIH — — 35 mA Flash VCC Active Current (Read-While-Program) *6 ICC3f CEf = VIL, OE = VIH — — 53 mA Flash VCC Active Current (Read-While-Erase) *8 ICC4f CEf = VIL, OE = VIH — — 53 mA Flash VCC Active Current (Erase-Suspend-Program)*8 ICC5f CEf = VIL, OE = VIH — — 40 mA WP/ACC Acceleration Program Current IACC VCCf = VCCf Max, WP/ACC = VACC Max — — 20 mA tRC / tWC = Min — 15 20 FCRAM VCC Active Current ICC1r VCCr = VCCr Max, CE1r = VIL, CE2r = VIH, VIN = VIH or VIL, IOUT = 0 mA tRC / tWC = 1 µs — 2.5 3.0 Flash VCC Standby Current ISB1f VCCf = VCCf Max, CEf = VCCf ± 0.3 V, RESET = VCCf ± 0.3 V, WP/ACC = VCCf ± 0.3 V — 1 5 µA Flash VCC Standby Current (RESET) ISB2f VCCf = VCCf Max, RESET = VSS ± 0.3 V, WP/ACC = VCCf ± 0.3 V — 1 5 µA Flash VCC Curren t (Automatic Sleep Mode) *6 ISB3f VCCf = VCCf Max, CEf = VSS ± 0.3 V, RESET = VCCf ± 0.3 V, WP/ACC = VCCf ± 0.3 V, VIN = VCCf ± 0.3 V or VSS ± 0.3 V — 1 5 µA FCRAM VCC Standby Current ISBr VCCr = VCCr Max, CE1r = CE2r = VIH, VIN = VIH or VIL, IOUT = 0 mA — 0.5 1 mA FCRAM VCC Standby Current ISB1r VCCr = VCCr Max, CE1r > VCCr – 0.2V, CE2r > VCCr– 0.2V, VIN < 0.2 V or VIN> VCCr – 0.2 V, IOUT = 0 mA — — 70 µA FCRAM VCC Standby Current *9 ISB2r VCCr = VCCr Max,CE1r > VCCr – 0.2V, CE2r > VCCr– 0.2V, VIN Cycle time = tRC Min, IOUT = 0 mA — — 5 mA FCRAM VCC Power Down Current IPDr VCCr = VCCr Max, VIN > VCCf – 0.2 V or VIN < 0.2 V, CE2r < 0.2V, IOUT = 0 mA — — 10 µA mA (Continued) 8 MB84VD23381FJ-80 (Continued) Parameter Value Symbol Test Conditions Input Low Level VIL — Input High Level VIH Voltage for Autoselect and Sector Protection (RESET) *7 VID — 11.5 — 12.5 V Voltage for WP/ACC Sector Protection/Unprotection and Program Acceleration VACC — 8.5 9.0 9.5 V FCRAM Output Low Level VOL VCCr = VCCr Min, IOL =1.0 mA — — 0.4 V FCRAM Output High Level VOH VCCr = VCCr Min, IOH = –0.5 mA 2.2 — — V Flash Output Low Level VOL VCCf = VCCf Min, IOL = 4.0 mA — — 0.45 V Flash Output High Level VOH VCCf = VCCf Min, IOH = –0.1 mA VCCf–0.4 — — V Flash Low VCC Lock-Out Voltage VLKO 2.3 2.4 2.5 V — Min Typ Max –0.3 — 0.5 Flash 2.0 FCRAM 2.2 — — VCCf+0.3 VCCr+0.3 Unit V V *1 : All voltage are referenced to VSS. *2 : FCRAM DC characteristics are measured after following POWER-UP timing. *3 : IOUT depends on the output load conditions. *4 : The ICC current listed includes both the DC operating current and the frequency dependent component. *5 : ICC active while Embedded Algorithm (program or erase) is in progress. *6 : Automatic sleep mode enables the low power mode when address remain stable for 150 ns. *7 : Applicable for only VCC applying. *8 : Embedded Algorithm (program or erase) is in progress. (@5 MHz) *9 : ISB2r depends on VIN cycle time. Please refer to ■ APPENDIX A. 9 MB84VD23381FJ-80 2. AC Characteristics • CE Timing Parameter Symbol Value Condition Min Standard CE Recover Time tCCR 0 ns CE Hold Time tCHOLD 3 ns CE1r High to WE Invalid time for Standby Entry — tCHWX — 20 ns • Timing Diagram for alternating FCRAM to Flash CEf tCCR tCCR CE1r WE tCHWX tCCR CE2r 10 Unit JEDEC tCHOLD tCCR MB84VD23381FJ-80 ■ 64 M FLASH MEMORY CHARACTERISTICS for MCP 1. FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY • Sixteen 4K words, and one hundred twenty-six 32 K words. • Individual-sector, multiple-sector, or bulk-erase capability. Bank A Bank B SA0 : 8KB (4KW) SA1 : 8KB (4KW) SA2 : 8KB (4KW) SA3 : 8KB (4KW) SA4 : 8KB (4KW) SA5 : 8KB (4KW) SA6 : 8KB (4KW) SA7 : 8KB (4KW) SA8 : 64KB (32KW) SA9 : 64KB (32KW) SA10 : 64KB (32KW) SA11 : 64KB (32KW) SA12 : 64KB (32KW) SA13 : 64KB (32KW) SA14 : 64KB (32KW) SA15 : 64KB (32KW) SA16 : 64KB (32KW) SA17 : 64KB (32KW) SA18 : 64KB (32KW) SA19 : 64KB (32KW) SA20 : 64KB (32KW) SA21 : 64KB (32KW) SA22 : 64KB (32KW) SA23 : 64KB (32KW) SA24 : 64KB (32KW) SA25 : 64KB (32KW) SA26 : 64KB (32KW) SA27 : 64KB (32KW) SA28 : 64KB (32KW) SA29 : 64KB (32KW) SA30 : 64KB (32KW) SA31 : 64KB (32KW) SA32 : 64KB (32KW) SA33 : 64KB (32KW) SA34 : 64KB (32KW) SA35 : 64KB (32KW) SA36 : 64KB (32KW) SA37 : 64KB (32KW) SA38 : 64KB (32KW) SA39 : 64KB (32KW) SA40 : 64KB (32KW) SA41 : 64KB (32KW) SA42 : 64KB (32KW) SA43 : 64KB (32KW) SA44 : 64KB (32KW) SA45 : 64KB (32KW) SA46 : 64KB (32KW) SA47 : 64KB (32KW) SA48 : 64KB (32KW) SA49 : 64KB (32KW) SA50 : 64KB (32KW) SA51 : 64KB (32KW) SA52 : 64KB (32KW) SA53 : 64KB (32KW) SA54 : 64KB (32KW) SA55 : 64KB (32KW) SA56 : 64KB (32KW) SA57 : 64KB (32KW) SA58 : 64KB (32KW) SA59 : 64KB (32KW) SA60 : 64KB (32KW) SA61 : 64KB (32KW) SA62 : 64KB (32KW) SA63 : 64KB (32KW) SA64 : 64KB (32KW) SA65 : 64KB (32KW) SA66 : 64KB (32KW) SA67 : 64KB (32KW) SA68 : 64KB (32KW) SA69 : 64KB (32KW) SA70 : 64KB (32KW) Word Mode 000000h 001000h 002000h 003000h 004000h 005000h 006000h 007000h 008000h 010000h 018000h 020000h 028000h 030000h 038000h 040000h 048000h 050000h 058000h 060000h 068000h 070000h 078000h 080000h 088000h 090000h 098000h 0A0000h 0A8000h 0B0000h 0B8000h 0C0000h 0C8000h 0D0000h 0D8000h 0E0000h 0E8000h 0F0000h 0F8000h 100000h 108000h 110000h 118000h 120000h 128000h 130000h 138000h 140000h 148000h 150000h 158000h 160000h 168000h 170000h 178000h 180000h 188000h 190000h 198000h 1A0000h 1A8000h 1B0000h 1B8000h 1C0000h 1C8000h 1D0000h 1D8000h 1E0000h 1E8000h 1F0000h 1F8000h 1FFFFFh Bank C Bank D SA71 : 64KB (32KW) SA72 : 64KB (32KW) SA73 : 64KB (32KW) SA74 : 64KB (32KW) SA75 : 64KB (32KW) SA76 : 64KB (32KW) SA77 : 64KB (32KW) SA78 : 64KB (32KW) SA79 : 64KB (32KW) SA80 : 64KB (32KW) SA81 : 64KB (32KW) SA82 : 64KB (32KW) SA83 : 64KB (32KW) SA84 : 64KB (32KW) SA85 : 64KB (32KW) SA86 : 64KB (32KW) SA87 : 64KB (32KW) SA88 : 64KB (32KW) SA89 : 64KB (32KW) SA90 : 64KB (32KW) SA91 : 64KB (32KW) SA92 : 64KB (32KW) SA93 : 64KB (32KW) SA94 : 64KB (32KW) SA95 : 64KB (32KW) SA96 : 64KB (32KW) SA97 : 64KB (32KW) SA98 : 64KB (32KW) SA99 : 64KB (32KW) SA100 : 64KB (32KW) SA101 : 64KB (32KW) SA102 : 64KB (32KW) SA103 : 64KB (32KW) SA104 : 64KB (32KW) SA105 : 64KB (32KW) SA106 : 64KB (32KW) SA107 : 64KB (32KW) SA108 : 64KB (32KW) SA109 : 64KB (32KW) SA110 : 64KB (32KW) SA111 : 64KB (32KW) SA112 : 64KB (32KW) SA113 : 64KB (32KW) SA114 : 64KB (32KW) SA115 : 64KB (32KW) SA116 : 64KB (32KW) SA117 : 64KB (32KW) SA118 : 64KB (32KW) SA119 : 64KB (32KW) SA120 : 64KB (32KW) SA121 : 64KB (32KW) SA122 : 64KB (32KW) SA123 : 64KB (32KW) SA124 : 64KB (32KW) SA125 : 64KB (32KW) SA126 : 64KB (32KW) SA127 : 64KB (32KW) SA128 : 64KB (32KW) SA129 : 64KB (32KW) SA130 : 64KB (32KW) SA131 : 64KB (32KW) SA132 : 64KB (32KW) SA133 : 64KB (32KW) SA134 : 8KB (4KW) SA135 : 8KB (4KW) SA136 : 8KB (4KW) SA137 : 8KB (4KW) SA138 : 8KB (4KW) SA139 : 8KB (4KW) SA140 : 8KB (4KW) SA141 : 8KB (4KW) Word Mode 200000h 208000h 210000h 218000h 220000h 228000h 230000h 238000h 240000h 248000h 250000h 258000h 260000h 268000h 270000h 278000h 280000h 288000h 290000h 298000h 2A0000h 2A8000h 2B0000h 2B8000h 2C0000h 2C8000h 2D0000h 2D8000h 2E0000h 2E8000h 2F0000h 2F8000h 300000h 308000h 310000h 318000h 320000h 328000h 330000h 338000h 340000h 348000h 350000h 358000h 360000h 368000h 370000h 378000h 380000h 388000h 390000h 398000h 3A0000h 3A8000h 3B0000h 3B8000h 3C0000h 3C8000h 3D0000h 3D8000h 3E0000h 3E8000h 3F0000h 3F8000h 3F9000h 3FA000h 3FB000h 3FC000h 3FD000h 3FE000h 3FF000h 3FFFFFh Sector Architecture 11 MB84VD23381FJ-80 FlexBankTM Architecture Bank 1 Bank 2 Bank Splits Volume Combination Volume Combination 1 8 Mbit Bank A 56 Mbit Remainder (Bank B, C, D) 2 24 Mbit Bank B 40 Mbit Remainder (Bank A, C, D) 3 24 Mbit Bank C 40 Mbit Remainder (Bank A, B, D) 4 8 Mbit Bank D 56 Mbit Remainder (Bank A, B, C) Example of Virtual Banks Combination Bank 1 Bank Splits Volume Combination Sector Size Volume 1 8 Mbit Bank A 8 × 8 Kbyte/4 Kword + 56 Mbit 15 × 64 Kbyte/32 Kword 2 16 Mbit Bank A + Bank D 16 × 8 Kbyte/4 Kword + 48 Mbit 30 × 64 Kbyte/32 Kword 3 24 Mbit Bank B 48 × 64 Kbyte/32 Kword 40 Mbit 4 32 Mbit Bank A + Bank B 8 × 8 Kbyte/4 Kword + 32 Mbit 63 × 64 Kbyte/32 Kword Bank 2 Combination Sector Size Bank B + 8 × 8 Kbyte/4 Kword Bank C + + 111 × 64 Kbyte/32 Kword Bank D Bank B + 96 × 64 Kbyte/32 Kword Bank C Bank A + 16 × 8 Kbyte/4 Kword + Bank C + 78 × 64 Kbyte/32 Kword Bank D Bank C 8 × 8 Kbyte/4 Kword + + Bank D 63 × 64 Kbyte/32 Kword Note : When multiple sector erase over several banks is operated, the system cannot read out of the bank to which a sector being erased belongs. For example, suppose that erasing is taking place at both Bank A and Bank B, neither Bank A nor Bank B is read out (they would output the sequence flag once they were selected.) Meanwhile the system would get to read from either Bank C or Bank D. Simultaneous Operation Case 1 2 3 4 5 6 7 Bank 1 Status Read mode Read mode Read mode Read mode Autoselect mode Program mode Erase mode * Bank 2 Status Read mode Autoselect mode Program mode Erase mode * Read mode Read mode Read mode * : By writing erase suspend command on the bank address of sector being erased, the erase operation gets suspended so that it enables reading from or programming the remaining sectors. Note: Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. Actually, the Bank consists of 4 banks, Bank A, Bank B, BankC and Bank D. Bank Address (BA) meant to specify each of the Banks. 12 MB84VD23381FJ-80 Sector Address Tables Sector Address Bank Bank A Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 Bank Address A21 A20 A19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address Range A18 A17 A16 A15 A14 A13 A12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X Word Mode 000000h to 000FFFh 001000h to 001FFFh 002000h to 002FFFh 003000h to 003FFFh 004000h to 004FFFh 005000h to 005FFFh 006000h to 006FFFh 007000h to 007FFFh 008000h to 00FFFFh 010000h to 017FFFh 018000h to 01FFFFh 020000h to 027FFFh 028000h to 02FFFFh 030000h to 037FFFh 038000h to 03FFFFh 040000h to 047FFFh 048000h to 04FFFFh 050000h to 057FFFh 058000h to 05FFFFh 060000h to 067FFFh 068000h to 06FFFFh 070000h to 077FFFh 078000h to 07FFFFh (Continued) 13 MB84VD23381FJ-80 (Continued) Sector Address Bank Bank B Sector SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 Bank Address A21 A20 A19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Address Range A18 A17 A16 A15 A14 A13 A12 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Word Mode 080000h to 087FFFh 088000h to 08FFFFh 090000h to 097FFFh 098000h to 09FFFFh 0A0000h to 0A7FFFh 0A8000h to 0AFFFFh 0B0000h to 0B7FFFh 0B8000h to 0BFFFFh 0C0000h to 0C7FFFh 0C8000h to 0CFFFFh 0D0000h to 0D7FFFh 0D8000h to 0DFFFFh 0E0000h to 0E7FFFh 0E8000h to 0EFFFFh 0F0000h to 0F7FFFh 0F8000h to 0FFFFFh 100000h to 107FFFh 108000h to 10FFFFh 110000h to 117FFFh 118000h to 11FFFFh 120000h to 127FFFh 128000h to 12FFFFh 130000h to 137FFFh 138000h to 13FFFFh 140000h to 147FFFh 148000h to 14FFFFh 150000h to 157FFFh 158000h to 15FFFFh 160000h to 167FFFh 168000h to 16FFFFh 170000h to 177FFFh 178000h to 17FFFFh 180000h to 187FFFh 188000h to 18FFFFh 190000h to 197FFFh 198000h to 19FFFFh 1A0000h to 1A7FFFh 1A8000h to 1AFFFFh 1B0000h to 1B7FFFh 1B8000h to 1BFFFFh 1C0000h to 1C7FFFh 1C8000h to 1CFFFFh 1D0000h to 1D7FFFh 1D8000h to 1DFFFFh 1E0000h to 1E7FFFh 1E8000h to 1EFFFFh 1F0000h to 1F7FFFh 1F8000h to 1FFFFFh (Continued) 14 MB84VD23381FJ-80 (Continued) Sector Address Bank Bank C Sector SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 Bank Address A21 A20 A19 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address Range A18 A17 A16 A15 A14 A13 A12 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Word Mode 200000h to 207FFFh 208000h to 20FFFFh 210000h to 217FFFh 218000h to 21FFFFh 220000h to 227FFFh 228000h to 22FFFFh 230000h to 237FFFh 238000h to 23FFFFh 240000h to 247FFFh 248000h to 24FFFFh 250000h to 257FFFh 258000h to 25FFFFh 260000h to 267FFFh 268000h to 26FFFFh 270000h to 277FFFh 278000h to 27FFFFh 280000h to 287FFFh 288000h to 28FFFFh 290000h to 297FFFh 298000h to 29FFFFh 2A0000h to 2A7FFFh 2A8000h to 2AFFFFh 2B0000h to 2B7FFFh 2B8000h to 2BFFFFh 2C0000h to 2C7FFFh 2C8000h to 2CFFFFh 2D0000h to 2D7FFFh 2D8000h to 2DFFFFh 2E0000h to 2E7FFFh 2E8000h to 2EFFFFh 2F0000h to 2F7FFFh 2F8000h to 2FFFFFh 300000h to 307FFFh 308000h to 30FFFFh 310000h to 317FFFh 318000h to 31FFFFh 320000h to 327FFFh 328000h to 32FFFFh 330000h to 337FFFh 338000h to 33FFFFh 340000h to 347FFFh 348000h to 34FFFFh 350000h to 357FFFh 358000h to 35FFFFh 360000h to 367FFFh 368000h to 36FFFFh 370000h to 377FFFh 378000h to 37FFFFh (Continued) 15 MB84VD23381FJ-80 (Continued) Sector Address Bank Bank D 16 Sector SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 Bank Address A21 A20 A19 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Address Range A18 A17 A16 A15 A14 A13 A12 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1 Word Mode 380000h to 387FFFh 388000h to 38FFFFh 390000h to 397FFFh 398000h to 39FFFFh 3A0000h to 3A7FFFh 3A8000h to 3AFFFFh 3B0000h to 3B7FFFh 3B8000h to 3BFFFFh 3C0000h to 3C7FFFh 3C8000h to 3CFFFFh 3D0000h to 3D7FFFh 3D8000h to 3DFFFFh 3E0000h to 3E7FFFh 3E8000h to 3EFFFFh 3F0000h to 3F7FFFh 3F8000h to 3F8FFFh 3F9000h to 3F9FFFh 3FA000h to 3FAFFFh 3FB000h to 3FBFFFh 3FC000h to 3FCFFFh 3FD000h to 3FDFFFh 3FE000h to 3FEFFFh 3FF000h to 3FFFFFh MB84VD23381FJ-80 Sector Group Addresses Sector Group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 A21 0 0 0 0 0 0 0 0 A20 0 0 0 0 0 0 0 0 A19 0 0 0 0 0 0 0 0 A18 0 0 0 0 0 0 0 0 A17 0 0 0 0 0 0 0 0 SGA8 0 0 0 0 0 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 SGA17 SGA18 SGA19 SGA20 SGA21 SGA22 SGA23 SGA24 SGA25 SGA26 SGA27 SGA28 SGA29 SGA30 SGA31 SGA32 SGA33 SGA34 SGA35 SGA36 SGA37 SGA38 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 SGA39 1 1 1 1 1 SGA40 SGA41 SGA42 SGA43 SGA44 SGA45 SGA46 SGA47 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A16 0 0 0 0 0 0 0 0 0 1 1 A15 0 0 0 0 0 0 0 0 1 0 1 A14 0 0 0 0 1 1 1 1 A13 0 0 1 1 0 0 1 1 A12 0 1 0 1 0 1 0 1 Sectors SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 X X X SA8 to SA10 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X SA11 to SA14 SA15 to SA18 SA19 to SA22 SA23 to SA26 SA27 to SA30 SA31 to SA34 SA35 to SA38 SA39 to SA42 SA43 to SA46 SA47 to SA50 SA51 to SA54 SA55 to SA58 SA59 to SA62 SA63 to SA66 SA67 to SA70 SA71 to SA74 SA75 to SA78 SA79 to SA82 SA83 to SA86 SA87 to SA90 SA91 to SA94 SA95 to SA98 SA99 to SA102 SA103 to SA106 SA107 to SA110 SA111 to SA114 SA115 to SA118 SA119 to SA122 SA123 to SA126 SA127 to SA130 0 0 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 X X X SA131 to SA133 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 17 MB84VD23381FJ-80 Flash Memory Autoselect Codes Type A21 to A12 A6 A3 A2 A1 A0 Code (HEX) Manufacture’s Code BA L L L L L 04h Device Code BA L L L L H 227Eh Extended Device Code *2 BA L H H H L 2202h BA L H H H H 2201h Sector Group Addresses L L L H L 01h*1 Sector Group Protection Legend: L = VIL, H = VIH. See DC Characteristics for voltage levels. *1 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *2 : A read cycle at address (BA) 01h outputs device code. When 227Eh was output, this indicates that there will require two additional codes, called Extended Device Codes. Therefore the system may continue reading out these Extended Device Codes at the address of (BA) 0Eh, as well as at (BA) 0Fh. 18 MB84VD23381FJ-80 Flash Memory Command Definitions Fourth Bus Read/Write Cycle Bus Write Cycles Req’d First Bus Write Cycle Second Bus Write Cycle Third Bus Write Cycle Fifth Bus Write Cycle Sixth Bus Write Cycle Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Read/Reset 1 XXXh F0h — — — — — — — — — — Read/Reset 3 555h AAh 2AAh 55h 555h F0h RA RD — — — — Autoselect 3 555h AAh 2AAh 55h (BA) 555h 90h — — — — — — Program 4 555h AAh 2AAh 55h 555h A0h PA PD — — — — Program Suspend 1 BA B0h — — — — — — — — — — Program Resume 1 BA 30h — — — — — — — — — — Chip Erase 6 555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h 555h 10h Sector Erase 6 555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h SA 30h Erase Suspend 1 BA B0h — — — — — — — — — — Erase Resume 1 BA 30h — — — — — — — — — — Extended Sector Group Protection *2 4 XXXh 60h SPA 60h SPA 40h SPA SD — — — — Set to Fast Mode 3 555h AAh 2AAh 55h 555h 20h — — — — — — Fast Program *1 2 XXXh A0h PA PD — — — — — — — — Reset from Fast Mode *1 2 BA 90h XXXh — — — — — — — — Query 1 (BA) 55h 98h — — — — — — — — — — HiddenROM Entry 3 555h AAh 2AAh 55h 555h 88h — — — — — — HiddenROM Program *3 4 555h AAh 2AAh 55h 555h A0h (HRA) PA PD — — — — HiddenROM Exit *3 4 555h AAh 2AAh 55h 90h XXXh 00h — — — — Command Sequence *4 F0h (HRBA) 555h (Continued) 19 MB84VD23381FJ-80 (Continued) *1: This command is valid while Fast Mode. *2: This command is valid while RESET = VID. *3: This command is valid while HiddenROM mode. *4: The data “00h” is also acceptable. Notes : • Address bits A21 to A11 = X = “H” or “L” for all address commands except or Program Address (PA), Sector Address (SA), and Bank Address (BA), and Sector Group Address (SPA). • Bus operations are defined in ■ DEVICE BUS OPERATION. • RA = Address of the memory location to be read PA = Address of the memory location to be programmed Addresses are latched on the falling edge of the write pulse. SA = Address of the sector to be erased. The combination of A21, A20, A19, A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. BA = Bank Address (A21, A20, A19) • RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the falling edge of write pulse. • SPA = Sector group address to be protected. Set sector group address and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0). SD = Sector group protection verify data. Output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. • HRA = Address of the HiddenROM area: 000000h to 00007Fh • HRBA = Bank Address of the HiddenROM area (A21 = A20 = A19 = VIL) • The system should generate the following address patterns: 555h or 2AAh to addresses A10 to A0 • Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. • Command combinations not described in “Flash Memory Command Definitions” are illegal. 20 MB84VD23381FJ-80 2. AC Characteristics • Read Only Operations Characteristics (Flash) Symbol Parameter JEDEC Standard Condition Value* Min Max Unit Read Cycle Time tAVAV tRC — 70 — ns Address to Output Delay tAVQV tACC CEf = VIL OE = VIL — 70 ns Chip Enable to Output Delay tELQV tCEf OE = VIL — 70 ns Output Enable to Output Delay tGLQV tOE — — 30 ns Chip Enable to Output High-Z tEHQZ tDF — — 25 ns Output Enable to Output High-Z tGHQZ tDF — — 25 ns Output Hold Time From Addresses, CEf or OE, Whichever Occurs First tAXQX tOH — 0 — ns — tREADY — — 20 µs RESET Pin Low to Read Mode *: Test Conditions–Output Load : 1 TTL gate and 30 pF Input rise and fall times: 5 ns Input pulse levels: 0.0 V to VCCf Timing measurement reference level Input: 0.5×VCCf Output: 0.5×VCCf 21 MB84VD23381FJ-80 • Read Operation Timing Diagram (Flash) tRC Address Address Stable tACC CEf tOE tDF OE tOEH WE tOH tCE High-Z High-Z Outputs Valid Outputs • Hardware Reset/Read Operation Timing Diagram (Flash) tRC Address Address Stable tACC CEf tRH tRP tRH tCE RESET tOH Outputs 22 High-Z Outputs Valid MB84VD23381FJ-80 • Write/Erase/Program Operations (Flash) Parameter Symbol Value Unit JEDEC Standard Min Typ Max Write Cycle Time tAVAV tWC 70 ns Address Setup Time tAVWL tAS 0 ns tASO 12 ns tWLAX tAH 45 ns tAHT 0 ns Data Setup Time tDVWH tDS 30 ns Data Hold Time tWHDX tDH 0 ns 0 ns tOEH 10 ns CEf High During Toggle Bit Polling tCEPH 20 ns OE High During Toggle Bit Polling tOEPH 20 ns Read Recover Time Before Write tGHWL tGHWL 0 ns Read Recover Time Before Write tGHEL tGHEL 0 ns CEf Setup Time tELWL tCS 0 ns WE Setup Time tWLEL tWS 0 ns CEf Hold Time tWHEH tCH 0 ns WE Hold Time tEHWH tWH 0 ns Write Pulse Width tWLWH tWP 35 ns CEf Pulse Width tELEH tCP 35 ns Write Pulse Width High tWHWL tWPH 25 ns CEf Pulse Width High tEHEL tCPH 25 ns Programming Operation tWHWH1 tWHWH1 6 60 µs Sector Erase Operation *1 tWHWH2 tWHWH2 0.2 1 s tVCS 50 µs Rise Time to VID * tVIDR 500 ns Rise Time to VACC *3 tVACCR 500 ns Voltage Transition Time *2 tVLHT 4 µs tWPP 100 µs Address Setup Time to OE Low During Toggle Bit Polling Address Hold Time Address Hold Time from CEf or OE High During Toggle Bit Polling Output Enable Hold Time Read Toggle and Data Polling VCCf Setup Time 2 Write Pulse Width * 2 (Continued) 23 MB84VD23381FJ-80 (Continued) Symbol Parameter Unit JEDEC Standard Min Typ Max tOESP 4 µs tCSP 4 µs Recover Time from RY/BY tRB 0 ns RESET Pulse Width tRP 500 ns RESET High Level Period Before Read tRH 200 ns Program/Erase Valid to RY/BY Delay tBUSY 90 ns Delay Time from Embedded Output Enable tEOE 70 ns Erase Time-out Time tTOW 50 µs Erase Suspend Transition Time tSPD 20 µs OE Setup Time to WE Active *2 CEf Setup Time to WE Active * 2 *1: This does not include preprogramming time. *2: This timing is for Sector Group Protection operation. *3: This timing is for Accelerated Program operation. 24 Value MB84VD23381FJ-80 • Write Cycle (WE control) (Flash) 3rd Bus Cycle Data Polling 555h Address tWC PA tAS PA tRC tAH CEf tCS tCH tCE OE tGHWL tWP tOE tWPH tWHWH1 WE Data A0h tOH tDF tDS tDH PD DQ7 DOUT DOUT Notes : • PA is address of the memory location to be programmed. • PD is data to be programmed at word address. • DQ7 is the output of the complement of the data written to the device. • DOUT is the output of the data written to the device. • Figure indicates last two bus cycles out of four bus cycle sequence. 25 MB84VD23381FJ-80 • Write Cycle (CEf control) (Flash) 3rd Bus Cycle Data Polling 555h Address tWC PA PA tAS tAH WE tWS tWH OE tGHEL tCP tCPH tWHWH1 CEf tDS Data A0h tDH PD DQ7 DOUT Notes : • PA is address of the memory location to be programmed. • PD is data to be programmed at word address. • DQ7 is the output of the complement of the data written to the device. • DOUT is the output of the data written to the device. • Figure indicates last two bus cycles out of four bus cycle sequence. 26 MB84VD23381FJ-80 • AC Waveforms Chip/Sector Erase Operations (Flash) 555h Address tWC 2AAh tAS 555h 555h 2AAh SA* tAH CEf tCS tCH OE tGHWL tWP tWPH tDS tDH WE AAh Data 30h for Sector Erase 55h 80h AAh 55h 10h/ 30h tVCS VCCf * : SA is the sector address for Sector Erase. Addresses = 555h (Word) for Chip Erase. 27 MB84VD23381FJ-80 • AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash) CEf tCH tDF tOE OE tOEH WE tCE * DQ7 Data DQ7 DQ7 = Valid Data High-Z tWHWH1 or 2 DQ6 to DQ0 DQ6 to DQ0 = Output Flag Data tBUSY DQ6 to DQ0 Valid Data tEOE RY/BY * : DQ7 = Valid Data (the device has completed the Embedded operation) . 28 High-Z MB84VD23381FJ-80 • AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash) Address tAHT tASO tAHT tAS CEf tCEPH WE tOEPH tOEH tOEH OE tDH DQ6/DQ2 tOE Toggle Data Data tCE Toggle Data Toggle Data * Stop Toggling Output Valid tBUSY RY/BY * : DQ6 stops toggling (the device has completed the Embedded operation). 29 MB84VD23381FJ-80 • Bank-to-bank Read/Write Timing Diagram (Flash) Address Read Command Read Command Read Read tRC tWC tRC tWC tRC tRC BA1 BA2 (555h) BA1 BA2 (PA) BA1 BA2 (PA) tAS tACC tAH tAS tAHT tCE CEf tOE tCEPH OE tGHWL tDF tOEH tWP WE tDS DQ Valid Output tDH Valid Intput (A0h) tDF Valid Output Valid Intput (PD) Valid Output Status Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2. BA1 : Address corresponding to Bank 1 BA2 : Address corresponding to Bank 2 30 MB84VD23381FJ-80 • RY/BY Timing Diagram during Write/Erase Operations (Flash) CEf Rising edge of the last WE signal WE Entire programming or erase operations RY/BY tBUSY • RESET, RY/BY Timing Diagram (Flash) WE RESET tRP tRB RY/BY tREADY 31 MB84VD23381FJ-80 • Temporary Sector Unprotection (Flash) VCCf tVIDR tVCS tVLHT VID VIH RESET CEf WE tVLHT Program or Erase Command Sequence tVLHT RY/BY Unprotection period • Acceleration Mode Timing Diagram (Flash) VCCf tVACCR tVCS tVLHT VACC VIH WP/ACC CEf WE tVLHT Program Command Sequence RY/BY Acceleration period 32 tVLHT MB84VD23381FJ-80 • Extended Sector Group Protection (Flash) VCCf tVCS RESET tVLHT tVIDR tWC Address tWC SPAX SPAX SPAY A6, A3, A2, A0 A1 CEf OE TIME-OUT tWP WE Data 60h 60h 40h 01h 60h tOE SPAX : Sector Group Address to be protected SPAY : Next Sector Group Address to be protected TIME-OUT : Time-Out window = 250 µs (Min) 33 MB84VD23381FJ-80 ■ 64 M FCRAM AC Charactaristics for MCP • READ OPERATION (FCRAM) Parameter Symbol Value Min Max Unit Notes Read Cycle Time tRC 90 ns Chip Enable Access Time tCE 80 ns *1, *3 Output Enable Access Time tOE 45 ns *1 Chip Enable Access Time tAA 80 ns *1, *4 Output Data Hold Time tOH 5 ns *1 CE1r Low to Output Low-Z tCLZ 5 ns *2 OE Low to Output Low-Z tOLZ 0 ns *2 CE1r High to Output High-Z tCHZ 30 ns *2 OE High to Output High-Z tOHZ 25 ns *2 Address Setup Time to CE1r Low tASC −5 ns *5 tASO 45 ns *3, *6 tASO[ABS] 10 ns *7 tAX 5 ns *4 CE1r Low to Address Hold Time tCLAH 90 ns *4 OE Low to Address Hold Time tOLAH 45 ns *4, *8 CE1r High to Address Hold Time tCHAH −5 ns OE High to Address Hold Time tOHAH –5 ns CE1r Low to OE Low Delay Time tCLOL 45 1000 ns *4, *6, *8, *9 OE Low to CE1r High Delay Time tOLCH 45 ns *8 tCP 20 ns tOP 45 1000 ns *6, *8, *9 tOP[ABS] 20 ns *7 Address Setup Time to OE Address Invalid Time CE1r High Pulse Width OE High Pulse Width *1: The output load is 30 pF. *2: The output load is 5 pF. *3: The tCE is applicable if OE is brought to Low before CE1r goes Low and is also applicable if actual value of both or either tASO or tCLOL is shorter than specified value. *4: Applicable only to A0 and A1 when both CE1r and OE are kept at Low for the address access. *5: Applicable if OE is brought to Low before CE1r goes Low. *6: The tASO, tCLOL (Min) and tOP (Min) are reference values when the access time is determined by tOE. If actual value of each parameter is shorter than specified minimum value, tOE becomes longer by the amount of subtracting actual value from specified minimum value. For example, if actual tASO, tASO (actual) , is shorter than specified minimum value, tASO (Min) , during OE control access (i.e., CE1r stays Low) , the tOE becomes tOE (Max) + tASO (Min) − tASO (actual) . *7: The tASO[ABS] and tOP[ABS] are the absolute minimum values during OE control access. *8: If actual value of either tCLOL or tOP is shorter than specified minimum value, both tOLAH and tOLCH become tRC (Min) − tCLOL (actual) or tRC (Min) − tOP (actual) . *9: Maximum value is applicable if CE1r is kept at Low. 34 MB84VD23381FJ-80 • WRITE OPERATION (FCRAM) Parameter Symbol Value Min Max Unit Notes Write Cycle Time tWC 90 ns *1 Address Setup Time tAS 0 ns *2 Address Hold Time tAH 45 ns *2 CE1r Write Setup Time tCS 0 1000 ns CE1r Write Hold Time tCH 0 1000 ns WE Setup Time tWS 0 ns WE Hold Time tWH 0 ns LB and UB Setup Time tBS 0 ns LB and UB Hold Time tBH −5 ns OE Setup Time tOES 0 1000 ns *3 tOEH 45 1000 ns *3, *4 tOEH[ABS] 20 ns *5 OE High to CE1r Low Setup Time tOHCL −3 ns *6 OE High to Address Hold Time tOHAH −5 ns *7 CE1r Write Pulse Width tCW 60 ns *1, *8 WE Write Pulse Width tWP 60 ns *1, *8 CE1r Write Recovery Time tWRC 15 ns *1, *9 WE Write Recovery Time tWR 15 1000 ns *1, *3, *9 Data Setup Time tDS 20 ns Data Hold Time tDH 0 ns CE1r High Pulse Width tCP 20 ns OE Hold Time *9 *1: Minimum value must be equal or greater than the sum of actual tCW (or tWP) and tWRC (or tWR) . *2: New write address is valid from either CE1r or WE that is brought to High. *3: Maximum value is applicable if CE1r is kept at Low and both WE and OE are kept at High. *4: The tOEH is specified from end of tWC (Min) , and is a reference value when access time is determined by tOE. If actual value is shorter than specified minimum value, tOE becomes longer by the amount of subtracting actual value from specified minimum value. *5: The tOEH[ABS] is the absolute minimum value if write cycle is terminated by WE and CE1r stays Low. *6: tOHCL (Min) must be satisfied if read operation is not performed prior to write operation. In case OE is disabled after tOHCL (Min) , WE Low must be asserted after tRC (Min) from CE1r Low. In other words, read operation is initiated if tOHCL (Min) is not satisfied. *7: Applicable if CE1r stays Low after read operation. *8: tCW and tWP are applicable if write operation is initiated by CE1r and WE, respectively. *9: tWRC and tWR are applicable if write operation is terminated by CE1r and WE, respectively. The tWR (Min) can be ignored if CE1r is brought to High together or after WE is brought to High. In such a case, the tCP (Min) must be satisfied. 35 MB84VD23381FJ-80 • POWER DOWN PARAMETER (FCRAM) Parameter Symbol Value Min Max Unit CE2r Low Setup Time for Power Down Entry tCSP 10 ns CE2r Low Hold Time after Power Down Entry tC2LP 100 ns CE1r High Hold Time following CE2r High after Power Down Exit tCHH 350 µs CE1r High Setup Time following CE2r High after Power Down Exit tCHS 10 ns Note • OTHER TIMING PARAMETER (FCRAM) Parameter Symbol CE1r High to OE Invalid Time for Standby Entry Value Unit Note Min Max tCHOX 20 ns CE1r High to WE Invalid Time for Standby Entry tCHWX 20 ns *1 CE2r Low Hold Time after Power-up tC2LH 50 µs *2 CE2r HIgh Hold Time after Power-up tC2HL 50 µs *3 CE1r High Hold Time following CE2r High after Power-up tCHH 350 µs *2 tT 1 25 ns *4 Input Transition Time *1: It may write some data into any address location if tCHWX is not satisfied. *2: Must satisfy tCHH(Min) after tC2LH(Min). *3: Requires Power Down mode entry and exit after tC2HL. *4: The Input Transition Time (tT) at AC testing is 5 ns as shown in below. If actual tT is longer than 5 ns, it may violate some timing parameters of AC specification. • AC TEST CONDITIONS (FCRAM) Parameter Condition Value Unit Input High Level VIH VCCr = 2.7 V to 3.1 V 2.3 V Input Low Level VIL VCCr = 2.7 V to 3.1 V 0.4 V VREF VCCr = 2.7 V to 3.1 V 1.3 V tT Between VIL and VIH 5 ns Input Timing Measurement Level Input Transition Time 36 Symbol Note MB84VD23381FJ-80 • READ Timing #1 (OE Control Access) (FCRAM) tRC Address tRC Address Valid Address Valid tOHAH tCE tASO tOHAH CE1r tOLCH tCLOL tOP tOE tOE OE tASO tOHZ tOLZ tOHZ tOH tOH tOLZ DQ (Output) Valid Data Output Valid Data Output Note : CE2r and WE must be High for entire read cycle. • READ Timing #2 (CE1r Control Access) (FCRAM) tRC Address tRC Address Valid tASC Address Valid tCE tCHAH tCE tASC tCHAH CE1r tOLCH tCP tOE tCHZ tCHZ OE tOH tCLZ tCLZ tOH DQ (Output) Valid Data Output Valid Data Output Note : CE2r and WE must be High for entire read cycle. 37 MB84VD23381FJ-80 • READ Timing #3 (Address Access after OE Control Access) (FCRAM) tRC tRC Address (A19 to A2) Address Valid Address (A1, A0) Address Valid tASO Address Valid (No change) Address Valid tOLAH tOHAH tAA tAX CE1r tOE tOHZ OE tOLZ tOH tOH DQ (Output) Valid Data Output Valid Data Output Note : CE2r and WE must be High for entire read cycle. • READ Timing #4 (Address Access after CE1r Control Access) (FCRAM) tRC Address (A19 to A2) Address Valid Address (A1, A0) Address Valid tASC tRC Address Valid (No change) Address Valid tCLAH tAA tCHAH tAX CE1r tCE tCHZ OE tOH tCLZ tOH DQ (Output) Valid Data Output Note : CE2r and WE must be High for entire read cycle. 38 Valid Data Output MB84VD23381FJ-80 • WRITE Timing #1 (CE1r Control) (FCRAM) tWC Address Address Valid tAS tAH tAS CE1r tCW tWRC tWS tWH tWS tBS tBH tBS WE UB, LB tOHCL OE tDS tDH DQ (Input) Valid Data Input Note : CE2r must be High for write cycle. 39 MB84VD23381FJ-80 • WRITE Timing #2-1 (WE Control, Single Write Operation) (FCRAM) tWC Address tOHAH CE1 Read Address Write Address tAS tAH tASO Low tWP tWR tOEH WE tOHBH tBS tBH tBSO UB, LB tOES OE tOHZ tOH tDS tDH DQ Read Data Output Note : CE2r must be High for write cycle. 40 Write Data Input tOLZ MB84VD23381FJ-80 • WRITE Timing #2 (WE Control, Continuous Write Operation) (FCRAM) tWC Address Address Valid tOHAH tAS tAH tAS CE1r tOHCL tCS tWP tWR WE tBS tBH tBS UB, LB tOES OE tOHZ tDS tDH DQ (Input) Valid Data Input Note : CE2r must be High for write cycle. 41 MB84VD23381FJ-80 • READ/WRITE Timing #1-1 (CE1r Control) (FCRAM) tWC Address Write Address tCHAH tAS Read Address tAH tASC CE1r tCP tWRC tWS tWH tCW tWH tWS WE tBS tBH UB, LB tOHCL tCLOL OE tCHZ tOH tDS tDH DQ Read Data Output Write Data Input Note : Write address is valid from either CE1r or WE of last falling edge. 42 tOLZ tCLZ MB84VD23381FJ-80 • READ/WRITE Timing #1-2 (CE1r Control) (FCRAM) tRC Address Read Address Write Address tASC tCHAH tAS tWRC CE1r tWRC(Min) tWH tCP tWS tWH tWS WE tBH tCE tBS UB, LB tOEH tOHCL OE tCHZ tDH tCLZ tOH DQ Write Data Input Read Data Output Note : The tOEH is specified from the time satisfied both tWRC and tWR (Min) . 43 MB84VD23381FJ-80 • READ (OE Control) /WRITE (WE Control) Timing #2-1 (FCRAM) tWC Address tOHAH CE1r Read Address Write Address tAS tAH tASO Low tWP tWR WE tBS tBH UB, LB tOES tOEH OE tOHZ tOH tDS tDH DQ Read Data Output Write Data Input Note : CE1r can be tied to Low for WE and OE controlled operation. When CE1r is tied to Low, output is exclusively controlled by OE. 44 tOLZ MB84VD23381FJ-80 • READ (OE Control) /WRITE (WE Control) Timing #2-2 (FCRAM) tRC Address Read Address Valid Write Address tOHAH tASO CE1r tAS Low tWR WE tBH tBS UB, LB tOEH tOE tOES OE tDH tOHZ tOH tOLZ DQ Write Data Input Read Data Output Note : CE1r can be tied to Low for WE and OE controlled operation. When CE1r is tied to Low, output is exclusively controlled by OE. 45 MB84VD23381FJ-80 • POWER DOWN Timing (FCRAM) CE1r tCHS CE2r tCSP tC2LP tCHH High-Z DQ Power Down Entry Power Down Mode Power Down Exit • POWER-UP Timing 1 (FCRAM) CE1r tCHS tC2LH tCHH * CE2r VCCr VCCr Min 0V * : It is recommended CE2r to kept at Low during VCCr power-up. The tC2LH specifies after VCCr reaches specified minimum level. • POWER-UP Timing 2 (FCRAM) CE1r tCHS tC2HL tCSP tC2LP tCHH CE2r tC2HL VCCr VCCr Min 0V * : The tC2LH specifies from CE2r Low to High transition after VCCr reaches specified minimum level. CE1r must be brought to High prior to or together with CE2r Low to High transition. 46 MB84VD23381FJ-80 • Standby Entry Timing after Read or Write (FCRAM) CE1r tCHOX tCHWX OE WE Active (Read) Standby Active (Write) Standby Note : Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes tRC (Min) period from either last address transition of A0 and A1, or CE1r Low to High transition. 47 MB84VD23381FJ-80 ■ DATA RETENTION CHARACTERISTICS (FCRAM) Parameter Symbol Value Conditions Max Unit VDR CE1r = CE2r ≥ VCCr − 0.2 V or, CE1r = CE2r = VIH, 2.1 3.1 V IDR 2.3 V ≤ VCCr ≤ 2.7 V, VIN = VIH*or VIL, CE1r = CE2r = VIH*, IOUT = 0 mA 1 mA IDR1 2.3 V ≤ VCCr ≤ 2.7 V, VIN ≤ 0.2 V or VIN ≥ VCCr − 0.2 V, CE1r = CE2r ≥ VCCr − 0.2 V, IOUT = 0 mA 70 µA Data Retention Setup Time tDRS 2.7 V ≤ VCCr ≤ 3.1 V at data retention entry 0 ns Data Retention Recovery Time tDRR 2.7 V ≤ VCCr ≤ 3.1 V after data retention 90 ns 0.5 V/µs VCCr Data Retention Supply Voltage VCCr Data Retention Supply Current ∆V/∆t VCCr Voltage Transition Time *: 2.0 V ≤ VIH ≤ VCCr + 0.3 V • Data Retention Timing (FCRAM) tDRS tDRR 3.1 V VCCr ∆V/∆t ∆V/∆t 2.7 V CE2r 2.1 V CE1r CE1r= CE2r > VCCr-0.2 V or VIH* Min 0.4 V VSS Data Retention Mode Data bus must be in High-Z at data retention entry. *: 2.0 V ≤ VIH ≤ VCCr + 0.3 V 48 Min MB84VD23381FJ-80 ■ ERASE AND PROGRAMMING PERFORMANCE (Flash) Value Parameter Unit Remarks Min Typ Max Sector Erase Time — 0.5 2 s Excludes programming time prior to erasure Word Programming Time — 6 100 µs Excludes system-level overhead Chip Programming Time — 25.2 95 s Excludes system-level overhead 100,000 — — cycle Erase/Program Cycle Note : Typical Erase conditions TA = +25°C, VCCf_1 & VCCf_2 = 2.9V Typical Program conditions TA = +25°C, VCCf_1 & VCCf_2 = 2.9V Data= Checker ■ PIN CAPACITANCE Parameter Input Capacitance Symbol CIN Test Setup Value Unit Typ Max VIN = 0 11 14 pF Output Capacitance COUT VOUT = 0 12 16 pF Control Pin Capacitance CIN2 VIN = 0 14 16 pF WP/ACC Pin Capacitance CIN3 VIN = 0 21.5 26 pF Note : Test conditions TA = +25 °C, f = 1.0 MHz ■ HANDLING OF PACKAGE Please handle this package carefully since the sides of package create acute angles. ■ CAUTION • The high voltage (VID) cannot apply to address pins and control pins except RESET. Exception is when autoselect and sector group protect function are used, then the high voltage (VID) can be applied to RESET. • Without the high voltage (VID) , sector group protection can be achieved by using “Extended Sector Group Protection” command. 49 MB84VD23381FJ-80 ■ ORDERING INFORMATION MB84VD23381 FJ -80 PBS PACKAGE TYPE PBS = 65-ball FBGA SPEED OPTION See Product Selector Guide Device Revision DEVICE NUMBER/DESCRIPTION 64 Mega-bit (4 M × 16-bit) Dual Operation Flash Memory 3.0 V-only Read, Program, and Erase 16 Mega-bit (1 M × 16-bit) FCRAM 50 MB84VD23381FJ-80 ■ APPENDIX A • ISB2r vs. VIN Cycle Time ISB2r vs. VIN Cycle time (VCCr = 3.0V) 2.5 : RT = +25ooC : LT = −25 oC : HT = +85 C ISB2r [mA] 2.0 1.5 1.0 0.5 0.0 0 200 400 600 800 1000 VIN Cycle time [ns] 51 MB84VD23381FJ-80 ■ PACKAGE DIMENSION 65-ball plastic FBGA (BGA-65P-M01) 9.00±0.10(.354±.004) 0.20(.008) S B +0.15 1.19 –0.10 (Seated height) +.006 .047 –.004 0.39±0.10 (Stand off) (.015±.004) B 0.40(.016) REF 0.80(.031) REF 10 0.80(.031) REF 9 8 7 6 5 4 3 2 1 A 9.00±0.10 (.354±.004) 0.40(.016) REF 0.10(.004) S K J H G F E D C B A INDEX BALL INDEX-MARK AREA 0.20(.008) S A S +0.10 65-Ø0.45 –0.05 +.004 0.08(.003) M S A B 65-Ø.018 –.002 0.10(.004) S C 2001 FUJITSU LIMITED B65001S-c-1-2 Dimensions in mm (inches). Note: The values in parentheses are reference values. 52 MB84VD23381FJ-80 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0307 FUJITSU LIMITED Printed in Japan