TECHNICAL DATA KK74HC123A Dual Retriggerable Monostable Multivibrator The KK74HC123A is identical in pinout to the LS/ALS123. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. There are two trigger inputs, A INPUT (negative edge) and B INPUT (positive edge). These inputs are valid for rising/falling signals. The device may also be triggered by using the CLR input (positiveedge) because of the Schmitt-trigger input; after triggering the output maintains the MONOSTABLE state for the time period determined by the external resistor RX and capacitor CX. Taking CLR low breaks this MONOSTABLE STATE. If the next trigger pulse occurs during the MONOSTABLE period it makes the MONOSTABLE period longer. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 3.0 to 6.0 V • Low Input Current: 1.0 µA • High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION KK74HC123AN Plastic KK74HC123AD SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE PIN 16 =VCC PIN 8 = GND Note (1) CX, RX, DX are external components. (2) DX is a clamping diode. The external capacitor is charged to VCC in the stand-by state, i.e. no trigger. When the supply voltage is turned off CX is discharged mainly through an internal parasitic diode. If CX is sufficiently large and VCC decreases rapidy, there will be some possibility of damaging the I.C. with a surge current or latch-up. If the voltage supply filter capacitor is large enough and VCC decrease slowly, the surge current is automatically limited and damage the I.C. is avoided. The maximum forward current of the parasitic diode is approximately 20 mA. Inputs A X H Outputs B CLR H H L H L* H* Inhibit H * * Inhibit X L Q Note Q Output Enable L H H L H X X Output Enable Output Enable L L H Inhibit X = don’t care * - except for monostable period 1 KK74HC123A MAXIMUM RATINGS* Symbol Parameter Value Unit -0.5 to +7.0 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V ±20 ±30 mA VOUT IIN DC Input Current, per Pin A, B, CLR CX, RX IOUT DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±50 mA PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750 500 mW -65 to +150 °C 260 °C Tstg TL Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT Parameter Min DC Supply Voltage (Referenced to GND) Operating Temperature, All Package Types tr, tf Input Rise and Fall Time - CLR (Figure 2) VCC =2.0 V VCC =4.5 V VCC =6.0 V A or B ** RX External Timing Resistor CX External Timing Capacitor Unit 6.0 V 0 VCC V -55 +125 °C 0 0 0 1000 500 400 ns - No Limit 10 2.0 1000 1000 kΩ 0 No Limit µF 3.0 DC Input Voltage, Output Voltage (Referenced to GND) TA Max VCC <4.5 V VCC ≥ 4.5 V ** The In74HC123 will function at 2.0 V but for optimum pulse width stability, VCC should be above 3.0 V. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 KK74HC123A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol Parameter Test Conditions Guaranteed Limit V 25 °C to -55°C ≤85 °C ≤125 °C Unit VIH Minimum HighLevel Input Voltage VOUT=0.1 V or VCC-0.1 V ⎢IOUT⎢≤ 20 µA 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V VIL Maximum Low Level Input Voltage VOUT=0.1 V or VCC-0.1 V ⎢IOUT⎢ ≤ 20 µA 2.0 4.5 6.0 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 V VOH Minimum HighLevel Output Voltage VIN=VIH or VIL ⎢IOUT⎢ ≤ 20 µA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 VIN=VIH or VIL ⎢IOUT⎢ ≤ 4.0 mA ⎢IOUT⎢ ≤ 5.2 mA 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 VIN=VIH or VIL ⎢IOUT⎢ ≤ 4.0 mA ⎢IOUT⎢ ≤ 5.2 mA VOL Maximum LowLevel Output Voltage VIN=VIH or VIL ⎢IOUT⎢ ≤ 20 µA V IIN Maximum Input Leakage Current (A, B, CLR) VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA IIN Maximum Input Leakage Current (RX, CX) VIN=VCC or GND 6.0 ±50 ±500 ±500 nA ICC Maximum Quiescent Supply Current (per Package) Standby State VIN=VCC or GND Q1 and Q2 = Low IOUT=0µA 6.0 130 220 350 µA 25°C -45°C to 85°C -55°C to 125°C 400 600 800 ICC Maximum Supply Current (per Package) Active State VIN=VCC or GND Q1 and Q2 = High IOUT=0µA Pins 15 and 7 = 0.5 VCC 6.0 µA 3 KK74HC123A AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=6.0 ns) Guaranteed Limit VCC Symbol Parameter V 25 °C to -55°C ≤85 °C ≤125 °C Unit tPLH, tPHL Maximum Propagation Delay, Input A or B to Q or Q (Figures 1 and 3) 2.0 4.5 6.0 255 50 45 320 65 55 385 75 65 ns tPLH, tPHL Maximum Propagation Delay , CLR to Q or Q (Figures 2 and 3) 2.0 4.5 6.0 215 45 35 270 55 45 325 65 55 ns tTLH, tTHL Maximum Output Transition Time, Any Output(Figures 2 and 3) 2.0 4.5 6.0 75 16 14 95 20 17 110 22 20 ns - 10 25 10 25 10 25 pF CIN Maximum Input Capacitance A, B, CLR CX, RX Power Dissipation Capacitance (Per Multivibrator) CPD Typical @25°C,VCC=5.0 V Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC 150 pF TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns) VCC Guaranteed Limit Symbol Parameter V 25 °C to -55°C ≤85°C ≤125°C Unit trec Minimum Recovery Time, Inactive to A or B (Figure 2) 2.0 4.5 6.0 0 0 0 0 0 0 0 0 0 ns tw Minimum Pulse Width, Input A or B (Figure 1) 2.0 4.5 6.0 100 20 17 125 25 20 150 30 25 ns tw Minimum Pulse Width, CLR (Figure 2) 2.0 4.5 6.0 100 20 17 125 25 20 150 30 25 ns tr, tr Maximum Input Rise and Fall Times, CLR (Figure 2) 2.0 4.5 6.0 1000 500 400 1000 500 400 1000 500 400 ns A or B (Figure 2) 2.0 4.5 6.0 No Limit 4 KK74HC123A Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Test Circuit 5 KK74HC123A TIMING DIAGRAM EXPANDED LOGIC DIAGRAM 6 KK74HC123A N SUFFIX PLASTIC DIP (MS - 001BB) A Dimension, mm 9 16 Symbol MIN MAX A 18.67 19.69 B 6.1 7.11 B 1 8 5.33 C F L C D 0.36 0.56 F 1.14 1.78 G 2.54 H 7.62 -T- SEATING PLANE N G K M H D J 0.25 (0.010) M T NOTES: 1. Dimensions “A”, “B” do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side. J 0° 10° K 2.92 3.81 L 7.62 8.26 M 0.2 0.36 N 0.38 D SUFFIX SOIC (MS - 012AC) Dimension, mm A 16 9 H B 1 G P 8 R x 45 C -TK D SEATING PLANE J 0.25 (0.010) M T C M NOTES: 1. Dimensions A and B do not include mold flash or protrusion. 2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B ‑ 0.25 mm (0.010) per side. F M Symbol MIN MAX A 9.8 10 B 3.8 4 C 1.35 1.75 D 0.33 0.51 F 0.4 1.27 G 1.27 H 5.72 J 0° 8° K 0.1 0.25 M 0.19 0.25 P 5.8 6.2 R 0.25 0.5 7