TECHNICAL DATA KK74HC573A Octal 3-State Noninverting Transparent Latch High-Performance Silicon-Gate CMOS N SUFFIX PLASTIC DIP The KK74HC573A is identical in pinout to the LS/ALS573. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. These latches appear transparent to data (i.e., the outputs change asynchronously) when LE is high. When LE goes low, data meeting the setup and hold time becomes latched. • • • • Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 µA High Noise Immunity Characteristic of CMOS Devices 20 1 DW SUFFIX SOIC 20 1 ORDERING INFORMATION Plastic DIP SOIC KK74HC573AN KK74HC573ADW TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM 1 20 V CC D0 2 19 Q0 2 19 Q0 D1 3 18 Q1 D1 3 18 Q1 D2 4 17 Q2 D2 4 17 Q2 D3 5 16 Q3 D3 5 16 Q3 D4 6 15 Q4 D4 6 15 Q4 D5 7 14 Q5 D5 7 14 Q5 D6 8 13 Q6 D6 8 13 Q6 9 D7 9 12 Q7 D7 12 Q7 GND 10 11 LE D0 DATA INPUTS OE LE OE NONINVERTING OUTPUTS 11 FUNCTION TABLE 1 Inputs PIN 20=VCC PIN 10 = GND Output OE LE D Q L H H H L H L L L L X no change H X X Z H= high level L = low level X = don’t care Z = high impedance 1 KK74HC573A MAXIMUM RATINGS* Symbol Parameter Value Unit -0.5 to +7.0 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Input Current, per Pin ±20 mA IOUT DC Output Current, per Pin ±35 mA ICC DC Supply Current, VCC and GND Pins ±75 mA PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750 500 mW -65 to +150 °C 260 °C VOUT IIN Tstg TL Storage Temperature Lead Temperature, 1.5 mm from Case for 4 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min Max Unit 2.0 6.0 V 0 VCC V -55 +125 °C 0 0 0 1000 500 400 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 KK74HC573A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VC Guaranteed Limit C Symbol Parameter Test Conditions V 25 °C to -55°C ≤85 °C ≤125 °C Unit VIH Minimum High-Level Input Voltage VOUT ≥ VCC-0.1 V ⎢IOUT⎢≤ 20 µA 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V VIL Maximum Low -Level Input Voltage VOUT⎢ ≤ 0.1 V ⎢IOUT⎢ ≤ 20 µA 2.0 4.5 6.0 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 V VOH Minimum High-Level Output Voltage VIN=VIH ⎢IOUT⎢ ≤ 20 µA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 VIN= VIL ⎢IOUT⎢ ≤ 6.0 mA ⎢IOUT⎢ ≤7.8 mA 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 VIN=VIH ⎢IOUT⎢ ≤ 6.0 mA ⎢IOUT⎢ ≤ 7.8 mA VOL Maximum Low-Level Output Voltage VIN= VIL ⎢IOUT⎢ ≤ 20 µA V IIN Maximum Input Leakage Current VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA IOZ Maximum Three State Leakage Current Output in High-Impedance State VIN =VIH VOUT= VCC or GND 6.0 ±0.5 ±5.0 ±10 µA ICC Maximum Quiescent Supply Current (per Package) VIN=VCC or GND IOUT=0µA 6.0 4.0 40 160 µA 3 KK74HC573A AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns) VCC Symbol Parameter Guaranteed Limit V 25 °C to -55°C ≤85°C ≤125°C Unit tPLH, tPHL Maximum Propagation Delay, Input D to Q (Figures 1 and 5) 2.0 4.5 6.0 150 30 26 190 38 33 225 45 38 ns tPLH, tPHL Maximum Propagation Delay, LE to Q (Figures 2 and 5) 2.0 4.5 6.0 160 32 27 200 40 34 240 48 41 ns tPLZ, tPHZ Maximum Propagation Delay, OE to Q (Figures 3 and 6) 2.0 4.5 6.0 150 30 26 190 38 33 225 45 38 ns tPZH, tPZL Maximum Propagation Delay, OE to Q (Figures 3 and 6) 2.0 4.5 6.0 150 30 26 190 38 33 225 45 38 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 5) 2.0 4.5 6.0 60 12 10 75 15 13 90 18 15 ns Maximum Input Capacitance - 10 10 10 pF Maximum Three-State Output Capacitance (Output in High-Impedance State) - 15 15 15 pF CIN COUT CPD Power Dissipation Capacitance (Per Enabled Output) Typical @25°C,VCC=5.0 V Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC 23 pF TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns) Guaranteed Limit VCC Symbol Parameter V 25 °C to -55°C ≤85°C ≤125°C Unit tSU Minimum Setup Time, Input D to Latch Enable (Figure 4) 2.0 4.5 6.0 50 10 9 65 13 11 75 15 13 ns th Minimum Hold Time, Latch Enable to Input D (Figure 4) 2.0 4.5 6.0 5 5 5 5 5 5 5 5 5 ns tw Minimum Pulse Width, Latch Enable (Figure 2) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns tr, tf Maximum Input Rise and Fall Times (Figure 1) 2.0 4.5 6.0 1000 500 400 1000 500 400 1000 500 400 ns 4 KK74HC573A tr D tf LE VCC 90% 50% 10% 0В tw 0В tPLH VCC 50% t PHL Q 50% 10% t PLH t PHL 90% Q t TLH 50% t THL Figure 1. Switching Waveforms Figure 2. Switching Waveforms VCC 50% OE t PZL 0В t PLZ Q 50% 10% t PHZ t PZH Q 90% 50% D HIGH IMPEDANCE VOL 0В th t su VOH VCC 50% LE 0В HIGH IMPEDANCE Figure 3. Switching Waveforms Figure 4. Switching Waveforms * Includes all probe and jig capacitance * Includes all probe and jig capacitance TEST POINT DEVICE UNDER TEST VCC 50% TEST POINT OUTPUT DEVICE UNDER TEST * CL Connect to V CC when testing tPLZ and tPZL Connect to GND when testing tPHZ and tPZH 1k OUTPUT * CL Figure 5. Test Circuit Figure 6. Test Circuit EXPANDED LOGIC DIAGRAM D0 D1 D D2 D LE Q D3 D LE Q D4 D LE Q D5 D LE Q D6 D LE Q D7 D LE Q D LE Q LE Q LE OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 5 KK74HC573A N SUFFIX PLASTIC DIP (MS - 001AD) A Dimension, mm 11 20 B 1 10 Symbol MIN MAX A 24.89 26.92 B 6.1 7.11 5.33 C F L C -T- SEATING PLANE N D 0.36 0.56 F 1.14 1.78 G 2.54 H 7.62 J 0° 10° K 2.92 3.81 0.25 (0.010) M T L 7.62 8.26 1. Dimensions “A”, “B” do not include mold flash or protrusions. M 0.2 0.36 N 0.38 G K M H D NOTES: J Maximum mold flash or protrusions 0.25 mm (0.010) per side. D SUFFIX SOIC (MS - 013AC) A 20 11 H Dimension, mm B 1 P 10 G R x 45 C -TK D SEATING PLANE J 0.25 (0.010) M T C M F M Symbol MIN MAX A 12.6 13 B 7.4 7.6 C 2.35 2.65 D 0.33 0.51 F 0.4 1.27 G 1.27 H 9.53 J 0° 8° 1. Dimensions A and B do not include mold flash or protrusion. K 0.1 0.3 2. Maximum mold flash or protrusion 0.15 mm (0.006) per side M 0.23 0.32 P 10 10.65 R 0.25 0.75 NOTES: for A; for B ‑ 0.25 mm (0.010) per side. 6