KODENSHI KK74HCT373A

TECHNICAL DATA
KK74HCT373A
Octal 3-State Noninverting
Transparent Latch
The KK74HCT373A may be used as a level converter for interfacing
TTL or NMOS outputs to High-Speed CMOS inputs.
The KK74HCT373A is identical in pinout to the LS/ALS373.
The eight latches of the KK74HCT373A are transparent D-type latches.
While the Latch Enable is high the Q outputs follow the Data Inputs.
When Latch Enable is taken low, data meeting the setup and hold times
becomes latched.
The Output Enable does not affect the state of the latch, but when
Output Enable is high, all outputs are forced to the high-impedance state.
Thus, data may be latched even when the outputs are not enabled.
• TTL/NMOS-Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
ORDERING INFORMATION
KK74HCT373AN Plastic
KK74HCT373ADW SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
PIN 20=VCC
PIN 10 = GND
Output
Output
Enable
Latch
Enable
D
Q
L
H
H
H
L
H
L
L
L
L
X
No Change
H
X
X
Z
X = Don’t Care
Z = High Impedance
1
KK74HCT373A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
-0.5 to +7.0
V
VCC
DC Supply Voltage (Referenced to GND)
VIN
DC Input Voltage (Referenced to GND)
-1.5 to VCC +1.5
V
DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
DC Input Current, per Pin
±20
mA
IOUT
DC Output Current, per Pin
±35
mA
ICC
DC Supply Current, VCC and GND Pins
±75
mA
PD
Power Dissipation in Still Air, Plastic DIP**
SOIC Package**
750
500
mW
-65 to +150
°C
260
°C
VOUT
IIN
Tstg
TL
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
**Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIN, VOUT
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Figure 1)
Min
Max
Unit
4.5
5.5
V
0
VCC
V
-55
+125
°C
0
500
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or
VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
2
KK74HCT373A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
Symbol
Parameter
Test Conditions
Guaranteed Limit
V
25 °C
to
-55°C
≤85
°C
≤125
°C
Unit
VIH
Minimum HighLevel Input Voltage
VOUT=0.1 V or VCC-0.1 V
⎢IOUT⎢≤ 20 µA
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VIL
Maximum Low Level Input Voltage
VOUT=0.1 V or VCC-0.1 V
⎢IOUT⎢ ≤ 20 µA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOH
Minimum HighLevel Output Voltage
VIN=VIH or VIL
⎢IOUT⎢ ≤ 20 µA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
VIN=VIH or VIL
⎢IOUT⎢ ≤ 6.0 mA
4.5
3.98
3.84
3.7
VIN= VIL or VIH
⎢IOUT⎢ ≤ 20 µA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
VIN= VIL or VIH
⎢IOUT⎢ ≤ 6.0 mA
4.5
0.26
0.33
0.4
VOL
Maximum LowLevel Output Voltage
V
IIN
Maximum Input
Leakage Current
VIN=VCC or GND
5.5
±0.1
±1.0
±1.0
µA
IOZ
Maximum ThreeState Leakage
Current
Output in High-Impedance
State
VIN= VIL or VIH
VOUT=VCC or GND
5.5
±0.5
±5.0
±10
µA
ICC
Maximum Quiescent
Supply Current
(per Package)
VIN=VCC or GND
IOUT=0µA
5.5
4.0
40
160
µA
∆ICC
Additional Quiescent
Supply Current
VIN=2.4 V, Any One Input
VIN=VCC or GND,
Other Inputs
≥-55°C
25°C to
125°C
mA
2.9
2.4
IOUT=0µA
5.5
3
KK74HCT373A
AC ELECTRICAL CHARACTERISTICS (VCC =5.0 V ± 10%, CL=50pF, tr=tf=6.0 ns)
Guaranteed Limit
Symbol
Parameter
25 °C
to
-55°C
≤85°C
≤125°C
Unit
tPLH, tPHL
Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
28
35
42
ns
tPLH, tPHL
Maximum Propagation Delay , Latch Enable to Q
(Figures 2 and 5)
32
40
48
ns
tPLZ, tPHZ
Maximum Propagation Delay ,Output Enable to
Q (Figures 3 and 6)
30
38
45
ns
tPZL, tPZH
Maximum Propagation Delay , Output Enable to
Q (Figures 3 and 6)
35
44
53
ns
tTLH, tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
12
15
18
ns
Maximum Input Capacitance
10
10
10
pF
Maximum Three-State Output Capacitance
(Output in High-Impedance State)
15
15
15
pF
CIN
COUT
Power Dissipation Capacitance (Per Latch)
TA=25°C,VCC=5.0 V
CPD
Used to determine the no-load dynamic power
consumption:
PD=CPDVCC2f+ICCVCC
65
pF
tSU
Minimum Setup Time, Input D to Latch Enable
(Figure 4)
10
13
15
ns
th
Minimum Hold Time,Latch Enable to Input D
(Figure 4)
10
13
15
ns
tw
Minimum Pulse Width, Latch Enable (Figure 2)
12
15
18
ns
tr, tf
Maximum Input Rise and Fall Times (Figure 1)
500
500
500
ns
4
KK74HCT373A
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Switching Waveforms
Figure 5. Test Circuit
Figure 6. Test Circuit
EXPANDED LOGIC DIAGRAM
5
KK74HCT373A
N SUFFIX PLASTIC DIP
(MS - 001AD)
A
Dimension, mm
11
20
B
1
10
Symbol
MIN
MAX
A
24.89
26.92
B
6.1
7.11
5.33
C
F
L
C
-T- SEATING
PLANE
D
0.36
0.56
F
1.14
1.78
G
2.54
H
7.62
N
G
K
M
J
H
D
0.25 (0.010) M T
NOTES:
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
J
0°
10°
K
2.92
3.81
L
7.62
8.26
M
0.2
0.36
N
0.38
D SUFFIX SOIC
(MS - 013AC)
A
20
11
H
Dimension, mm
B
1
P
10
G
R x 45
C
-TK
D
SEATING
PLANE
J
0.25 (0.010) M T C M
NOTES:
1. Dimensions A and B do not include mold flash or protrusion.
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
for A; for B ‑ 0.25 mm (0.010) per side.
F
M
Symbol
MIN
MAX
A
12.6
13
B
7.4
7.6
C
2.35
2.65
D
0.33
0.51
F
0.4
1.27
G
1.27
H
9.53
J
0°
8°
K
0.1
0.3
M
0.23
0.32
P
10
10.65
R
0.25
0.75
6