TECHNICAL DATA KK74HCT163A Presettable Counters High-Performance Silicon-Gate CMOS The KK74HCT163A is identical in pinout to the LS/ALS163. The KK74HCT163 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. The KK74HCT163A is programmable 4-bit synchronous counter that feature parallel Load, synchronous Reset, a Carry Output for cascading and count-enable controls. The KK74HCT163A is binary counter with synchronous Reset. • TTL/NMOS Compatible Input Levels • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 4.5 to 5.5 V • Low Input Current: 1.0 µA ORDERING INFORMATION KK74HCT163AN Plastic KK74HCT163AD SOIC TA = -55° to 125° C for all packages LOGIC DIAGRAM PIN ASSIGNMENT PIN 16 =VCC PIN 8 = GND FUNCTION TABLE Inputs Outputs Reset Load Enable P Enable T L X X H L H Clock Q0 Q1 Q2 Q3 Function X L L L L Reset to “0” X X P0 P1 P2 P3 Preset Data H X L No change No count H H L X No change No count H H H H Count up Count X X X X No change No count X=don’t care P0,P1,P2,P3 = logic level of Data inputs Ripple Carry Out = Enable T • Q0 • Q1 • Q2 • Q3 1 KK74HCT163A MAXIMUM RATINGS* Symbol Parameter Value Unit -0.5 to +7.0 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Input Current, per Pin ±20 mA IOUT DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±50 mA PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750 500 mW -65 to +150 °C 260 °C VOUT IIN Tstg TL Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) Min Max Unit 4.5 5.5 V 0 VCC V -55 +125 °C 0 500 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 KK74HCT163A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol Parameter Test Conditions Guaranteed Limit V 25 °C to -55°C ≤85 °C ≤125 °C Unit VIH Minimum HighLevel Input Voltage VOUT=0.1 V or VCC-0.1 V ⎢IOUT⎢≤ 20 µA 4.5 5.5 2.0 2.0 2.0 2.0 2.0 2.0 V VIL Maximum Low Level Input Voltage VOUT=0.1 V or VCC-0.1 V ⎢IOUT⎢ ≤ 20 µA 4.5 5.5 0.8 0.8 0.8 0.8 0.8 0.8 V VOH Minimum HighLevel Output Voltage VIN=VIH or VIL ⎢IOUT⎢ ≤ 20 µA 4.5 5.5 4.4 5.4 4.4 5.4 4.4 5.4 V VIN=VIH or VIL ⎢IOUT⎢ ≤ 6.0 mA 4.5 3.98 3.84 3.7 VIN=VIH or VIL ⎢IOUT⎢ ≤ 20 µA 4.5 5.5 0.1 0.1 0.1 0.1 0.1 0.1 VIN=VIH or VIL ⎢IOUT⎢ ≤ 6.0 mA 4.5 0.26 0.33 0.4 VOL Maximum LowLevel Output Voltage V IIN Maximum Input Leakage Current VIN=VCC or GND 5.5 ±0.1 ±1.0 ±1.0 µA ICC Maximum Quiescent Supply Current (per Package) VIN=VCC or GND IOUT=0µA 5.5 4.0 40 160 µA ∆ICC Additional Quiescent Supply Current VIN = 2.4 V, Any One Input VIN=VCC or GND, Other Inputs ≥-55°C 25°C to 125°C mA 2.9 2.4 IOUT=0µA 5.5 3 KK74HCT163A AC ELECTRICAL CHARACTERISTICS (VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns) Guaranteed Limit Symbol Parameter 25 °C to -55°C ≤85°C ≤125°C Unit fmax Maximum Clock Frequency (Figures 1,6) 30 24 20 MHz tPLH Maximum Propagation Delay, Clock to Q 34 43 51 ns tPHL (Figures 1,6) 41 51 62 ns tPLH Maximum Propagation Delay, Enable T to Ripple Carry Out (Figures 2,6) 32 40 48 ns 39 49 59 ns tPHL tPLH Maximum Propagation Delay, Clock to Ripple 35 44 53 ns tPHL Carry Out (Figures 1,6) 43 54 65 ns Maximum Output Transition Time, Any Output, (Figures 1 and 6) 15 19 22 ns Maximum Input Capacitance 10 10 10 pF tTLH, tTHL CIN Power Dissipation Capacitance (Per Gate) CPD Typical @25°C,VCC=5.0 V Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC+∆ICCVCC 60 pF TIMING REQUIREMENTS (VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns) Guaranteed Limit Symbol Parameter 25 °C to -55°C ≤85°C ≤125°C Unit tsu Minimum Setup Time, Preset Data Inputs to Clock (Figure 4) 30 38 45 ns tsu Minimum Setup Time, Load to Clock (Figure 4) 27 34 41 ns tsu Minimum Setup Time, Reset to Clock (Figure 3) 32 40 48 ns tsu Minimum Setup Time, Enable T or Enable P to Clock (Figure 5) 40 50 60 ns th Minimum Hold Time, Clock to Preset Data Inputs (Figure 4) 10 13 15 ns th Minimum Hold Time, Clock to Load (Figure 4) 3 3 3 ns th Minimum Hold Time, Clock to Reset (Figure 3) 3 3 3 ns th Minimum Hold Time, Clock to Enable T or Enable P (Figure 5) 3 3 3 ns trec Minimum Recovery Time, Load Inactive to Clock (Figure 4) 25 31 38 ns tw Minimum Pulse Width, Clock (Figure 1) 16 20 24 ns tw Minimum Pulse Width, Reset (Figure 4) 16 20 24 ns tr, tf Maximum Input Rise and Fall Times (Figure 1) 500 500 500 ns 4 KK74HCT163A Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Switching Waveforms Figure 5. Switching Waveforms Figure 6. Test Circuit 5 KK74HCT163A VCC=Pin 16 GND=Pin 8 The flip-flops shown in the circuit diagrams are Toggle-Enable flip-flops. A Toggle-Enable flip-flop is a combination of a D flip-flop and a T flip-flop. When loading data from Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of the flip-flop. The logic level at the Pn input is then clocked to the Q output of the flip-flop on the next rising edge of the clock. A logic zero on the Reset device input forces the internal clock (C) high and resets the Q output of the flip-flop low. Figure 7.Expanded logic diagram 6 KK74HCT163A Sequence illustrated in waveforms: 1. Reset outputs to zero. 2. Preset to binary twelve. 3. Count to thirteen, fourteen, fifteen, zero, one, and two. 4. Inhibit. Figure 8. Timing Diagram 7 KK74HCT163A TYPICAL APPLICATIONS CASCADING Note:When used in these cascaded configurations the clock fmax guaranteed limits may not apply. Actual performance will depend on number of stages. This limitation is due to set up times between Enable (Port) and clock. Figure 9. N-Bit Synchronous Counters Figure 10. Nibble Ripple Counter 8 KK74HCT163A N SUFFIX PLASTIC DIP (MS - 001BB) A Dimension, mm 9 16 Symbol MIN MAX A 18.67 19.69 B 6.1 7.11 B 1 8 5.33 C F L C D 0.36 0.56 F 1.14 1.78 G 2.54 H 7.62 -T- SEATING PLANE N G K M H D J 0.25 (0.010) M T NOTES: 1. Dimensions “A”, “B” do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side. J 0° 10° K 2.92 3.81 L 7.62 8.26 M 0.2 0.36 N 0.38 D SUFFIX SOIC (MS - 012AC) Dimension, mm A 16 9 H B 1 G P 8 R x 45 C -TK D SEATING PLANE J 0.25 (0.010) M T C M NOTES: 1. Dimensions A and B do not include mold flash or protrusion. 2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B ‑ 0.25 mm (0.010) per side. F M Symbol MIN MAX A 9.8 10 B 3.8 4 C 1.35 1.75 D 0.33 0.51 F 0.4 1.27 G 1.27 H 5.72 J 0° 8° K 0.1 0.25 M 0.19 0.25 P 5.8 6.2 R 0.25 0.5 9