DA9187.002 29 January, 2004 MAS9187 12 X 8-bit D to A Converter • 3-pin Serial Data Interface • Low Voltage Output Buffer DESCRIPTION MAS9187 is 12-channel 8-bit DAC, designed primarily for trimmer replacement. Device is controlled by a simple 3-line input. The output buffers operate in the entire voltage range from ground to the positive power supply rail. FEATURES • • • • • DAC is selected with four first bits in serial input data (SDI-pin) and the DAC output value is set according to the last 8 bits in serial input data. APPLICATIONS Twelve 8-bit DACs on a single monolithic chip Voltage level output TSSOP 20 package Single, low +1.8 V supply Power-on reset • • • High resolution monitors Automatic gain control Trimmer replacement BLOCK DIAGRAM SDI CLK 12-bit Shift Register 8-bit data 8-BIT DAC O12 8-BIT DAC O10 O11 8-BIT DAC O9 8-BIT DAC 8-BIT DAC XCS Address Decoder 8-BIT DAC 8-BIT DAC 8-BIT DAC VDD O4 O3 8-BIT DAC VREFHVREFL O6 O5 8-BIT DAC 8-BIT DAC O8 O7 8-BIT DAC O2 O1 GND 1 (7) DA9187.002 29 January, 2004 PIN CONFIGURATION VREFH O1 1 20 VDD 2 19 XRESET VREFH 1 O1 2 20 VDD O2 3 O3 4 18 O11 16 O9 18 O3 4 17 O12 O11 O4 5 16 O10 O5 O6 6 15 O9 14 O8 O4 5 O5 6 O6 7 XSHDN 8 13 O7 XSHDN 8 XCS 9 12 SDI XCS 9 GND 10 11 CLK GND 10 7 19 O12 17 O10 MAS9187A2 YYWW 3 MAS9187A1 YYWW O2 15 O8 14 O7 13 SDI 12 CLK 11 VREFL Top view YYWW = year, week PIN DESCRIPTION Pin Number MAS9187 A1 MAS9187 A2 Function 1 VREFH VREFH DAC output reference high voltage 2 O1 O1 DAC 1, address 0x0 3 O2 O2 DAC 2, address 0x1 4 O3 O3 DAC 3, address 0x2 5 O4 O4 DAC 4, address 0x3 6 O5 O5 DAC 5, address 0x4 7 O6 O6 DAC 6, address 0x5 8 XSHDN XSHDN Device analog part power-down signal (active low) 9 XCS XCS Device enable signal (rising edge loads data to DAC) 10 GND GND Device ground-pin 11 CLK VREFL Data clock / DAC output low reference voltage 12 SDI CLK Serial input data / Data clock 13 O7 SDI DAC 7, address 0x6 / Serial input data 14 O8 O7 DAC 8, address 0x7 / DAC 7, address 0x6 15 O9 O8 DAC 9, address 0x8 / DAC 8, address 0x7 16 O10 O9 DAC 10, address 0x9 / DAC 9, address 0x8 17 O11 O10 DAC 11, address 0xA / DAC 10, address 0x9 18 O12 O11 DAC 12, address 0xB / DAC 11, address 0xA 19 XRESET O12 Device Digital part reset – middle code preset pin/DAC 12, address 0xB 20 VDD VDD Device power supply pin MAS9187 has two bonding options available: • • MAS9187A1, where VREFL pin is bonded to GND pin and XRESET pin can be used MAS9187A2, where XRESET pin is bonded to VDD pin and VREFL pin can be used 2 (7) DA9187.002 29 January, 2004 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Power Supply (VDD to GND) Conditions VDD Input Voltage Range (any other pin) Min Max Unit -0.3 +6.0 V -0.3 VDD + 0.3 V 1000 mW +150 °C Continuous Power Dissipation Storage Temperature Range -65 RECOMMENDED OPERATION CONDITIONS Parameter Symbol Conditions Min Supply Voltage Range VDD 2.7 Operating Temperature Temp -40 Range Note 1: MAS9187Axx3 and MAS9187Axx4 minimum supply voltage 1.8 V Typ Max Unit Note 3.6 5.5 +85 V 1) °C ELECTRICAL CHARACTERISTICS (VDD = 3.0 V ± 10% or 5.0 V ± 10%, VREFH = VDD, VREFL = 0V, -40°C ≤ TA ≤ +85°C unless otherwise noted) DC Parameters ◆ Digital Inputs Parameter Symbol DAC Resolution Conditions Min N Typ Max 8 Unit Bits DAC Differential Nonlinearity Error DNL -1 +1 LSB DAC Integral Nonlinearity Error INL -1 +1 LSB DAC Full-scale Error GFSE -1 +1 LSB DAC Zero Code Error BZSE -1 +1 LSB DAC Output Resistance ROUT 60 Ω Max Unit 30 ◆ Reference Input Parameter Symbol Conditions Min REFH Voltage Range VREFH VREFH > VREFL 0 VDD REFL Voltage Range (MAS9187A2 only) VREFL VREFH > VREFL 0 VDD REFH Input Resistance RREFH REFL Input Resistance RREFL 5 Typ 10 kΩ 10 kΩ 3 (7) DA9187.002 29 January, 2004 ◆ Digital Input Parameter Symbol Conditions Min Typ Max Digital Logic High VIH Digital Logic Low VIL 0.3*VDD Digital Input Current IIL ±1 Unit 0.7*VDD uA ◆ Power Supplies Parameter Symbol Conditions Power Supply Range VDD Supply Current IDD VDD = 3.60V Supply Current IDD VDD = 5.50V Shutdown Current Min Typ 2.7 ISHDN Max Unit Note 5.5 V 1) 6 mA 20 mA 5 uA Typ Max 3 0.5 Note 1: MAS9187Axx3 and MAS9187Axx4 minimum supply voltage 1.8 V AC Parameters ◆ AC Characteristics Dynamic Performance Parameter Power Supply Sensitivity (100Hz) Symbol Conditions Min Unit PSRR 54 dB Vout Settling time (±1/2 LSB error band) TS 6 µs Crosstalk between adjacent outputs CT 63 dB Switching Characteristics o (Minimum values at +25 C, VDD = 3.60 V) Parameter Symbol Conditions Min Typ Max Unit Input Clock High Pulse Width TCH 16 ns Input Clock Low Pulse Width TCL 7 ns Data Setup Time TDS -5 ns Data Hold Time TDH 5 ns XCS Fall to First Clock Pulse Fall TCLCL 16 ns XCS High Pulse Width TCSW 22 ns TRS 28 ns CLK Rise to XCS Rise Hold Time TCSH 22 ns XCS Rise to CLOCK Rise Setup TCS1 -5 ns RESET Pulse Width 4 (7) DA9187.002 29 January, 2004 OPERATING MODES DAC maximum output voltage is set using VREFH and VREFL pins (= 255/256 * (VREFH-VREFL)+VREFL) (note: VREFL=GND in case of MAS9187A1). XRESET pin is used for middle code preset: DAC registers are reset and middle code will appear at the DAC output. Serial input data is written to SDI while XCS is low. Data is read at CLK rising edge to on-chip shift register. Rising XCS-pin stops data reading and 12 CLK-cycles are used as the input data (4 address bits and 8 data bits). The last 12 bits before rising XCS are used as input data. ◆ Timing diagram SDI A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 CLK XCS DAC Register Load VOUT APPLICATION AND TEST CIRCUIT INFORMATION +3.0v 20 VDD 1 VREFH MAS9187A2 8 XSHDN O12 Controller Clock Data In Latch 12 13 O11 CLK O10 O9 SDI O8 9 O7 XCS O6 16 15 14 7 6 5 O1 10 17 O4 O2 GND 18 O5 O3 100 nF 19 4 3 2 VREFL 11 5 (7) DA9187.002 29 January, 2004 PACKAGE (TSSOP-20) OUTLINES e/ 2 A VIEW B-B b E E1 c1 12° REF c S R b1 INDEX AREA GAUGE PLANE e A L 0.25 12° REF L1 D A A2 b B B A1 VIEW A-A b Symbol Min Nom Max Unit A A1 A2 b b1 c c1 D E E1 e L L1 R S -0.05 0.85 0.19 0.19 0.09 0.09 6.40 --0.90 -0.22 --6.50 6.4 BSC 4.40 0.65 BSC 0.60 1.00 REF -0.20 1.10 0.15 0.95 0.30 0.25 0.20 0.16 6.60 0.75 mm mm mm mm mm mm mm mm mm mm mm mm --- mm mm 4.30 0.50 0.09 -- 4.50 Dimensions do not include mold or interlead flash, protrusions or gate burrs. Reference Standard : JEDEC MO-153 . SOLDERING INFORMATION Resistance to Soldering Heat Maximum Temperature Maximum Number of Reflow Cycles Reflow profile Seating Plane Co-planarity Lead Finish According to RSH test IEC 68-2-58/20 2*220°C 240°C 2 Thermal profile parameters stated in JESD22-A113 should not be exceeded. http://www.jedec.org max 0.08 mm Solder plate 7.62 - 25.4 µm, material Sn 85% Pb 15% 6 (7) DA9187.002 29 January, 2004 ORDERING INFORMATION Product Code Product Package Comments MAS9187AUA1 MAS9187AUA2 MAS9187AUA3 MAS9187AUA4 12 x 8-bit D to A Converter 12 x 8-bit D to A Converter 12 x 8-bit D to A Converter 12 x 8-bit D to A Converter TSSOP-20 TSSOP-20 TSSOP-20 TSSOP-20 0 V Reference Level Scalable Reference Level 0 V Reference Level, VDD min 1.8 V Scalable Reference Level, VDD min 1.8 V LOCAL DISTRIBUTOR MICRO ANALOG SYSTEMS OY CONTACTS Micro Analog Systems Oy Kamreerintie 2, P.O. Box 51 FIN-02771 Espoo, FINLAND Tel. +358 9 80 521 Fax +358 9 805 3213 http://www.mas-oy.com NOTICE Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Micro Analog Systems Oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. 7 (7)