MAS MAS9191AJ-T

DA9191A.000
July 31, 1997
MAS9191A
Single Chip AMPS/ETACS/NAMPS Audio/Data Processor
•
•
•
•
Single chip solution for all audio and data processing
Low power consumption with several power down modes
SAT decoding and transponding circuitry
Simple 4-wire serial interface
DESCRIPTION
The MAS9191A is a high integration BeCMOS IC for
implementing the audio and data signal processing in
AMPS, ETACS or NAMPS cellular phones. The
power consumption of the device is very low due to
several automatic and software controlled power
down modes as well as the low power characteristics
of the BeCMOS process. DTMF receiver is also
included to enable answering machine functions for
the cellular phone. Only a minimal number of
external components are needed to meet typical
baseband requirements.
FEATURES
•
•
•
•
•
•
•
APPLICATIONS
•
•
Voice signal processing including compressor,
expander, de-emphasis and pre-emphasis filters
and digital gain adjustments
DTMF and ST generators and DTMF receiver
Busy/Idle extraction and arbitration with TX block,
voting, BCH, data buffering and framing, DCC
coding with hardware
Three 8-bit DACs and two operational amplifiers
On-chip oscillator with clock output for uP
3.3V or 5V operation with low power
consumption(RX block at 2mA/3.3V)
64-pin TQFP package, -40..85oC operation range
AMPS/ETACS Cellular phone
NAMPS Cellular phone
BLOCK DIAGRAM
AMPLIFIER
ANTI ALIASING
GAIN
CONTROL
LOWPASS
FI LTER
HIGHPASS
FI LTER
COMPRESSOR
GAIN
CONTROL
PRE-EMPHASIS
GAIN
CONTROL
LOWPASS
FILTER
LIMITER
GAIN
CONTROL
LOWPASS
FILTER
GAIN
CONTROL
LOWPASS
FILTER
MIC
TX
GAIN
CONTROL
TX
Buffer
DTMF
Genera tor
BCH
Coding
DCC
Conversion
Framing
STB
SRxD
BUSY / I DLE
SCL
Serial
Interface
STxD
Manchester
coding
SAT
Generation
SIGNALLING
TONE
LOWPASS
FILTER
AMPLIFIER
XSTAL1
XSTAL2
SYS1 (NAMPS)
COMPARATOR
3
8-bit
DACs
BANDPASS
FILTER
SAT
Detection
SYS1 (NAMPS)
RX
Buffer
AMPLIFIER
BCH
Decoding
Voting
Frame
Decoding
Manchester
Decoder
2 Utility
Operational
Amplifiers
COMPARATOR
SIDETONE
DPLL
AMPLIFIER
BUZZER
AMPLIFIER
SPEAKER
LO WPASS
FILTER
GAIN
CONTROL
LOWPASS
FILTER
EXPANDER
BANDPASS
FILTER
DE-EMPHASI S
DTMF
Receiver
LOWPASS
FI LTER
LOWPASS
FILTER
GAIN
CONTROL
RX
1
DA9191A.000
July 31, 1997
PIN CONFIGURATION
RX
ALP
TEST2
TEST1
CLKOUT
TXCTRL
VSS
XTAL2
XTAL1
VDD
49
50
51
52
53
54
55
56
57
58
59
60
61
VDAT
TXACCIN
TXON
BUSY
LPFIN
VSAT
62
63
64
TAUDOUT
TAUDIN
XINT
DACOUT3
DACOUT2
DACOUT1
AGND
TX
1
2
3
48 VREF
47 DEOUT
46 RBPFIN
4
5
45 RBPFOUT
44 VSAR
6
7
43 VDAR
42 EXPIN
8
TXACCOUT 9
PREIN
10
COUT
11
CAMP2I
12
CWCIN
CAMP20
COMPIN
MICOUT
41 EAMPOUT
40 EWCIN
39 EXPOUT
38 RXACCIN
13
37 RXACCOUT
36 RAUDIN
14
15
35 EST
34 STGT
16
33 EINR
32 SIDETONE
31 SIDEFB
30 EARP1
29 EARP2
28 EXTERP
27 BUZOUT
26 BUZFB
25 SRxD
24 STxD
23 STB
22 SCL
21 XRESET
20 EXTMIC
19 MICFB
18 MIC
17 MICSGND
TQFP64 package
PIN DESCRIPTION
Pin name
Pin
Type
AGND
1
AO
TX
2
AO
TAUDOUT
3
AO
TAUDIN
4
AI
LPFIN
5
AI
VSAT
6
G
VDAT
7
P
TXACCIN
8
AI
TXACCOUT
9
AO
PREIN
10
AI
COUT
11
AO
Function
Signal ground. The signal ground is generated internally and is equal to
VDD/2. The analog ground needs an external capacitor connected to
system ground.
Transmitted data signal output. Connect this output through a 22nF
capacitor to the transmitter.
TX audio output from the TX audio block..
TX audio input. The input for the TX audio signal, normally connected
through a 22nF capacitor to TAUDOUT
Input for TX limiter, lowpass filter or GC6 depending on the position of
switches S15 and S16. The pin is normally left unconnected.
Ground for TX. Connect to system ground.
Power supply for TX block. Use a bypass capacitor between pins VSAT
and VDAT.
TX block extra Op Amp input. See application note in the APPLICATIONS
section.
TX block Op Amp output.
Pre-emphasis filter input. Filter has a +6dB/octave (±1dB) frequency
response in the range 300Hz...3kHz.
Compressor output signal. The compression ratio is 2:1
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July 31, 1997
PIN DESCRIPTION
Pin name
Pin
Type
Function
CAMP2I
12
AI
CWCIN
13
AI
CAMP2O
14
AO
COMPIN
15
AI
MICOUT
16
AO
MICSGND
17
AO
MIC
18
AI
MICFB
19
AO
Compressor input. The input is connected through a 22nF capacitor to
MICOUT.
Microphone amplifier output. See COMPIN. This output is used as a
source for the side tone and for detection of the TX audio level.
Microphone signal ground. This is the internal signal ground VDD/2. If noise
appears on the microphone signal an external capacitor may be needed
between this pin and system ground.
Microphone amplifier input. Using this pin and the MICFB output the
microphone amplifier frequency response can be adjusted according to
the microphone used. The level at this input should be in the range
5..10mVrms. The maximum gain of the microphone amplifier is 30 dB.
Microphone amplifier feedback output
EXTMIC
20
AI
External microphone input. The level should be 100mVrms at 1kHz.
XRESET
21
I
Master reset. Active low.
SCL
22
I
STB
23
I
STxD
24
O
Serial interface clock input. The data is transferred in both directions at the
rising edge of this signal.
Serial interface strobe signal. With strobe signal the MAS9191A stores the
given address from the serial interface buffer and enters the data mode.
The serial interface stays in the data mode until eight SCL pulses are
received after the strobe signal.
Serial interface transmit data output.
SRxD
25
I
Serial interface receive data input
BUZFB
26
AI
Buzzer feedback is the input for the buzzer driver.
BUZOUT
27
AO
Buzzer output.
EXTERP
28
AO
Output for external accessories
EARP1
29
AO
Earpiece differential outputs of earpiece amplifier. The outputs are
capable of driving a ceramic earpiece directly.
EARP2
30
AO
SIDEFB
31
AO
Side tone feedback output
SIDETONE
32
AI
EINR
33
AI
Side tone input. The level of the side tone is controlled with external
components.
External RX input.
STGT
34
AI
EST
35
AO
RAUDIN
36
AI
RXACCOUT
37
AO
Compressor 2nd amplifier input as well as GC4 input. Use an external
22nF capacitor between COUT and this pin.
Compressor window comparator input. Use an external 22nF capacitor
between CAMP2O and this pin.
Compressor 2nd amplifier output.
Steering control input for DTMF receiver. When the level at this input
changes from below VDD/2 to above VDD/2 the pin is pulled up internally.
When this occurs the DTMF tone is stored and an interrupt is generated.
Enable Steering output. This pin is high when the DTMF receiver has
detected a valid DTMF tone.
Input for filter 6. Connect through a 22nF capacitor to the expander output
(EXPOUT).
Output of uncommitted Op Amp in MAS9191A. The Op Amp is normally
used for RX audio level detection. The application circuit for this function is
in the APPLICATIONS section. Connect the level detected by the circuit
to the A/D converter of the general purpose micro controller.
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July 31, 1997
PIN DESCRIPTION
Pin name
Pin
Type
Function
RXACCIN
38
AI
RX block extra Op Amp input
EXPOUT
39
AO
Expander output. The expander ratio is 1:2.
EWCIN
40
AI
EAMPOUT
41
AO
Expander window comparator input. Connect a 22nF capacitor between
EWCIN and EAMPOUT.
Expander amplifier output.
EXPIN
42
AI
VDAR
43
P
VSAR
44
G
RBPFOUT
45
AO
RX bandpass filter output.
RBPFIN
46
AI
DEOUT
47
AO
VREF
48
AO
RX
49
AI
RX bandpass filter input. Connect a 22nF capacitor between this pin and
DEOUT
RX de-emphasis filter output. The filter has a -6dB/octave (±1dB)
frequency response in the range 300Hz...3kHz.
Reference voltage. Connect a capacitor between this pin and system
ground.
RX input from RF. This level is 100mVrms at 1kHz.
ALP
50
AI
Audio loop input. Connect through a 22nF capacitor to the TX pin.
TEST2
51
I
Test input. Connect to ground during normal operation.
TEST1
52
I
CLKOUT
53
O
Test input. Connect to ground during normal operation. If connected to
VDD and TEST2 is connected to ground, the external clock can then be
connected to XTAL1.
4.8 MHz clock output from oscillator circuit.
TXCTRL
54
AO
VSS
55
G
Transmission control output. If a TX collision occurs this open-collector
output is set to low. The TXCTRL will remain low until the TX block is reset
with the TXRST bit or with XRESET.
Digital ground. Connect a bypass capacitor between VSS and VDD.
XTAL2
56
O
Crystal oscillator output.
XTAL1
57
I
VDD
58
P
Crystal oscillator input or external clock input if TEST1 is high and TEST2
is low.
Power supply input for digital block.
TXON
59
O
BUSY
60
O
XINT
61
O
DACOUT3
62
AO
DACOUT2
63
AO
Active low interrupt output to micro controller. The interrupt is active until
status register 10HEX is read.
Output of DAC 3. The DAC output is connected to ground if the DAC is in
power down mode. The output of the DAC is controlled by register 18HEX.
Enter the values in two’s complement form into the DAC register.
Output of the DAC 2. The control register is located at 17HEX.
DACOUT2
64
AO
Output of the DAC 1. The control register is located at 16HEX.
Expander input. Connect a 22nF capacitor between EXPIN and
RBPFOUT.
Power supply for RX audio block. Use a bypass capacitor between VDAR
and VSAR.
Ground for RX block. Connect to system ground.
Transmission detection for debugging. This output indicates when a
transmission is occurring.
Busy/Idle output. Indicates the state of the busy/idle bit.
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July 31, 1997
ABSOLUTE MAXIMUM RATINGS
(GND = 0V)
Parameter
Symbol
Supply voltage*
Conditions
Min
Max
VDD
Storage temperature*
Unit
6.0
Ts
-55
V
o
+125
C
RECOMMENDED OPERATION CONDITIONS
(GND = 0V)
Parameter
Symbol
Supply voltage*
o
VDD
Supply current
IDD
Operating temperature*
Ta
Conditions
Ta=-40...85 C
o
Ta=-40...85 C, VDD=3.3V±5%
Min
Typ
Max
Unit
3.0
3.3
3.6
V
1.0
2.5
23
mA
-40
+85
o
C
ELECTRICAL CHARACTERISTICS
◆ Digital inputs
o
(Ta=-40...85 C)
Parameter
Symbol
Input high voltage*
VIH
Input low voltage*
VIL
Input leakage current
IIL
Input capacitance load*
CI
Conditions
Min
Typ
Max
0.7VDD
Unit
V
-10
0.7VDD
V
+10
uA
1
pF
◆ Digital outputs
(VDD = 3.3V±5%, Ta=-40...85 C)
o
Parameter
Symbol
Conditions
Output low voltage*
VOL
XINT @ +0.4mA
Output high voltage*
VOH
XINT @ -0.4mA
Min
Typ
Max
Unit
0.1VDD
V
0.9VDD
V
◆ Analog inputs
o
(Ta=-40...85 C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
External microphone level*
VEXTMIC
100
mVrms
Microphone level*
VMIC
10
mVrms
RX input level*
VRX
100
mVrms
* Guaranteed by design only.
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DA9191A.000
July 31, 1997
ELECTRICAL CHARACTERISTICS
◆ Analog outputs
o
(Ta=-40...85 C)
Parameter
Signal ground
Symbol
Conditions
AGND
Min
Typ
VDD/20.1V
Max
Unit
VDD/2+
0.1V
V
Reference voltage
Vref
Earpiece output impedance*
ZO
Earpiece load resistance*
RL
Earpiece series load capacitance*
CL
External earpiece load resistance*
RL
External earpiece load capacitance*
CL
Earpiece amplifier gain
Avol
Rx level
VO
RX level 100mVrms
200
mVrms
Earpiece level non-differential*
VO
RX level 100mVrms
70
mVrms
Earpiece level differential*
VO
RX level 100mVrms
155
mVrms
TX level
VO
EXTMIC level 100mVrms
200
mVrms
DTMF signal levels at TX
VO
f = 697 … 941 Hz
-1
+1
f = 1209 … 1633 Hz
-1
+1
ETACS
131
148
163
AMPS
123
138
152
VO
470
556
612
mVrms
VO
488
556
612
mVrms
NAMPS, DTX mode off
81
93
105
mVrms
NAMPS, DTX mode on
325
373
421
SAT signal level at TX
Data signal level at TX
(AMPS/ETACS)
ST signal level at TX
(AMPS/ETACS)
Data, ST, SAT level at TX
DACs, output level
VO
VO
AGND
+1.2V
500
1
30
DACs, differential nonlinearity
DNL
DACs, integral nonlinearity
INL
nF
kΩ
1.26
0.3V
Ω
kΩ
120
VO
1
nF
3.26
dB
dB
mVrms
-0.95
VDD0.3
+0.95
LSB
-2.0
+2.0
LSB
10
ms
Vdac ±1%
DACs, settling time*
V
30
V
DACs, load resistance*
RL
DACs, load capacitance*
CL
80
pF
OP AMPs, load capacitance*
CL
1
nF
kΩ
* Guaranteed by design only.
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July 31, 1997
ELECTRICAL CHARACTERISTICS
◆ Expander
o
(Ta=-40...85 C)
Parameter
Conditions
Min
Expanding ratio*
Typ
Max
Unit
1:2
Operation range input*
-24
+10
dB
Operation range output*
-48
+20
dB
Gain step*
1.333
Integral nonlinearity
-0.5
Attack time*
7.4
Decay time*
9.5
dB
+0.5
dB
9.2
14.3
ms
11.9
14.3
ms
◆ Compressor
o
(Ta=-40...85 C)
Parameter
Conditions
Min
Compressing ratio*
Typ
Max
Unit
2:1
Operation range input*
-39.4
+20
dB
Operation range output*
-19.7
+10
dB
Gain step*
1.333
Integral nonlinearity
-0.5
Attack time*
2.9
Decay time*
13
dB
+0.5
dB
3.9
4.6
ms
16.9
20
ms
◆ AC Characteristics
o
(Ta=-40...85 C)
Parameter
RX S/N ratio
TX S/N ratio
Conditions
Min
Typ
Max
Unit
Psophometric weighting
48
dB
50
dB
RX THD
34
dB
TX THD
34
dB
Crosstalk RX to TX*
50
dB
Crosstalk TX to RX*
50
dB
Mute attenuation
50
dB
* Guaranteed by design only.
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July 31, 1997
ELECTRICAL CHARACTERISTICS
20.0 dB
16.0 dB
12.0 dB
8.0 dB
4.0 dB
0.0 dB
-4.0 dB
-8.0 dB
-12.0 dB
-16.0 dB
-20.0 dB
-24.0 dB
-28.0 dB
-32.0 dB
-36.0 dB
-40.0 dB
-44.0 dB
-48.0 dB
-52.0 dB
-56.0 dB
-60.0 dB
100Hz
1kHz
10kHz
RX Total frequency response
20.0 dB
16.0 dB
12.0 dB
8.0 dB
4.0 dB
0.0 dB
-4.0 dB
-8.0 dB
-12.0 dB
-16.0 dB
-20.0 dB
-24.0 dB
-28.0 dB
-32.0 dB
-36.0 dB
-40.0 dB
-44.0 dB
-48.0 dB
-52.0 dB
-56.0 dB
-60.0 dB
100 Hz
1kHz
10kHz
TX Total frequency response
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July 31, 1997
ELECTRICAL CHARACTERISTICS
20.0 dB
17.0 dB
14.0 dB
11.0 dB
8.0 dB
5.0 dB
2.0 dB
-1.0 dB
-4.0 dB
-7.0 dB
-10.0 dB
-13.0 dB
-16.0 dB
-19.0 dB
-22.0 dB
-25.0 dB
-28.0 dB
-31.0 dB
-34.0 dB
-37.0 dB
-40.0 dB
100Hz
1kHz
10kHz
Filter F2 frequency response
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DA9191A.000
July 31, 1997
ELECTRICAL CHARACTERISTICS
◆ Timing
o
(Ta=-40...85 C)
Parameter
Symbol
Conditions
Min
Typ
Max
SCL cycle
T1
0.5
us
Data setup time
T2
60
ns
Data hold time
T3
20
ns
STB rising edge after SCL falling edge
T4
10
ns
STB width
T5
5
us
MSB data bit valid after STB falling edge
T6
Register read
SCL rising edge after SCL falling edge
T7
Register read
5
us
Next data bit valid after SCL falling edge
T8
Register read
30
ns
Ready for next address
T9
7
us
5
Unit
us
◆ Timing Diagram
T3
T1
T4
T8
T7
T5
T9
T6
T2
STB
SCL
SRxD
STxD
R/W
A6
A5
A4
A3
A2 A1
A0
D7
D7
D6 D5
D6
D4 D3
D5 D4
D2
D1 D0
D3 D2
D1 D0
R/W
10
A5
A4
A3
S11
S10
M1
F7
RX-Buffer
S8
GC2
F6
BCH
Decoding
S7
S5
1:2
EXPANDER
Voting
DCC
Conversion
F10
Framing
S13 GC4
S4
Frame
Decoding
LPFIN
SYS0
SYS1
LIMITER
SIGNALING TONE
F9HP
GC5
S15
F5
S3
DPLL
Manchester
Decoder
SAT
Detection
SAT
Generation
C1
C2
S17
SYS1
S18
F11
S2
RXTST
SYS1
Manchester
coding TXDATA
S14
F4
SATEN
TXTST
TAUDIN
S16 GC6
F2
F12
TXTST
DTMF
Receiver
GC8
GC7
STGT
F3
F1
GC1
S1
- A7
+
RX
ALP
VREF
AGND
TXACCOUT
TXACCIN
RXACCOUT
RXACCIN
DACOUT3
8-bit DAC
- A1
+
DACOUT2
BUSY
TXON
TXCTRL
CLKOUT
TX
8-bit DAC
OSC
F14
DACOUT1
GC9
8-bit DAC
SGND
S20
F13
F15
S19
RXMUTE
EST
EXTERP
EARP1
EARP2
BUZFB
BUZOUT
S9
BCH
Coding
COMPRESSOR
2:1
S12
FUNCTIONS
◆ Schematic diagram
SIDEFB
A2
SYS0
SYS1
LPFIN
F9HP
BUSY / IDLE
SIDETONE
XINT
XRESET
STxD
SRxD
Serial
Interface
F9HP
SYS0
SYS1
CAMP2I
COUT
STB
TX-Buffer
F9LP
LPFIN
SCL
DTMF
Generator
GC3
CAMP2O
CWCIN
EXTMIC
F8
TAUDOUT
MICFB
MICSGND
M2
MICOUT
A6
TAUDIN
MIC
DA9191A.000
July 31, 1997
EST
STGT
DEOUT
RBPFIN
RBPFOUT
EXPIN
PREIN
EAMPOUT
EWCIN
COMPIN
EXPOUT
RAUDIN
EINR
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July 31, 1997
FUNCTIONS
◆ Data Reception
The data reception block is in the power down state
after a reset. The power down mode of the block is
controlled by the RXSIP bit in register 07HEX. The
Manchester encoded data is received through the RX
pin. The data is amplified with GC1 and filtered with
filter F1. The comparator C1 is used to convert data to
a digital signal. The digital PLL circuit recovers the bit
clock from the Manchester encoded data. The bit
clock is 8kHz in the ETACS mode and 10kHz in the
AMPS mode. The mode is set with the SYS0 bit of
register 12HEX. The recovered bit clock is used in the
Manchester decoder and the data is then transmitted
to the frame decoding block. The frame decoding
block finds dotting sequences, busy/idle bits and word
syncs from the data. To avoid data being generated
by random noise, the frame decoding block enters the
data reception mode only after it has received two
consecutive word syncs (11100010010) separated by
463 bits in the forward control channel and 77 bits in
the forward voice channel. In this case the voting and
BCH block are activated. When the frame decoding
block loses five consecutive synchronization patterns
it rejects the data reception mode and sets the voting
and BCH blocks in power down state. The voice and
control channel modes are selected with the CTCV bit
of register 12HEX.
Forward control channel data format. The numbers under the frames show the number of bits in each section.
Busy/
Idle
1
Busy/
Idle
1
Bit
Sync
10
Busy/
Idle
1
Data
Busy/
Idle
1
Data
10
Busy/
Idle
1
bit sync
Data
10
= 1010101010
Busy/
Idle
1
Data
Busy/
Data
Idle
10
1
10
1. Repeat of word B
Busy/
Idle
1
Data
Busy/
Data
Idle
10
1
10
5. Repeat of word B
Busy/
Idle
1
Busy/
Idle
1
Word
Sync
11
10
Data
Busy/
Idle
1
10
Data
Busy/
Data
Idle
10
1
10
1. Repeat of word A
Busy/
Idle
1
Data
Data
Busy/
Idle
1
10
Busy/
Idle
1
Data
10
Busy/
Data
Idle
10
1
10
2. Repeat of word A
Bit
Sync
10
Busy/
Idle
1
word sync = 11100010010
The busy/idle bits are extracted from the data.
Busy/idle bits are used to indicate the current status
of the reverse control channel (RECC). The RECC is
busy if the busy/idle bit is low and idle if the busy/idle
bit is high. The state determination is made with
2-out-of-3 voting. The TX block uses the busy/idle
indication for arbitration. The STR bit of register
12HEX selects the words from stream A or stream B.
Forward voice channel data format.
Bit Sync
101
Word
Sync
11
Bit Sync
37
1.Word
repeat
40
Word
Sync
11
Bit Sync
37
9.Word
repeat
40
Word
Sync
11
Bit Sync
37
On the forward voice channel after bit synchronization
and word synchronization are received and the AUMUT
bit in register 13HEX is set to high, the RX audio block
will be muted until the 920 bits are received. The
repeated words are transferred to the voting block. The
voting is done bit by bit, 3-out-of-5. If three consecutive
words are identical, the receiver is powered down and
no remaining words are read. After the voting block the
data is transmitted to the BCH block. This block
performs decoding of the received BCH coded data.
The following polynomial is used:
G(x) = x12 + x10 + x8 + x5 + x4 + x3 + x0
2.Word
repeat
40
Word
Sync
11
Bit Sync
37
10.Word
repeat
40
Word
Sync
11
Bit Sync
37
3.Word
repeat
40
Word
Sync
11
11.Word
repeat
40
If only one error occurs in data the BCH block can
correct it. If more than one error occurs the BCH block
cannot correct them and the BCHER bit of register
11HEX is set to high. The BCH block transfers the data
to the RX buffer. When the buffer is full the RXWRD bit
of register 10HEX is set to high and this causes interrupt
line XINT to go active. When register 10HEX is read the
interrupt is cleared. The data buffer can be read by
reading register 15HEX four times. If the next word is
coming and the previous word has not been read from
the buffer, the word is missed. The new and the old
words are compared.
12
DA9191A.000
July 31, 1997
FUNCTIONS
◆ Data Transmission
After a reset the TX block is in power down. The
power down mode is controlled by bit TXSIP (TX
section in power down) in register 07HEX. The TXRST
bit located in register 12 HEX is used every time a TX
collision occurs or for any other TX block reset
causes. When the device is ready to receive data,
the TXWRD bit of register 10HEX is high. If five bytes
are written into register 19HEX the data transmission
begins. The data is transferred from the serial
interface to the TX buffer and the TXWRD bit is set
high again, which causes XINT to become active.
When the block comes out of power down mode the
XINT is active because the device is ready to receive
data (TXWRD goes high). The lower nibble of the
fifth byte is ignored. The 36 bits of data are coded by
the BCH coder with following polynomial:
G(x) = x12 + x10 + x8 + x5 + x4 + x3 + x0
The BCH coder adds 12 parity bits to the data and
the data is transferred to the DCC coding block. The
DCC coder adds a digital color code on the reverse
control channel (RECC) according following table.
DCC(1:0)
Coded DCC
00
0000000
01
0011111
10
1100011
11
1111100
The framing block adds bit sync (101010...10) and word sync (11100010010) sequences to the frames and
performs needed repeats depending on the mode.
Reverse control channel data format. The numbers under the frames show the number of bits in each section.
Bit sync
Word sync
Coded DCC
First word
Second word
repeated 5 times repeated 5 times
30
11
7
240
240
Reverse voice channel data format.
1.Repeat
Bit Sync
Word
of word 1
Sync
101
11
48
5.Repeat
Bit Sync
Word
of word 1
Sync
37
11
48
5.Repeat
Bit Sync
Word
of word 2
Sync
37
11
48
Bit Sync
37
Bit Sync
37
The Manchester encoder block encodes the data into
a Manchester coded format with bit clock. The bit
clock is 8kHz in the ETACS mode and 10kHz in the
AMPS mode. The mode can be controlled by bit
SYS0 of register 12HEX. The data polarity can be
inverted with bit INVTX of register 13HEX.If the BUSY
bit does not go active between 56 and 104 bits of the
transmitted message a transmission collision occurs.
In this case the data which is in the TX block and the
data that the user is writing to the device will not be
Word
Sync
11
Word
Sync
11
2.Repeat
of word 1
Bit Sync
48
37
Bit Sync
1.Repeat
of word 2
48
37
Word
Sync
11
Word
Sync
11
transmitted. The TXCOL bit of register 10HEX will go
high in this case and cause an interrupt. The TXCOL
will remain active until the TX block is reset with the
TXRST bit of register 12HEX. If the TXCTREN bit is
active in register 12HEX the TXCTRL output turns the
transmitter off when a TX collision occurs. If the
AUMUT bit in register 13HEX is set to high the TX
audio block is muted with switch S19 on the voice
channel while data transmission is occurring.
13
DA9191A.000
July 31, 1997
FUNCTIONS
◆ Data Reception in Narrow Band mode
Forward voice channel data format for narrow band.
DSAT
Sync word
24
30
Sync word = 011001010110101001100110100110
Data
DSAT
40
24
DSAT = Digital Supervisory Audio Tone is one of seven 24-bit digital sequences added to the voice transmission.
DSAT is transmitted at 200 NRZ bits/second. The following is a list of the seven DSAT sequences.
DSAT sequence
0
2556CBHEX
1
255B2BHEX
2
256A9BHEX
3
25AD4DHEX
4
26AB2BHEX
5
26B2ADHEX
6
2669ABHEX
The 40-bit long data sequence is generated at a 100 Manchester bits/second rate. The data sequence contains 28
bits of data and 12 parity bits.
The incoming data is captured by two 8-bit shift
registers. When one shift register is full the RXWRD
flag is set and an interrupt is generated. The
captured data must be read by the micro controller
within 20ms after the interrupt. Meanwhile, the other
shift register is being filled and when it is full a new
interrupt is generated. The shift registers are clocked
in at 400 Hz. Two samples of each state of both the
200 NRZ bits/second data and the 100 Manchester
bits/second data are loaded into the registers. Note
that there are as many transitions in the 200 NRZ
bits/second data as in the 100 Manchester
bits/second data. The micro controller will then be
used to filter the digital bit sequence and detect the
DSAT, SYNC WORD and DATA out of the bit
stream. The DATA must be checked with following
algorithm:
G(x) = x12 + x10 + x8 + x5 + x4 + x3 + x0
400 Hz
8-bit
shift register
SCL
C1
STxD
Rx
SCL
8-bit
shift register
400 Hz
14
DA9191A.000
July 31, 1997
FUNCTIONS
◆ Data Transmission in Narrow Band mode
Reverse voice channel data format for narrow band.
DSAT/DST
Sync word
24
30
Sync word = 011001010110101001100110100110
The data contains 36 data bits and 12 parity bits. The
transmitted data is 100 bits/sec Manchester code.
DSAT, DST and SYNC WORD are transmitted as
200 bits/sec NRZ code. The DSAT on the TX side is
similar to the DSAT on RX side. However, under
certain conditions the inverted DSAT, or DST (Digital
Signaling Tone), must be transmitted. The DST is
one of seven 24-bit digital sequences consisting of
Data
DSAT/DST
40
24
the logical inverse of the seven DSAT sequences.
The conversions DSAT/ DST and DST/DSAT must
be made without disturbing the phase of the DSAT.
There is also a special 24-bit digital mask for each of
the seven sequences. The mask defines the first bit
to be inverted when converting from DSAT to DST
or vice versa. Only when the bit in the mask is one
can the polarity be changed.
DSAT
DST
MASK
0
2556CBHEX
DAA934HEX
FF003EHEX
1
255B2BHEX
DAA4D4HEX
0BBF82HEX
2
256A9BHEX
DA9564HEX
BD780FHEX
3
25AD4DHEX
DA52B2HEX
3FF118HEX
4
26AB2BHEX
D954D4HEX
0AE6F6HEX
5
26B2ADHEX
D94D52HEX
8001FFHEX
6
2669ABHEX
D69654HEX
1C0FCDHEX
MAS9191A does not include frame coding logic for
narrow band operation. The DSAT, DST, SYNC
WORD and DATA must be generated by micro
controller. The BCH function must also be performed
by the micro controller using the following algorithm:
G(x) = x12 + x10 + x8 + x5 + x4 + x3 + x0
The generated bit sequence is written into shift
register 19HEX 8 bits at a time. While the next byte is
written to one of the 8-bit shift registers the other is
clocked out with a 200Hz clock. Each time the
contents of a shift register transmitted, the TXWRD
flag is set and an interrupt is generated. Note that
200 NRZ bits/second data has as many transitions
as 100 Manchester bits/second data.
200 Hz
SCL
8-bit
shift register
SRxD
GC8
F12
Tx
SCL
200 Hz
8-bit
shift register
15
DA9191A.000
July 31, 1997
FUNCTIONS
◆ SAT detection & regeneration
SAT detection is active on voice channel in AMPS or
TACS mode (SYS1=0). The supervisory audio tone is
detected with a digital PLL. The detector compares the
received SAT to the given SAT color code (SCC).
When the given SAT is detected the SATDET bit of
register 11HEX is set to high. If SATINTEN bit of
register 13HEX is on the rising and falling edge of
SATDET will cause the interrupt SATINT. On the voice
SCC1
0
0
1
1
SCC0
0
1
0
1
◆ SAT, ST or Data Transmission
The SAT and signaling tone (ST) are sent only on
the voice channel in AMPS or TACS mode
(SYS1=0). The SATEN and STON can be used to
control the SAT and ST transmission. However, the
device will automatically stop transmitting SAT and
ST signals whenever data is being transmitted, even
though SATEN or STON is high. The signaling tone
is 8kHz in ETACS and 10kHz in AMPS. Also, switch
S17 for TX data and switch S18 for ST can be used
to disable the transmission. The switches must be on
during transmission. The control bits for these
switches are located in register 0DHEX. The SAT,
TXDATA and the ST are summed and amplified with
◆ DTMF Receiver
For enabling answering machine functions, the chip
has an internal DTMF receiver. The receiver is in
power down mode after a reset. The DTMFRP bit of
register 07HEX controls the receiver power down
mode. The receiver has two separate filters for
separation of the low and high frequencies. The
comparator and logic section measures the low and
high frequency periods with an averaging algorithm.
When the valid DTMF tone is detected the external
steering logic output pin EST is set to high. With an
external RC time constant the tone detect time and
tone dropout times can be adjusted. The STGT
input/output pin has an internal comparator and pullup and pull-down transistors. When EST is active
and STGT goes from below to above the Vref level
(VDD/2) the STGT is pulled up with an internal
transistor. This causes the STD signal to go high,
which causes the XINT line to become active. At the
same time the detected DTMF tone is stored in
register 04HEX. When the DTMF tone is not present
the EST will go low, which causes the STGT to fall.
When the STGT falls below the Vref level (VDD/2)
the internal logic pulls the input down. The external
RC circuit will filter out very short gaps in the
received DTMF tone. The interrupt caused by the
channel the SAT regeneration can be enabled with bit
SATEN of register 14HEX. By setting bit NOMSAT of
register 14HEX nominal SAT frequency is generated.
Otherwise, the SAT output frequency will follow
received SAT frequency. The block is in power down
mode when the TXSIP (transmit section in power
down) bit is active in register 07HEX. After a reset the
block is in power down mode.
SAT frequency
5970 Hz
6000 Hz
6030 Hz
invalid code
GC8. The gain of the amplifier is -3.75dB...+3.75dB
with 16 steps. The adjustment is made with bits 0..3
of register 0DHEX. After being amplified the signal is
filtered with 4th order SC filter F12. The cutoff
frequency of the filter is 19kHz in AMPS, 15kHz in
ETACS and 200Hz in NAMPS (SYS1=1). The gain of
the filter at 1kHz is 0dB. In the NAMPS mode, the
signal is then fed to low pass filter F15, which is a
2nd order RC type filter. After filtering the signal is
summed to the TX audio signal depending on the
state of switch S20. The switch is controlled by bit 6
of register 01HEX .Register 07HEX bit AUDIOP is used
to set these blocks into power down mode.
DTMF detector is cleared by reading status register
10HEX. If the interrupt is cleared but register 04HEX is
not read until the next DTMF tone is received, then
the previous tone will be lost. The formula below can
be used to calculate tone present and tone absent
times. By adding diodes to the external circuit the
tone present and tone dropout times can be altered.
If one of the diodes is removed, the absent and
present times are calculated using the parallel
combination of R1 and R2.
C
STGT
C
STGT
R1
EST
R1
R2
EST
Time = R*C ln(VDD/VREF)
16
DA9191A.000
July 31, 1997
FUNCTIONS
◆ RX Audio
The RX audio block starts with switch S1. The switch
is controlled by bit S1 of register 0EHEX. The input
ALP is used for enabling the audio loopback mode.
In normal operation RX is used. Behind the switch is
amplifier GC1 with adjustable gain from -3dB to
+3dB. The gain is controlled with bits 0..3 in register
0EHEX.The amplifier output is connected to the
second order lowpass filter F1. The cutoff frequency
of the filter is 50 kHz and the gain at 1kHz is 0dB.
The filter output is connected to data comparator C1
and to the SAT bandpass filter F2 and to the rest of
the RX audio block. The polarity of the received data
can be inverted with bit INVRX, which is located in
register 13HEX. The data comparator output is
connected to the DPLL and Manchester decoder
blocks. The filter F2 is a 6kHz bandpass filter for
supervisory audio tone. The filter is a second order
SC filter. The filter output is connected to SAT
comparator C2 and the SAT detection block.
the data is received on the voice channel the
lowpass filter F3 input is grounded automatically with
this switch. With switches S6 and S7 the received
audio and transmitted audio can be summed. The
control bits of the switches are located in register
03HEX. This signal is fed to F4 and to the DTMF
receiver. The function of the DTMF receiver is
described in the next section RX de-emphasis filter
F4 has a -6dB/octave (±1dB) frequency response in
the range 300Hz ... 3kHz. The filter can be bypassed
with S2-RXTST0-RXTST1. Switch S2-RXTST0RXTST1 is connected to the DEOUT pin. The
performance of C1, C2 and F2 can be monitored with
switch S2-RXTST0-RXTST1. Bits 5 and 6 in register
02HEX and bit 5 in register 0EHEX control this switch.
An external capacitor is needed between DEOUT
and RBPFIN. The RBPFIN input is connected to filter
F5, which is a 6th order bandpass filter. The gain of
this filter is 0dB at 1kHz. The filter can be bypassed
with switch S4. After S4 the signal is connected to
the RBPFOUT pin. An external capacitor is used to
connect the signal to the EXPIN input.
The signal from F1 is connected to filter F3 through a
switch which is used by the internal logic when the
AUMUT bit of register 13HEX is active. In this case if
C1 C2 F2
MICOUT
RX data, SAT
S2
RXTST0
RXTST1
S4
S7
F5
F4
GC1
F1
F3
S1
RXMUTE
S6
ALP
RX
+
DEOUT
EST
STGT
RBPFIN
SIDETONE
DTMF
Receiver
S9
A2
SIDEFB
BUZOUT
A3
BUZFB
S5
EARP2
+
A4
S10
EARP1
RBPFOUT
EXPIN
EAMPOUT
EWCIN
EINR
S11
1:2
S8
F7
EXPOUT
A5
+
RAUDIN
EXTERP
EXPANDER
F6
GC2
M1
Audio Receive Path
17
DA9191A.000
July 31, 1997
FUNCTIONS
The signal is fed to the SC-type audio expander with
expansion ratio 1:2. The expander can also be
bypassed with switch S5. The switch is controlled
with bit S5 in register 03HEX. After switch S5 the
signal goes to the EXPOUT output pin. An external
capacitor is used to connect the signal to the
RAUDIN input and to filter F6. Filter F6 is a 4th order
SC-type lowpass filter. The gain at 1kHz is 0dB. After
filtering the signal and the external accessory input
EINR can be summed with switch S8. The control bit
for the switch is in register 03HEX. The summed signal
is amplified with GC2, which has a -15dB...+15dB
gain with 16 steps. The gain is controlled with bits
0..3 in register 03HEX. The amplified signal can be
summed with SIDETONE. The side tone can be
switched on with S9, which has a control bit in
register 02HEX. The side tone input has an internal Op
Amp with feedback signal SIDEFB. The gain of the
Op Amp is controlled by external components.
COMPIN is normally used as an input for the side
tone amplifier circuit.
Filter F7 is a second order low pass filter. The cutoff
frequency is 20kHz and the gain at 1kHz is 0dB.
After filtering the signal can be connected to three
amplifiers with switches M1, S10 and S11. The
control bits are located in registers 02HEX and 03HEX.
A4 is the earphone amplifier, which is a single input
differential output amplifier. Amplifier A5 is for
external accessories and is capable of driving a
capacitive load. The load capacitance is 1nF and the
block has a 4.82dB gain. The third amplifier A3 is a
buzzer driver. It drives the signal to the power
transistor, which drives the buzzer. The buzzer
represents a high inductive load of 1.2mH/25ohm.
The block stabilizes the current flow through the
external buzzer which depends on the current gain
factor of the external bipolar transistor. The emitter
resistor of the transistor must be 6.8 ohms. Three
current values (peak values) can be chosen with
switch M1:10mA, 66mA and 160mA. The tolerance
of the external resistor will directly affect the buzzer
current. The RX audio block can be set into power
down mode together with the TX audio block. The
AUDIOP bit in Register 07HEX is used for this
purpose. The blocks are in power down mode after a
reset.
18
DA9191A.000
July 31, 1997
FUNCTION
◆ TX Audio
The TX audio block is in the power down mode after
a reset. The block is set to the operation mode with
the AUDIOP bit of register 07HEX. The same bit also
controls the RX audio block. The TX audio block
starts with switch M2, which is controlled by bits 4
and 5 in register 00HEX. Switch M2 connects one of
the following blocks as an input source: 1) After a
reset the input source is connected to signal ground.
2) In the second position the input is connected to
the microphone amplifier A6. The gain of amplifier A6
is determined with external components. The
maximum gain is 30 dB. 3) In the third position the
input is connected to EXTMIC, which is for external
accessories. 4) The fourth position selects the DTMF
generator. The DTMF generator is controlled with
registers 05HEX and 06HEX. Register 05HEX controls
the low frequencies and register 06HEX controls the
high frequencies. A detailed description of how to
use these registers is in the REGISTERS section.
The DTMF generator is in the power down mode
after a reset and can be set up with the DTMFTP bit
of register 07HEX.
PREIN
CAMP2I
COUT
COMPIN
CWCIN
MICOUT
The signal is then filtered with anti-aliasing filter F8.
The gain at 1kHz is 0dB and the cutoff frequency is
15kHz. After the filter the signal is amplified with
CAMP2O
GC3. The gain is
-3dB...+3dB with 16 steps
according to bits 0..3 in register 00HEX. The amplified
signal is then fed to lowpass filter F9LP and highpass
filter F9HP, which are 4th order SC filters. During
normal operation the output of filter F9HP is
connected to output MICOUT. With switch SYS0SYS1 the highpass filter can be transferred to the
output of GC5 after the signal has been compressed
and pre-emphasized. Bit 6 in register 12HEX and bit 6
in register 14HEX control switch SYS0-SYS1. Connect
MICOUT through a 22nF capacitor to the
compressor input COMPIN. The MICOUT can also
be used as a source for the side tone amplifier and
for detecting the audio level with the uncommitted Op
Amp (See APPLICATIONS section). The compressor
is an SC audio type with a 2:1 compressing ratio.
The detailed values are found in the ELECTRICAL
CHARACTERISTICS section under Compressor.
The compressor can be bypassed internally with
switch S12 or externally with S13. The bypass gain is
0dB (100 mVrms). The compressor requires one
external 22nF capacitor between pins CAMP20 and
CWCIN. Another 22nF capacitor is needed between
pins CAMP2IN and COUT. This capacitor also
serves as an external DC blocking capacitor between
the compressor output and gain control GC4 input.
DTMF
Generator
GC3
F8
A6
F9HP
F9LP
SYS0
SYS1
GC4
S12
M2
F10
S13
S14
2:1
SYS0
SYS1
COMPRESSOR
PRE-EMPHASIS
GC6
GC5
LIMITER
S15
F11
GC7
TAUDIN
TAUDOUT
S7
LPFIN
MIC
MICSGND
MICFB
EXTMIC
S19
S16
GC9
F13
+
F14
TX
TXTST
SYS0
SYS1
TX data, ST
S20
Audio Transmit Path
19
DA9191A.000
July 31, 1997
FUNCTIONS
The gain of GC4 can be adjusted in the range 0.67..+5.33dB with bits 0..3 in register 0AHEX. After
GC4 the signal is filtered with pre-emphasis filter
F10, which has a +6dB/octave (±1dB) frequency
response at the range 300Hz..3kHz. At 1kHz the
gain is 0dB. The pre-emphasis filter can be bypassed
with switch S14.The signal is then amplified with
GC5. Gain control GC5 is an SC-type with a
programmable gain adjustment. The range is 0dB..20 dB with 16 steps according to bits 0..3 in register
0AHEX.
At the output of GC5 is output pin LPFIN (or
highpass filter F9HP) and a SC-type limiter. The
limiting level is 439mVp and the tolerance is ±5%.
The 0dB level is 370mVp. The limiter can be
bypassed with switch S15. The lowpass filter F11
with a 6kHz notch follows the limiter. The gain of the
filter is 2.94dB at 1kHz. The filter and the limiter can
be bypassed with switch S16. GC6 and GC7 are
continuous time programmable gain adjustment
blocks. The gain of GC6 is -3dB ... +3dB with 16
step according to bits 0..3 in register 0BHEX. The gain
of GC7 is adjustable within - 3dB ... +1dB with bits
0..3 in register 0BHEX in 16 steps.
GC7 output is connected to pin TAUDOUT through
switch TXTST. The data transmission signal can be
examined at TAUDOUT with this switch. Also with
switch TXTST, the performance of GC8,
3.75..3.75dB., F12 and F15 can be observed with an
input at TAUDIN. An external capacitor between pins
TADOUT and TAUDIN is required. The TAUDIN
input is connected to switch S19. The switch can be
used to mute the TX audio block. S19 is controlled
with bit 5 in register 01HEX. Switch S19 is also
controlled by the TX framing block. During data
transmission on the voice channel and with the
AUMUT bit in register 13HEX set to high the TX audio
block is muted with S19. Following S19 is a second
order lowpass filter F13 with 15kHz cutoff frequency.
After filtering the signal is summed with the data
signal and amplified with GC9. The gain of the
amplifier GC9 is adjustable with bits 0..3 located in
register 0CHEX. The adjustment is done in 16 steps in
the range -3.0.. +3.0dB .The output of the amplifier
GC9 is then filtered with F14. The filter is a third
order lowpass filter with 54kHz cutoff frequency. The
gain at 1kHz is 0dB.
DTX bit of the regiter 0DHEX is used to set DATA,
DSAT and DST deviation. When the device is not in
DTX (Discontinous Transmission) the DTX = 0 and
there is nominal level at TX, 93 mVrms. If DTX is on,
the level is increased to 373 mVrms.
20
DA9191A.000
July 31, 1997
FUNCTIONS
◆ DACs
The device has three 8-bit DACs. The DACs can be
set to the power down mode by using bits
XPDDAC1, XPDDAC2 and XPDDAC3. The DACs
are in power down mode after a reset. The Vref for
the DACs is VDD/2. The output values of the DACs
are entered in 8-bit two’s complement form into
registers 16HEX, 17HEX and 18HEX. The typical step
size is 13 mV and the DC output level is in the range
0.3V..VDD-0.3V. The differential nonlinearity is ±0.5
LSB and the integral ±2LSB. The settling time is
10ms (max). The minimum load resistance is 30k
and the maximum load capacitance is 80pF.
◆ Op Amps
There are two uncommitted inverting operational
amplifiers in the device. The input pins are RXACCIN
and TXACCIN. The output pins are RXACCOUT and
TXACCOUT. The Op Amps are capable of driving
capacitive loads up to 1nF.
◆ Serial Interface
The serial interface has three inputs: SCL (serial
clock), STB (strobe) and SRxD(received data).
Output pin STxD is used for transmitting data. The
data is latched with the rising edge of the SCL signal.
The MSB is received first and the LSB last. Before
the STB signal, eight address bits must first be
shifted in. The STB signal sets the device into the
data mode. The MSB of the address byte defines the
read/write operation. If the MSB is high the data is
read from the device. If the MSB is low, the data is
written to the device. After the STB the written data is
shifted in with the rising edge of the SCL. If the data
is to be read from the device, the STxD output is in
the state of MSB data bit after the STB signal. The
falling edge of the SCL shifts the next data bit to the
STxD output. Eight data bits must be shifted out at
which time the device exits the data mode. Because
the serial interface transmit buffer is dynamic, data
will be valid on the buffer only 200 uS after the STB
signal appears. This means that the SCL frequency
must be at least 5kHz.
DATA
ADDRESS
STB
SCL
SRxD
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
R/W
STxD
DATA
ADDRESS
STB
SCL
SRxD
STxD
A6
A5
A4
A3
A2
A1
A0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
21
DA9191A.000
July 31, 1997
FUNCTIONS
◆ Registers
Address
00HEX
01HEX
02HEX
03HEX
04HEX
(84HEX)
05HEX
06HEX
07HEX
0AHEX
0BHEX
0CHEX
0DHEX
0EHEX
10HEX (90HEX)
11HEX (11HEX)
12HEX
13HEX
14HEX
15HEX (95HEX)
AMPS
I/O
Write
Write
Write
Write
Write
Read
Write
Write
Write
Write
Write
Write
Write
Write
Read
Read
Write
Write
Write
Read
15HEX (95HEX)
NAMPS
16HEX
17HEX
18HEX
19HEX
AMPS
Read
19HEX
NAMPS
Write
Write
Write
Write
Write
Bit 7
0
0
0
S8
0
X
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
M2[1:0]
GC3[3:0]
S20
S19
S16
S15
S14
S13
S12
RXTST[1:0]
S9
S11
S10
M1[1:0]
S7
S6
S5
GC2[3:0]
Vref[2:0]
0
0
0
0
X
X
X
DTMF[3:0]
0
LOWF[5:0]
HIGHF[7:0]
XPDDAC3
XPDDAC2
XPDDAC1
RXSIP
TXSIP
AUDIOP
GC4[3:0]
GC7[3:0]
0
0
S4
0
S18
S3
X
X
X
BCHERR
0
S17
S2
BUSY
DTMFRP
DTMFTP
GC5[3:0[
GC6[3:0]
GC9[3:0]
GC8[3:0]
GC1[3:0]
TXTST
DTX
S1
SATINT
TXCOL
TXWRD
RXWRD
STD
TXON
WSYNC
DOT
SATDET
X
CTCV
STON
SATEN
SYS0
STR
RXRST
TXRST
TXCTRE
SATINTE
STDE
RXINTE
AUMUT
INVRX
INVTX
DCC[1:0]
NOMSAT
SYS1
0
0
0
0
SCC[1:0]
1ST RX[0:7]
2ND RX[8:15]
3RD RX[16:23]
4TH RX[24:27]
0
0
0
8 bits of captured data after comparator with shift register clocked at 400Hz
DAC1[7:0]
DAC2[7:0]
DAC3[7:0]
1ST TX[0:7]
2ND TX[8:15]
3RD TX[16:23]
4TH TX[24:31]
5TH TX[32:35]
0
0
0
8 bit sequence to be transmitted with shift register clocked at 200Hz
0
0
22
DA9191A.000
July 31, 1997
FUNCTIONS
Register 00HEX (write only)
Bit
Name
3-0
GC3[3:0]
State
0000-1111
Function
Control range for GC3: -3.0dB … +3.0dB, 0.4dB/step
0000
-3.0dB
0001
-2.6dB
0010
-2.2dB
…….
5-4
1111
+3.0dB
1000
+0.2dB default value
M2[1:0]
00
AGND
01
A6-OUT
10
EXTMIC
11
DTMFGEN
6
reserved
0
reserved for future use, set to 0
7
reserved
0
reserved for future use, set to 0
Connected to F8 input
Register 01HEX (write only)
Bit
0
1
2
3
4
5
6
7
Name
S12
S13
S14
S15
S16
S19
S20
reserved
State
Function
0
Compressor output
1
Compressor input
0
COUT
1
PREIN
0
F10 output
1
F10 input
0
Limiter output
1
Limiter input
0
F11 output
1
Limiter input
0
AGND
1
TAUDIN
0
(SYS1 = 0)
1
(SYS1 = 1)
0
(SYS1 = 0)
1
(SYS1 = 1)
0
AGND
connected to COUT
connected to GC4 input
connected to GC5 input
connected to F11 input
connected to GC6 input
connected to F13 input
summed to GC9 input
F12 output
AGND
F15 output
reserved for future use, set to 0
23
DA9191A.000
July 31, 1997
FUNCTIONS
Register 02HEX (write only)
Bit
Name
1-0
M1[1:0]
2
3
4
6-5
7
State
Function
00
AGND
01
10mA gain
10
66mA gain
11
160mA gain
0
AGND
1
Filter F7 output
0
AGND
1
Filter F7 output
0
AGND
1
Amplifier A2 output
RXTST0-
00
determined by S2
RXTST1
01
C1
10
F2
11
C2
0
reserved for future use, set to 0
S10
S11
S9
reserved
connected to amplifier A3 input
connected to amplifier A4 input
connected to amplifier A5 input
summed to F7 input
connected to DEOUT
Register 03HEX (write only)
Bit
Name
3-0
GC2[3:0]
State
0000-1111
Function
Control range for GC2: -15.0dB … +15.0dB, 2.0dB/step
0000
-15.0dB
0001
-13.0dB
0010
-11.0dB
…….
4
5
6
7
S5
S6
S7
S8
1111
+15.0dB
1000
+1.0dB default value
0
EXPOUT
1
EXPIN
0
AGND
1
RAUDIN
0
AGND
1
COMPIN
0
AGND
1
EINR
connected to EXPOUT
summed into F6 input
summed into GC2 input
24
DA9191A.000
July 31, 1997
FUNCTIONS
Register 04HEX (bits 7-4 write only, bits 3-0 read only)
Bit
Name
State
Function
3-0
DTMF[3:0]
6-4
Vref[2:0]
7
reserved
0001
‘1’ Tone detected
0010
‘2’ Tone detected
0011
‘3’ Tone detected
0100
‘4’ Tone detected
0101
‘5’ Tone detected
0110
‘6’ Tone detected
0111
‘7’ Tone detected
1000
‘8’ Tone detected
1001
‘9’ Tone detected
1010
‘0’ Tone detected
1011
‘*’ Tone detected
1100
‘#’ Tone detected
1101
‘A’ Tone detected
1110
‘B’ Tone detected
1111
‘C’ Tone detected
0000
‘D’ Tone detected
Internal reference voltage adjustment
000
+0.75dB
001
+0.50dB
010
+0.25dB
011
0.00dB default value
100
-0.25dB
101
-0.50dB
110
-0.75dB
111
-1.00dB
0
reserved for future use, set to 0
Register 05HEX (write only)
Bit
Name
5-0
LOWF[5:0]
7-6
reserved
State
00H-3FH
Function
Transmitted low frequency DTMF tone
Nominal
Real frequency
000000
No signal
No signal
100110
697 Hz
695.8 Hz
101010
770 Hz
769.0 Hz
101111
852 Hz
860.6 Hz
110011
941 Hz
933.8 Hz
00
reserved for future use, set to 0
25
DA9191A.000
July 31, 1997
The register value for other frequencies may be calculated with the formula: LG[5:0] = (fOUT * 217) / 2.4MHz.
FUNCTIONS
Register 06HEX (write only)
Bit
Name
7-0
HIGHF[7:0]
State
Function
00H-FFH
Transmitted high frequency DTMF tone
Nominal
Real frequency
00000000
No signal
No signal
01000010
1209 Hz
1208.5 Hz
01001001
1336 Hz
1336.7 Hz
01010001
1477 Hz
1483.2 Hz
01011001
1633 Hz
1629.6 Hz
The register value for other frequencies may be calculated with the formula: HG[7:0] = (fOUT * 217) / 2.4MHz.
Register 07HEX (write only)
Bit
0
1
2
3
4
5
6
7
Name
DTMFTP
DTMFRP
AUDIOP
TXSIP
RXSIP
XPDDAC1
XPDDAC2
XPDDAC3
State
Function
0
DTMF transmitter in power down
1
DTMF transmitter active
0
DTMF receiver in power down
1
DTMF receiver active
0
AUDIO in power down
1
AUDIO active
0
Digital TX section in power down
1
Digital TX section active
0
Digital RX section in power down
1
Digital RX section active
0
DAC1 in power down
1
DAC1 active
0
DAC2 in power down
1
DAC2 active
0
DAC3 in power down
1
DAC3 active
26
DA9191A.000
July 31, 1997
FUNCTIONS
Register 0AHEX (write only)
Bit
Name
3-0
GC5[3:0]
State
0000-1111
Function
Control range for GC5: 0.0dB … -20.0dB, 1.33.0dB/step
0000
0.0dB
0001
-1.33dB
0010
-2.67dB
…….
7-4
GC4[3:0]
1111
-20.0dB
0000
0.0dB default value
0000-1111
Control range for GC4: -0.67dB … +5.33dB, 0.4.0dB/step
0000
-0.67dB
0001
-0.27dB
0010
+0.13dB
…….
1111
+5.33dB
1000
+2.53dB default value
Register 0BHEX (write only)
Bit
Name
3-0
GC6[3:0]
State
0000-1111
Function
Control range for GC6: -3.0dB … +3.0dB, 0.4dB/step
0000
-3.0dB
0001
-2.6dB
0010
-2.2dB
…….
7-4
GC7[3:0]
1111
+3.0dB
1000
+0.2dB default value
0000-1111
Control range for GC7: -3.0dB … +1.0dB, 0.266.0dB/step
0000
-3.0dB
0001
-2.6dB
0010
-2.2dB
…….
1111
+1.0dB
1011
-0.067dB default value
27
DA9191A.000
July 31, 1997
FUNCTIONS
Register 0CHEX (write only)
Bit
Name
3-0
GC9[3:0]
State
0000-1111
Function
Control range for GC9: -3.0dB … +3.0dB, 0.4dB/step
0000
-3.0dB
0001
-2.6dB
0010
-2.2dB
…….
4
1111
+3.0dB
1000
+0.2dB default value
TXTST
0
1
7-5
reserved
000
GC7 output connected to TAUDOUT
ST, SAT and TXDATA connected to GC8 input
ST, SAT and TXDATA connected to TAUDOUT
TAUDIN connected to GC8 input
reserved for future use, set to 0
Register 0DHEX (write only)
Bit
Name
3-0
GC8[3:0]
State
0000-1111
Function
Control range for GC8: -3.75dB … +3.75dB, 0.5dB/step
0000
-3.75dB
0001
-3.25dB
0010
-2.75dB
…….
4
5
6
7
DTX
S17
S18
reserved
1111
+3.75dB
1000
+0.25dB default value
0
Discontinuous transmission disabled
1
Discontinuous transmission enabled
0
(SYS1 = 0)
1
(SYS1 = 0)
0
(SYS1 = 1)
1
(SYS1 = 1)
0
AGND
Summed into GC8 input
TXDATA signal
AGND
TX Buffer output signal
AGND
1
Signaling Tone
0
reserved for future use, set to 0
28
DA9191A.000
July 31, 1997
FUNCTIONS
Register 0EHEX (write only)
Bit
Name
3-0
GC1[3:0]
State
0000-1111
Function
Control range for GC1: -3.0dB … +3.0dB, 0.4dB/step
0000
-3.0dB
0001
-2.6dB
0010
-2.2dB
…….
4
5
6
7
1111
+3.0dB
1000
+0.2dB default value
S1
S2
S3
S4
0
RX
1
ALP
0
F4 output
1
F4 input
0
signal from S2-RXTST0-RXTST1
1
RBPFIN
0
F5 output
1
F5 input
connected to GC1 input
connected to DEOUT
connected to F5 input
connected to RBPFOUT
Register 10HEX (read only)
Bit
0
1
2
3
4
7-5
Name
STD
RXWRD
TXWRD
TXCOL
SATINT
reserved
State
Function
0
DTMF tone not received
1
DTMF tone received
0
RX buffer empty
1
0
RX word received (SYS1 = 0)
Next captured byte ready (SYS1 = 1)
Transmitting previous byte or word
1
TX buffer empty
0
No TX collision detected
1
TX collision detected
0
SATDET signal stable
1
rising or falling edge of SATDET detected
0,1
not in use
The rising edge of the signals STD, RXWRD, TXWRD, TXCOL and SATINT activates the interrupt line XINT. If the
signal(s) changes when register 10HEX or one of the other registers is read, the interrupt line will be activated right
after the register read. Reading this register sets the interrupt line inactive. If a new interrupt is generated during
register read , the interrupt line will be activated again right after register is read.
29
DA9191A.000
July 31, 1997
FUNCTIONS
Register 11HEX (read only)
Bit
Name
State
Function
not in use
0
reserved
0,1
1
SATDET
0
Invalid SAT frequency received
1
Valid SAT frequency received. See SCC in register 14HEX.
0
No dotting sequence detected
1
Dotting sequence detected
0
No word sync detected
1
Word sync detected
0
No transmission
1
Word transmission on
0
BUSY bit detected
1
IDLE bit detected
0
No BCH error detected
1
BCH error detected
2
3
4
5
6
7
DOT
WSYNC
TXON
BUSY
BCHERR
reserved
0,1
not in use
Function
Register 12HEX (write only)
Bit
Name
State
0
STON
0
No signaling tone transmission
1
Signaling transmission on
0
Control channel
1
Voice channel
0
TX control disabled
1
TX control active. TXCTRL output pin can be used to control transmitter
0
Digital TX section operating
1
Digital TX section reset
0
Digital RX section operating
1
Digital RX section reset
0
Stream A
1
Stream B
1
2
3
4
5
6
7
CTCV
TXCTREN
TXRST
RXRST
STR
SYS0
SATEN
0
(SYS1 = 0)
1
(SYS1 = 0)
0
(SYS1 = 1)
1
(SYS1 = 1)
0
1
ETACS mode
AMPS mode
F9HP input connected to F9LP output.
NAMPS mode
F9HP input connected to GC5 output.
NAMPS mode
SAT transmission disabled
SAT transmission enabled
30
DA9191A.000
July 31, 1997
FUNCTIONS
Register 13HEX (write only)
Bit
Name
State
1-0
DCC[1:0]
00-11
Digital color code
00
0000000
01
0011111
10
1100011
11
1111100
2
3
4
5
6
7
INVTX
INVRX
AUMUT
RINTE
STDE
SATINTE
Function
0
TXDATA not inverted
1
Invert TXDATA polarity
0
RX input not inverted
1
Invert RX input polarity
0
No automatic mute
1
TX and RX audio muted automatically on the voice channel
0
RX interrupts disabled
1
RX interrupts enabled
0
STDE (DTMF receiver) interrupts disabled
1
STDE (DTMF receiver) interrupts enabled
0
SAT detection interrupts disabled
1
SAT detection interrupts enabled
Register 14HEX (write only)
Bit
Name
1-0
SCC[1:0]
5-2
6
7
reserved
SYS1
NOMSAT
State
Function
00
5958Hz-5982Hz SAT frequency expected
01
5988Hz-6012Hz SAT frequency expected
10
6018Hz-6042Hz SAT frequency expected
11
Invalid state
0000
reserved for future use, set to 0
0
Wide band mode (AMPS/ETACS)
1
Narrow band mode (NAMPS)
0
Transmitted SAT will follow received SAT
1
Nominal SAT frequency transmitted
31
DA9191A.000
July 31, 1997
FUNCTIONS
Register 15HEX (read only)
Bit
Name
7-0
RX byte
SYS1 = 0
State
Function
00H-FFH
When RXWRD is high
1st byte
nd
2
byte
3rd byte
th
4 byte
7-0
RX byte
SYS1 = 1
00H-FFH
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
b10
b11
b12
b13
b14
b15
b16
b17
b18
b19
b20
b21
b22
b23
b24
b25
b26
b27
0
0
0
0
Captured byte with 400Hz after data comparator.
MSB = first captured bit.
The received word is read by reading register 15HEX four times.
Register 16HEX (write only)
Bit
Name
7-0
DAC1[7:0]
State
00H-FFH
Function
Control port for DAC1 output level
80H
100mVDC
FFH
100mVDC + 7FH x 13mVDC
00H
100mVDC + 80H x 13mVDC
7FH
100mVDC + FFH x 13mVDC
Register 17HEX (write only)
Bit
Name
7-0
DAC2[7:0]
State
00H-FFH
Function
Control port for DAC2 output level
80H
100mVDC
FFH
100mVDC + 7FH x 13mVDC
00H
100mVDC + 80H x 13mVDC
7FH
100mVDC + FFH x 13mVDC
Register 18HEX (write only)
Bit
Name
7-0
DAC3[7:0]
State
00H-FFH
Function
Control port for DAC3 output level
80H
100mVDC
FFH
100mVDC + 7FH x 13mVDC
00H
100mVDC + 80H x 13mVDC
7FH
100mVDC + FFH x 13mVDC
32
DA9191A.000
July 31, 1997
FUNCTIONS
Register 19HEX (write only)
Bit
Name
7-0
TX byte
SYS1 = 0
State
Function
00H-FFH
When TXWRD is high
1st byte
nd
2
byte
3rd byte
00H-FFH
b2
b3
b4
b5
b6
b7
b8
b9
b10
b11
b12
b13
b14
b15
b16
b17
b18
b19
b20
b21
b22
b23
b24
b25
b26
b27
b28
b29
b30
b31
th
b32
b33
b34
b35
0
0
0
0
5 byte
TX byte
SYS1 = 1
b1
th
4 byte
7-0
b0
Byte for transmitter. Byte is shifted out with 200Hz clock.
MSB will be transmitted first.
The transmitted word is written by writing to register 19HEX five times.
33
DA9191A.000
July 31, 1997
APPLICATION INFORMATION
RF
FRONT END
IF
DEMODULATO R
RX
Interfaces
- DISPLAY
- KEYPAD
MAS9191A
RX VCO
AUDIO/DATA
PROCESSOR
DUAL
SYNTHESIZER
DUPLEX
FILTER
POWER
AMP
MICRO
CONTROLLER
DAC
VCXO
TX
TX VCO
MEMORY
Typical MAS9191A application in AMPS/ETACS cellular system.
TEST CIRCUIT
side tone
22nF
22nF
16
15
13
14
11
12
4
3
2
RF Modulator
C
R
C
22nF
22nF
19
R
MIC
22nF
22pF
18
1
100nF
17
57
A6
4.8MHz
22pF
20
EXTMIC
1M
56
22nF
Serial bus
micro
controller
31
2
C
R
MAS 9191A
C
R
side tone
32
A6
buzzer
100nF
100
3
6.8
27
100nF
26
48
29
A4
earphone
100nF
100nF
22nF
49
30
IF
DTMF Receiver
1nF
EXTEARP
1
A3
34
28
35
36
39
40
41
42
45
46
47
R
4
C
22nF
22nF
22nF
22nF
VDD
1
components determine the gain of microphone amplifier A6
2
components determine the gain of SIDETONE amplifier A2
3
NPN transistor for the buzzer
4
components determine RC time constant if DTMF receiver is used
34
DA9191A.000
July 31, 1997
PACKAGE OUTLINES
64 LEAD TQFP OUTLINE
0.30
0.45
0.45
0.75
SEATING PLANE
0°-7°
16.00 TYPICAL
16.00 TYPICAL
14.00 TYPICAL
14.00 TYPICAL
0.05
0.15
1.35
1.45
1.60
MAX
0.09
0.20
0.80 TYPICAL
ALL MEASUREMENTS IN mm
35
DA9191A.000
July 31, 1997
ORDERING INFORMATION
Product Code
MAS9191AJ
MAS9191AJ-T
Product
AMPS/ETACS single chip
audio/data processor
AMPS/ETACS single chip
audio/data processor
Package
TQFP64
Comments
TQFP64
Tape and Reel
LOCAL DISTRIBUTOR
MICRO ANALOG SYSTEMS OY CONTACTS
Micro Analog Systems Oy
Kamreerintie 2, P.O. Box 51
FIN-02771 Espoo, FINLAND
Tel. +358 9 80 521
Fax +358 9 805 3213
http://www.mas-oy.com
NOTICE
Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or
performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits shown in
this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that the
circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Micro Analog
Systems Oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.
36