MITSUMI LX1692IDW

LX1692
®
TM
Full Bridge Resonant CCFL Controller
P RODUCTION D ATA S HEET
KEY FEATURES
DESCRIPTION
The LX1692 regulates the CCFL
brightness in three ways: analog
dimming, digital dimming, or combined
analog and digital dimming methods
simultaneously to achieve the widest
dimming range (> 60 to 1).
The LX1692 can accept a brightness
control signal that is either an analog
voltage or a direct low frequency PWM.
The LX1692 also features integrated
gate drivers for the four external power
MOSFETs.
An integrated 4V LDO powers all
internal control circuitry which greatly
simplifies supply voltage requirements.
The LX1692 is available in a 20-Pin
TSSOP and SOIC.
IMPORTANT: For the most current data, consult MICROSEMI’s website: http://www.microsemi.com
Protected by U.S. Patents: 5,615,093; 5,923,129; 5,930,121; 6,198,234; Patents Pending
BENEFITS
PRODUCT HIGHLIGHT
VSUPPLY
LX1692
A
I_R
B
C_BST
C
C_TO
D
Part
DUAL
FET
Balancer
C_R
DUAL
FET
BRITE_IN
EA_OUT
ƒ For Wide Voltage Range Inverter
Application (7V to 22V)
ƒ Patent Resonant Strike for
Unsurpassed Striking Power
Combined with Best Efficiency
ƒ Low Stress to Transformers
ƒ Excellent Open Circuit Voltage
Regulation Reduces Transformer
Breakdown Voltage
Requirements While Striking
Higher Voltage Lamps
ƒ One Inverter for Multiple Panel
Types
ƒ Wide Dimming Range
Analog Dimming: >3 to 1
Digital Dimming : >20 to 1
Combined: >60 to 1
ƒ Fool-Proof Striking
ƒ Programmable Burst Dimming
Frequency
ƒ Programmable Time Out
Protection
ƒ Fixed Operating Frequency
ƒ Open Lamp Voltage Protection,
Short Lamp Protection, Arc
Protection1
WWW . Microsemi .C OM
Microsemi’s LX1692 is a cost
reduced, third generation Direct Drive
CCFL (Cold Cathode Fluorescent
Lamp) controller. The integrated
controller is optimized to drive
CCFL’s using resonant full bridge
inverter topology.
Resonant full bridge topology
provides near sinusoidal waveforms
over a wide supply voltage range in
order to maximize the life of CCFL
lamps, control EMI emissions, and
maximize efficiency. This new architecture also provides a wide dimming
range.
The LX1692 includes safety
features that limit the transformer
secondary voltage and protect against
fault conditions which include open
lamp, broken lamp and short-circuit
faults.
ƒ Even Display Light Distribution
ƒ Longer Lamp Life with Optimized
Lamp Current Amplitude
ƒ Reduced Operating Voltage
Lowers Corona Discharge and
Prolongs Module Life
ƒ High “Nits / Watt” Efficiency
Makes Less Heat and Brighter
Displays
APPLICATIONS
ISNS
ƒ LCD TV
ƒ LCD Monitor
TA (°C)
-20 to +85
PW
Plastic TSSOP
20-Pin
DW
LX1692
PACKAGE ORDER INFO
Plastic SOIC
20-Pin
RoHS Compliant / Pb-free
RoHS Compliant / Pb-free
LX1692IPW
LX1692IDW
Note: Available in Tape & Reel. Append the letters “TR” to the part number. (i.e. LX1692IPW-TR)
1
Arc protection is provided if the arcing level is enough to be trigged.
Copyright © 2004
Rev. 1.1, 2/9/2006
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 1
LX1692
TM
®
Full Bridge Resonant CCFL Controller
P RODUCTION D ATA S HEET
ABSOLUTE MAXIMUM RATINGS
PACKAGE PIN OUT
Note: Exceeding these ratings could cause damage to the device. All voltages are with respect
Ground. Currents are positive into, negative out of specified terminal.
20
1
DW
85°C/W
11
10
VDDP
AOUT
BOUT
GND
COUT
DOUT
ISNS
OV_SNS
ICOMP
OC_SNS
PW PACKAGE
(Top View)
to
THERMAL DATA
Plastic SOIC 20-Pin
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA
VDDA
C_R
C_BST
C_TO
I_R
ENABLE
BRITE_A
VIN_SNS
BRITE_D
VCOMP
VDDA
C_R
C_BST
C_TO
I_R
ENABLE
BRITE_A
VIN_SNS
BRITE_D
VCOMP
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VDDP
AOUT
BOUT
GND
COUT
DOUT
ISNS
OV_SNS
ICOMP
OC_SNS
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Supply Input Voltage(VDDP)............................................................................................. 6.6V
VIN_SNS .........................................................-0.3V to (VDDP+0.5V), not to exceed +6.6V
Digital Input (ENABLE) ................................... -0.3V to (VDDP+0.5V) , not to exceed +6.6V
Analog Inputs (ISNS, OV_SNS, OC_SNS)clamped to ±14V Max Peak Current ±100mA
Analog Inputs (BRITE_A, BRITE_D) ............. -0.3V to (VDDP +0.5V) , not to exceed +6.6V
Digital Outputs (AOUT, BOUT, COUT, DOUT) -0.3V to (VDDP +0.5V) , not to exceed +6.6V
Analog Outputs (I_R, ICOMP, VCOMP)........ -0.3V to (VDDP + 0.5V) , not to exceed +6.6V
Maximum Operating Junction Temperature .....................................................................150°C
Storage Temperature Range....................................................................................-65 to 150°C
Peak Package Solder Reflow Temp.(40 seconds max. exposure) .........................260°C(+0, -5)
DW PACKAGE
(Top View)
PW
Plastic TSSOP 20-Pin
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA
99°C/W
RoHS / Pb-free 100% Matte Tin Lead Finish
Junction Temperature Calculation: TJ = TA + (PD x θJA).
The θJA numbers are guidelines for the thermal performance of the device/pc-board system. All of the
above assume no ambient airflow.
FUNCTIONAL PIN DESCRIPTION
Description
C_R
Lamp Frequency Programming Capacitor Pin – lamp running frequency is set by the combination of C_R and
I_R. The internal lamp current oscillator frequency can be forced to follow an external clock signal at this pin. In
this case, the programmed frequency must be lower than the external frequency. Minimum pulse width for
external synch signal is 1µsec. Maximum duty is 50%
I_R
Current Reference Resistor Input. Connects to an external resistor that determines the magnitude of internal
bias currents. The I_R pin is a DC reference voltage of 1V. This voltage cannot be used for other than its
intended function. The reference current established at this pin by connecting an external resistor is used to
charge a capacitor at the C_R pin. The nominal lamp frequency can be adjusted by varying this resistor value in
the range of 20K to 100K Ohms. (Note: C is in pF, R is in KΩ , Freq is in KHz).
242 × 10 3
FLAMP =
CC _ R ⋅ RI _ R
Other reference currents derived from I_R are used for the digital dimming burst oscillator and the strike time
out function.
Copyright © 2004
Rev. 1.1, 2/9/2006
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 2
PACKAGE DATA
Name
LX1692
TM
®
Full Bridge Resonant CCFL Controller
P RODUCTION D ATA S HEET
FUNCTIONAL PIN DESCRIPTION (CONTINUED)
C_BST
Description
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Name
Burst dimming mode frequency set capacitor. Internal bias currents set via the I_R pin are scaled down and
used to charge and discharge the capacitor connected at the C_BST pin. The voltage at the C_BST pin is a
sawtooth waveform displaying a voltage that ranges from 0.5V to 2.5V. The frequency of the PWM for digital
dimming is set by the I_R and C_BST pins.
98039
where RI_R is in KΩ and CC_BST is in nF, FDIM is Hz
FDIM =
CC _ BST .RI _ R
The internal burst oscillator frequency can also be forced to follow an external clock signal at this pin. In this
case, the programmed frequency must be lower than the external frequency.
C_TO
Time Out set capacitor. An external capacitor is charged with an on chip current source to create a voltage
ramp. Over voltage fault shutdown is disabled until C_TO voltage rises above 3.5V, providing a user
programmed strike interval. After C_TO is reached to the internal threshold level, then it will be discharged to
0V. Also Short lamp detection will be disabled until C_TO voltage rises above 0.5V. Strike Interval time is
where RI_R is in KΩ and CC_TO is in µF
t = 0.035 RI _ R ⋅ CC _ TO
And Short lamp detection disable time internal is t = 0.005 RI _ R ⋅ CC _ TO
VDDA
Analog Voltage Regulator Output. This output pin is used to connect an external capacitor to stabilize and filter
the on-chip LDO regulator. The input of the LDO is the switched VDDP supply. The LDO output is nominally
4.0V and is used to drive all circuitry except the output buffers at AOUT, BOUT, COUT and DOUT. The drop
out voltage is typically 0.05V at 2mA; the average internal load. This output can supply up to a 5mA external
load. The output capacitor should be a 100nF ceramic dielectric type.
ENABLE
Chip Enable Input. If logic high, all functions are enabled. If logic low, internal power is disconnected from the
VDDP pin, disabling all functions. Logic threshold is 1.85V / 1.35V maximum over supply and temperature
range. Maximum current into VDDP when ENABLE < 0.8V, is 50µA. ENABLE may be connected directly to
VDDP if the disable function is not used
BRITE_D
Brightness Control Input for digital dimming. The input signal can be a DC voltage or low frequency PWM
signal. Active DC voltage range is 0.5V to 2.5V. Signals above 2.5V makes continuous operation, voltages
between 0.5V and 2.5V makes PWM digital dimming. Digital dimming pulse width varies from 100% duty at
2.5V to 0% duty at 0.5V. A minimum BRITE_D input voltage (externally supplied) of approximately TBDV is
required to prevent fault stop. PWM inputs from either 3.3V or 5V logic are permissible. Frequency may range
up to 1KHz. Max jitter of more than 1µs / V on this input may cause noticeable lamp flicker. Refer to Dimming
configuration Table for setting.
VCOMP
Voltage loop compensation pin for transformer output voltage regulation. An external capacitor is connected
from this pin to Ground to adjust loop response. An external resistor divider is connected to limit the maximum
output duty cycle while the IC is operating in strike mode. Recommended resistor divider value are 100K from
VDDA and 300K to GND.
BRITE_A
Brightness control input for analog dimming. The input signal can be a DC voltage or a PWM signal that has
been externally filtered to DC. Active DC voltage range is 0 to 2V. Signals above 2V and below 0.45V are
clamped and do not change amplitude of output current.
VIN_SNS
Input voltage sense pin. An external resistor and capacitor are connected to this pin to control slope of the
frequency tracking oscillator and open lamp voltage regulator timing ramp. Ramp slope becomes steeper as the
external bridge power supply increases providing rapid line voltage transient response.
This feature permits using very low profile transformers that can easily saturate if simultaneously exposed to
both high voltage and high duty cycle operation.
Copyright © 2004
Rev. 1.1, 2/9/2006
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 3
PACKAGE DATA
ICOMP
Error Amp Output for the lamp current regulator. This error amplifier is a gm type and does not require an
external capacitor for stability. An External capacitor is connected from this pin to Ground to adjust loop
response of the inverter module. This capacitor value can vary from 0.1nF to 33nF as required by specific
applications. Error amplifier output voltage is not allowed to exceed the peak voltage of its associated
comparator ramp by more than 10%.
LX1692
®
TM
Full Bridge Resonant CCFL Controller
P RODUCTION D ATA S HEET
FUNCTIONAL PIN DESCRIPTION (CONTINUED)
Description
OC_SNS
Over current sense input. The OC_SNS input is compared to a 2V reference. The comparator output shuts off
the PWM outputs to prevent possible secondary failures. The input voltage at this pin is not rectified. Normal
operating voltage levels will be in the range of ±0.5V to VDDP. An abnormal voltage can operate continuously
as high as ±7V peak under load fault conditions. Transients under fault conditions up to ±11 VPEAK are
permitted. An input voltage above 4 peak but less than ±11V peak may cause saturation but will not cause
malfunction, phase reversal, or reliability issues with the IC.
OV_SNS
Over Voltage Sense Input. This input pin monitors a voltage divider (approximately 1000:1) placed across the
lamp. During strike mode the frequency tracking oscillator uses the voltage waveform from the divider to
determine and track load resonant frequency, and the open lamp voltage regulator uses it to regulate open
circuit voltage. During both run and strike modes, fault detection comparators monitor voltage amplitude to
determine if load opens or shorts occur. See functional description section for details on internal circuit
operation. Frequency range of the input signal is from 30KHz to 150KHz and must not be rectified. Normal
operating voltage levels will be in the range of ±0.5 to ±VDDP peak, centered about +0.2 VDC. An abnormal
voltage can operate continuously as high as ±7V peak under load fault conditions. Transients under load fault
conditions up to ±11V peak are permitted. An input voltage above ±4Vpk may cause saturation, but will not
cause malfunction, phase reversal, or reliability issues with the IC
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Name
ISNS
Current Sense Input. The ISNS input is full wave rectified by an On-Chip circuit, then presented to the inverting
input of the current error amplifier. Frequency range of the input signal is DC to 200KHz. The ISNS pin also
monitors lamp current to determine if the lamp is ignited. If a single cycle at the ISNS pin is greater than 0.7V,
the strike / run flip flop is clocked to the RUN state and threshold of the strike comparator is lowered to 0.3V.
During RUN mode current levels are continuously monitored to detect less than 0.3V. A counter clocked by
RMPD_OUT is reset each time current is sensed at this input. If the counter overflows (256 counts) a fault latch
is set which shuts down the IC. This fault is expected to occur when the lamp is shorted to ground through an
impedance of less than 2K ohms or the ISNS resistor itself is shorted. The counter is inhibited during digital
dimming off time. Normal operating voltage levels will be in the range of ±0.5V to ±5.5V. An abnormal voltage
can operate continuously as high as ±7V peak under load fault conditions. Transients under fault conditions up
to ±11 VPK are permitted. Input voltages up 4V peak are linearly rectified. An input voltage above ±4V peak
but less than ±11V peak may cause saturation but will not cause malfunction, phase reversal, or reliability
issues with the IC.
DOUT
A buffer P-FET driver output. Has a 20K pull up, RDSON nominal = 30 Ω
COUT
A buffer P-FET driver output. Has a 20K pull up, RDSON nominal = 30 Ω
BOUT
A buffer N-FET driver output. Has a 20K pull down, RDSON nominal = 30 Ω
AOUT
A buffer N-FET driver output. Has a 20K pull down, RDSON nominal = 30 Ω
GND
Ground
VDDP
Input Supply Voltage, 4.5V to 5.5V input range. VDDP is switched (see ENABLE) to remove power from chip.
An LDO regulator follows the switch and generates 4.0VDC. The output driver stages are powered directly from
the VDDP input. The output capacitor should be a 1000nF or larger ceramic dielectric type.
PACKAGE DATA
Copyright © 2004
Rev. 1.1, 2/9/2006
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 4
LX1692
®
TM
Full Bridge Resonant CCFL Controller
P RODUCTION D ATA S HEET
ELECTRICAL CHARACTERISTICS
Parameter
`
POWER
Power Supply Input Voltage
Power Supply Output Voltage
VDDP Operating Current
`
`
`
`
`
VDDP
VDD_A
IBB
ENABLE INPUT
ENABLE Logic Threshold
VTH_EN
ENABLE threshold Hysteresis
VH_EN
ENABLE High
VEN_HIGH
ENABLE Low
VEN_LOW
Sleep Mode Current
IDD_SLEEP
Input Resistance
RENR
UNDER VOLTAGE LOCKOUT
UVLO Threshold VDDP
VTH_UVLO_P
UVLO Hysteresis
VH_UVLO
BRIGHTNESS CONTROL
BRITE_A Voltage Range
VR_BR_A
Full Brightness BRITE_A Input
VBR_FULL _A
Full Darkness BRITE_A Input
VDARK_FULL_A
Full Darkness BRITE_A input Offset VDARKFULL_OS
BRITE_D Voltage Range
VR_BR_D
Full Brightness BRITE_D Input
VBR_FULL _D
Full Darkness BRITE_D Input
VDARK_FULL_D
BURST RAMP GENERATOR
Ramp Valley Voltage
VRVV
Ramp Peak Voltage
VRPV
Ramp Frequency
FRamp
Burst Duty Cycle Range
BRITE_D to DIMPWM Jitter
JBDD
Burst PWM min Duty Resolution
DRBST
LAMP FREQUENCY GENERATOR
Lamp Frequency Range
FLAMP
Max Lamp Strike Frequency
FLAMP_STK
Lamp Run Ramp Frequency
Lamp Run Ramp Frequency
Regulation
Ramp Valley Voltage
Ramp Peak Voltage
Ramp PWM Jitter
VIN_SNS RAMP
FLAMP_RUN
FLAMP_REG
VDDP = 4.5V to 5.5V, I Load = 5mADC
CAOUT = CBOUT = CCOUT = CDOUT =2000pF,
fLAMP = 62.5kHz
Min
LX1692
Typ
Max
4.5
3.8
4.0
5.5
4.2
V
V
10
15
mA
1.85
500
2.0
V
mV
V
V
µA
KΩ
1.6
2.4
0
VENABLE = 0V
Rising edge
20
100
3.8
VRPCV
VIN_SNS Discharge Current
IVRVV
VDDP
0.8
50
VR_BR_D = VDDA, TA=25°C
VR_BR_D = VDDA
VR_BR_D = VDDA, BRITE_A = 0V
VR_BR_A = VDDA, TA = 25°C
VR_BR_A = VDDA
VR_BR_A = VDDA
C_BST = 10nF, I_R = 40K
0
1.9
0.35
0.4
2.37
0.43
0.43
2.37
230
0
C_BST = 10nF, BRITE_D = 2.4V
2
0
0.45
2.5
0.55
0.55
2.5
250
1
30
Lamp is not ignited
Lamp Ignited, Run Mode, TA = 25°C, I_R = 40K,
C_R = 100pF
4.5 > VDDP < 5.5V, TA = 25°C
VDDP = 5.5V
60.6
62.5
V
mV
VDDP
2.1
0.55
VDDP
2.63
0.67
V
V
V
V
V
V
V
0.67
2.63
270
100
3
1
V
V
Hz
%
µs
%
150
150
KHz
KHz
64.4
KHz
±0.5
±0.1
%/V
%/°C
V
V
µs
0.2
2.0
1
VIN = 8V, C_P = C_R = 100pF, R_P = TBD,
VDDP = 5V
5
7
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
12.5
Units
4.2
200
VLRVV
VLRPV
LFJ
Ramp Peak Clamp Voltage
Copyright © 2004
Rev. 1.1, 2/9/2006
Test Conditions
70°C except where
VDDP+0
.9
18
V
mA
Page 5
ELECTRICALS
`
Symbol
≤
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Unless otherwise specified, the following specifications apply over the operating ambient temperature -20°C ≤ TA
otherwise noted and the following test conditions:.
LX1692
Full Bridge Resonant CCFL Controller
®
TM
P RODUCTION D ATA S HEET
ELECTRICAL CHARACTERISTICS (CONTINUED)
Parameter
`
`
`
BIAS BLOCK
Voltage at Pin I_R
Pin I_R Max Source Current
STRIKING BLOCK
ISNS Input Strike Threshold
Min ISNS Input Threshold
Lamp current Regulation Reference
Voltage During Strike Period
Number of Zero Crossing Signal
Delay Steps During Strike
Number of Pulses Zero Crossing
Signal per Step During Strike
Initial Delay Time
Last Delay Time
OVSNS Zero Comparator HIGH
OVSNS zero Comparator LOW
OVSNS Peak Comparator High
OVSNS Peak Comparator Low
PROTECTION
Open Lamp Detection Enable
Threshold
Over Voltage Detection Threshold
Over Current Detection Threshold
Open Lamp Striking Time Out
Open Lamp Time Out ( After Ignition)
Short Lamp/Over Current Detection
Enable Threshold
Over Current Time Out
Short Lamp Time Out (Strike)
Short Lamp Time Out (Run)
Over Voltage Time Out
Symbol
V_IR
IMAX_IR
Test Conditions
Min
70°C except where
LX1692
Typ
Max
Units
1.0
75
V
µA
VISNS_STK
VISNSMIN
1.0
0.3
Vpk
Vpk
VREF_STK
2
V
NSTEP
128
Steps
NPS
8
Pulses
3.6
0.3
0.843
-0.443
2.13
-1.73
µs
us
V
V
V
V
VFEN
3.5
V
VOVSTH
VOCTH
3.2
2.0
V
V
TFDLY
TLDLY
VOVZH
VOVZL
VOVPH
VOVPL
TSTKO
TOL
VDCOD
TOC
TSL_STK
TSL_RUN
TOSL
I_R = 40K
≤
After 128 steps
4.5V > VDDP < 5.5V, ISNS = 0V, , C_TO = 1µF,
I_R = 40K, VC_TO > 3.5V
VISNS < 0.3V, VC_TO >3.5V,
Lamp Freq = 60Khz
4.5V > VDDP < 5.5V, ISNS = 0V, C_TO = 1µF,
I_R = 40K
VOC_SNS >2.0V, Lamp Freq = 60Khz
VOV_SNS < 0.5V, VISNS < 1V
VOV_SNS < 0.5V, VISNS > 0.3V
1.2
VOV_SNS > 3.2V, pulsed input
1.4
2.1
1.6
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Unless otherwise specified, the following specifications apply over the operating ambient temperature -20°C ≤ TA
otherwise noted and the following test conditions:.
sec
msec
0.7
V
500
135
500
µsec
msec
µsec
16
count
ELECTRICALS
Copyright © 2004
Rev. 1.1, 2/9/2006
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 6
LX1692
®
TM
Full Bridge Resonant CCFL Controller
P RODUCTION D ATA S HEET
Unless otherwise specified, the following specifications apply over the operating ambient temperature -20°C ≤ TA
otherwise noted and the following test conditions:.
Parameter
`
Test Conditions
Min
70°C except where
LX1692
Typ
Max
Units
PWM BLOCK
ISNS Input Voltage Range
`
Symbol
≤
VR_ISNS
Maximum recommended for linear operation of
error amplifier
-4
OC_SNS Input Voltage Range
VR_OC
-4
OV_SNS Input Voltage Range
VR_OV
-4
VIN_SNS Input Voltage Range
VR_VINS
-0.3
ICOMP Error Amp
ISNS =1.5V
100
220
GM_EAMP
Transconductance
100
ICOMP Output Source Current
IS_EAMP
ΔV_EAIN = 1.0V
ICOMP Output Sink Current
ISK_EAMP
100
ΔV_EAIN = 1.0V
ICOMP Output Voltage Range
VR_EAMP
0
ISNS-BRITE_A Input Offset Voltage
VOS_EAMP
-100
0
ISNS=1.5V, Ta=25°C
ICOMP Discharge Current
ID_ICOMP
10
ICOMP to A/B Output Propagation
1100
TD_COMP
Delay
VCOMP High voltage
VHI_VCOMP VOVSNS = 0V, See Note 1
VDDA
VCOMP Sink Current
ILO_VCOMP
VVCOMP = 2V
1.5
OUTPUT BUFFER BLOCK
Output Resistance
RON_SRC
VDDP = 5V
30
Output Resistance
RON_SINK
VDDP = 5V
30
Pull Up Resistance
RUP
Cout, Dout
20
Pull Down Resistance
RDN
Aout, Bout
20
VDDP-0.4
Output voltage High
VOH
CAOUT = CBOUT= CCOUT = CDOUT=2000pF
Output voltage low
VOL
CAOUT = CBOUT= CCOUT = CDOUT=2000pF
0
Min off time
tOFF
320
Note 1. External resistor divider is connected to Vcomp pin. 100K between VDDA and Vcomp, 300K between Vcomp to GND.
+4
Vpk
+4.0
+4.0
VDDP
Vpk
Vpk
Vpk
410
µmho
VDDA
100
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ELECTRICAL CHARACTERISTICS (CONTINUED)
µA
µA
V
mV
mA
ns
V
mA
VDDP
0.4
Ω
Ω
KΩ
KΩ
V
V
ns
ELECTRICALS
Copyright © 2004
Rev. 1.1, 2/9/2006
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 7
LX1692
®
TM
Full Bridge Resonant CCFL Controller
P RODUCTION D ATA S HEET
SIMPLIFIED BLOCK DIAGRAM
WWW . Microsemi .C OM
VDDA
VDDP
4V
LDO
VDDA
VDDP
Sleep
Logic
SLEEP
C_R
VDDP
Ramp OSC
VDDA
RMP_RST
AOUT
BOUT
Burst
OSC
C_BST
PWM
Block
C_BST
VDDA
Output
Driver
GND
+
0.5V
C_TO
COUT
DOUT
-
+
3.5V
-
1V
+
Fault
Detection &
Timer Logic
VDDA
I_R
VDDP
LDET
-
-
SLEEP
ENABLE
1.0V/0.3V
ISNS
+
FWR
2V
BRITE_A
2V
0
SEL
1
OUT
DIM
+
-
0.45V
-
3.2V
OV_SNS
+
VIN_SNS
RMP_RST
BRITE_D
Resonant
Timing
Detection &
Control
Logic
-
+
ICOMP
DIM
+
-
BLOCK DIAGRAM
C_BST
VCOMP
OC_SNS
+
-
2.0V
Figure 1 – Block Diagram
Copyright © 2004
Rev. 1.1, 2/9/2006
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 8
LX1692
Full Bridge Resonant CCFL Controller
®
TM
P RODUCTION D ATA S HEET
STATE DIAGRAM
WWW . Microsemi .C OM
VIN
QD
QC
COUT_P
AOUT
DOUT_P
DOUT_P
COUT_P
T1
BOUT
C1
AOUT
0
BOUT
QA
56 78
0
1234
5
QB
VIN
VIN
VIN
T1
T1
T1
C1
C1
C1
T0-T1
T1-T2
T2-T3
VIN
VIN
VIN
T1
C1
T1
T1
C1
T3-T4
C1
T4-T5
T5-T6
VIN
VIN
T1
T1
BLOCK DIAGRAM
C1
T6-T7
1234
C1
T7-T8
Figure 2 – State Diagram
Copyright © 2004
Rev. 1.1, 2/9/2006
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 9
LX1692
Full Bridge Resonant CCFL Controller
®
TM
P RODUCTION D ATA S HEET
VIN
CN1
C1 N/U
C10 10µF
R7 47K
D1 5.1V
VDDA
C5 0.1µF
20
VDDA
C2 100pF
2
C3 10nF
3
C4 1µF
4
R1 40K
5
C9 100pF
C_R
AOUT
C_BST
BOUT
VIN
Part
C16 0.1µF
BRITE_A
ISNS
VIN_SNS
OVSNS
BRITE_D
ICOMP
R9
100K
R3 47K
C13 18nF
S2P S1N
U3
R6 R
14
13
12
9
R2 10K
C12 18pF
3KV
G1N D1N
COUT
8
R4 120K
C2 5.1V
16
DOUT
C14 100nF
G2P D2P
GND
ENABLE
T1 1:N
U2
R8 47K
17
7
CN2
CON2
C11 2.2µF
G1N D1N
18
6
G2P D2P
S2P S1N
19
I_R
VDDA
C8 1µF
VDDP
C_TO
VDDP
C17 0.1µF
U1
1
WWW . Microsemi .C OM
TYPICAL APPLICATION
10
C6 15nF
11
VCOMP
OC_SNS
LX1692
C7 10nF
R5
300K
Figure 3 – Schematic
APPLICATIONS
Copyright © 2004
Rev. 1.1, 2/9/2006
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 10
LX1692
TM
®
Full Bridge Resonant CCFL Controller
P RODUCTION D ATA S HEET
FUNCTIONAL DESCRIPTION
Copyright © 2004
Rev. 1.1, 2/9/2006
FAULT PROTECTION
The LX1692 has shut down protection for all common
lamp fault conditions. These include the following:
a. Open or broken lamp
b. High Voltage Arcing on transformer secondary side
c. Short across lamp terminals
d. Short from high side of lamp to ground
e. Short from low side of lamp to ground ( current
sense resistor shorted)
Three inputs from the lamp are monitored to detect these
conditions, ISNS, OV_SNS, and OC_SNS.
Fault
protection is designed to prevent fire or smoke from being
generated by terminating inverter operation in the event of
failures in the high voltage components and the power
FET’s. All fault shut down events can only be reset by
ENABLE or VDDP cycling.
OPEN LAMP
When the IC is first powered on or enabled, the inverter
output voltage must be made higher than the normal
operating voltage of the lamp to cause ignition. The
LX1692 generates this higher “strike” voltage by operating
at the open circuit resonant frequency of the load
inductance and capacitance. Because of its high unloaded
Q, a large resonant rise of voltage occurs across the lamp,
and produces ignition. Both resonant frequency and Q of
the lamp circuit are higher when the lamp is off than when
on. The lamp may not ignite immediately when specified
strike voltage is applied. It is customary to apply strike
voltage for from 0.3 to 3 seconds to insure ignition of cold,
dark, or aged lamps. The LX1692 has a programmable
time out for this purpose. During strike time out, open
lamp voltage is regulated to a value programmed by a
voltage divider across the lamp and sensed at the OV_SNS
pin.
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 1
DESCRIPTION
OSCILLATOR CHARACTERISTICS
The main oscillator in the LX1692 has two frequency
control loops; a resonant tracking loop and a fixed
frequency loop. The fixed frequency loop is user set via the
I_R resistor and the C_R capacitor value. The resonant
tracking loop follows the natural resonant frequency of the
load.
STRIKING THE LAMP
Lamp ignition is determined by monitoring the lamp
current feedback voltage at the ISNS pin. If less than 1.0V
during the strike period, the lamp is considered not ignited
and Strike mode continues until ignition is detected or
strike time out (approximately 1 - 2 seconds) is reached. If
greater than 1.0V, strike is declared and a latch is set. The
IC is now in “run” mode. And threshold voltage for strike
detect is reduced to 0.3V to permit a minimum 3:1 analog
dimming ratio to be achieved.
During strike, lamp operating frequency is always
controlled by the resonant frequency tracking loop. At
power up the lamp is not ignited and the loads’ natural
resonant frequency will be typically1.3 to 1.5 times higher
than after the lamp has ignited.
The tracking oscillator frequency will slew to near the
natural resonant frequency of the load. At open circuit
resonance load Q is high and produces a large rise of
voltage across the lamp, eliminating the need to use a high
transformer turns ratio.
Additionally, since frequency is high, the volt-seconds
applied to the transformer primary is minimized. This
permits the use of smaller transformers that have reduced
core cross sectional area. During striking operation, ICOMP
is limited to 2.5V until ignition latch is set.
When it starts the striking operation, it starts the striking
frequency as user programmed operating frequency.
And when OVSNS is detected zero cross point , then
tracking oscillator will start to sweep the frequency up to
near to the circuit resonant frequency and it will track the
frequency to reach user programmed open lamp voltage.
At the moment of lamp ignition, operating frequency
immediately switches to the programmed value of the fixed
frequency oscillator. Lamp current flow is sensed by the
strike detection comparator, which decides to return PWM
timing control to the fixed frequency oscillator
WWW . Microsemi .C OM
OPERATING MODES
Two operating modes, Strike and Run, are employed by
the LX1692. Upon power up or ENABLE going true, strike
mode is entered. After a successful strike, e.g., lamp is
ignited, run mode is entered. If ignition is unsuccessful, or
if the lamp extinguishes while running, a fault is declared
and the controller automatically shuts down.
LX1692
TM
®
Full Bridge Resonant CCFL Controller
P RODUCTION D ATA S HEET
FUNCTIONAL DESCRIPTION (CONTINUED)
HIGH VOLTAGE ARC OR OVER PROGRAMMED VOLTAGE
If a high voltage arc occurs due to intermittent lamp
contacts or component failure, if the over voltage feedback
divider is improperly designed, or if the open lamp voltage
regulation circuitry fails, the peak voltage on the OV_SNS
pin will rise above + 3.2 VDC. This creates a pulse that
increments a 4 bit accumulating counter. After 16 events
are counted, an open lamp fault is declared and the IC
outputs are latched off. This fault is enabled at all times,
including during lamp striking. The 4 bit counter is reset
by signal C_BST which typically operates at 100 to 300
Hz. Also, OVSNS pin voltage is greater than 3.2V, then
ICOMP pin will be forced to discharge to 0V about 600ns.
OPEN LAMP VOLTAGE REGULATION
The open lamp voltage regulator regulates the peak voltage
on the OV_SNS pin to ±1.97 volts, + the 0.2 volt offset,
with a maximum tolerance ±8% (±158 mV). Assuming an
additional ±5% tolerance for each of the two capacitors or
resistors in the high voltage divider, maximum open lamp
voltage tolerance at the system level is ±18%. At the high
side of tolerance, OV_SNS peak voltage is +2.42V, on the
low side of tolerance, OV_SNS input voltage will be
regulated at +1.914 VPK. If tighter total voltage regulation
is needed in a given application, the feedback divider can
be made with 1% resistors.
INTERMITTENT OR BROKEN LAMP AFTER SUCCESSFUL
SHORT CIRCUITS ACROSS THE LAMP TERMINALS AND
SHORTS FROM THE HIGH VOLTAGE TERMINAL TO
GROUND.
Soft shorts, including the UL safety test that places a 2K
ohm resistor across the lamp connector, are normally not a
problem because the current regulation circuitry limits
current flow to the normal lamp amplitude. However, if
the short is strong enough to lower the voltage at the
OV_SNS pin to less than 0.7 volts peak, the 7 bit shorted
lamp time out counter reset is blocked. If this counter
overflows a fault is declared and the IC outputs are latched
off. This fault detection is enabled during both strike and
run modes. This fault detection is disabled until voltage at
C_TO rises above 0.5V. The watch dog counter is not
allowed to increment during digital dimming off time
while in run mode. This fault will also be generated In the
event of a hard short directly across the lamp terminals, or
from the high voltage terminal to ground.
WWW . Microsemi .C OM
Strike time out is programmed by selecting the capacitor
value at the C_TO pin. If the lamp has not ignited before
the end of strike time out, a fault is declared and the IC
outputs are latched off.
SHORT CIRCUITS FROM GROUND TO THE LOW SIDE LAMP
TERMINAL.
A Short to ground from the lamp return terminal also
shorts out the lamp current sense resistor, removing current
feedback to the controller. This short is detected as a rise
in voltage across the OC_SNS resistor which is located on
the normally grounded side of the HV transformer
secondary. A comparator senses peak voltage > 2.0VDC at
the OC_SNS pin. This comparator clocks the 4 bit watch
dog timer described above in the open lamp fault logic.
Sixteen events during a single cycle of the C_BST signal
will overflow the watchdog counter and cause an over
current shut down during either strike or run mode.
IGNITION
Copyright © 2004
Rev. 1.1, 2/9/2006
ON CHIP LDO REGULATOR
Output voltage is 4.0 ±5%. Supplies all internal
circuitry except output driver stage. Capable to source
5mA to external circuitry.
UNDER VOLTAGE LOCKOUT
Keeps chip outputs active off until VDDA is high
enough to insure stable operation.
DIMMING MODES
Separate input pins are available for digital and analog
dimming modes for maximum flexibility. See dimming
truth table below. Digital dimming rise and fall times can
be controlled by the ICOMP capacitor (See Dimming
Modes Table).
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 2
DESCRIPTION
After run mode is entered, an intermittent or open lamp
problem can also be detected at the ISNS input. After
ignition, peak voltage on the ISNS input is dependent on
lamp current amplitude and voltage on the BRITE_A pin.
I_SNS signal amplitude should be designed to be greater
than ±400 mVPK (280 mVRMS) to insure a false open lamp
fault shut down does not occur. A comparator monitors
ISNS and generates a reset pulse to a watch dog timer for
any peak voltage > 0.3V. The watch dog, a 9 bit binary
counter, is reset once every cycle of I_SNS voltage. If
lamp current flowing through the ISNS resistor is too low
(e.g., voltage is less than 0.3V peak), reset pulses are not
generated and the counter is allowed to overflow and set the
fault latch. Nominal short circuit duration is 500 micro
seconds when operating at 65KHz.
LX1692
Full Bridge Resonant CCFL Controller
®
TM
P RODUCTION D ATA S HEET
DIMMING MODES
BRITE A
BRITE D
DC voltage controlled analog
0 – 2V
VDDA
DC voltage controlled reverse analog
VDDA
VDDA
ISNS
0–2V
CBST
I Range
cap
3:1
cap
1:3
External PWM controlled digital
VDDA
PWM
cap
60:1
DC voltage controlled digital
VDDA
0.5-2.5V
Cap
30:1
Analog + voltage controlled Digital
0 -2V
0.5-2.5V
Cap
60:1
WWW . Microsemi .C OM
MODE
APPLICATIONS
Copyright © 2004
Rev. 1.1, 2/9/2006
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 3
LX1692
Full Bridge Resonant CCFL Controller
®
TM
P RODUCTION D ATA S HEET
PACKAGE DIMENSIONS
20-Pin Thin Small Shrink Outline (TSSOP)
Dim
A
A1
A2
b
c
D
E
E1
e
L
Θ1
*LC
3 2 1
E
E1
e
D
1
A2 A
SEATING PLANE
DW
WWW . Microsemi .C OM
PW
b
L
A1
c
MILLIMETERS
MIN
MAX
1.10
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
6.40
6.60
6.25
6.55
4.30
4.50
0.65 BSC
0.45
0.75
0°
8°
0.10
INCHES
MIN
MAX
0.043
0.002
0.006
0.031
0.041
0.007
0.012
0.004
0.008
0.252
0.260
0.246
0.258
0.169
0.177
0.026 BSC
0.018
0.030
0°
8°
0.004
20-Pin Plastic (SOWB) Wide body SOIC
A
20
11
P
B
1
G
10
D
F
L
C
Seating Plane
J
M
K
MILLIMETERS
MIN
MAX
12.65
12.85
7.49
7.75
2.35
2.65
0.25
0.46
0.64
0.89
1.27 BSC
0.23
0.32
0.10
0.30
8.13
8.64
0°
8°
10.26
10.65
0.10
−
INCHES
MIN
MAX
0.498
0.506
0.295
0.305
0.093
0.104
0.010
0.018
0.025
0.035
0.050 BSC
0.009
0.013
0.004
0.012
0.320
0.340
0°
8°
0.404
0.419
0.004
−
*Lead Coplanarity
Note:
1. Dimensions do not include mold flash or protrusions; these
shall not exceed 0.155mm(.006”) on any side.
Lead
dimension shall not include solder coverage.
Copyright © 2004
Rev. 1.1, 2/9/2006
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 4
MECHANICALS
Dim
A
B
C
D
F
G
J
K
L
M
P
*LC
LX1692
TM
®
Full Bridge Resonant CCFL Controller
P RODUCTION D ATA S HEET
NOTES
WWW . Microsemi .C OM
NOTES
PRODUCTION DATA – Information contained in this document is proprietary to
Microsemi and is current as of publication date. This document may not be modified in
any way without the express written consent of Microsemi. Product processing does not
necessarily include testing of all parameters. Microsemi reserves the right to change the
configuration and performance of the product and to discontinue product at any time.
Copyright © 2004
Rev. 1.1, 2/9/2006
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 5