RangeMAX™ I N T E G R A T E D LX1688 MULTIPLE LAMP CCFL CONTROLLER P R O D U C T S KEY FEATURES DESCRIPTION generation technique. Safety and reliability features include a dual feedback control loop that permits regulation of maximum lamp strike voltage as well as lamp current. Regulating maximum lamp voltage permits the designer to provide for ample worst-case lamp strike voltage while conservatively limiting maximum open circuit voltage. In addition the controller features include auto shutdown for an open or broken lamp, and a lamp fault detection with a status reporting output. To improve design flexibility the IC includes the ability to select the polarity of both the chip enable and dim (BRITE) inputs. Also included is a switched VDD output of up to 10mA that will allow the user to power other circuitry that can be switched on and off with the inverters enable input. This preserves the micro power sleep mode with no additional components. WWW . Microsemi .C OM The LX1688 is a fixed frequency, dual current/voltage mode, switching regulator that provides the control function for Cold Cathode Fluorescent Lighting (CCFL). This controller can be used to drive a single lamp, but is specifically designed for multiple lamp LCD panels. The IC can be configured as a master or slave and synchronize up to 12 controllers. The LX1688 includes highly integrated universal ‘PWM or DC’ dim input that allows either a PWM or DC input to adjust brightness without requiring external conditioning, since a single external capacitor CPWM can be used to integrate a PWM input. Burst mode dimming is possible if the user supplies a low frequency PWM signal on the BRITE input and no CPWM capacitor is used. The controller utilizes Linfinity’s patented direct drive fixed frequency topology and patented resonant lamp strike Provision to synchronize lamp current & frequency with other controllers Dimming with analog or digital (PWM) methods (>20:1) Programmable Fixed frequency Adjustable Power-up reset ENABLE/BRITE Polarity Selection Voltage limiting on step-up transformer secondary winding Open lamp timeout circuitry Switched VDD output (10mA) Micro-Amp Sleep Mode Operates with 3.3V to 5V Supply 100mA output drive capability APPLICATIONS/BENEFITS Desktop LCD Monitors Multiple lamp panels Low Ambient Light Displays High Efficiency Lower Cost than Conventional Buck/Royer Inverter Topologies Improved Lamp Strike Capability Improved Over-Voltage Control IMPORTANT: For the most current data, consult MICROSEMI’s website: http://www.microsemi.com PRODUCT HIGHLIGHT D IM M IN G (B R IT E ) ENABLE RAMP RESET 24 13 LX1688 MASTER FETS 12 IN P U T CO NNECTO R PHASE SYNC LAM PS 125 Hz 5% Duty cycle Burst 65KHz run frequency S T R IK E STATUS FAULT 1 FAULT 1 ENABLE B R IT E FAULT 2 24 13 FETS 12 LX1688 SLAVE LX1688 S T R IK E STATUS VDD FAULT 2 Ch3 10.0mV Ω Ch2 10.0mV Ω M 100µs Simplified quad lamp inverter showing synchronized output waveforms PACKAGE ORDER INFO Copyright 2001 Rev. 1.1a, 2003-03-21 TJ (°C) MIN VDD MAX VDD 0 to 70 -40 to 85 3.0V 3.0V 5.5V 5.5V PW Plastic TSSOP 24-Pin LX1688CPW LX1688IPW Microsemi Integrated Products, Power Management 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 1 RangeMAX™ I N T E G R A T E D LX1688 MULTIPLE LAMP CCFL CONTROLLER P R O D U C T S PACKAGE PIN OUT Supply Voltage (VDD_P, VDD) ....................................................................... 6.5V Digital Inputs ..............................................................................-0.3V to VDD +0.5V Analog Inputs ............................................................................–0.1V to VDD +0.5V Digital Outputs .......................................................................... -0.3V to VDD +0.5V Analog Outputs ......................................................................... -0.1V to VDD +0.5V Operating Junction Temperature ..................................................................125°C Storage Temperature ....................................................................................150°C Lead Temperature (Soldering, 10 Seconds) .................................................300°C AOUT VSS_P VSS BEPOL BRITE CPOR ENABLE I_R CPWM1 CPWM2 RMP_RST PHA_SYNC Note 1: Exceeding these ratings could cause damage to the device. All voltages are with respect to Ground. Currents are positive into, negative out of the specified terminal. 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 BOUT VDD_P VDD VDDSW TRI_C OLSNS ISNS ICOMP VCOMP VSNS SLAVE FAULT PWPACKAGE (Top View) WWW . Microsemi .C OM ABSOLUTE MAXIMUM RATINGS THERMAL DATA PW Plastic TSSOP 24-Pin THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA 100°C/W Junction Temperature Calculation: TJ = TA + (PD x θJC). The θJA numbers are guidelines for the thermal performance of the device/pc-board system. All of the above assume no ambient airflow. FUNCTIONAL PIN DESCRIPTION Pin Name AOUT VSS_P VSS BEPOL BRITE CPOR ENABLE I_R CPWM1 RMP_RST PHA_SYNC Copyright 2001 Rev. 1.1a, 2003-03-21 Output Driver A Connects to dedicated GND for Aout and Bout Drivers Connects to analog GND Tri-mode input pin to control the polarity of the ENABLE and BRITE signal Analog/PWM input for brightness control Connects an external capacitor CPOR to VDD and is used for setting power-up reset pulse width. Pin Name BOUT TRI_C Output Driver B Connects to dedicated VDD for Aout and Bout Drivers Connects to analog VDD Switchable VDD output controlled by ENABLE Connects to external capacitor CTRI OLSNS Analog input to detect open-lamp condition VDD_P VDD VDDSW Used to enable or disable the chip ISNS Connects to external resistor RI; for bias current setting for internal oscillator Connects to external capacitor CPWM, used for integrating an external digital PWM signal for analog dimming Connects to external capacitor CPWM, used for integrating an external digital PWM signal for analog dimming. If SLAVE = “0”, RMP_RST is a CMOS output; if SLAVE = “1”, it is a CMOS input that locks the ramp oscillation frequency to the master clock If SLAVE= “0”, PHA_SYNC is a CMOS output; if SLAVE = “1”, it is a CMOS input that make the AOUT/BOUT phase synchronous with the master Description ICOMP VCOMP VSNS Analog input from lamp current, has built-in 300mv offset Current error Amp’s output; connects to external capacitor CICOMP Voltage error Amp’s output; connects to external capacitor CVCOMP, can be used for soft-start Analog input voltage from transformer output SLAVE Input control pin for setting the IC either in Master or Slave mode; “1” for slave mode and “0” for master mode. FAULT Digital output to indicate maximum number of lamp striking attempts has occurred without lamp ignition. Microsemi Integrated Products, Power Management 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 2 PACKAGE DATA CPWM2 Description RangeMAX™ I N T E G R A T E D LX1688 MULTIPLE LAMP CCFL CONTROLLER P R O D U C T S RECOMMENDED OPERATING CONDITIONS LX1688 Typ Min Units Max Supply Voltage (VDD ,VDDP) 3 5.5 V BRITE Linear DC Voltage Range 1 2.5 V BRITE PWM Logic Signal Voltage Range 0 VDD V Digital Inputs (SLAVE, PHA_SYNC, RMP_RST, BEPOL, ENABLE ) 0 VDD V ELECTRICAL CHARACTERISTICS O WWW . Microsemi .C OM Parameter O Unless otherwise specified, specifications apply over the range: TA=-40 to 85 C, VDD (For LX1688IWP) & TA= 0 to 70 C, VDD (For LX1688CWP), VDD_P = 3.0 to 5.5V. RI = 80Kohms, CTRI = 0.083µF Parameter Symbol Test Conditions Min LX1688 Typ. Max Units Dimmer Conventional¹ Dimming BRITE Input Voltage VBRITE_MAX VBEPOL = VDD 2.6 2.5 VBRITE_MIN VBEPOL = VDD 0.4 0.5 Reverse Dimming BRITE Input Voltage VBRITE_MAX VBEPOL = VSS or float 0.4 0.5 VBRITE_MIN VBEPOL = VSS or float 2.6 2.5 Max Brightness VBRT Voltage VBRT_FULL VBEPOL = VSS, VBRITE = 0.4V 1.90 2.0 2.05 Full-darkness VBRT voltage VBRT_DARK VBEPOL = VSS, VBRITE = 2.6V V V V 0 0.05 V ISNS input threshold voltage VTH_IAMP TA= 0 to 70 C 150 300 450 mV ISNS input threshold voltage VTH_IAMP TA=-40 to 85 C O 150 300 550 mV BRITE-to-ICOMP propagation delay TD_BRITE O 2 µS Strike and Ramp Generator Max. number of strike before fault Triangular Wave Generator Analog Output Peak Voltage Triangular Wave Generator Analog Output Valley Voltage Triangular Wave Generator Oscillation Frequency Max. Lamp Strike Frequency NFAULT 63 VP_TRI 2.3 2.5 2.6 V VV_TRI 0.15 0.3 0.40 V F_TRI 7 10 13 Hz 150 195 60 65 70 KHz 57 65 70 KHz 4 6 % /V 650 800 840 ‘mV 300 400 500 ‘mV 1 us FMAX_STK Lamp Run Frequency FLAMP Lamp Run Frequency FLAMP FLAMP_REG OLSNS threshold voltage VTH_OLSNS OLSNS hysteresis VH_OLSNS OLSNS-to-ICOMP propagation delay Fault, PHA_SYNC, RMP_RST, logic high threshold Fault, PHA_SYNC, RMP_RST, logic low threshold TD_OLSNS Minimum Fault-pin output current I_FAULT VOLSNS > 0.65V GBNT ² KHz VDD – 0.5 VH V 0.7 VL 10 ELECTRICALS Lamp Run Frequency regulation over VDD FMAX_STK = FLAMP X ~2.5 VOLSNS > 0.65V; VDD=5V O TA= 0 to 70 C VOLSNS > 0.65V; VDD=5V O TA=-40 to 85 C 15 1 V ‘mA ¹Conventional polarity means that the lamp brightness increases with increasing voltage on the BRITE pin. Reverse polarity means that brightness decreases with increasing voltage ² Guaranteed but not production tested Copyright 2001 Rev. 1.1a, 2003-03-21 Microsemi Integrated Products, Power Management 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 3 RangeMAX™ I N T E G R A T E D LX1688 MULTIPLE LAMP CCFL CONTROLLER P R O D U C T S ELECTRICAL CHARACTERISTICS (CONTINUED) Symbol Test Conditions Min LX1688 Typ. Max Units Strike and Ramp Generator (continued) Minimum PHA_SYNC-pin output current I_PHA_SYNC VSLAVE = 0V 10 Minimum RMP_RST-pin output current I_RMP_RST VSLAVE = 0V 10 Minimum A_SYNC output pulse duty-cycle DO_ASYNC VSLAVE = 0V 49 50 Minimum A_SYNC input pulse duty-cycle DI_ASYNC VSLAVE = VDD 48 50 % Minimum RMP_RST output pulse duty-cycle DO_RST VSLAVE = 0V 10 17 % Minimum RMP_RST input pulse duty-cycle DI_RST VSLAVE = VDD 5 ‘mA mA % % Output Buffer Output Sink Current ISK_OUTBUF Output Source Current IS_OUTBUF Output Sink Current ISK_OUTBUF VAOUT, BOUT = 1V VDD = 5.5V VAOUT, BOUT = 4.5V VDD = 5.5V VAOUT, BOUT = 1V, VDD = 3V 100 ‘mA 100 ‘mA 50 ‘mA Output Source Current IS_OUTBUF VAOUT, BOUT = 2V, VDD = 3V 50 ‘mA Output Sink Current ISK_OUTBUF VAOUT, BOUT = 1V, VDD = 5.5V 100 ‘mA WWW . Microsemi .C OM Parameter PWM VSNS threshold voltage VTH_VSNS VCOMP Discharge Current ID_VCOMP IAMP transconductance GM_IAMP 1.2 1.25 1.3 ∆ISNS = 0.2V 100 200 V ‘mA 4 500 µmho µA IS_IAMP VCOMP, ICOMP = 0 75 VAMP, IAMP output sink current ISK_IAMP VCOMP, ICOMP =VDD 75 µA ICOMP discharge current ID_ICOMP 10 ‘mA VAMP, IAMP output source current ∆VSNS = 0.1V VAMP transconductance GM_ICMP ICOMP-to-output propagation delay TD_ICOMP 200 500 800 µmho nS 1100 BIAS Voltage at Pin I_R 0.95 V_IR Pin I_R max. source current IMAX_IR Power-on Reset Pulse Width TPOR CPOR =.1uF Minimum VDDSW sourcing Current IMIN_VDDSW VDDSW Off Current IOFF_VDDSW (VDD – VDDSW ) < 0.2V VENABLE = 0.8V, VBEPOL = VDD VDDSW = 0V 10 1.05 V 50 µA 31 mS 25 ‘mA 1 15 5.5 8 2 4 1.7 2.4 µA General Operating Current VDD = VDD_P = 5V VOLSNS = VDD = VDD_P = 5V, CA = CB = 1000pF IDD Output buffer operating current IDD_P VTH_EN ENABLE threshold hysteresis VTH_EN Sleep-mode current (see table-1 for Pin ENABLE polarity) VDD_P Leakage in Sleep Mode 0.8 IDD_SLEEP IDD_SLEEP IDD_SLEEP IDD_SLEEP UVLO threshold UVLO hysteresis Copyright 2001 Rev. 1.1a, 2003-03-21 VTH_UVLO VH_UVLO V V 0.2 VENABLE = 0.8V (VBEPOL = VDD or float) VENABLE = 2.5V (VBEPOL = VDD or float) VENABLE = 0.8V (VBEPOL = VSS) VENABLE = 2.5V (VBEPOL = VSS) Rising turn-on threshold mA ELECTRICALS ENABLE logic threshold mA 20 50 20 50 20 300 20 300 2.8 2.9 µA 2.6 Falling turn-off hysteresis Microsemi Integrated Products, Power Management 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 190 V mV Page 4 RangeMAX™ I N T E G R A T E D LX1688 MULTIPLE LAMP CCFL CONTROLLER P R O D U C T S ISNS Input Threshold Voltage Vs Temperature Typical Operating Current (VDD) 6 380 360 5.5 340 VDD=5.5V ISNS Input Threshold (V) VDD Input Current (mA) WWW . Microsemi .C OM CHARACTERISTIC CURVES 5 4.5 VDD=3V 4 3.5 320 VDD=5.5V 300 280 260 240 VDD=3V 220 200 3 -40 180 -15 10 35 Temperature (°C) 60 85 -40 35 60 85 Under Voltage Lockout Vs Temperature 70 2.9 68 2.85 VDD=5V UVLO Thresholds (V) Output Frequency (KHz) 10 Temperature (°C) Output Frequency Vs Temperature 66 -15 64 62 VDD=3V 60 58 Turn On 2.8 2.75 2.7 2.65 Turn Off 2.6 2.55 56 2.5 -40 -15 10 35 60 85 -40 -15 10 35 60 85 Temperature (°C) T emperature (°C) Power-on-Reset Pulse Width Vs Temperature VDD=5V I_R Voltage Vs Temperature VDD=V 1.010 40 1.008 35 TPOR(mS) I_R Voltage (V) 1.006 1.004 1.002 30 25 1.000 20 0.998 Copyright 2001 Rev. 1.1a, 2003-03-21 -15 10 35 Temperature (°C) 60 85 15 -40 -15 10 35 Temperature (°C) Microsemi Integrated Products, Power Management 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 60 CHARTS 0.996 -40 85 Page 5 RangeMAX™ I N T E G R A T E D LX1688 MULTIPLE LAMP CCFL CONTROLLER P R O D U C T S TABLE 1 ENABLE POLARITY DIMMING POLARITY* VDD + (HI = CHIP_ON, LOW = CHIP_OFF CONVENTIONAL FLOAT + (HI = CHIP_ON, LOW = CHIP_OFF) REVERSE VSS - (LOW = CHIP_ON, HI = CHIP_OFF) REVERSE * Conventional polarity means that the lamp brightness increases with increasing voltage on the BRITE pin. Reverse polarity means that brightness decreases with increasing voltage OPERATIONAL MODES Controller Mode Controller Operation Input Pin: OLSNS Input Pin: SLAVE Output Pin: FAULT Pin: RMP_RST Pin: A_SYNC Run > 0.6V VSS L Output: FINT Output: FINT / 2 Striking < 0.2V VSS L Output: FINT Output: FINT / 2 Master Slave Fault X VSS H Output: FINT Output: FINT / 2 Run > 0.6V VDD L Input: FEXT Input: FEXT / 2 Striking < 0.2V VDD L Input: FEXT Input: FEXT / 2 Fault X VDD H Input: FEXT Input: FEXT / 2 Lamp Frequency WWW . Microsemi .C OM Pin BEPOL FINT / 2 Ramping up / down Off FEXT / 2 Ramping up / down Off BLOCK DIAGRAM ISNS VSNS VCOMP ICOMP FEXT/2 ERROR AMP TFF R PHA_SYNC Q PWR_ GD VAMP RAMP RUN GENERATOR FINT SLAVE RMP_RST FAULT Q 300mV 1V 200K + - 1V B OUT CURRENT COMPARATOR IAMP VSS_P + BRT 2.5V BRITE PWR_ GD PWR_BD FAULT OUTPUT STEERING LOGIC STRIKE GENERATOR FEXT A OUT Q 1.25V PWR_ BD T VDD_P VOLTAGE COMPARATOR 100K + - 100K 100K 100K 0-2V 800mV 600mV IGNITE OLSNS 0.5V CPW 1 1M BEPOL 1M PWR_ BD TRI WAVE GEN 6 BIT COUNTER TRI_C VDD POLARITY DECODE BIAS GEN UVLO PWR_GD FAULT ENABLE BLOCK DIAGRAM CPW 2 PWR_BD TTL BUF TTL BUF FAULT INTERNAL VDD VDDSW VSS VSS Copyright 2001 Rev. 1.1a, 2003-03-21 VDD I_R CPOR Microsemi Integrated Products, Power Management 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 6 RangeMAX™ I N T E G R A T E D LX1688 MULTIPLE LAMP CCFL CONTROLLER P R O D U C T S The LX1688 is a backlight controller specifically designed with a special feature set needed in multiple lamp desktop monitors, and other multiple lamp displays. While utilizing the same architecture as Linfinity’s LX1686 controller it eliminates the synchronized digital dimming and adds, lamp ‘strike’ count out timer, lamp fault status output, and external clock input/output that permits multiple controllers to synchronize their output current both in frequency and phase. Operation From 3.3V and/or 5.0V Input Supply The LX1688 is designed to operate and meet all specifications at 3.3V ±10% to 5.0V ±10%. The under voltage lockout is set at nominally 2.8V with a 190mV hysteresis. Copyright 2001 Rev. 1.1a, 2003-03-21 BEPOL Input The BEPOL pin is a tri-mode input that controls the polarity of the ENABLE and BRITE input signals. Depending on the state of this pin (VDD, floating, or VSS) the controller can be set to allow active high enable with active high full brightness or active high or low enable with active low full brightness (see Table 1). BRITE Input (Dimming Input) The BRITE input is capable of accepting either a DC voltage (≥.5V to ≤2.5V) or a PWM digital signal that is clamped on chip (<.5V or >2.5V). A digital signal can either be passed unfiltered to effect pulse ‘digital’ dimming or filtered with a capacitor to effect analog dimming with a digital PWM signal. Analog Dimming Methods: • Mechanical or digital potentiometer set to provide 1V to 2.5V on the wiper output. A filter cap from BRITE to signal ground is recommended. • D/A converter output directly connected to BRITE input. A R/C filter using a capacitor from the CPW1 input to ground for applications where the ADC output may contain noise sufficient to modulate the BRITE input. • A high frequency PWM digital logic pulse connected directly to the BRITE input. The Brightness (BRT, internal node) output will be sensitive only to the PWM duty cycle, and not to the PWM signal amplitude, so long as the amplitude exceeds 2.6V for a logic high (1) and is less than .4V for a logic (0). This pulse frequency will typically be between 1KHz and 100KHz and will not be synchronized with the LCD video frame rate. A capacitor (CPWM) between CPW1 and CPW2 will integrate the PWM signal for use by the controller. Digital Dimming Methods: • Low frequency PWM digital logic pulses connected directly to the BRITE input. As above the Brightness (BRT internal) will be sensitive only to the PWM duty cycle, and not to the PWM signal amplitude, so long as the amplitude exceeds 2.6V for a logic high (1) and is less than .4V for a logic (0). This pulse frequency will typically be in the range of 90-320Hz Microsemi Integrated Products, Power Management 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 7 DESCRIPTION Master/Slave Clock Synchronization One or more controllers (up to 11) may be designated as slave controllers and receive ramp reset and phase synchronization from the designated master controller. This will allow up to 12 lamps (24 with two lamps in series/controller design) to all operate in phase and frequency synchronization. This is important to prevent random interference between lamps through unpredictably changing electric and magnetic fields that will inevitably link them. The LX1688 has two independent oscillators, one for lamp strike and one for the lamp run frequency. The strike oscillator ramps the operating frequency slowly up and down when the open lamp sense input (OLSNS) indicates the lamp is not ignited. During this lamp strike condition the operating frequency of each IC will vary up and down as needed to strike its lamp. The controller is so designed that the master controller clock remains at the pre-selected frequency for fully ignited lamps even while striking. Likewise the designated slave controller will not alter the frequency or phase of the master clock during its strike phase. Thus each controller will vary its frequency as needed to strike its lamp then it will synchronize to the master clock frequency and phase. The TRI_C wave generator (see Block Diagram) sets the rate of operating frequency variation during lamp strike. The TRI_C generator is connected to a 6-bit counter that times out after 63 cycles and then latches the FAULT output high if the OLSNS input indicates no lamp current is flowing. Even in the case of timeout fault the master controller clock will continue to provide synchronization to the slave controllers. When synchronizing more than one controller the Ramp Reset (RMP_RST), Phase Sync (PHA_SYNC), and Slave Input/Output are used. RMP_RST and PHA_SYNC should be connected between all the controllers. The master controller should have its SLAVE pin connected to VSS (GND) and the slave controllers SLAVE input to VDD (High). WWW . Microsemi .C OM DETAILED DESCRIPTION RangeMAX™ I N T E G R A T E D LX1688 MULTIPLE LAMP CCFL CONTROLLER P R O D U C T S DETAILED DESCRIPTION (CONTINUED) I_R Pin The run mode frequency of the output is one half the internal ramp frequency, which is proportional to a bias current set by resistor RI of 80.6K. The output frequency can thus be adjusted by varying the value of RI-R, the typical range from about 50K to 100K. Since there is some variation in the frequency due to change in the input supply (VDD) it is recommended that the value of RI-R be selected at the nominal input voltage. Sleep Mode (ENABLE Signal) and Switched VDD (VDDSW) Since the LX1688 can be used in portable battery operated systems, a very low power sleep mode is included. The IC will consume less than 10µA quiescent current from both the VDD and VDD_P pins combined, when the ENABLE pin is deactivated. The polarity of the ENABLE pin is programmable by the BEPOL input (see table 1). In addition the controller provides a switched supply pin VDDSW this output supplies at least 10mA at VDD ─ .2V for external circuitry. This output can be used to power additional circuitry that can be enabled with the controller. WWW . Microsemi .C OM and may or may not be externally synchronized to the LCD video frame rate. It will directly gate the signal BRT. CPWM should not be used in this case. Fault Pin The fault pin is a digital output that indicates that the maximum numbers of strike attempts has occurred without lamp ignition. In this condition the FAULT pin will go active high with typically 20mA drive capability. Holding the OLSNS pin low (<200mV) will also force timeout and activate the FAULT pin. When used as a master, fault condition true does not inhibit master clock outputs PHA_SYNC and RMP_RST. BIAS & TIMING EQUATIONS Formula 1: Formula 2: Triangular Wave Generator Frequency, FTRI Lamp Frequency (AOUT’s switching frequency), FLAMP FTRI = 1 [Hz] (25 × RI × CTRI ) FLAMP = 1 [Hz] 200e-12 × RI Formula 3: Formula 4: Minimum Current Error Amp Bandwidth, BWIEA_MIN Minimum Voltage Error Amp Bandwidth, BWVEA_MIN BWIEA_MIN = 0.000048 [Hz] CICOMP BWVEA_MIN = 0.000048 [Hz] CVCOMP Formula 5: Formula 6: Softstart time, TSS Minimum Power-on Reset Pulse Width, TMIN_POR Copyright 2001 Rev. 1.1a, 2003-03-21 TMIN_POR = 2.3e6 × CPOR [sec] Microsemi Integrated Products, Power Management 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 DESCRIPTION TSS = 4,500,000 × CVCOMP [sec] Page 8 RangeMAX™ I N T E G R A T E D LX1688 MULTIPLE LAMP CCFL CONTROLLER P R O D U C T S CN1 1 VIN C1 VIN 2 GND 3 GND 4 5 VBRITE 6 RMP_RST 7 PHA_SYNC 8 ENABLE 9 10 VDDSW 10% 470nF 16V U2 SI9945AEY 8 RMP_RST PHA_SYNC R4 39 7 2 6 VDDP R5 39 5 4 C13 0.1uF 50V T1 1:75 5 3 2 4 1 C12 C14 VDDP Q2 BC847ALT1 Q1 + 1 R8 100K 2 1 R6 C2 1 16V 10% 470nF 2 Analog Ground must connect to power ground at this point only 3 4 VDD 5 10nF 16V C3 10% R1 80.6K 1% 6 7 8 9 10 RMP_RST PHA_SYNC 11 12 AOUT BOUT VSS_P VSS VDD_P VDD BEPOL VDD_SW BRITE CPOR ENABLE TRI_C OLSNS ISNS ICOMP I_R CPWM1 VCOMP CPWM2 VSNS RMP_RST SLAVE PHA_SYNC FAULT 23 20 C6 82nF 17 16 15 14 2.2nF 50V 5% COG VDD VDDSW 18 10K C15 R2 47 22 19 D1 R7 3 BAW56 82 24 PCB BC847ALT1 220µ 25V 3 2.2PF CN2 1 HV1 2 LV1 WWW . Microsemi .C OM TYPICAL APPLICATION 16V 10% C8 C5 220nF 16V 10% C7 16V 10% 100nF 2.2nF 16V 5% C9 4.7nF 16V 10% 10nF 16V 10% C11 10nF 16V 10% C10 C4 220nF 16V 10% VDD R9 1K 1 2 D2 3 BAW56 R12 R10 1M D3 3 BAV99 2 1 2.74K 1% C16 3.3nF COG 50V 5% R11 2.74K 1% 13 LED1 R3 220 OPTION Figure 1- Schematic for LX1688 Inverter Module configured as a Master APPLICATIONS Copyright 2001 Rev. 1.1a, 2003-03-21 Microsemi Integrated Products, Power Management 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 9 RangeMAX™ I N T E G R A T E D LX1688 MULTIPLE LAMP CCFL CONTROLLER P R O D U C T S Application example with LX1688 This section will highlight the features of LX1688 controller by showing a practical example. Three identical inverter modules are connected to each other and each module drives a single lamp. One module configured as a master and two others configured as slaves. A complete schematic hooked up a a master is given in Figure 1, the schematic provides all necessary functions such as high voltage feedback for regulation the peak lamp voltage, short-circuit protection, open lamp sensing and lamp current regulation needed for a typical application. The section follows with measurement waveforms and list of material of the actual modules. For more detail design procedure and circuit description please refer to application note (AN-13), which is available in Microsemi’s web site. Input Voltage The LX1688 controller can operate at 3.3 to 5.0V ±10%, in this application all modules were driven by the same power voltage (a constant 5.0V), which provides VDD for controllers, and input voltage for the power section. Notice that VDD feeds all analog signals and VDD_P feeds only the output driver stage, these two signals should be filtered separately (Figure 1). Setting lamp frequency The value of R1 determines magnitude of internal current sources that set timing parameters. Equation (2) gives the relationship between Lamp frequency (FLAMP) and (RI_R), R1 in schematic. For this application we choose R6=80.6 Kohm, which results to a lamp frequency at 62.0 KHz. Setting Master/Slave configuration Simply connecting pin 14 to the ground for a master and to the VDD for a slave will do master and slave configuration. As shown in figure 2, module (A) configured as master and modules (B) and (C) configured as slaves. Synchronization of Frequency and Phase To synchronize the Lamp frequency and phase of all modules, it is required to connect the RMP_RST pin of all the modules together and connect PHA_SYNC pin of all the modules together. Layout consideration By designing the layout in a proper way we can reduce the overall noise and EMI for the module. The gate drivers for MOSFETs should have an independent loop that doesn’t interface with the more sensitive analog control function, therefore LX1688 provides two power inputs with separate ground pins (analog/signal), VDD feeds all analog signals and VDD_P feeds only the output drivers, as shown in figure1 these two pins (pin 23, 24) are separated and filtered by R14, C2 and C7. The connection of two ground pins should be at only one point as shown in figure1. The power traces should be short and wide as possible and all periphery components such capacitors should be located as closed as possible to the controller. Oscilloscope Waveforms Pictures The following oscilloscope waveform pictures are taken from the actual circuits and will show the operation of the modules in different modes when three identical modules are synchronized, one as a master, and two others as slaves. Microsemi Integrated Products, Power Management 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 APPLICATIONS Dimming The LX1688 includes highly integrated universal ‘PWM or DC’ dim input that allows either a PWM or DC input without requiring external conditioning. In this application we choose Digital Dimming by applying a PWM signal to BRITE pin. All modules were driven by the same PWM signals, but notice that it is possible to dim each module quite separately. BEPOL pin has three different modes (see table 1), in this application it is connected to VDD which means active high enable with active high full brightness. The PWM signal can be varied in frequency between 48-320 HZ. No capacitor between CPWM1 and CPWM2 is necessary. Copyright 2001 Rev. 1.1a, 2003-03-21 WWW . Microsemi .C OM APPLICATION INFORMATION Page 10 RangeMAX™ I N T E G R A T E D LX1688 MULTIPLE LAMP CCFL CONTROLLER P R O D U C T S 1 2 3 4 VIN VIN GND C2 470nF 16V 10% GND 5 6 7 8 9 10 VDDP C1 470nF 16V 10% CN 1 VBR ITE 1 AOU T BOU T VSS_P VDD_P 2 RM P _R ST 23 3 VSS ENA BLE VDD VDD SW VDD 21 BEPOL BRIT E CPOR T RI_ C ENABLE ISNS CPW M1 VCOMP CPW M2 VSNS 2 3 4 6 7 8 9 10 SLAVE PHA_SYNC FAUL T 12 VDDP CN 1 1 2 GN D 3 C2a 470nF 16V 10% GN D VBR ITE 1 AO U T BO U T VSS_P VDD_P 4 24 6 23 3 VSS VDD VD D SW 21 BEPO L 20 BRIT E T RI_ C CPOR O LSNS 17 I_R CPW M1 ICO MP CPW M2 23 3 VSS VDD VD D SW 21 20 BRIT E T RI_ C CPOR O LSNS 17 I_R CPW M1 ICO MP C9b 16 VCO MP 10 CPW M2 VSNS C11b 14 RMP_RST 12 PH A-SYN C R3a 220 PHA_SYNC VDDSW R13a 100K C5b: 220nF 16V 10% C6b: 82nF 16V 10% C7b: 100nF 16V 10% C8b: 2.2nF 50V 5% C9b: 4.7nF 16V 10% C10-11b: 10nF 16V 10% C10b 15 11 13 C8b ISNS 8 Power Output Section C7b 18 ENABLE RMP_R ST C6b 19 7 C11a C5b VDD_SW 6 R1b 9 80.6K 1% C4b 220nF 16v 10% VDDSW BEPO L C3b 10nF 16V 10% VDD R2b 47 22 VDD 4 VBRITE C10a VSNS LED1a 24 Slave 2 SLAVE FAUL T 13 R3b 220 LED1b APPLICATIONS C5a: 220nF 16V 10% C6a: 82nF 16V 10% C7a: 100nF 16V 10% C8a: 2.2nF 50V 5% C9a: 4.7nF 16V 10% C10-11a: 10nF 16V 10% PHA_SYNC BO U T VDD_P P H A _SY NC EN AB LE SLAVE FAUL T AO U T VSS_P 2 14 RMP_RST 12 Slave 1 1 R M P _R ST 15 11 PH A-SYN C C2b 470nF 16V 10% VBR ITE C9a 16 VCO MP 10 RMP_R ST GN D GN D Power Output Section C8a ISNS 8 R1a 9 80.6K 1% 10 VDDP C1b 470nF 16V 10% 5 C7a 18 ENABLE VIN VIN C6a 19 7 9 C4a 220nF 16v 10% C5a VDD_SW 6 C3a 10nF 16V 10% 8 VDDSW 5 7 22 VDD 4 VBRITE VDD R2a 47 P H A _SY NC EN AB LE R3 220 5 2 R M P _R ST 13 LED1 VIN 5 C11 14 RMP_RST Master C1a 470nF 16V 10% C9 C10 16 15 11 VIN C8 ICOMP 10 C5 : 220nF 16V 10% C6 : 82nF 16V 10% C7 : 100nF 16V 10% C8 : 2.2nF 50V 5% C9 : 4.7nF 16V 10% C10-11 : 10nF 16V 10% Power Output Section C7 17 I_R PHA-SYNC C6 18 8 RM P_RST 20 19 OLSNS 7 R1 9 80.6K 1% C4 220nF 16v 10% C5 VDD_SW 6 C3 10nF 16V 10% VDD R2 47 22 VDDSW 4 5 1 24 P HA_SY NC VBRITE CN 1 WWW . Microsemi .C OM TYPICAL SLAVE APPLICATIONS VDDSW R13b 100K Figure 2- Schematic modules connected as a Master and Slaves Copyright 2001 Rev. 1.1a, 2003-03-21 Microsemi Integrated Products, Power Management 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 11 RangeMAX™ I N T E G R A T E D LX1688 MULTIPLE LAMP CCFL CONTROLLER P R O D U C T S Multiple Lamp Sync The figure 3 shows the sync signals (PHA_SYNC and RMP_RST) timing relationship to Gate signal AOUT, for the master module. AOUT and PHA_SYNC running at the same frequency and RMP_RST signal has the twice frequency. Strike Mode Every IC includes a separate strike controller that operates from the primary oscillator; therefore the strike controller is independent of the sync signals. The following oscilloscope waveform picture is taken when the master module is on striking mode and the salves are on running mode. Figure 3- Sync signals-Timing relationship to AOUT WWW . Microsemi .C OM APPLICATION INFORMATION (CONTINUED) Figure 5- Master is in striking mode while slaves are in CH2= AOUT(Master), CH3=PHA_SYNC, CH4=RMP_RST running mode CH2= AOUT(Master), CH3=AOUT(Slave1), CH4=AOUT(Slave2) Output Drivers The figure 4 shows the gate signals of the modules, which are operating, in running mode during digital dimming with 95% duty cycle. As shown all signals are synchronized. The difference between each signal’s duty cycles is because each lamp has an independent control loop. Figure 4- Output drivers of both Master Copyright 2001 Rev. 1.1a, 2003-03-21 Microsemi Integrated Products, Power Management 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 APPLICATIONS and Slaves. CH2=AOUT(Master), CH3=AOUT(Slave1), CH4=AOUT(Slave2) Page 12 RangeMAX™ I N T E G R A T E D P R O D U C T S LX1688 MULTIPLE LAMP CCFL CONTROLLER WWW . Microsemi .C OM APPLICATION INFORMATION (CONTINUED) Digital Dimming The following oscilloscope waveforms are showing gate signals of Master and slaves during digital dimming at 50% and 5% duty cycle. Figure 6- Gate signals during digital dimming with 50% duty cycle CH2= AOUT(Master), CH3=AOUT(Slave1), CH4=AOUT(Slave2) Figure 7- Gate signals during digital dimming with 5% duty cycle CH2= AOUT(Master), CH3=AOUT(Slave1), CH4=AOUT(Slave2) Output currents Figure 8 shows the output current of master and slaves during digital dimming with 5% duty cycle. The lamp currents are operating in phase and frequency synchronization. This prevents random interface between controllers and reduces EMI. Figure 8- Output current during digital dimming with 5% duty cycle R1= out(Master) R2=Iout(Slave1) R3=Iout(Slave2) Lamp Current at 10mA/Div APPLICATIONS Copyright 2001 Rev. 1.1a, 2003-03-21 Microsemi Integrated Products, Power Management 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 13 RangeMAX™ I N T E G R A T E D LX1688 MULTIPLE LAMP CCFL CONTROLLER P R O D U C T S Reference Designator U1 U2 Q1, Q2 D1, D2 D3 LED1 R1 R2 R3 R4, R5 R6 R7 R8 R9 R10 R11, R12 C1, C2 C3 C4 C5 C6 C7 C8 C9 C10, C11 C12 C13 C14 C15 C16 T1 Manufacture Part Number Backlight Controller Dual N-Channel MOSFET NPN Transistor Dual Diode Dual Diode LED 80.6 K 1% 1/16 W 47 ohm 5% 1/8 W 220 ohm 5% 1/8 W 39 ohm 5% 1/16 W 82 ohm 5% 1/16 W 10 K 5% 1/16 W 100 K 5% 1/16 W 1 K 5% 1/16 W 1 M 5% 1/16 W 2.74 K 1% 1/16 W 470 nF 16V 10% X7R 1206 10 nF 16V 10% 0805 220 nF 16V 10% X7R 1206 220 nF 16V 20% 0805 82 nF 16V 10% X7R 0603 100 nF 16V 20% X7R 2.2 nF 50V 10% 4.7 nF 16V 10% X7R 10 nF 16V 10% X7R 220 uF Tantalum 7343 220 pF 2KV 5% COG 2.2 pF PCB 2.2nF 50V 5% COG 3.3 nF 50V 5% COG Low profile, High voltage xfmr, turns ratio 1:75 Connector, 10 pin Connector, 2 pin Microsemi Siliconix Motorola Motorola Philips LX1688 Si9945AEY BC847ALT1 BAW56 BAV99 NOVACAP AVX AVX AVX NOVACAP AVX AVX AVX NOVACAP 0805YC224MAT2A 0603YC823KAT2A 0603YC104MAT2A 0603B22K500NT 0603YC472KAT2A 0603YC103KAT2A AVX NOVACAP Microsemi 08055A222JAT2A 0805N332J500NT SGE2645-1 Molex Molex 53261-1090 1206N221J202NT LIST OF MATERIAL CN1 CN2 Part Description WWW . Microsemi .C OM LX1688 MODULE BOARD LIST OF MATERIAL Table 2- List of material for LX1688 inverter module Copyright 2001 Rev. 1.1a, 2003-03-21 Microsemi Integrated Products, Power Management 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 14 RangeMAX™ I N T E G R A T E D LX1688 MULTIPLE LAMP CCFL CONTROLLER P R O D U C T S PHYSICAL DIMENSIONS WWW . Microsemi .C OM 24-PIN THIN SMALL SHRINK OUTLINE (TSSOP) PW 3 2 1 P E F D E A H SEATING PLANE Dim G MILLIMETERS MIN MAX 0.85 0.95 0.19 0.30 0.09 0.20 7.70 7.90 4.30 4.50 0.65 BSC 0.05 0.15 – 1.10 0.50 0.75 0° 8° 6.4 BSC – 0.10 L C M INCHES MIN MAX 0.033 0.037 0.007 0.012 0.0035 0.008 0.303 0.311 0.169 0.177 0.025 BSC 0.002 0.005 – .0433 0.020 0.030 0° 8° 0.252 BSC – 0.004 MECHANICALS A B C D E F G H L M P *LC B Note: 1. Dimensions do not include mold flash or protrusions; these shall not exceed 0.155mm(.006”) on any side. Lead dimension shall not include solder coverage PRODUCTION DATA – Information contained in this document is proprietary to Microsemi and is current as of publication date. This document may not be modified in any way without the express written consent of Microsemi. Product processing does not necessarily include testing of all parameters. Microsemi reserves the right to change the configuration and performance of the product and to discontinue product at any time. Copyright 2001 Rev. 1.1a, 2003-03-21 Microsemi Integrated Products, Power Management 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 15