TI SN74AS866A

SN54AS866, SN74AS866A
8-BIT MAGNITUDE COMPARATORS
SDAS183A – DECEMBER 1982 – REVISED JUNE 1990
•
•
•
description
These Advanced Schottky devices are capable of
performing high-speed arithmetic or logical
comparisons on two 8-bit binary or two’s
complement words. Three fully decoded
decisions about words P and Q are externally
available at the outputs. These devices are fully
expandable to any word length by connecting the
totem pole P>Q and P<Q outputs of each stage to
the P>Q and P<Q inputs of the next higher-order
stage. The cascading paths are implemented with
only a two-gate-level delay to reduce overall
comparison times for long words. The opencollector P=Q output may be wire-ANDed
together.
Both input words P and Q plus all three outputs
(P>Q, P<Q, and P = Q) are equipped with latches
to provide the designer with temporary data
storage for avoiding race conditions. The enable
circuitry is implemented with minimal delay times
to enhance performance when the devices are
cascaded for longer word lengths. Each latch is
transparent when the appropriate latch enable,
PLE, QLE, or OLE is high.
SN54AS866 . . . JD PACKAGE
SN74AS866A . . . N PACKAGE
(TOP VIEW)
QLE
L/A
p < Qin
P > Qin
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
P = Qout
GND
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
VCC
CLRQ
PLE
P7
P6
P5
P4
P3
P2
P1
P0
P < Qout
P > Qout
OLE
SN54AS866 . . . FK PACKAGE
SN74AS866A . . . FN PACKAGE
(TOP VIEW)
P > Qin
P < Qin
L/A
QLE
VCC
CLRQ
PLE
•
Package Options Include Plastic Small
Outline Packages, Both Plastic and Ceramic
Chip Carriers, and Standard Plastic and
Ceramic DIPs
Input and Output Latches with Active-High
Enables
Fast Compare to Zero
Arithmetic and Logical Comparison
Open-Collector P = Q Output
Q7
Q6
Q5
Q4
Q3
Q2
Q1
4
5
3 2 1 28 27 26
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
P7
P6
P5
P4
P3
P2
P1
Q0
P = Qout
GND
OLE
P > Qout
P < Qout
P0
•
The enable inputs PLE and QLE and data inputs
P and Q utilize pnp input transistors to reduce the
low-level input current requirement to typically
– 0.25 mA, which minimizes loading effects.
The Q register may be cleared to zero for a fast comparison of the P word to zero.
The SN54AS866 is characterized for operation over the full military temperature range of – 55°C to 125°C. The
SN74AS866A is characterized for operation from 0°C to 70°C.
Copyright  1990, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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1
SN54AS866, SN74AS866A
8-BIT MAGNITUDE COMPARATORS
SDAS183A – DECEMBER 1982 – REVISED JUNE 1990
logic symbol†
L/A
PLE
2
26
18
PO
19
P1
20
P2
21
P3
22
P4
23
P5
24
P6
25
P7
4
P>Q
3
P<Q
15
QLE
CLR Q 27
QLE 1
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
12
11
10
9
8
7
6
5
COMP
M [LOGIC]
M [ARITH, 2s COMP]
C1
1D
1=0 0
P
C3
R
C2
2D
7
P > Q 3D
P < Q 3D
P = Q 3D
16
17
13
1=0 0
Q
7
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
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P>Q
P<Q
P=Q
SN54AS866, SN74AS866A
8-BIT MAGNITUDE COMPARATORS
SDAS183A – DECEMBER 1982 – REVISED JUNE 1990
logic diagram (positive logic)
15
OLE
26
P7=Q7
C1
PLE
25
P7
1D
P7
P7
24
P6=Q6
P6
P6
P6
23
P5=Q5
P5
P3
P5
22
P4
P4
P3=Q3
P4
21
P3
P3
P2=Q2
P3
20
P2
P2
19
P1
1D
P1=Q1
17
P2
16
P1
13
P1
18
C1
P<Q
P>Q
P=Q
P0=Q0
P0
P0
P0
27
CLRQ
1
QLE
5
Q7
1D
Q7
Q7
6
Q6
Q6
Q6
7
Q5
Q5
Q5
8
Q4
Q4
Q4
9
Q3
Q3
4MSB=
Q3
10
Q2
Q2
Q2
11
Q1
Q1
Q1
12
Q0
4
P>QIN 3
P<1I 2
L/A
R
C1
Q0
Q0
Arith
Logic
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3
SN54AS866, SN74AS866A
8-BIT MAGNITUDE COMPARATORS
SDAS183A – DECEMBER 1982 – REVISED JUNE 1990
FUNCTION TABLE
INPUTS
OUTPUTS
COMPARISON
L/A
DATA INPUTS
P0 – P7, Q0 – Q7
P>Q
P<Q
P>Q
P<Q
P=Q
Logical
H
P>Q
X
X
H
L
L
Logical
H
P<Q
X
X
L
H
L
Logical
H
P=Q
L
L
L
L
H
Logical
H
P=Q
L
H
L
H
L
Logical
H
P=Q
H
L
H
L
L
Logical
H
P=Q
H
H
H
H
L
Arithmetic
L
P AG Q
X
X
H
L
L
Arithmetic
L
Q AG P
X
X
L
H
L
Arithmetic
L
P=Q
L
L
L
L
H
Arithmetic
L
P=Q
L
H
L
H
L
Arithmetic
L
P=Q
H
L
H
L
L
Arithmetic
L
P=Q
H
H
H
H
L
AG = arithmetically greater than
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Off-state output voltage, P = Q output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Operating free-air temperature range: SN54AS866 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
SN74AS866A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
recommended operating conditions
SN54AS866
SN74AS866A
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
High-level output current, all outputs except P=Q
VOH
IOL
High-level output voltage, P=Q output
Low-level output current
20
tsu
th
Setup time to PLE, OLE, OLE↓
2
2
Hold time after PLE, QLE, OLE↓
4
4
tA
Operating free-air temperature
High-level input voltage
2
– 55
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V
V
0.8
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other specifications
are design goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
4
2
UNIT
0.8
V
–2
–2
mA
5.5
5.5
V
20
mA
125
0
ns
70
°C
SN54AS866, SN74AS866A
8-BIT MAGNITUDE COMPARATORS
SDAS183A – DECEMBER 1982 – REVISED JUNE 1990
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
IOH
VOL
P>Q, P<Q
P=Q only
II
IIH
L/A, OLE
Others
SN54AS866
TYP†
MAX
TEST CONDITIONS
SN74AS866A
TYP†
MAX
MIN
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
II = – 18 mA
IOH = – 2 mA
VCC = 4.5 V,
VCC = 4.5 V,
VOH = 5.5 V
IOL = 20 mA
VCC = 5.5 V,
VI = 7 V
5V
VCC = 5
5.5
V,
7V
VI = 2
2.7
VCC = 5.5 V,
VI = 0.4 V
MIN
– 1.2
VCC – 2
UNIT
– 1.2
V
0.25
mA
VCC – 2
0.25
0.35
0.5
0.35
0.5
V
0.1
0.1
mA
40
40
20
20
–4
–4
–2
–2
µA
L/A, OLE,
P>Qin,
IIL
P<Qin
mA
CLRQ
P, Q, PLE, QLE
IO‡
ICC
– 0.25
VCC = 5.5 V,
VCC = 5.5 V,
VO = 2.25 V
See Note 1
–1
– 20
– 0.25
– 112
160
– 20
240
– 112
mA
240
mA
160
NOTE 1: ICC is measured with all inputs high except L/A, which is low.
switching characteristics (see Note 2
PARAMETER
FROM
((INPUT))
tPLH
tPHL
L/A
tPLH
tPHL
P<Q P>Q
P<Q,
tPLH
tPHL
Any
y P or Q
Data Input
tPLH
tPHL
CLRQ
PARAMETER
TO
(
)
(OUTPUT)
P<Q,, P>Q
FROM
((INPUT))
VCC = 4.5 V to 5.5 V,,
CL = 50 pF,
p ,
RL = 500 Ω,
TA = MIN to MAX§
SN54AS866
SN74AS866A
MIN TYP†
MAX
MIN TYP†
MAX
1
8.5
14
1
8.5
19
1
7.5
14
1
7
13
1
5
10
1
5
8
1
5.5
10
1
5.5
8
1
13.5
21
1
13.5
17.5
1
10
17
1
10
15
1
16
21
1
16
20
1
12
17
1
12
16
VCC = 4.5 V to 5.5 V,
pF,,
CL = 50 p
RL = 280 Ω,
TA = MIN to MAX§
TO
(
)
(OUTPUT)
SN54AS866
MIN TYP†
MAX
tPLH
tPHL
P<Q,
tPLH
tPHL
Any
y P or Q
Data Input
P=Q
tPLH
tPHL
CLRQ
P=Q
P>Q
P=Q
UNIT
ns
ns
ns
ns
UNIT
SN74AS866A
MIN TYP†
MAX
1
6.5
12
1
6.5
16
1
8
14
1
8
14
1
10
15
1
10
17
1
9
14
1
9
14
1
12
17
1
12
24
1
13
18
1
13
21
ns
ns
ns
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit, IOS.
§ For conditions shown MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTE 2: Load circuit and voltage waveforms are shown in Section 1 of the ALS/AS Logic Data Book, 1986.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other specifications
are design goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
POST OFFICE BOX 655303
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5
SN54AS866, SN74AS866A
8-BIT MAGNITUDE COMPARATORS
SDAS183A – DECEMBER 1982 – REVISED JUNE 1990
TYPICAL APPLICATION DATA
This sequence of comparisons illustrates how the CLRQ function can be used to perform dual comparisons of the
varying P terms (P0, P1, etc.). When CLRQ is high, the P term is compared to the Q term. When CLRQ is taken low,
the P term is compared to zero. This or similar sequences can enhance performance and reduce package count to
perform value range checks.
’AS866(A)
COMP
M [LOGIC]
M [ARITH, 2s COMP]
L/A
C1
PLE = H
1D
1=0 0
P
P
QLE
7
P>Q
P<Q
QLE
CLRQ
QLE
C3
R
C2
2D
P > Q 3D
P < Q 3D
P = Q 3D
P>Q
P<Q
P=Q
CLRQ
P0:Q0
P1:Q0
P0:Zero
P2:Q0
P1:Zero
1=0 0
Q
Q
7
Figure 1. Magnitude Comparisons Combined With Quick Comparisons to Zero
(Range Verifications)
6
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Copyright  1998, Texas Instruments Incorporated