N Na t i on a l S e m i c o n du c t o r CLC5903 Dual Digital Tuner / AGC 0 0 General Overview Features The CLC5903 Dual Digital Tuner / AGC IC is a two channel digital downconverter (DDC) with integrated automatic gain control (AGC). The CLC5903 is a key component in the Enhanced Diversity Receiver Chipset (EDRCS) which includes one CLC5903 Dual Digital Tuner / AGC, two CLC5957 12-bit analog-to-digital converters (ADCs), and two CLC5526 digitally controlled variable gain amplifiers (DVGAs). This system allows direct IF sampling of signals up to 300MHz for enhanced receiver performance and reduced system costs. 78MSPS Operation Low Power, 145mW/channel, 52 MHz, Dec=192 Two Independent Channels with 14-bit inputs Serial Daisy-chain Mode for quad receivers Greater than 100 dB image rejection Greater than 100 dB spurious free dynamic range 0.02 Hz tuning resolution User Programmable AGC with enhanced Power Detector The CLC5903 is an enhanced replacement for the CLC5902 in the Diversity Receiver Chipset (DRCS). The main improvements relative to the CLC5902 are a 50% increase in maximum sample rate from 52MHz to 78MHz, a 62% reduction in power consumption from 760mW to 290mW, and the added flexibility to independently program filter coefficients in the two channels. A block diagram for a DRCS-based narrowband communications system is shown in Figure 1. Channel Filters include a Fourth Order CIC followed by 21-tap and 63-tap Symmetric FIRs FIR filters process 21-bit Data with 16-bit Programmable Coefficients Two independent FIR coefficient memories which can be routed to either or both channels. Flexible output formats include 12-bit Floating Point or 8, 16, 24, and 32 bit Fixed Point The CLC5903 offers high dynamic range digital tuning and filtering based on hard-wired digital signal processing (DSP) technology. Each channel has independent tuning, phase offset, filter coefficients, and gain settings. Channel filtering is performed by a series of three filters. The first is a 4-stage Cascaded Integrator Comb (CIC) filter with a programmable decimation ratio from 8 to 20 48. Next there a re two symmetric FIR filters, a 21-tap and a 63-tap, both with independent programmable coefficients. The first FIR filter decimates the data by 2, the second FIR decimates by either 2 or 4. Channel filter bandwidth at 52MSPS ranges from ±650kHz down to ±1.3kHz. At 78MSPS, the maximum bandwidth increases to ±975kHz. Serial and Parallel output ports JTAG Boundary Scan 8-bit Microprocessor Interface 128 pin PQFP and 128 pin FBGA packages 100% Software compatible with the CLC5902 Pin compatible with the CLC5902 except for VDD voltage Applications The CLC5903’s AGC controller monitors the ADC output and controls the ADC input signal level by adjusting the DVGA setting. AGC threshold, deadband+hysteresis, and the loop time constant are user defined. Total dynamic range of greater than 120dB full-scale signal to noise in a 200kHz bandwidth can be achieved with the Diversity Receiver Chipset. CLC5526 CLC5957 LC IF A Cellular Basestations Satellite Receivers Wireless Local Loop Receivers Digital Communications CLC5903 12 ADC DVGA DAV IF B DVGA 8 12 ADC Dual Digital Tuner/AGC DAV LC CLK SCK_IN SerialOutA/B SerialOutB SCK SFS RDY ParallelOutput[15..0] ParallelOutputEnable ParallelSelect[2..0] Figure 1. Diversity Receiver Chipset Block Diagram ©2004 National Semiconductor Corporation DS200286 www.national.com Revision 1.6 CLC5903 Dual Digital Tuner / AGC June 2004 CLC5903 RD WR CE A[7:0] D[7:0] Microprocessor Interface AGAIN[2..0] ASTROBE AIN BIN Channel A Controls GAIN_A FREQ_A COEF_SEL_F1A PHASE_A DITH_A COEF_SEL_F2A AGC_IC_A AGC_RB_A 14 MUX A MUX B 14 Channel A Tuning, Channel Filters, and AGC (see Figure 16) Channel B Tuning, Channel Filters, and AGC (see Figure 16) Output Formatter Floating Point: 4-bit Exponent and 8-bit Mantissa or Two’s Complement: 32-bit Truncated or 24-bit Rounded or 16-bit Rounded or 8-bit Truncated (see Figure 29) SCK_IN AOUT/BOUT BOUT SCK SFS RDY POUT[15..0] PSEL[2..0] POUT_EN BSTROBE BGAIN[2..0] TEST_REG Input Source Channel B Controls Output Controls A_SOURCE B_SOURCE GAIN_B FREQ_B COEF_SEL_F1B PHASE_B DITH_B COEF_SEL_F2B AGC_IC_B AGC_RB_B RATE SOUT_EN SCK_POL SFS_POL RDY_POL MUX_MODE PACKED FORMAT DEBUG_EN DEBUG_TAP SFS_MODE SDC_EN CKA CKB CLK GEN SI MR Sync Logic Common Channel Controls DEC DEC_BY_4 SCALE EXP_INH EXT_DELAY AGC_HOLD_IC AGC_LOOP_GAIN AGC_TABLE AGC_COMB_ORD PAGE_SEL_F1 F1A_COEFF F1B_COEFF PAGE_SEL_F2 F2A_COEFF F2B_COEFF Figure 2. CLC5903 Dual Digital Tuner / AGC Block Diagram with Control Register Associations Functional Description Each channel has its own AGC circuit for use with narrowband radio channels where most of the channel filtering precedes the ADC. The AGC closes the loop around the CLC5526 DVGA, compressing the dynamic range of the signal into the ADC. AGC gain compensation in the CLC5903 removes the DVGA gain steps at the output. The time alignment of this gain compensation circuit can be adjusted to support ADCs with different latencies. The AGC can be configured to operate continuously or set to a fixed gain step. The two AGC circuits operate independently but share the same programmed parameters and control signals. The CLC5903 block diagram is shown in Figure 2. The CLC5903 contains two identical digital down-conversion (DDC) circuits. Each DDC accepts an independently clocked 14-bit sample at up to 78MSPS, down converts from a selected carrier frequency to baseband, decimates the signal rate by a programmable factor ranging from 32 to 16384, provides channel filtering, and outputs quadrature symbols. A crossbar switch enables either of the two inputs or a test register to be routed to either DDC channel. Flexible channel filtering is provided by the two programmable decimating FIR filters. The final filter outputs can be converted to a 12-bit floating point format or standard two’s complement format. The output data is available at both serial and parallel ports. The chip receives configuration and control information over a microprocessor-compatible bus consisting of an 8-bit data I/O port, an 8-bit address port, a chip enable strobe, a read strobe, and a write strobe. The chip’s control registers (8 bits each) are memory mapped into the 8-bit address space of the control port. Page select bits allow access to the overlaid A and B set of FIR coefficients. The CLC5903 maintains over 100 dB of spurious free dynamic range and over 100 dB of out-of-band rejection. This allows considerable latitude in channel filter partitioning between the analog and digital domains. JTAG boundary scan and on-chip diagnostic circuits are provided to simplify system debug and test. The frequencies, phase offsets, and phase dither of the two sine/cosine numerically controlled oscillators (NCOs) can be independently specified. Two sets of coefficient memories and a crossbar switch allow shared or independent filter coefficients and bandwidth for each channel. Both channels share the same decimation ratio and input/output formats. www.national.com The CLC5903 supports 3.3V I/O even though the core logic voltage is 1.8V. The CLC5903 outputs swing to the 3.3V rail so they can be directly connected to 5V TTL inputs if desired. 2 Operating Ratings Positive IO Supply Voltage (VDDIO) -0.3V to 4.2V Positive IO Supply Voltage (VDDIO) 3.3V ±10% Positive CoreSupply Voltage (VDD) -0.3V to 2.4V Positive Core Supply Voltage (VDD) 1.8V ±10% Voltage on Any Input or Output Pin -0.3V to VDDIO+0.5V Input Current at Any Pin ±25mA Package Input Current ±50mA Package Dissipation at TA=25°C Operating Temperature Range Package Thermal Resistance θja θjc 128 pin PQFP 39°C/W 20°C/W 128 pin FBGA 30°C/W N/A Package 1W ESD Susceptibility Human Body Model Machine Model 2000V 200V Soldering Temperature, Infrared, 10 seconds 300°C Storage Temperature -65°C to 150°C NOTE: Absolute maximum ratings are limiting values, to be -40°C to +85°C Reliability Information Transistor Count 1.4 million Ordering Information applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of Temperature Range Order Code these conditions is not necessarily implied. Exposure to maximum ratings for extended periods may affect device reliability. Description CLC5903VLA -40°C to +85°C 128-pin PQFP (industrial temperature range) CLC5903SM -40°C to +85°C 128-pin FBGA (industrial temperature range) CLC5903 Electrical Characteristics (Note 1) DC Characteristics (FS=78MHz, CIC Decimation=48, F2 Decimation=2; unless specified) Symbol Parameter Min Typ Max Units VIL Voltage input low -0.5 0.7 V VIH Voltage input high 2.3 VDDIO+0.5 V IOZ Input current 20 uA VOL Voltage output low (IOL = 4mA/16mA, see Note 2) 0.4 V VOH Voltage output high (IOH = -4mA/-16mA, see Note 2) CIN Input capacitance 2.4 V 5.0 pF Max Units 78 MHz AC Characteristics (FS=78MHz, CIC Decimation=48, F2 Decimation=2; unless specified) Parameter (CL=50pF) Symbol Min Typ FCK Clock (CKA|B) Frequency (Figure 7) SFDR Spurious Free Dynamic Range -100 dBFS SNR Signal to Noise Ratio -127 dBFS Tuning Resolution 0.02 Hz Phase Resolution 0.005 ° tMRA MR Active Time (Figure 5) 4 CK periods tMRIC MR Inactive to first Control Port Access (Figure 5) 10 CK periods 3 www.national.com CLC5903 Absolute Maximum Ratings CLC5903 AC Characteristics (Continued) (FS=78MHz, CIC Decimation=48, F2 Decimation=2; unless specified) Symbol Parameter (CL=50pF) Min Typ Max Units tMRSU MR Setup Time to CKA|B (Figure 5) 6 ns tMRH MR Hold Time to CKA|B (Figure 5) 2 ns tSISU SI Setup Time to CKA|B (Figure 6) 6 ns tSIH SI Hold Time from CKA|B (Figure 6) 2 ns tSIW SI Pulse Width (Figure 6) 4 CK periods tCKDC CKA|B duty cycle (Figure 7) 40 tRF CKA|B rise and fall times (VIL to VIH) (Figure 7) tSU Input setup before CKA|B goes high (A|BIN) (Figure 7) 3 ns tHD Input hold time after CKA|B goes high (A|BIN) (Figure 7) 1 ns tCKL Minimum time low for CK = CKA | CKB (Figure 8) 3.1 ns tSTIW A|BSTROBE Inactive Pulse Width (Figure 9) tGSTB A|BGAIN setup before A|BSTROBE (Figure 9) 6 tSFSV SCK to SFS Valid (Note 3) (Figure 10) -1 5 ns tOV SCK to A|BOUT Valid (Note 4) (Figure 10) -1 5 ns tRDYW RDY Pulse Width (Figure 10) tRDYV SCK to RDY valid (Figure 10) tOENV 60 % 2 ns 2 CK period ns 2 5 ns POUT_EN Active to POUT[15..0] Valid (Figure 11) 12 ns tOENT POUT_EN Inactive to POUT[15..0] Tri-State (Figure 11) 10 ns tSELV PSEL[2..0] to POUT[15..0] Valid (Figure 12) 13 ns tPOV RDY to POUT[15..0] New Value Valid (Note 5) (Figure 13) 7 ns tJPCO Propagation Delay TCK to TDO (Figure 14) 25 ns tJSCO Propagation Delay TCK to Data Out (Figure 14) 35 ns tJPDZ Disable Time TCK to TDO (Figure 14) 25 ns tJSDZ Disable Time TCK to Data Out (Figure 14) 35 ns tJPEN Enable Time TCK to TDO (Figure 14) 0 25 ns tJSEN Enable Time TCK to Data Out (Figure 14) 0 35 ns tJSSU Setup Time Data to TCK (Figure 14) 10 ns tJPSU Setup Time TDI, TMS to TCK (Figure 14) 10 ns tJSH Hold Time Data to TCK (Figure 14) 45 ns tJPH Hold Time TCK to TDI, TMS (Figure 14) 45 ns tJCH TCK Pulse Width High (Figure 14) 50 ns tJCL TCK Pulse Width Low (Figure 14) 40 ns JTAGFMAX TCK Maximum Frequency (Figure 14) tCSU Control Setup before the controlling signal goes low (Figure 15) 5 ns tCHD Control hold after the controlling signal goes high (Figure 15) 5 ns www.national.com -1 CK periods 10 4 MHz CLC5903 AC Characteristics (Continued) (FS=78MHz, CIC Decimation=48, F2 Decimation=2; unless specified) Parameter (CL=50pF) Symbol Min Typ Max Units tCSPW Controlling strobe pulse width (Write) (Figure 15) tCDLY Control output delay controlling signal low to D (Read) (Figure 15) 30 ns tCZ Control tri-state delay after controlling signal high (Figure 15) 20 ns IDD Dynamic Supply Current (FCK =78MHz, N=48, SCK=39MHz) 120 200 mA IDDIO Dynamic Supply Current (FCK =78MHz, N=48, SCK=39MHz) 65 100 mA 30 ns Note 1: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Note 2: All output pins provide 16mA output drive except TDO (pin 116) which provides 4mA output drive. Note 3: tSFSV refers to the rising edge of SCK when SCK_POL=0 and the falling edge when SCK_POL=1. Note 4: tOV refers to the rising edge of SCK when SCK_POL=0 and the falling edge when SCK_POL=1. Note 5: tRDYV refers to the rising edge of RDY when RDY_POL=0 and the falling edge when RDY_POL=1. CLC5903SM Pinout A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 AIN12 VDDIO AGAIN1 SCAN_EN TCK VDD POUT_SEL1 VSSIO VDDIO POUT3 NC NC B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 AIN10 VSSIO NC TRST TMS TDO POUT4 NC SCK_IN POUT5 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 AIN7 AIN11 NC VSS TDI POUT0 POUT2 NC VSSIO POUT6 POUT8 D5 D6 ASTROB D1 D2 D3 D4 AIN5 AIN8 AIN13 AGAIN2 E1 E2 E3 E4 AIN2 AIN1 AIN6 AIN9 AGAIN0 POUT_SEL2 POUT_SEL0 POUT_EN A12 D7 D8 D9 D10 D11 D12 POUT1 VSS POUT7 VDDIO POUT11 POUT10 E9 E10 E11 E12 POUT9 VSSIO POUT13 POUT12 F1 F2 F3 F4 F9 F10 F11 F12 VSS CKA AIN3 AIN4 SFS POUT14 VDD POUT15 G1 G2 G3 G4 G9 G10 G11 G12 VDD BIN13 BIN12 AIN0 RDY BOUT VSSIO AOUT H1 H2 H3 H4 H9 H10 H11 H12 BIN10 BIN11 BIN9 BIN5 D D SCK VDDIO J12 J1 J2 J3 J4 BIN7 BIN8 BIN6 BIN3 J5 J6 J7 J8 J9 J10 J11 BGAIN2 SI NC CE D VSSIO D K1 K2 K3 K4 VSS K5 K6 K7 K8 K9 K10 K11 K12 BIN4 BIN2 BIN0 CKB L1 L2 L3 L4 BSTROB VSSIO A A RD NC D VDD L5 L6 L7 L8 L9 L10 L11 BIN1 VSS NC L12 BGAIN1 NC A A A A D NC M1 M2 D M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 NC VDDIO BGAIN0 MR A VDD VSS A WR VSSIO VDDIO D Top View Figure 3. CLC5903SM FBGA Pinout 5 www.national.com CLC5903 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 CKB NC BIN BIN BIN BIN BIN BIN BIN VSSIO BIN BIN BIN BIN BIN BIN (MSB) BIN VDD CKA VSS AIN AIN AIN AIN AIN AIN AIN VDDIO AIN AIN AIN AIN AIN AIN (MSB) AIN VSSIO NC NC CLC5903VLA Pinout 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 CLC5903VLA Dual Digital Tuner / AGC (Top View) 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 VDDIO AGAIN AGAIN AGAIN ASTROBE NC SCAN_EN TRST VSS TCK TMS TDI TDO VDD POUT_SEL POUT_SEL POUT_SEL POUT_EN VSSIO POUT POUT VDDIO POUT POUT POUT VSS NC NC NC VSSIO D D D D D VDD D VSS RDY BOUT VDDIO SCK SFS AOUT VSSIO POUT VDD POUT POUT POUT VSSIO POUT POUT VDDIO POUT POUT POUT POUT POUT VSSIO SCK_IN NC NC NC 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 VDDIO BGAIN BGAIN BGAIN BSTROBE NC MR SI VSSIO A VDD A VSS A A A A A A WR RD CE VSSIO D D VDDIO Figure 4. CLC5903VLA PQFP Pinout Pin Descriptions Signal MR AIN[13:0], BIN[13:0] www.national.com PQFP Pin FBGA Pin Description 45 M4 MASTER RESET, Active low Resets all registers within the chip. ASTROBE and BSTROBE are asserted during MR. 4:10,12:18, 22:28, 30:36 D3,A1,C2, B1,E4,D2, C1,E3,D1, F4,F3,E1, E2,G4; G2,G3,H2, H1,H3,J2, J1,J3,H4, K1,J4,K2, L1,K3 INPUT DATA, Active high 2’s complement input data. AIN and BIN are the MSBs. The data is clocked into the chip on the rising edge of the corresponding clock (CKA, CKB). The CLC595X connects directly to these input pins with no additional logic. Tie unused input bits low. 6 Signal CLC5903 Pin Descriptions (Continued) PQFP Pin FBGA Pin Description AOUT BOUT 82 78 G12 G10 SERIAL OUTPUT DATA, Active high The 2’s complement serial output data is transmitted on these pins, MSB first. The output bits change on the rising edge of SCK (falling edge if SCK_POL=1) and should be captured on the falling edge of SCK (rising if SCK_POL=1). These pins are tri-stated at power up and are enabled by the SOUT_EN control register bit. See Figure 10 and Figure 30 timing diagrams. In Debug Mode AOUT=DEBUG, BOUT=DEBUG. AGAIN[2:0], BGAIN[2:0] 125:127 40:42 D4,A3,D5 J5,L4,M3 OUTPUT DATA TO DVGA, Active high 3 bit bus that sets the gain of the DVGA determined by the AGC circuit. ASTROBE, BSTROBE 124 43 C4 K5 DVGA STROBE, Active low Strobes the data into the DVGA. See Figure 9 and Figure 35 timing diagrams. SCK 80 H11 SERIAL DATA CLOCK, Active high or low The serial data is clocked out of the chip by this clock. The active edge of the clock is user programmable. This pin is tri-stated at power up and is enabled by the SOUT_EN control register bit. See Figure 10 and Figure 30 timing diagrams. In Debug Mode outputs an appropriate clock for the debug data. If RATE=0 the input CK duty cycle will be reflected to SCK. SCK_IN 99 B11 SERIAL DATA CLOCK INPUT, Active high or low Data bits from a serial daisy-chain slave are clocked into a serial daisy-chain master on the falling edge of SCK_IN (rising if SCK_POL=1 on the slave). Tie low if not used. SFS 81 F9 SERIAL FRAME STROBE, Active high or low The serial word strobe. This strobe delineates the words within the serial output streams. This strobe is a pulse at the beginning of each serial word (PACKED=0) or each serial word I/Q pair (PACKED=1). The polarity of this signal is user programmable. This pin is tri-stated at power up and is enabled by the SOUT_EN control register bit. See Figure 10 and Figure 30 timing diagrams. In Debug Mode SFS=DEBUG. POUT[15:0] 84,86:88, 90,91, 93:97,104: 106, 108,109 F12,F10, E11,E12, D11,D12, E9,C12,D9, C11,B12, B9,A10,C8, D7,C7 PARALLEL OUTPUT DATA, Active high The output data is transmitted on these pins in parallel format. The POUT_SEL[2..0] pins select one of eight 16-bit output words. The POUT_EN pin enables these outputs. POUT is the MSB. In Debug Mode POUT[15..0]=DEBUG[19..4]. POUT_SEL[2:0] 112:114 D6,A7,B7 PARALLEL OUTPUT DATA SELECT, Active high The 16-bit output word is selected with these 3 pins according to Table 2. Not used in Debug Mode. For a serial daisy-chain master, POUT_SEL[2:0] become inputs from the slave: POUT_SEL=SFSSLAVE, POUT_SEL=BOUTSLAVE, and POUT_SEL=AOUTSLAVE. Tie low if not used. POUT_EN 111 B8 PARALLEL OUTPUT ENABLE. Active low This pin enables the chip to output the selected output word on the POUT[15:0] pins. Not used in Debug Mode. Tie high if not used. RDY 77 G9 READY FLAG, Active high or low The chip asserts this signal to identify the beginning of an output sample period (OSP). The polarity of this signal is user programmable. This signal is typically used as an interrupt to a DSP chip, but can also be used as a start pulse to dedicated circuitry. This pin is active regardless of the state of SOUT_EN. In Debug Mode RDY=DEBUG. CKA, CKB 20, 38 F2 K4 INPUT CLOCK. Active high The clock inputs to the chip. The corresponding AIN and BIN signals are clocked into the chip on the rising edge of this signal. CKA and CKB are OR’d together on chip to create the CK signal. SI is clocked into the chip on the rising edge of CK. Tie low if not used. J6 SYNC IN. Active low The sync input to the chip. The decimation counters, dither, and NCO phase can be synchronized by SI. This sync is clocked into the chip on the rising edge of CK (CK = CKA + CKB). Tie this pin high if external sync is not required. All sample data is flushed by SI. To properly initialize the DVGA ASTROBE and BSTROBE are asserted during SI. SI 46 7 www.national.com CLC5903 Pin Descriptions Signal (Continued) PQFP Pin FBGA Pin 62,63, 69:73,75 J9,L10, M12,K11, L12,H9, J11,H10 DATA BUS. Active high This is the 8 bit control data I/O bus. Control register data is loaded into the chip or read from the chip through these pins. The chip will only drive output data on these pins when CE is low, RD is low, and WR is high. A[7:0] 48,50, 52:57 M5,L6,L7, K7,L8,M8, K8,L9 ADDRESS BUS. Active high These pins are used to address the control registers within the chip. Each of the control registers within the chip are assigned a unique address in a flat address space. A control register can be written to or read from by setting A[7:0] to the register’s address. RD 59 K9 READ ENABLE. Active low This pin enables the chip to output the contents of the selected register on the D[7:0] pins when CE is also low. WR 58 M9 WRITE ENABLE. Active low This pin enables the chip to write the value on the D[7:0] pins into the selected register when CE is also low. This pin can also function as RD/WR if RD is held low. D[7:0] Description CE 60 J8 CHIP ENABLE. Active low This control strobe enables the read or write operation. The contents of the register selected by A[7:0] will be output on D[7:0] when RD is low and CE is low. If WR is low and CE is low, then the selected register will be loaded with the contents of D[7:0]. TDO 116 B6 TEST DATA OUT. Active high TDI 117 C6 TEST DATA IN. Active high with pull-up TMS 118 B5 TEST MODE SELECT. Active high with pull-up TCK 119 A5 TEST CLOCK. Active high. Tie low if JTAG is not used. TRST 121 B4 TEST RESET. Active low with pull-up Asynchronous reset for TAP controller. Tie low or to MR if JTAG is not used. SCAN_EN 122 A4 SCAN ENABLE. Active low with pull-up Enables access to internal scan registers. Tie high. Used for manufacturing test only! VSS 19,51,76, 103,120 C5,D8,F1, J12,L2,M7 Core Ground. Quantity 5 in PQFP (6 in FBGA). VDD 21,49,74, 85,115 A6,F11,G1, K12,M6 Core Power, 1.8V. Quantity 5. VSSIO 3,29,47,61, 68,83,89, 98,110 A8,B2,C10, E10,G11, J10,K6,M10 I/O Ground. Quantity 9 (8 in FBGA). VDDIO 11,39,64, 79,92,107, 128 A2,A9,D10, H12,M2, M11 I/O Power, 3.3V. Quantity 7 (6 in FBGA). NC 1,2,37,44, 65,66,67, 100,101, 102,123 A11,A12, B3,B10,C3, C9,J7,K10, L11,L5,L3, M1 No Connect. These pins should be left floating. Quantity 11 (12 in FBGA). www.national.com 8 CLC5903 Timing Diagrams CK tMRH tMRSU tMRA MR tMRIC RD or WR Figure 5. CLC5903 Master Reset Timing CK tSIH tSISU tSIW SI Figure 6. CLC5903 Synchronization Input (SI) Timing 1/FCK tCKDC tCKDC CKA|B VIL tHD VIH tRF tSU A|BIN Note: AIN relative to CKA, BIN relative to CKB Figure 7. CLC5903 ADC Input and Clock Timing tCKL CKA CKB CK Note: CK = CKA | CKB Figure 8. CLC5903 CKA vs. CKB Timing tSTIW A|BSTROBE tGSTB A|BGAIN[2..0] Figure 9. CLC5903 DVGA Interface Timing 9 www.national.com CLC5903 Timing Diagrams (Continued) SCK SCK_POL=0 SCK=CK/2 SCK SCK_POL=1 tSFSV tSFSV SFS SFS_POL=0 SFS SFS_POL=1 tOV tOV lsb or undef A|BOUT msb Previous Q Output Word msb-1 msb-2 msb-3 I Output Word RDY RDY_POL=0 tRDYW RDY RDY_POL=1 tRDYV Figure 10. CLC5903 Serial Port Timing POUT_EN tOENV tOENT POUT[15..0] Figure 11. CLC5903 Parallel Output Enable Timing POUT_SEL[2..0] n n+1 n+2 tSELV POUT[15..0] tSELV output (n) output (n+1) output (n+2) Figure 12. CLC5903 Parallel Output Select Timing RDY RDY_POL=0 RDY RDY_POL=1 POUT[15..0] tPOV old output new output Figure 13. CLC5903 Parallel Output Data Ready Timing www.national.com 10 CLC5903 TCK tJPCO tJPEN tJPDZ TDO tJCL tJCH TCK tJPSU tJPH TDI, TDS TCK tJSCO tJSEN tJSDZ D TCK tJSSU tJSH D Figure 14. CLC5903 JTAG Port Timing CE WR RD tCHD tCSU A[7:0] tCDLY tCZ D[7:0] READ CYCLE; NORMAL MODE CE tCSPW WR RD tCSU A[7:0] tCHD D[7:0] WRITE CYCLE; NORMAL MODE CE WR tCHD tCSU A[7:0] tCDLY tCZ D[7:0] READ CYCLE; RD HELD LOW tCSPW CE WR A[7:0] tCSU tCHD D[7:0] WRITE CYCLE; RD HELD LOW Figure 15. CLC5903 Control I/O Timing 11 www.national.com Input Source The input crossbar switch allows either AIN, BIN, or a test register to be routed to the channel A or channel B AGC/ DDC. The AGC outputs, AGAIN and BGAIN, are not switched. If AIN and BIN are exchanged the AGC loop will be open and the AGCs will not function properly. AIN and BIN should meet the timing requirements shown in Figure 7. Detailed Description Control Interface The CLC5903 is configured by writing control information into 148 control registers within the chip. The contents of these control registers and how to use them are described under Control Register Addresses and Defaults on page 21. The registers are written to or read from using the D[7:0], A[7:0], CE, RD and WR pins (see Table for pin descriptions). This interface is designed to allow the CLC5903 to appear to an external processor as a memory mapped peripheral. See Figure 15 for details. Selecting the test register as the input source allows the AGC or DDC operation to be verified with a known input. See the test and diagnostics section for further discussion. Down Converters A detailed block diagram of each DDC channel is shown in Figure 16. Each down converter uses a complex NCO and mixer to quadrature downconvert a signal to baseband. The “FLOAT TO FIXED CONVERTER” treats the 15-bit mixer output as a mantissa and the AGC output, EXP, as a 3-bit exponent. It performs a bit shift on the data based on the value of EXP. This bit shifting is used to expand the compressed dynamic range resulting from the DVGA operation. The DVGA gain is adjusted in 6dB steps which are equivalent to each digital bit shift. The control interface is asynchronous with respect to the system clock, CK (CK = CKA + CKB). This allows the registers to be written or read at any time. In some cases this might cause an invalid operation since the interface is not internally synchronized. In order to assure correct operation, SI must be asserted after the control registers are written. The D[7:0], A[7:0], WR, RD and CE pins should not be driven above the positive supply voltage. Digitally compensating for the DVGA gain steps in the CLC5903 causes the DDC output to be linear with respect to the DVGA input. The AGC operation will be completely transparent at the CLC5903 output. Master Reset A master reset pin, MR, is provided to initialize the CLC5903 to a known condition and should be strobed after power up. This signal will clear all sample data and all user programmed data (filter coefficients and AGC settings). All outputs will be disabled (tri-stated). ASTROBE and BSTROBE will be asserted to initialize the DVGA values. Control Register Addresses and Defaults on page 21 describes the control register default values. The exponent (EXP) can be forced to its maximum value by setting the EXP_INH bit. If x in ( n ) is the DDC input, the signal after the “FLOAT TO FIXED CONVERTER” is x 3 ( n ) = x in ( n ) • cos ( ωn ) • 2 Synchronizing Multiple CLC5903 Chips A system containing two or more CLC5903 chips will need to be synchronized if coherent operation is desired. To synchronize multiple CLC5903 chips, connect all of the sync input pins together so they can be driven by a common sync strobe. Synchronization occurs on the rising edge of CKA|B when SI goes back high. When SI is asserted all sample data will be flushed immediately, the numerically controlled oscillator (NCO) phase offset will be initialized, the NCO dither generators will be reset, and the CIC decimation ratio will be initialized. Only the configuration data loaded into the microprocessor interface remains unaffected. 17 SIN COS x3 ( n ) Data @ FCK/N 21 Data @ FCK/N*2 NCO PHASE_A N = DEC + 1 Figure 16. CLC5903 Down Converter, Channel A (Channel B is identical) www.national.com DEC_BY_4 F2_COEF 12 I SAT 21 F2 FILTER DECIMATE BY 2 OR 4 21 SAT & ROUND 21 F1 FILTER DECIMATE BY 2 22 SHIFT UP 22 SAT & ROUND 15 17 F1_COEF DEC CIC FILTER DECIMATE BY 8 TO 2K Data @ FCK = FS (FSAMPLE) GAIN_A SCALE 14 15 FLOAT TO FIXED CONVERTER EXPONENT MUXA FREQ_A SHIFT UP EXP 3 x in ( n ) (1) The “FLOAT TO FIXED CONVERTER” circuit expands the dynamic range compression performed by the DVGA. Signals from this point onward extend across the full dynamic range of the signals applied to the DVGA input. This allows the AGC to operate continuously through a burst without producing artifacts in the signal due to the settling response of the decimation filters after a 6dB DVGA gain adjustment. For example, if the DVGA input signal were to increase causing the ADC output level to cross the AGC threshold level, the gain of the DVGA would change by -6dB. The 6dB step is allowed to propagate through the ADC and mixers and is compensated out just before the filtering. The accuracy of EXP_INH EXP (from AGC) EXP for the I component. Changing the ‘cos’ to ‘sin’ in this equation will provide the Q component. SI may be held low as long as desired after a minimum of 4 CK periods. ROUND CLC5903 Detailed Description (Continued) TO OUTPUT CIRCUIT Q Data @ FCK/N*2*F2_DEC = OFS (Output FSAMPLE) the compensation is dependent on timing and the accuracy of the DVGA gain step. The CLC5903 allows the timing of the gain compensation to be adjusted in the EXT_DELAY register. This operating mode requires 21 bits (14-bit ADC output + 7-bit shift) to represent the full linear dynamic range of the signal. The output word must be set to either 24-bit or 32-bit to take advantage of the entire dynamic range available. The CLC5903 can also be configured to output a floating point format with up to 138dB of numerical resolution using only 12 output bits. The “SHIFT UP” circuit will be discussed in the Four Stage CIC filter section on page 14. A 4-stage cascaded-integrator-comb (CIC) filter and a two-stage decimate by 4 or 8 finite impulse response (FIR) filter are used to lowpass filter and isolate the desired signal. The CIC filter reduces the sample rate by a programmable factor ranging from 8 to 2048 (decimation ratio). The CIC outputs are followed by a gain stage and then followed by a two-stage decimate by 4 or 8 filter. The gain circuit allows the user to boost the gain of weak signals by up to 42 dB in 6 dB steps. It also rounds the signal to 21 bits and saturates at plus or minus full scale. The first stage of the two stage filter is a 21-tap, symmetric decimate by 2 FIR filter (F1) with programmable 16 bit tap weights. The coefficients of the first 11 taps are downloaded to the chip as 16 bit words. Since the filter is a symmetric configuration only the first 11 coefficients must be loaded. The F1 section on page 15 provides a generic set of coefficients that compensate for the rolloff of the CIC filter and provide a passband flat to 0.01dB with 70 dB of out of band rejection. A second coefficient set is provided that has a narrower output passband and greater out-of-band rejection. The second set of coefficients is ideal for systems such as GSM where far-image rejection is more important than adjacent channel rejection. The second stage is a 63 tap decimate by 2 or 4 programmable FIR filter (F2) also with 16 bit tap weights. Filter coeffi- cients for a flat response from -0.4FS to +0.4FS of the output sample rate with 80dB of out of band rejection are provided in the F2 section. A second set of F2 coefficients is also provided to enhance performance for GSM systems. The user can also design and download their own final filter to customize the channel’s spectral response. Typical uses of programmable filter F2 include matched (root-raised cosine) filtering, or filtering to generate oversampled outputs with greater out of band rejection. The 63 tap symmetrical filter is downloaded into the chip as 32 words, 16 bits each. Saturation to plus or minus full scale is performed at the output of F1 and F2 to clip the signal rather than allow it to roll over. The CLC5903 provides two sets of coefficient memory for both F1 and F2. These coefficient memories can be independently routed to channel A, channel B, or both channel A and B with a crossbar switch. The coefficients can be switched on the fly but some time will be required before valid output data is available. The Numerically Controlled Oscillator The tuning frequency of each down converter is specified as a 32 bit word (.02Hz resolution at CK=52MHz) and the phase offset is specified as a 16 bit word (.005°). These two parameters are applied to the Numerically Controlled Oscillator (NCO) circuit to generate sine and cosine signals used by the digital mixer. The NCOs can be synchronized with NCOs on other chips via the sync pin SI. This allows multiple down converter outputs to be coherently combined, each with a unique phase and amplitude. The tuning frequency is set by loading the FREQ register according to the formula FREQ = 232F/FCK, where F is the desired tuning frequency and F CK is the chip’s clock rate. FREQ is a 2’s complement word. The range for F is from -FCK/2 to +FCK(1-2-31)/2. In some cases the sampling process causes the order of the I and Q components to be reversed. Should this occur simply invert the polarity of the tuning frequency F. Complex NCO Output 0 0 -20 -20 -40 -40 Magnitude (dB) Magnitude (dB) Complex NCO Output -60 -80 -60 -80 -100 -100 -120 -120 -140 -140 -160 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 -160 -0.5 0.5 Frequency Normalized to FS -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 Frequency Normalized to FS (b) After Phase Dithering (a) Before Phase Dithering Figure 17. Example of NCO spurs due to phase truncation 13 www.national.com CLC5903 Detailed Description (Continued) Complex NCO Output Phase Dither Disabled The 2’s complement format represents full-scale negative as 10000000 and full-scale positive as 01111111 for an 8-bit example. 0 N C O f r e q u e n c y sw e p t The 16 bit phase offset is set by loading the PHASE register according to the formula PHASE = 2 16P/2π, where P is the desired phase in radians ranging between 0 and 2π. PHASE is an unsigned 16-bit number. P ranges from 0 to 2π(1-2-16). -20 Magnitude (dB) -40 Phase dithering can be enabled to reduce the spurious signals created by the NCO due to phase truncation. This truncation is unavoidable since the frequency resolution is much finer than the phase resolution. With dither enabled, spurs due to phase truncation are below -100 dBc for all frequencies and phase offsets. Each NCO has its own dither source and the initial state of one is maximally offset with respect to the other so that they are effectively uncorrelated. The phase dither sources are on by default. They are independently controlled by the DITH_A and DITH_B bits. The amplitude resolution of the ROM creates a worst-case spur amplitude of -101dBc rendering amplitude dither unnecessary. -60 -80 -100 -120 -140 -160 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 Figure 18. NCO Spurs due to Phase Quantization Complex NCO Output Phase Dither Enabled 0 Figure 18 shows the spur levels as the tuning frequency is scanned over a narrow portion of the frequency range. The spurs are again a result of phase quantization but their locations move about as the frequency scan progresses. As before, the peak spur level drops when dithering is enabled. When dither is enabled and the fundamental frequency is exactly at FS/8, the worst-case spur due to amplitude quantization can be observed at -101dBc in Figure 19. -20 Magnitude (dB) -40 Four Stage CIC Filter The mixer outputs are decimated by a factor of N in a four stage CIC filter. N is programmable to any integer between 8 and 2048. Decimation is programmed in the DEC register where DEC = N - 1. The programmable decimation allows the chip’s usable output bandwidth to range from about 2.6kHz to 1.3MHz when the input data rate (which is equal to the chip’s clock rate, FCK) is 52 MHz. For the maximum sample rate of 78MHz, the CLC5903’s output bandwidth will range from about 4.76kHz to 1.95MHz. A block diagram of the CIC filter is shown in Figure 20. -60 -80 -100 -120 -140 -160 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 Figure 19. Worst Case Amplitude Spur, NCO at FS/8 The CIC filter has a gain equal to N 4 (filter decimation^4) which must be compensated for in the “SHIFT UP” circuit shown in Figure 20 as well as Figure 16. This circuit has a gain equal to 2(SCALE-44), where SCALE ranges from 0 to 40. This circuit divides the input signal by 2 44 providing maxi- Data @ FCK = FS (FSAMPLE) DECIMATE BY FACTOR OF N SCALE 22 66 22-bit input to SHIFT_UP is aligned at the bottom of the 66-bit path when SCALE=0. N = DEC + 1 Figure 20. Four-stage decimate by N CIC filter www.national.com 0.5 Frequency Normalized to FS The CIC filter is primarily used to decimate the high-rate incoming data while providing a rough lowpass characteristic. The lowpass filter will have a sin(x)/x response (similar to the AGC’s CIC shown in Figure 36 on page 24) where the first null is at FS/N. DATA IN 0.5 Frequency Normalized to FS The spectrum plots in Figure 17 show the effectiveness of phase dither in reducing NCO spurs due to phase truncation for a worst-case example (just below F S/8). With dither off, the spur is at -86.4dBFS. With dither on, the spur is below -125dBFS, disappearing into the noise floor. This spur is spread into the noise floor which results in an SNR of -83.6dBFS. The channel filter’s processing gain will further improve the SNR. SHIFT UP CLC5903 Detailed Description (Continued) 14 DATA OUT Data @ FCK/N mum headroom through the CIC filter. For optimal noise performance the SCALE value is set to increase this level until the CIC filter is just below the point of distortion. A value is normally calculated and loaded for SCALE such that GAIN SHIFTUP ⋅ GAIN CIC ≤ 1 . The actual gain of the CIC filter will only be unity for power-of-two decimation values. In other cases the gain will be somewhat less than unity. The second set of coefficients (GSM set) are intended for applications that need deeper stop bands or need oversampled outputs. These requirements are common in cellular systems where out of band rejection requirements can exceed 100dB (see Figure 22). They are useful for wideband radio architectures where the channelization is done after the ADC. These filter coefficients introduce a gain of 0.984 and are: -49, -340, -1008, -1617, -1269, 425, 3027, 6030, 9115, 11620, 12606 Channel Gain The gain of each channel can be boosted up to 42 dB by shifting the output of the CIC filter up by 0 to 7 bits prior to rounding it to 21 bits. For channel A, the gain of this stage is: Frequency Response of F1 Using GSM Set 0 GAIN_A First Programmable FIR Filter (F1) The CIC/GAIN outputs are followed by two stages of filtering. The first stage is a 21 tap decimate-by-2 symmetric FIR filter with programmable coefficients. Typically, this filter compensates for a slight droop induced by the CIC filter while removing undesired alias images above Nyquist. In addition, it often provides stopband assistance to F2 when deep stop bands are required. The filter coefficients are 16-bit 2’s complement numbers. Unity gain will be achieved through the filter if the sum of the 21 coefficients is equal to 216. If the sum is not 216, then F1 will introduce a gain equal to (sum of coefficients)/216. The 21 coefficients are identified as coefficients h 1 ( n ), n = 0, …, 20 where h 1 ( 10 ) is the center tap. The coefficients are symmetric, so only the first 11 are loaded into the chip. Two example sets of coefficients are provided here. The first set of coefficients, referred to as the standard set (STD), compensates for the droop of the CIC filter providing a passband which is flat (0.01 dB ripple) over 95% of the final output bandwidth with 70dB of out-of-band rejection (see Figure 21). The filter has a gain of 0.999 and is symmetric with the following 11 unique taps (1|21, 2|20, ..., 10|12, 11): 29, -85, -308, -56, 1068, 1405, -2056, -6009, 1303, 21121, 32703 −40 −60 −80 −100 −120 0 0.1 0.2 0.3 0.4 Frequency Normalized To Filter Input Sample Rate 0.5 Figure 22. F1 GSM frequency response Second Programmable FIR Filter (F2) The second stage decimate by two or four filter also uses externally downloaded filter coefficients. F2 determines the final channel filter response. The filter coefficients are 16-bit 2’s complement numbers. Unity gain will be achieved through the filter if the sum of the 63 coefficients is equal to 216. If the sum is not 216, then the F2 will introduce a gain equal to (sum of coefficients)/216. The 63 coefficients are identified as h 2 ( n ) , n = 0 ,… ,62 where h 2 ( 31 ) is the center tap. The coefficients are symmetric, so only the first 32 are loaded into the chip. An example filter (STD F2 coefficients, see Figure 23) with 80dB out-of-band rejection, gain of 1.00, and 0.03 dB peak to peak passband ripple is created by this set of 32 unique coefficients: Frequency Response of F1 Using STD Set 0 −10 -14, -20, 19, 73, 43, -70, -82, 84, 171, -49, -269, -34, 374, 192, -449, −20 -430, 460,751, -357, -1144, 81, 1581, 443, -2026, -1337, 2437, 2886, −30 Magnitude (dB) −20 Magnitude (dB) , where GAIN_A ranges from 0 to 7. OverGAIN = 2 flow due to the GAIN circuit is saturated (clipped) at plus or minus full scale. Each channel can be given its own GAIN setting. −40 -2770, -6127, 2987, 20544, 29647 −50 A second set of F2 coefficients (GSM set, see Figure 24) suitable for meeting the stringent wideband GSM requirements with a gain of 0.999 are: −60 −70 -536, -986, 42, 962, 869, 225, 141, 93, -280, -708, -774, -579, -384, −80 −90 −100 -79, 536, 1056, 1152, 1067, 789, 32, -935, -1668, -2104, -2137, -1444, 0 0.1 0.2 0.3 0.4 Frequency Normalized To Filter Input Sample Rate 0.5 71, 2130, 4450, 6884, 9053, 10413, 10832 The filter coefficients of both filters can be used to tailor the spectral response to the user’s needs. For example, the first can be loaded with the standard set to provide a flat Figure 21. F1 STD frequency response 15 www.national.com CLC5903 Detailed Description (Continued) Combined Frequency Response of CIC/F1/F2 Using STD Set 0 Frequency Response of F2 Using STD Set FCK = 52MHz Decimation = 192 OFS = 270.83kHz 0 −10 −30 Magnitude (dB) −50 Magnitude (dB) −20 −40 −100 −50 −60 −70 −80 −150 −90 −100 0 0.1 0.2 0.3 0.4 Frequency Normalized To Filter Input Sample Rate 0 500 1000 1500 2000 Frequency (KHz) 2500 3000 Figure 25. CIC, F1, & F2 STD frequency response 0.5 Figure 23. F2 STD frequency response Combined Frequency Response of CIC/F1/F2 Using STD Set 0.1 Frequency Response of F2 Using GSM Set 0.08 5 0.06 0 0.04 Magnitude (dB) −5 −10 Magnitude (dB) −15 −20 −25 0.02 0 −0.02 −0.04 −30 −0.06 −35 −0.08 −40 −0.1 −45 −50 0 0.1 0.2 0.3 0.4 Frequency Normalized To Filter Input Sample Rate 0.5 0 Figure 24. F2 GSM frequency response 100 150 Frequency (KHz) 200 250 Combined Frequency Response of CIC/F1/F2 Using GSM Set response through to the second filter. The latter can then be programmed as a Nyquist (typically a root-raised-cosine) filter for matched filtering of digital data. 0 FCK = 52MHz Decimation = 192 OFS = 270.83kHz −20 The complete channel filter response for standard coefficients is shown in Figure 25. Passband flatness is shown in Figure 26. The complete filter response for GSM coefficients is shown in Figure 27. GSM Passband flatness is shown in Figure 28. The mask shown in Figure 27 is derived from the ETSI GSM 5.05 specifications for a normal Basestation Transceiver (BTS). For interferers, 9dB was added to the carrier to interference (C/I) ratios. For blockers, 9dB was added to the difference between the blocker level and 3dB above the reference sensitivity level. −40 −60 −80 −100 Channel Bandwidth vs. Sample Rate When the CLC5903 is used for GSM systems, a bandwidth of about 200kHz is desired. With a sample rate of 52MHz, the total decimation of 192 provides the desired 270.833kHz output sample rate. This output sample rate in combination with the FIR filter coefficients create the desired channel bandwidth. If the sample rate is increased to 65MHz, the decimation must also be increased to 65MHz/270.833kHz or 240. This new decimation rate will maintain the same output www.national.com 50 Figure 26. CIC, F1, & F2 STD Passband Flatness Magnitude (dB) CLC5903 Detailed Description (Continued) 0 500 1000 1500 2000 Frequency (KHz) 2500 3000 Figure 27. CIC, F1, & F2 GSM frequency response bandwidth. At 78MHz, the decimation must increase again to 78MHz/270.833kHz or 288. The output bandwidth may only be changed in relation to the output sample rate by creating a new set of FIR filter coefficients. As the filter bandwidth 16 Combined Frequency Response of CIC/F1/F2 Using GSM Set 1 Data Latency and Group Delay The CLC5903 latency calculation assumes that the FIR filter latency will be equal to the time required for data to propagate through one half of the taps. The CIC filter provides 4N equivalent taps where N is the CIC decimation ratio. F1 and F2 provide 21 and 63 taps respectively. When these filters are reflected back to the input rate, the effective taps are increased by decimation. This results in a total of 298N taps when the F2 decimation is 2 and 550N taps when the F2 decimation is 4. 0.5 −0.5 −1 The latency is then 149N CK periods when the F2 decimation is 2 and 275N CK periods when the F2 decimation is 4. −1.5 40 60 Frequency (KHz) 80 The CLC5903 filters are linear phase filters so the group delay remains constant. 100 Output Modes Figure 28. CIC, F1, & F2 GSM Passband Flatness decreases relative to the output sample rate, the CIC droop compensation performed by F1 may no longer be required. Overall Channel Gain The overall gain of the chip is a function of the amount of decimation (N), the settings of the “SHIFT UP” circuit (SCALE), the GAIN setting, the sum of the F1 coefficients, and the sum of the F2 coefficients. The overall gain is shown below in Equation 2. 4 1 G DDC = --- ( DEC + 1 ) 2 ⋅2 ⋅2 After processing by the DDC, the data is then formatted for output. All output data is two’s complement. The serial outputs power up in a tri-state condition and must be enabled when the chip is configured. Parallel outputs are enabled by the POUT_EN pin. Output formats include truncation to 8 or 32 bits, rounding to 16 or 24 bits, and a 12-bit floating point format (4-bit exponent, 8-bit mantissa, 138dB numeric range). This function is performed in the OUTPUT CIRCUIT shown in Figure 29. (2) [ SCALE – 44 – AGAIN ⋅ ( 1 – EXP_INH ) ] RDY_POL, SCK_POL, SFS_POL GAIN CK CH B ⋅ G F1 ⋅ G F2 Where: ∑ h1 ( i ) =1 G F1 = i---------------------16 2 (3) 63 ∑ h2 ( i ) =1 G F2 = i---------------------16 2 (4) It is assumed that the DDC output words are treated as fractional 2’s complement words. The numerators of G F1 and RDY SCK SFS AOUT BOUT SCK_IN FORMAT and: CH A 21 DIVIDE BY RATE POLARITY INVERT 20 SERIALIZER AND TDM FORMATTER 0 MUX_MODE PACKED SFS_MODE −2 NUMBER FORMAT CONTROL Magnitude (dB) 0 MUX POUT[15..0] 16 3 POUT_SEL[2..0] POUT_EN G F2 equal the sums of the impulse response coefficients of F1 and F2, respectively. For the STD and GSM sets, G F1 and G F2 are nearly equal to unity. Observe that the AGAIN term in (2) is cancelled by the DVGA operation so that the entire gain of the DRCS is independent of the DVGA setting 1 when EXP_INH=0. The --- appearing in (2) is the result of the 2 17 Figure 29. CLC5903 output circuit The channel outputs are accessible through serial output pins and a 16-bit parallel output port. The RDY pin is provided to notify the user that a new output sample period (OSP) has begun. OSP refers to the interval between output samples at the decimated output rate. For example, if the input rate (and clock rate) is 52 MHz and the overall decimation factor is 192 (N=48, F2 decimation=2) the OSP will be 3.69 microseconds which corresponds to an output sample www.national.com CLC5903 6dB conversion loss in the mixer. For full-scale square wave 1 inputs the --- should be set to 1 to prevent signal distortion. 2 Output Modes (Continued) CLC5903 Output Modes (Continued) clock stops and data is zero after transfers are complete SCK SFS AOUT I15 I14 I1 I0 Q15 Q14 Q1 Q0 (a) UNPACKED MODE, FRAME SYNC AT THE START OF EACH WORD clock stops and data is zero after transfers are complete SCK SFS I15 AOUT I1 I14 I0 Q15 Q14 Q1 Q0 (b) PACKED MODE, ONE FRAME SYNC AT THE START OF EACH DOUBLE-WORD TRANSFER RDY leading edge of RDY aligns with leading edge of SFS RDY is 2 CK periods wide Output Sample Period (OSP) SFS A|BOUT IA QA SFS AOUT IA QA IB SFS AOUT IA QA IB MUX_MODE=0, SFS_MODE=0|1 IA QA QB MUX_MODE=1, SFS_MODE=0 IA QA IB QB QB MUX_MODE=1, SFS_MODE=1 IA QA IB QB (c) ONE OR TWO CHANNEL MUX AND SFS MODES (PACKED MODE IS ON) clock stops and data is zero after transfers are complete SCK SFS AOUT mI7 mI6 mI0 eI3 eI2 eI0 eQ3 eQ0 mQ7 mQ0 (d) FLOATING POINT FORMAT Figure 30. Serial output formats. Refer to Figure 10 for detailed timing information rate of 270.833kHz. An OSP starts when a sample is ready and stops when the next one is ready. SERIAL OUTPUTS SFS_MODE Serial Outputs The CLC5903 provides a serial clock (SCK), a frame strobe (SFS) and two data lines (AOUT and BOUT) to output serial data. The MUX_MODE control register specifies whether the two channel outputs are transmitted on two separate serial pins, or multiplexed onto one pin in a time division multiplexed (TDM) format. Separate output pins are not provided for the I and Q halves of complex data. The I and Q outputs are always multiplexed onto the same serial pin. The I-component is output first, followed by the Q-component. By setting the PACKED mode bit to ‘1’ a complex pair may be treated as a single double-wide word. The RDY signal is used to identify the first word of a complex pair of the TDM formatted output when the SFS_MODE bit is set to ‘0’. Setting SFS_MODE to ‘1’ causes the CLC5903 to output a single SFS pulse for each output period. This SFS pulse will be coincident with RDY and only a single SCK period wide. The TDM modes are summarized in Table 1. www.national.com MUX_MODE AOUT BOUT 0 OUTA OUTB 1 OUTA, OUTB LOW 0 OUTA OUTB 1 OUTA, OUTB LOW 0 1 Table 1. TDM Modes The serial outputs use the format shown in Figure 30. Figure 30(a) shows the standard output mode (the PACKED mode bit is low). The chip clocks the frame and data out of the chip on the rising edge of SCK (or falling edge if the SCK_POL bit in the input control register is set high). Data should be captured on the falling edge of SCK (rising if SCK_POL=1). The 18 CLC5903 AGC (Continued) Master CLC5903 SCK To DSP SFS RDY ParallelOutput[15..0] ParallelOutputEnable ParallelSelect[2..0] 12 12 SDC_EN=1 MUX_MODE=0 12 4 SDC_EN=0 MUX_MODE=0 PACKED=1 12 AOUT 4 Slave CLC5903 POUT_SEL POUT_SEL POUT_SEL SCK_IN AOUT BOUT SFS SCK SCKMASTER=2*SCKSLAVE ADCs and DVGAs ADCs and DVGAs Figure 31. Serial Daisy-Chain Mode chip sends the I data first by setting SFS high (or low if SFS_POL in the input control register is set high) for one clock cycle, and then transmitting the data, MSB first, on as many SCK cycles as are necessary. Without a pause, the Q data is transferred next as shown in Figure 30(a). If the PACKED control bit is high, then the I and Q components are sent as a double length word with only one SFS strobe as shown in Figure 30(b). If both channels are multiplexed out the same serial pin, then the subsequent I/Q channel words will be transmitted immediately following the first I/Q pair as shown in Figure 30(c). Figure 30(c) also shows how SFS_MODE=1 allows the SFS signal to be used to identify the I and Q channels in the TDM serial transmission. The serial output rate is programmed by the RATE register to CK divided by 1, 2, 4, 8, 16, or 32. The serial interface will not work properly if the programmed rate of SCK is insufficient to clock out all the bits in one OSP. Serial Port Daisy-Chain Mode Two CLC5903s can be connected in series so that a single DSP serial port can receive four DDC output channels. This mode is enabled by setting the SDC_EN bit to ‘1’ on the serial daisy-chan (SDC) master. The SDC master is the CLC5903 which is connected to the DSP while the SDC slave’s serial output drives the master. The SDC master’s RATE register must be set so that its SCK rate is twice that of the SDC slave, the SDC master must have MUX_MODE=1, the SDC slave must have MUX_MODE=0 and PACKED=1, and both chips must come out of a MR or SI event within four CK periods of each other. In this configuration, the master’s serial output data is shifted out to the DSP then the slave’s serial data is shifted out. All the serial output data will be muxed onto the master’s AOUT pin as shown in Figure 31. Serial Port Output Number Formats Several numeric formats are selectable using the FORMAT control register. The I/Q samples can be rounded to 16 or 24 bits, or truncated to 8 bits. The packed mode works as described above for these fixed point formats. A floating point format with 138dB of dynamic range in 12 bits is also provided. The mantissa (m) is 8 bits and the exponent (e) is 4 bits. The MSB of each segment is transmitted first. When this mode is selected, the I/Q samples are packed regardless of the state of MUX_MODE, and the data is sent as mI/eI/eQ/ mQ which allows the two exponents to form an 8-bit word. This is shown in Figure 30(d). For all formats, once the defined length of the word is complete, SCK stops toggling. 19 Parallel Outputs Output data from the channels can also be taken from a 16-bit pa ra llel por t. A 3-bit wo rd a pplie d to th e POUT_SEL[2:0] pins determines which 16-bit segment is multiplexed to the parallel port. Table 2 defines this mapping. To allow for bussing of multiple chips, the parallel port is tri-stated unless POUT_EN is low. The RDY signal indicates the start of an OSP and that new data is ready at the parallel output. The user has one OSP to cycle through whichever registers are needed. The RATE register must be set so that each OSP is at least 5 SCK periods. Parallel Port Output Numeric Formats The I/Q samples can be rounded to 16 or 24 bits or the full 32 bit word can be read. By setting the word size to 32 bits it is possible to read out the top 16 bits and only observe the top 8 bits if desired. Additionally, the output samples can be formatted as floating point numbers with an 8-bit mantissa and a 4 bit exponent. For the fixed-point formats, the valid bits are justified into the MSBs of the registers of Table 2 and POUT_SEL Normal Register Contents Floating Point Register Contents 0 IA upper 16 bits 0000/eIA/mIA 1 IA lower 16 bits 0x0000 2 QA upper 16 bits 0000/eQA/mQA 3 QA lower 16 bits 0x0000 4 IB upper 16 bits 0000/eIB/mIB 5 IB lower 16 bits 0x0000 6 QB upper 16 bits 0000/eQB/mQB 7 QB lower 16 bits 0x0000 Table 2. Register Selection for Parallel Output all other bits are set to zero. For the floating point format, the valid bits are placed in the upper 16 bits of the appropriate channel register using the format 0000/eI/mI for the I samples. AGC The CLC5903 AGC processor monitors the output level of the ADC and servos it to the desired setpoint. The ADC input is controlled by the DVGA to maintain the proper setpoint www.national.com after programming the desired gain in the AGC_IC_A and AGC_IC_B registers. Allowing the AGC to free run should be appropriate for most applications. level. DVGA operation results in a compression of the signal through the ADC. The DVGA signal compression is reversed in the CLC5903 to provide > 120dB of linear dynamic range. This is illustrated in Figure 32. Output Power A O GC ve O rT p hi era s te R s an ge Diversity Receiver Chipset Full Scale D D C O pu ut Programming the AGC_COMB_ORD register allows the AGC power detector bandwidth to be reduced if desired. This will tend to improve the power detector’s ability to reject the signal carrier frequency and reduce overall AGC activity. Figure 36 on page 24 shows the power detector response. Power Management t The CLC5903 can be placed in a low power (static) state by stopping the input clock. To prevent this from placing the CLC5903 into unexpected states, the SI pin of the CLC5903 should be asserted prior to disabling the input clock and held asserted until the input clock has returned to a stable condition. ADC Full Scale Test and Diagnostics AGC Threshold The CLC5903 supports IEEE 1149.1 compliant JTAG Boundary Scan for the I/O's. The following pins are used: TRST TMS TDI TDO TCK ADC Output Deadband+Hysteresis Input Power 6dB In order to use the AGC, the DRCS Control Panel software may be used to calculate the programmable parameters. To generate these parameters, only the desired setpoint, deadband+hysteresis, and loop time constant need to be supplied. All subsequent calculations are performed by the software. Complete details of the AGC operation are provided in an appendix but are not required reading. Instruction Description BYPASS Connects TDI directly to TDO EXTEST Drives the ‘extest’ TAP controller output IDCODE Connects the 32-bit ID register to TDO SAMPLE/PRELOAD Drives the ‘samp_load’ TAP controller output HIGHZ Tri-states the outputs The JTAG Boundary Scan can be used to verify printed circuit board continuity at the system level. Deadband The user is able to program a value into TEST_REG and substitute this for the normal channel inputs from the AIN/ BIN pins by selecting it with the crossbar. With the NCO frequency set to zero this allows the DDCs and the output interface of the chip to be verified. Also, the AGC loop can be opened by setting AGC_HOLD_IC high and setting the gain of the DVGA by programming the appropriate value into the AGC_IC_A/B register. Reference Setpoint 6dB Hysteresis=Deadband-6dB DVGA Input Power Real-time access to the following signals is provided by configuring the control interface debug register: Figure 33. AGC Setup. • • • • AGC setpoint and deadband+hysteresis are illustrated in Figure 33. The loop time constant is a measure of how fast the loop will track a changing signal. Values down to approximately 1.0 microsecond will be stable with the second order LC noise filter. Since the DVGA operates with 6dB steps the deadband should always be greater than 6dB to prevent oscillation. An increased deadband value will reduce the amount of AGC operation. A decreased deadband value will increase the amount of AGC operation but will hold the ADC output closer to the setpoint. The threshold should be set so that transients do not cause sustained overrange at the ADC inputs. The threshold setting can also be used to set the ADC input near its optimal performance level. NCO sine and cosine outputs data after round following mixers data before F1 and F2 data after the CIC filter within the AGC The access points are multiplexed to a 20-bit parallel output port which is created from signal pins POUT[15:0], AOUT, BOUT, SFS, and RDY according to the table below: The AGC will free run when AGC_HOLD_IC is set to ‘0’. It may be set to a fixed gain by setting AGC_HOLD_IC to ‘1’ www.national.com (test reset) (test mode select) (test data in) (test data out) (test clock) The following JTAG instructions are supported: Figure 32. Output Gain Scaling vs. Input Signal DVGA Output Power CLC5903 Test and Diagnostics (Continued) 20 Normal Mode Pin Debug Mode Pin POUT[15:0] DEBUG[19..4] RDY DEBUG SFS DEBUG AOUT DEBUG BOUT DEBUG Control Registers The chip is configured and controlled through the use of 8-bit control registers. These registers are accessed for reading or writing using the control bus pins (CE, RD, WR, A[7:0], and D[7:0]) described in the Control Interface section. The two sets of FIR coefficients are overlaid at the same memory address. Use the PAGE_SEL registers to access the second set of coefficients. The register names and descriptions are listed below under Control Register Addresses and Defaults on page 21. A quick reference table is provided in the Condensed CLC5903 Address Map on page 22. Control Register Addresses and Defaults Width Type Defaulta Addr Bit DEC 11b R/W 7 0(LSBs) 1(MSBs) 7:0 2:0 DEC_BY_4 1b R/W 0 1 4 Controls the decimation factor in F2. 0=Decimate by 2. 1=Decimate by 4. This affects both channels. SCALE 6b R/W 0 2 5:0 CIC SCALE parameter. Format is an unsigned integer representing the number of left bit shifts to perform on the data prior to the CIC filter. Valid range is from 0 to 40. This affects both channels. GAIN_A 3b R/W 0 3 2:0 Value of left bit shift prior to F1 for channel A. GAIN_B 3b R/W 0 4 2:0 Value of left bit shift prior to F1 for channel B. RATE 1B R/W 1 5 7:0 Determines rate of serial output clock. The output rate is FCK/(RATE+1). Unsigned integer values of 0, 1, 3, 7, 15, and 31 are allowed. SOUT_EN 1b R/W 0 6 0 Enables the serial output pins AOUT, BOUT, SCK, and SFS. 0=Tristate. 1=Enabled. SCK_POL 1b R/W 0 6 1 Determines polarity of the SCK output. 0=AOUT, BOUT, and SFS change on the rising edge of SCK (capture on falling edge). 1=They change on the falling edge of SCK. Register Name Description CIC decimation control. N=DEC+1. Valid range is from 7 to 2047. Format is an unsigned integer. This affects both channels. SFS_POL 1b R/W 0 6 2 Determines polarity of the SFS output. 0=Active High. 1=Active Low. RDY_POL 1b R/W 0 6 3 Determines polarity of the RDY output. 0=Active High. 1=Active Low. MUX_MODE 1b R/W 0 6 4 Determines the mode of the serial outputs. 0=Each channel is output on its respective pin, 1=Both channels are multiplexed and output on AOUT. See also Table 1. PACKED 1b R/W 0 6 5 Controls when SFS goes active. 0=SFS pulses prior to the start of the I and the Q words. 1=SFS pulses only once prior to the start of each I/Q sample pair (i.e. the pair is treated as a double-sized word) The I word precedes the Q word. See Figure 30. FORMAT 2b R/W 0 6 7:6 Determines output number format. 0=Truncate serial output to 8 bits. Parallel output is truncated to 32 bits. 1=Round both serial and parallel to 16 bits. All other bits are set to 0. 2=Round both serial and parallel to 24 bits. All other bits are set to 0. 3=Output floating point. 8-bit mantissa, 4-bit exponent. All other bits are set to 0. FREQ_A 4B R/W 0 7-10 7:0 Frequency word for channel A. Format is a 32-bit, 2’s complement number spread across 4 registers. The LSBs are in the lower registers. The NCO frequency F is F/FCK=FREQ_A/ 232. PHASE_A 2B R/W 0 11-12 7:0 Phase word for channel A. Format is a 16-bit, unsigned magnitude number spread across 2 registers. The LSBs are in the lower registers. The NCO phase PHI is PHI=2*pi*PHASE_A/ 2^16. FREQ_B 4B R/W 0 13-16 7:0 Frequency word for channel B. Format is a 32-bit, 2’s complement number spread across 4 registers. The LSBs are in the lower registers. The NCO frequency F is F/FCK=FREQ_B/ 232. PHASE_B 2B R/W 0 17-18 7:0 Phase word for channel B. Format is a 16-bit, unsigned magnitude number spread across 2 registers. The LSBs are in the lower registers. The NCO phase PHI is PHI=2*pi*PHASE_B/ 2^16. A_SOURCE 2 R/W 0 19 1:0 0=Select AIN as channel input source. 1=Select BIN. 2=3=Select TEST_REG as channel input source. B_SOURCE 2 R/W 1 19 3:2 0=Select AIN as channel input source. 1=Select BIN. 2=3=Select TEST_REG as channel input source. EXP_INH 1b R/W 0 20 0 0=Allow exponent to pass into FLOAT TO FIXED converter. 1=Force exponent in DDC channel to a 7 (maximum digital gain). This affects both channels. Reserved 1b R/W 1 20 1 AGC_FORCE on the CLC5902. Do not use. Reserved 1b R/W 0 20 2 AGC_RESET_EN on the CLC5902. Do not use. AGC_HOLD_IC 1b R/W 0 20 3 0=Normal closed-loop operation. 1=Hold integrator at initial condition. This affects both channels. AGC_LOOP_GAIN 2b R/W 0 20 4:5: Bit shift value for AGC loop. Valid range is from 0 to 3. This affects both channels. Reserved 2B R/W 0 21-22 7:0 AGC_COUNT on the CLC5902. Do not use. AGC_IC_A 1B R/W 0 23 7:0 AGC fixed gain for channel A. Format is an 8-bit, unsigned magnitude number. The channel A DVGA gain will be set to the inverted three MSBs. 21 www.national.com CLC5903 SCK will be set to the proper strobe rate for each debug tap point. POUT_EN and PSEL[2..0] have no effect in Debug Mode. The outputs are turned on when the Debug Mode bit is set. Normal serial outputs are also disabled. CLC5903 Control Register Addresses and Defaults (Continued) Width Type Defaulta Addr Bit Description AGC_IC_B 1B R/W 0 24 7:0 AGC fixed gain for channel B. Format is an 8-bit, unsigned magnitude number. The channel B DVGA gain will be set to the inverted three MSBs. AGC_RB_A 1B R 0 25 7:0 AGC integrator readback value for channel A. Format is an 8-bit, unsigned magnitude number. The user can read the magnitude MSBs of the channel A integrator from this register. AGC_RB_B 1B R 0 26 7:0 AGC integrator readback value for channel B. Format is an 8-bit, unsigned magnitude number. The user can read the magnitude MSBs of the channel B integrator from this register. TEST_REG 14b R/W 0 27(LSBs) 28(MSBs) 7:0 5:0 Test input source. Instead of processing values from the A|BIN pins, the value from this location is used instead. Format is 14-bit 2s complement number spread across 2 registers. Reserved 1B - - 29 7:0 For future use. Reserved 1B - - 30 7:0 For future use. DEBUG_EN 1b R/W 0 31 0 DEBUG_TAP 5b R/W 0 31 5:1 DITH_A 1b R/W 1 31 6 DITH_B 1b R/W 1 31 7 AGC_TABLE 32B R/W 0 128-159 7:0 RAM space that defines key AGC loop parameters. Format is 32 separate 8-bit, 2’s complement numbers. This is common to both channels. F1_COEFF 22B R/W 0 160-181 7:0 Coefficients for F1. Format is 11 separate 16-bit, 2’s complement numbers, each one spread across 2 registers. The LSBs are in the lower registers. For example, coefficient h0[7:0] is in address 160, h0[15:8] is in address 161, h1[7:0] is in address 162, h1[15:8] is in address 163. PAGE_SEL_F1=1 maps these addresses to coefficient memory B. F2_COEFF 64B R/W 0 182-245 7:0 Coefficients for F2. Format is 32 separate 16-bit, 2’s complement numbers, each one spread across 2 registers. The LSBs are in the lower registers. For example, coefficient h0[7:0] is in address 182, h0[15:8] is in address 183, h1[7:0] is in address 184, h1[15:8] is in address 185. PAGE_SEL_F2=1 maps these addresses to coefficient memory B. COEF_SEL_F1A 1b R/W 0 246 0 Channel A F1 coefficient select register. 0=memory A, 1=memory B. COEF_SEL_F1B 1b R/W 0 246 1 Channel B F1 coefficient select register. 0=memory A, 1=memory B. PAGE_SEL_F1 1b R/W 0 246 2 F1 coefficient page select register. 0=memory A, 1=memory B. COEF_SEL_F2A 1b R/W 0 247 0 Channel A F2 coefficient select register. 0=memory A, 1=memory B. COEF_SEL_F2B 1b R/W 0 247 1 Channel B F2 coefficient select register. 0=memory A, 1=memory B. PAGE_SEL_F2 1b R/W 0 247 2 F2 coefficient page select register. 0=memory A, 1=memory B. SFS_MODE 1b R/W 0 248 0 0=SFS asserted at the start of each output word when PACKED=1 or each I/Q pair when PACKED=0, 1=SFS asserted at the start of each output sample period. SDC_EN 1b R/W 0 248 1 0=normal serial mode, 1=serial daisy-chain master mode. AGC_COMB_ORD 2b R/W 0 249 1:0 Enable reduced bandwidth AGC power detector. 0=2nd-order decimate-by-eight CIC, 1=1-tap comb added to CIC, 2=4-tap comb added to CIC. EXT_DELAY 5b R/W 0 249 6:2 Number of CK period delays in excess of 4 needed to align the DVGA gain step with the digital gain compensation step. Use the default of zero for the CLC5957 ADC. Register Name 0=Normal. 1=Enables access to the internal probe points. Selects internal node tap for debug. 0 selects F1 output for BI, 20 bits 1 selects F1 output for BQ, 20 bits 2 selects F1 output for AQ, 20 bits 3 selects F1 output for AI, 20 bits 4 selects F1 input for BI, 20 bits 5 selects F1 input for BQ, 20 bits 6 selects F1 input for AI, 20 bits 7 selects F1 input for AQ, 20 bits 8 selects NCO A, cosine output. 17 bits, 3 LSBs are 0. 9 selects NCO A, sine output, 17 bits, 3 LSBs are 0. 10 selects NCO B, cosine output, 17 bits, 3 LSBs are 0. 11 selects NCO B, sine output, 17 bits, 3 LSBs are 0. 12 selects NCO AI, rounded output, 15 bits, 5 LSBs are 0. 13 selects NCO AQ, rounded output, 15 bits, 5 LSBs are 0. 14 selects NCO BI, rounded output, 15 bits, 5 LSBs are 0. 15 selects NCO BQ, rounded output, 15 bits, 5 LSBs are 0. 16-31 selects AGC CIC filter output. 9 MSBs from ch A, next 9 bits from ch B, 2 LSBs are 0. 0=Disable NCO dither source for channel A. 1=Enable. 0=Disable NCO dither source for channel B. 1=Enable. a. These are the default values set by a master reset (MR). Sync in (SI) will not affect any of these values. Condensed CLC5903 Address Map Register Name DEC www.national.com Addr Addr Hex 0 0x00 Bit7 Dec7 Bit6 Dec6 Bit5 Dec5 22 Bit4 Dec4 Bit3 Dec3 Bit2 Dec2 Bit1 Dec1 Bit0 Dec0 Addr Addr Hex DEC_BY_4 1 0x01 SCALE 2 0x02 GAIN_A 3 0x03 Register Name Bit7 (Continued) Bit6 Bit5 Bit4 Bit3 DecBy4 Sc5 Sc4 Sc3 Bit2 Bit1 Bit0 Dec10 Dec9 Dec8 Sc2 Sc1 Sc0 GA2 GA1 GA0 GB0 GAIN_B 4 0x04 GB2 GB1 RATE 5 0x05 Rate7 Rate6 Rate5 Rate4 Rate3 Rate2 Rate1 Rate0 SERIAL_CTRL 6 0x06 FMT1 FMT0 Packed MuxMode RDY_POL SFS_POL SCK_POL SOUT_EN FREQ_A 7 0x07 FA7 FA6 FA5 FA4 FA3 FA2 FA1 FA0 8 0x08 FA15 FA14 FA13 FA12 FA11 FA10 FA9 FA8 9 0x09 FA23 FA22 FA21 FA20 FA19 FA18 FA17 FA16 PHASE_A FREQ_B PHASE_B SOURCE 10 0x0A FA31 FA30 FA29 FA28 FA27 FA26 FA25 FA24 11 0x0B PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 12 0x0C PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 13 0x0D FB7 FB6 FB5 FB4 FB3 FB2 FB1 FB0 14 0x0E FB15 FB14 FB13 FB12 FB11 FB10 FB9 FB8 15 0x0F FB23 FB22 FB21 FB20 FB19 FB18 FB17 FB16 16 0x10 FB31 FB30 FB29 FB28 FB27 FB26 FB25 FB24 17 0x11 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 18 0x12 PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 19 0x13 BS1 BS0 AS1 AS0 AGC_CTRL 20 0x14 AGC_COUNT 21 0x15 Reserved Reserved AgcLG1 AgcLG0 AgcHldIC Reserved Reserved ExpInh Reserved Reserved Reserved Reserved Reserved Reserved 22 0x16 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AGC_IC_A 23 0x17 AgcIcA7 AgcIcA6 AgcIcA5 AgcIcA4 AgcIcA3 AgcIcA2 AgcIcA1 AgcIcA0 AGC_IC_B 24 0x18 AgcIcB7 AgcIcB6 AgcIcB5 AgcIcB4 AgcIcB3 AgcIcB2 AgcIcB1 AgcIcB0 AGC_RB_A 25 0x19 AgcRbA7 AgcRbA6 AgcRbA5 AgcRbA4 AgcRbA3 AgcRbA2 AgcRbA1 AgcRbA0 AGC_RB_A 26 0x1A AgcRbB7 AgcRbB6 AgcRbB5 AgcRbB4 AgcRbB3 AgcRbB2 AgcRbB1 AgcRbB0 TEST_REG 27 0x1B Test7 Test6 Test5 Test4 Test3 Test2 Test1 Test0 Test13 Test12 Test11 Test10 Test9 Test8 DITH_B DITH_A TapSel4 TapSel3 TapSel2 TapSel1 TapSel0 DebugEnable 28 0x1C DEBUG 31 0x1F AGC_TABLE 128 0x80 The AGC Table loads from the low address to the high address in this order: 159 0x9F “1st location, 2nd location…” 160 0xA0 181 0xB5 The FIR Coefficients load from the low address to the high address in this order: 182 0xB6 “1st location low byte, 1st location high byte, 2nd location…” 245 0xF5 The Page Select bits determine which set of coefficient memory is written. F1_CTRL 246 0xF6 PgSelF1 CfSelF1B CfSelF1A F2_CTRL 247 0xF7 PgSelF2 CfSelF2B CfSelF2A F1_COEFF F2_COEFF SERIAL_CTRL2 248 0xF8 AGC_CTRL2 249 0xF9 ExtDelay4 23 ExtDelay3 ExtDelay2 ExtDelay1 ExtDelay0 SdcEn SfsMode CombOrd1 CombOrd0 www.national.com CLC5903 Condensed CLC5903 Address Map AGC Power Detection Filter: Amplitude Response 10 AGC Theory of Operation CIC CIC + 1−tap Comb CIC + 4−tap Comb 0 AGC_COMB_ORD=2 A block diagram of the AGC is shown in Figure 34. The DVGA interface comprises four pins for each of the channels. The first three pins of this interface are a 3-bit binary word that controls the DVGA gain in 6dB steps (AGAIN). The final pin is ASTROBE which allows the AGAIN bits to be latched into the DVGA’s register. A key feature of the ASTROBE, illustrated Figure 35, is that it toggles only if the data on AGAIN has changed from the previous cycle. Not shown is that ASTROBE and BSTROBE are independent. For example, ASTROBE only toggles when AGAIN has changed. BSTROBE will not toggle because AGAIN has changed. This is done to minimize unnecessary digital noise on the sensitive analog path through the DVGA. ASTROBE and BSTROBE are asserted during MR and SI to properly initialize the DVGAs. −10 AGC_COMB_ORD=0 −20 AGC_COMB_ORD=1 Magnitude/dB −30 −40 −50 −60 −70 −80 −90 −100 0 5 10 15 20 25 30 Frequency/MHz 35 40 45 50 Figure 36. Power detector filter response, 52MHz The absolute value circuit and the 2-stage, decimate-by-8 CIC filter comprise the power detection part of the AGC. The power detector bandwidth is set by the CIC filter to F CK/8. The absolute value circuit doubles the effective input frequency. This has the effect of reducing the power detector bandwidth from FCK/8 to FCK/16. circuit is about 10dB below the dc this means that the ripple in the detected level is about 0.7dB or less for input frequencies between FCK/20 to 19FCK/20. Setting the AGC_COMB_ORD register to either 1 or 2 will narrow the power detector’s bandwidth as shown in Figure 36. The “FIXED TO FLOAT CONVERTER” takes the fixed point 9-bit output from the CIC filter and converts it to a “floating point” number. This conversion is done so that the 32 values in the RAM can be uniformly assigned (dB scale) to detected power levels (54 dB range). This provides a resolution of 1.7dB between detected power levels. The truth table for this converter is given in Table 3. The upper three bits of the output represent the exponent (e) and the lower 2 are the mantissa (m). The exponent is determined by the position of the For a full-scale sinusoidal input, the absolute value circuit output is a dc value of 511 ⋅ ( 2 ⁄ π ) . Because the absolute value circuit also generates undesired even harmonic terms, the CIC filter (response shown in Figure 36), is required to, remove these harmonics. The first response null occurs at FCK/8, where FCK is the clock frequency, and the response magnitude is at least 25dB below the dc value from FCK/10 to 9FCK/10. Because the 2nd harmonic from the absolute value AGC_TABLE AGC_LOOP_GAIN FUNCTION PROGRAMMED INTO RAM 8 12 AGAIN 3 12 MUX 5 SHIFT DOWN 9 32X8 RAM 9 POUT FIXED TO FLOAT CONVERTER 16 POST CIC COMB FILTER 10 2 STAGE DECIMATE BY 8 CIC FILTER AIN[13:4] (from MUXA) SHIFT DOWN EXP ABSOLUTE VALUE CLC5903 AGC Theory of Operation (Continued) AGC_IC_A AGC_HOLD_IC LOG -REF Figure 34. CLC5903 AGC circuit, Channel A ASTROBE does not pulse because AGAIN[2:0] does not change CK CK/8 ASTROBE AGAIN[2:0] Figure 35. Timing diagram for AGC/DVGA interface, Channel A. Refer to Figure 9 for detailed timing information. www.national.com 24 leading ‘1’ out of the CIC filter. An output of ‘001XX’ corresponds to a leading ‘1’ in bit 2 (LSB is bit 0). The exponent increases by one each time the leading ‘1’ advances in bit position. The mantissa bits are the two bits that follow the leading ‘1’. If we define E as the decimal value of the exponent bits and M as the decimal value of the mantissa bits, the output of the CIC filter, P OUT, corresponding to a given “FIXED TO FLOAT CONVERTER” output is, P OUT = [ 4 ⋅ min ( E, 1 ) + M ] ⋅ 2 ( max ( E, 1 ) – 1 ) (5) , E ≥ 1. The max() and min() operators account for row 1 of Table 3 which is a special case because M=POUT. Equation 5 associates each address of the RAM with a CIC filter output. INPUT OUTPUT (eeemm) 0-3 000XX 4-7 001XX 8-15 010XX 16-31 011XX 32-63 100XX 64-127 101XX 128-255 110XX 256-511 111XX ( G – Go ) G L = – 6.02 ⋅ S RAM ⋅ 2 ( AGC_LOOP_GAIN – 8 ) . (10) The design equations are obtained by solving Equation 9 for GL and Equation 10 for S RAM . AGC_LOOP_GAIN is a con- (6) , ( G – Go ) ∂ [ 20 ⋅ log ( v i ⋅ 2 ) ], ∂G (9) The term GL in this equation is the loop gain, where G is the decimal equivalent of GAIN and Go accounts for the DVGA gain in excess of unity. This equation assumes that the DVGA gain control polarity is positive as is the case for the CLC5526. The gain around the entire loop must be negative. Observe in Equation 6 that the control gain is dependent on operating point G. If we instead compute the control gain with log conversion, K DVGA = The table data will then cross through zero at the address corresponding to this reference level. A deadband wider than 6dB should then be constructed symmetrically about this point. This prevents the loop from hunting due to the 6dB gain steps of the DVGA. Any deadband in excess of 6dB appears as hysteresis in the servo point of the loop as illustrated in Figure 33. The deadband is constructed by loading zeros into those addresses on either side of the one which corresponds to the reference level. 8 1 1 τ = ----------- ------- + --- . F CK G L 2 A log conversion is done in order to keep the loop gain independent of operating point. To see why this is beneficial, the control gain of the DVGA computed without log conversion is, = – v i ⋅ ln ( 2 ) ⋅ 2 (8) time constant of the loop given by, As shown in Figure 34, the 32X8 RAM look-up table implements the functions of log converter, reference subtraction, error amplifier, and deadband. The user must build each of these functions by constructing a set of 8-bit, 2’s complement numbers to be loaded into the RAM. Each of these functions and how to construct them are discussed in the following paragraphs. ( G – Go ) ∂ = (v ⋅ 2 ), ∂G i 511 2 20 log ---------- ⋅ --- = 44dB . 2 π The last function of the RAM table is that of error amplification. All the operations preceding this one gave a table slope S RAM = 1 . This must now be adjusted in order to control the Table 3. Fixed to Float Converter Truth Table ′ K DVGA The reference subtraction is constructed by subtracting the desired loop servo point (in dB) from the table values computed in the previous paragraph. For example, if it is desired that the DVGA servo the ADC input level (sinusoidal signal) to -6dBFS, the number to subtract from the data is (7) = – 6.02, which is no longer operating-point dependent. The log function is constructed by computing the CIC filter output associated with each address (Equation 5) and converting these to dB. Full scale (dc signal) is 20 log ( 511 ) = 54dB . 25 trol register value that determines the number of bits to shift the output of the RAM down by. This allows some of the loop gain to be moved out of the RAM so that the full output range of the table is utilized but not exceeded. The valid range for AGC_LOOP_GAIN is from 0 to 3 which corresponds to a 1 to 4 bit shift left. An example set of numbers to implement a loop having a reference of 6dB below full scale, a deadband of 8dB, and a loop gain of 0.108 is: -102 -102 -88 -80 -75 -70 -66 -63 -61 -56 -53 -50 -47 -42 -39 -36 -33 -29 -25 -22 -19 -15 -11 0 0 13 0 0 0 0 17 20 These values are shown plotted in Figure 37 with respect to the table addresses in (a), and the CIC filter output POUT in (b). For a 52MHz clock rate and AGC_LOOP_GAIN=2, these values result in a loop time constant of 1.5µs . The error signal from the loop gain “SHIFT DOWN” circuit is gated into the loop integrator. The gate is controlled by a timing and control circuit discussed in the next paragraph. A MUX within the integrator feedback allows the integrator to be initialized to the value loaded into AGC_IC_A (channel B can be set independently). The conditions under which it is initialized are configured in the registers associated with the timing and control circuit. The top eight bits of the integrator output can also be read back over the microprocessor interface from the AGC_RB_A (or AGC_RB_B) register. The top 3 bits below the sign become AGAIN and are output along with ASTROBE signal on the DVGA interface pins. The valid range of AGAIN is from 0 to 7 which corresponds to a valid range of 0 to 210-1 for the 11-bit, 2’s complement integrator output from which AGAIN is derived. This is illustrated in Fig- www.national.com CLC5903 AGC Theory of Operation (Continued) CLC5903 20 AGC RAM CONTENTS AGC RAM CONTENTS 20 0 -20 -40 -60 -80 -20 -40 -60 -80 -100 -100 -120 0 0 5 10 15 20 25 -120 30 0 10 20 30 40 50 60 POUT (dB) ADDRESS (a) (b) Figure 37. Example of programmed RAM contents AGAINa EXPb 000 = -12dB 111 = +0dB 001 = -6dB Inputc 21 20 19 18 17 16 15 14 ... 8 7 6 5 4 3 2 -12dB 14 13 12 11 10 9 8 7 ... 1 0 L L L L L L L 110 = -6dB -12dB 14 14 13 12 11 10 9 8 ... 2 1 0 L L L L L L 010 = +0dB 101 = -12dB -12dB 14 14 14 13 12 11 10 9 ... 3 2 1 0 L L L L L 011 = +6dB 100 = -18dB -12dB 14 14 14 14 13 12 11 10 ... 4 3 2 1 0 L L L L 100 = +12dB 011 = -24dB -12dB 14 14 14 14 14 13 12 11 ... 5 4 3 2 1 0 L L L 101 = +18dB 010 = -30dB -12dB 14 14 14 14 14 14 13 12 ... 6 5 4 3 2 1 0 L L 110 = +24dB 001 = -36dB -12dB 14 14 14 14 14 14 14 13 ... 7 6 5 4 3 2 1 0 L 111 = +30dB 000 = -42dB -12dB 14 14 14 14 14 14 14 14 ... 8 7 6 5 4 3 2 1 0 Table 4. 15-bit Mixer Output Alignment into the 22-bit SHIFT-UP Based On EXP.d a. AGAIN sets the DVGA or analog gain value. b. EXP sets the “FIXED TO FLOAT CONVERTER” or digital gain value. c. 22-bit input to SHIFT-UP block in Figure 16 horizontally, linearized SHIFT-UP value vertically. d. The numbers in the center of the table represent the mixer output bits. ‘L’ represents a logic low. ure 38. The integrator saturates at these limits to prevent overshoots as the integrator attempts to enter the valid range. The AGAIN value is inverted (EXP) and used to adjust the gain of the incoming signal to provide a linear output dynamic range. The relationship between the DVGA analog gain (AGAIN) and the “FIXED TO FLOAT CONVERTER” digital gain (EXP) is shown in Table 4. The DVGA’s compression of the incoming signal in the analog domain vs. the subsequent expansion in the digital domain is shown in Figure 32. 7 6 AGAIN 5 The AG C m ay be forc ed t o fr ee r un by se tt ing AG C _ H O L D _ I C l o w. W r i t i n g a n i n i t i a l c o n d i t i o n t o AGC_IC_A|B and then setting AGC_HOLD_IC high will force the AGC to a fixed gain. The three MSBs of the value written to AGC_IC_A|B are inverted and output to drive the DVGA. 4 3 2 The min integrator output must be limited to 0 so that the sign of AGAIN is positive 1 Allowing the AGC to free run should be appropriate for most applications. If the INH_EXP bit is not set, the DVGA gain word (EXP) is routed to the “FLOAT TO FIXED CONVERTER” in the DDCs prior to the programmable decimation filter. The EXP signals are delayed to account for the propagation delay of the DVGA interface and the CLC5957 ADC. www.national.com For this range to be the same size as all others, the max integrator output must be limited to 8x27-1=210-1 0 0 1x27 2x27 3x27 4x27 5x27 6x27 7x27 8x27 Integrator Output Figure 38. AGC integrator output limits 26 1 0 CLC5903 Evaluation Hardware Evaluation boards are available to facilitate designs based on the CLC5903: CLC-EDRCS-PCASM The Enhanced Diversity Receiver Chipset evaluation board providing a complete narrowband receiver from IF to digital symbols. CLC-CAPT-PCASM A simple method for capturing output data from CLC ADCs and the CLC5903. SOFTWARE Control panel software for the CLC5903 supports complete device configuration on both evaluation boards. Capture software manages the capture of data and its storage in a file on a PC. Matlab script files support data analysis: FFT, DNL, and INL plotting. This software and additional application information is available on the CLC Evaluation Kit CDROM. 27 www.national.com CLC5903 Physical Dimensions inches (millimeters) unless otherwise noted. CLC5903SM Figure 39. CLC5903SM FBGA Package Dimensions www.national.com 28 CLC5903 Dual Digital Tuner / AGC Physical Dimensions inches (millimeters) unless otherwise noted CLC5903VLA DETAIL A Dimension are in millimeters Figure 40. CLC5903VLA PQFP Package Dimensions LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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