NSC ADC10D1000CVAL

ADC10D1000QML
Low Power, 10-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/D
Converter
1.0 General Description
2.0 Features
The ADC10D1000 is the latest advance in National's UltraHigh-Speed ADC family of products. This low-power, highperformance CMOS analog-to-digital converter digitizes signals at 10-bit resolution at sampling rates of up to 1.0 GSPS
in dual channel mode or 2.0 GSPS in single channel mode.
The ADC10D1000 achieves excellent accuracy and dynamic
performance while consuming a typical 2.9 Watts of power.
This space grade, Radiation Tolerant part is rad hard to a
single event latch up level of greater than 120MeV and a total
dose (TID) of 100 krad(Si). The product is packaged in a hermatic 376 column thermally enhanced CCGA package rated
over the temperature range of -55°C to +125°C.
The ADC10D1000 builds upon the features, architecture and
functionality of the 8-bit GHz family of ADCs. New features
include an auto-sync feature for multi-chip synchronization,
independent programmable15-bit gain and 12-bit offset adjustment per channel, LC tank filter on the clock input, and the
option of two's complement format for the digital output data.
The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal track-and-hold amplifier and the self-calibration
scheme enable a very flat response of all dynamic parameters
beyond Nyquist, producing a high 8.9 Effective Number of Bits
(ENOB) with a 498 MHz input signal and a 1.0 GHz sample
rate while providing a 10−18 Code Error Rate (C.E.R.) Consuming a typical 2.9 Watts in Non-Demultiplex Mode at 1.0
GSPS from a single 1.9 Volt supply, this device is guaranteed
to have no missing codes over the full operating temperature
range.
Each channel has its own independent DDR Data Clock,
DCLKI and DCLKQ, which are in phase when both channels
are powered up, so that only one Data Clock could be used
to capture all data, which is sent out at the same rate as the
input sample clock. If the 1:2 Demultiplexed Mode is selected,
a second 10-bit LVDS bus becomes active for each channel,
such that the output data rate is sent out two times slower, but
two times wider to relax data-capture timing margin. The two
channels (I and Q) can also be interleaved (DES Mode) and
used as a single 2.0 GSPS ADC to sample on the Q input.
The output formatting is offset binary or two's complement
and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V
and 1.2V.
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© 2010 National Semiconductor Corporation
300718
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Total Ionizing Dose
100 krad(Si)
Single Event Latch-up
120 Mev-cm2/mg
Excellent accuracy and dynamic performance
Low power consumption
R/W SPI Interface for Extended Control Mode
Internally terminated, buffered, differential analog inputs
Ability to interleave the two channels to operate one
channel at twice the conversion rate
Test patterns at output for system debug
Programmable 15-bit gain and 12-bit plus sign offset
adjustments
Option of 1:2 demuxed or 1:1 non-demuxed LVDS outputs
Auto-sync feature for multi-chip systems
Single 1.9V±0.1V power supply
376 Ceramic Column Grid Array package (28.2mm x
28.2mm x 3.1mm with 1.27mm ball-pitch)
3.0 Key Specifications
(Non-Demux Non-DES Mode, Fs = 1.0 GSPS, Fin = 248 MHz)
10 Bits
■ Resolution
■ Conversion Rate
— Dual channels at 1.0 GSPS (typ)
— Single channel at 2.0 GSPS (typ)
10 −18 (typ)
■ Code Error Rate
9.0 bits (typ)
■ ENOB
56.1 dBc (typ)
■ SNR
63 dBc (typ)
■ SFDR
2.8 GHz (typ)
■ Full Power Bandwidth
±0.2 LSB (typ)
■ DNL
Power
Consumption
■
1.64W (typ)
— Single Channel Enabled
2.9W (typ)
— Dual Channels Enabled
6 mW (typ)
— Power Down Mode
4.0 Applications
■ Data Acquisition Systems
■ Wideband Communications
■ Direct RF Down Conversion
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ADC10D1000QML Low Power, 10-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/D Converter
May 10, 2010
ADC10D1000QML
5.0 Ordering Information
NS Part Number
SMD Part Number
NS Package Number
Package Description
CCC376A
376 Ceramic Column Grid Array
CCC376A
376 Ceramic Column Grid Array
CCC376A
376 Ceramic Column Grid Array
ADC10D1000CCMLS
Flight Part
ADC10D1000CCRQV
Flight Part
TBD
ADC10D1000CCMPR
Pre-flight Prototype
ADC10D1000CVAL
Ceramic Evaluation Board
376 Ceramic Column Grid Array
on Evaluation Board
6.0 Block Diagram
30071853
FIGURE 1. Simplified Block Diagram
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1.0 General Description ......................................................................................................................... 1
2.0 Features ........................................................................................................................................ 1
3.0 Key Specifications ........................................................................................................................... 1
4.0 Applications .................................................................................................................................... 1
5.0 Ordering Information ....................................................................................................................... 2
6.0 Block Diagram ................................................................................................................................ 2
7.0 Connection Diagram ........................................................................................................................ 6
8.0 Column Descriptions and Equivalent Circuits ....................................................................................... 7
9.0 Absolute Maximum Ratings ............................................................................................................ 15
10.0 Operating Ratings ....................................................................................................................... 15
11.0 Quality Conformance Inspection .................................................................................................... 15
12.0 Converter Electrical Characteristics ............................................................................................... 16
13.0 Specification Definitions ................................................................................................................ 26
14.0 Transfer Characteristic ................................................................................................................. 28
15.0 Timing Diagrams ......................................................................................................................... 29
16.0 Typical Performance Plots ............................................................................................................ 32
17.0 Functional Description .................................................................................................................. 38
17.1 OVERVIEW ......................................................................................................................... 38
17.2 POWER-ON RESET ............................................................................................................. 38
17.3 CONTROL MODES .............................................................................................................. 38
17.3.1 Non-Extended Control Mode ........................................................................................ 38
17.3.1.1 Non-Demultiplexed Mode Pin (NDM) ................................................................... 38
17.3.1.2 Dual Data Rate Phase Pin (DDRPh) .................................................................... 38
17.3.1.3 Calibration Pin (CAL) ......................................................................................... 39
17.3.1.4 Power Down I-channel Pin (PDI) ......................................................................... 39
17.3.1.5 Power Down Q-channel Pin (PDQ) ...................................................................... 39
17.3.1.6 Test Pattern Mode Pin (TPM) ............................................................................. 39
17.3.1.7 Full-Scale Input Range Pin (FSR) ....................................................................... 39
17.3.1.8 LVDS Output Common-mode Pin (VBG) ............................................................... 39
17.3.2 Extended Control Mode ............................................................................................... 40
17.3.2.1 The Serial Interface ........................................................................................... 40
17.4 FEATURES ......................................................................................................................... 43
17.4.1 Input Control and Adjust .............................................................................................. 44
17.4.1.1 Input Full-Scale Range Adjust ............................................................................ 44
17.4.1.2 Input Offset Adjust ............................................................................................ 44
17.4.1.3 DES/Non-DES Mode ......................................................................................... 44
17.4.1.4 Sampling Clock Phase Adjust ............................................................................. 44
17.4.1.5 LC Filter on Input Clock ..................................................................................... 44
17.4.2 Output Control and Adjust ............................................................................................ 44
17.4.2.1 DDR Clock Phase ............................................................................................. 45
17.4.2.2 LVDS Output Differential Voltage ........................................................................ 45
17.4.2.3 LVDS Output Common-Mode Voltage ................................................................. 45
17.4.2.4 Output Formatting ............................................................................................. 45
17.4.2.5 Demux/Non-demux Mode .................................................................................. 45
17.4.2.6 Test Pattern Mode ............................................................................................ 45
17.4.3 Calibration Feature ..................................................................................................... 46
17.4.3.1 Calibration Pins ................................................................................................ 46
17.4.3.2 How to Initiate a Calibration Event ....................................................................... 46
17.4.3.3 On-command Calibration ................................................................................... 46
17.4.3.4 Calibration Adjust .............................................................................................. 46
17.4.3.5 Calibration and Power-Down .............................................................................. 46
17.4.4 Power Down .............................................................................................................. 46
18.0 Applications Information ............................................................................................................... 47
18.1 THE ANALOG INPUTS ......................................................................................................... 47
18.1.1 Acquiring the Input ...................................................................................................... 47
18.1.2 The Reference Voltage and FSR .................................................................................. 47
18.1.3 Out-Of-Range Indication .............................................................................................. 47
18.1.4 AC-coupled Input Signals ............................................................................................ 47
18.1.5 Single-Ended Input Signals .......................................................................................... 48
18.2 THE CLOCK INPUTS ........................................................................................................... 48
18.2.1 CLK Coupling ............................................................................................................. 48
18.2.2 CLK Frequency .......................................................................................................... 48
18.2.3 CLK Level .................................................................................................................. 48
18.2.4 CLK Duty Cycle .......................................................................................................... 48
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ADC10D1000QML
Table of Contents
ADC10D1000QML
18.2.5 CLK Jitter ..................................................................................................................
18.2.6 CLK Layout ................................................................................................................
18.3 THE LVDS OUTPUTS ...........................................................................................................
18.3.1 Common-mode and Differential Voltage .........................................................................
18.3.2 Output Data Rate ........................................................................................................
18.4 SYNCHRONIZING MULTIPLE ADC10D1000S IN A SYSTEM ....................................................
18.4.1 AutoSync Feature .......................................................................................................
18.4.2 DCLK Reset Feature ...................................................................................................
18.5 SUPPLY/GROUNDING, LAYOUT AND THERMAL RECOMMENDATIONS .................................
18.5.1 Power Planes .............................................................................................................
18.5.1.1 Bypass Capacitors ............................................................................................
18.5.1.1.1 Ground Plane .........................................................................................
18.5.1.1.2 Power Supply Example ............................................................................
18.6 THERMAL MANAGEMENT ...................................................................................................
18.7 TEMPERATURE SENSOR DIODE .........................................................................................
18.8 RADIATION ENVIRONMENTS ..............................................................................................
18.8.1 Total Ionizing Dose .....................................................................................................
18.8.2 Single Event Latch-Up and Functional Interrupt ..............................................................
18.8.3 Single Event Upset .....................................................................................................
18.9 BOARD MOUNTING RECOMMENDATION .............................................................................
19.0 Register Definitions ......................................................................................................................
20.0 Revision History ..........................................................................................................................
21.0 Physical Dimensions ....................................................................................................................
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List of Figures
FIGURE 1. Simplified Block Diagram ............................................................................................................. 2
FIGURE 2. ADC10D1000 Connection Diagram ................................................................................................ 6
FIGURE 3. LVDS Output Signal Levels ......................................................................................................... 26
FIGURE 4. Input / Output Transfer Characteristic ............................................................................................. 28
FIGURE 5. Clocking in 1:4 Demux DES Mode ................................................................................................ 29
FIGURE 6. Clocking in 1:2 Demux Non-DES Mode* ......................................................................................... 29
FIGURE 7. Clocking in Non-Demux Mode Non-DES Mode** ............................................................................... 30
FIGURE 8. Clocking in Non-Demux Mode DES Mode ....................................................................................... 30
FIGURE 9. Data Clock Reset Timing ............................................................................................................ 31
FIGURE 10. On-Command Calibration Timing ................................................................................................ 31
FIGURE 11. Serial Interface Timing ............................................................................................................. 31
FIGURE 12. Serial Interface Timing (Zoom Start)*** ......................................................................................... 41
FIGURE 13. Serial Interface Timing (Zoom End)**** ......................................................................................... 41
FIGURE 14. Serial Data Protocol - Read Operation .......................................................................................... 42
FIGURE 15. Serial Data Protocol - Write Operation .......................................................................................... 42
FIGURE 16. DDR DCLK-to-Data Phase Relationship ........................................................................................ 45
FIGURE 17. AC-coupled Differential Input ..................................................................................................... 47
FIGURE 18. Single-Ended to Differential Conversion Using a Balun ...................................................................... 48
FIGURE 19. Differential Input Clock Connection .............................................................................................. 48
FIGURE 20. AutoSync Example ................................................................................................................. 49
FIGURE 21. DCLK RST +/- ....................................................................................................................... 50
FIGURE 22. Power and Grounding Example .................................................................................................. 51
FIGURE 23. CCGA Conceptual Drawing ....................................................................................................... 52
FIGURE 24. Typical Temperature Sensor Application ....................................................................................... 53
FIGURE 25. Landing Pattern Recommendation ............................................................................................... 54
List of Tables
TABLE 1. Analog Front-End and Clock Pins .................................................................................................... 7
TABLE 2. Control and Status Pins ................................................................................................................ 9
TABLE 3. Power and Ground Pins ............................................................................................................... 12
TABLE 4. High-Speed Digital Outputs .......................................................................................................... 13
TABLE 5. Static Converter Characteristics ..................................................................................................... 16
TABLE 6. Dynamic Converter Characteristics ................................................................................................. 17
TABLE 7. Analog Input/Output and Reference Characteristics ............................................................................. 20
TABLE 8. Channel-to-Channel Characteristics ................................................................................................ 20
TABLE 9. LVDS CLK Input Characteristics .................................................................................................... 21
TABLE 10. Digital Control and Output Pin Characteristics ................................................................................... 21
TABLE 11. Power Supply Characteristics (1:2 Demux Mode) .............................................................................. 22
TABLE 12. AC Electrical Characteristics ........................................................................................................ 23
TABLE 13. Non-ECM Pin Summary ............................................................................................................. 38
TABLE 14. Serial Interface Pins .................................................................................................................. 40
TABLE 15. Command and Data Field Definitions ............................................................................................. 40
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ADC10D1000QML
TABLE 16. Features and Modes ................................................................................................................
TABLE 17. LC Filter Code vs. fC .................................................................................................................
TABLE 18. LC Filter Bandwidth at 1GHz .......................................................................................................
TABLE 19. Test Pattern by Output Port in1:2 Demux Mode ................................................................................
TABLE 20. Test Pattern by Output Port inNon-Demux Mode ...............................................................................
TABLE 21. Calibration Pins .......................................................................................................................
TABLE 22. Input Channel Samples Produced at Data Outputs in Demultiplexed Mode ...............................................
TABLE 23. Input Channel Samples Produced at Data Outputs in Non-Demux Mode ..................................................
TABLE 24. Temperature Sensor Recommendation ..........................................................................................
TABLE 25. Solder Profile Specification .........................................................................................................
TABLE 26. Register Addresses ..................................................................................................................
ADC10D1000QML
7.0 Connection Diagram
30071801
FIGURE 2. ADC10D1000 Connection Diagram
The center ground pins are for thermal dissipation and must be soldered to a ground plane to ensure rated performance.
For best performance, a common ground plane on multiple PC board layers is recommended.
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TABLE 1. Analog Front-End and Clock Pins
Column
Name
H1/J1
N1/M1
VinI+/VinQ+/-
U2/V1
CLK+/-
V2/W1
Equivalent Circuit
Description
Differential Signal I- and Q-Inputs. In the NonDual Edge Sampling (Non-DES) Mode, each Iand Q-channel is sampled and converted by its
respective converter with each positive transition
of the CLK+/- input. In the DES Mode and Extended Control Mode (ECM), only the Q-channel
may be selected for conversion by the DESQ Bit
(Addr: 0h, Bit 6). In the DES mode the Q-channel
input is converted on the positive and negative
edge of the CLK± input.
Each I- and Q-channel input has an internal DCbias. Both channels must be AC coupled.
In Non-ECM, the full-scale range of these inputs
is determined by FSR (Pin Y3) and both I- and Qchannels have the same full-scale input range. In
ECM, the full-scale input range of the I- and Qchannel inputs is independently determined by
the setting of Addr: 3h and Addr: Bh, respectively. Note that the higher and lower full-scale input
range setting in Non-ECM does not exactly correspond to the maximum and minimum full-scale
input range in ECM.
Additional features include: an input offset adjust,
in Extended Control Mode.
Differential Converter Sampling Clock. In the
Non-DES Mode, the analog inputs are sampled
on the positive transitions of this clock signal. In
the DES Mode, the Q-channel is sampled on both
transitions of this clock. This clock must be ACcoupled. Additional features include: LC filter on
the clock input.
Differential DCLK Reset. A positive pulse on this
input is used to reset the DCLKI+/- and
DCLKQ+/- outputs of two or more ADC10D1000s
in order to synchronize them with other
ADC10D1000s in the system. DCLKI+/- and
DCLKQ+/- are always in phase with each other,
unless one channel is powered down, and do not
require a pulse from DCLK_RST+/- to become
synchronized. The pulse applied here must meet
timing relationships with respect to the CLK+/input. This feature may still be used while the chip
is in the AutoSync Mode.
DCLK_RST+/-
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ADC10D1000QML
8.0 Column Descriptions and Equivalent Circuits
ADC10D1000QML
Column
B1
C1/D2
C3/D3
Name
Equivalent Circuit
Description
Bandgap Voltage Output or LVDS Commonmode Voltage Select. This pin provides the
bandgap output voltage and is capable of
sourcing/ sinking 100 uA and driving a load of up
to 80 pF. Alternately, this pin may be used to
select the LVDS digital output common-mode
voltage. If tied to logic-high, the higher LVDS
common-mode voltage is selected. The lower
value is the default.
VBG
External Reference and Input Termination Trim
Resistor terminals. A 3.3 kΩ ±0.1% resistor
should be connected between Rtrim+/-. The
Rtrim resistor is used to establish the calibrated
100Ω input impedance of VinI+/-, VinQ+/- and
CLK+/-. These impedances may be fine tuned by
varying the value of the resistor by a
corresponding percentage; however, the tuning
range and performance is not guaranteed for
such an alternate value.
Rtrim+/-
A 3.3 kΩ ±0.1% resistor should be connected
between Rext+/-. The Rext resistor is used for
setting internal temperature-independent bias
currents; the value and precision of this resistor
should not be compromised.
Rext+/-
Temperature Sensor Diode Positive (Anode) and
Negative (Cathode) Terminals. This set of pins is
used for die temperature measurements.
E2/F3
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Tdiode+/-
8
Name
Y4/W5
Y5/U6
V6/V7
Equivalent Circuit
Description
Reference Clock Input. When the AutoSync
feature is active, and the ADC10D1000 is in
Slave Mode, the internal divided clocks are
synchronized with respect to this input clock. The
delay on this clock may be adjusted when
synchronizing multiple ADCs. This feature is
available in ECM via Control Register (Addr:
Eh).
RCLK+/-
Reference Clock Output 1 and 2. These signals
provide a reference clock at a rate of CLK/4,
when enabled, independently of whether the
ADC is in Master or Slave Mode. They are used
to drive the RCLK of another ADC10D1000, to
enable automatic synchronization for multiple
ADCs (AutoSync feature.) The impedance of
each trace from RCOut1+/- and RCOut2+/- to
the RCLK+/- of another ADC10D1000 should be
100Ω differential. Having two clock outputs
allows the auto-synchronization to propagate as
a binary tree. Use the DOC Bit (Addr: Eh, Bit 1)
to enable/ disable this feature; default is disabled.
RCOut1+/RCOut2+/-
TABLE 2. Control and Status Pins
Column
D6
Name
Equivalent Circuit
Description
Calibration Cycle Initiate. The user can command the
device to execute a self-calibration cycle by holding
this input high a minimum of tCAL_H after having held it
low a minimum of tCAL_L. This pin is active in both ECM
and Non-ECM. In ECM, this pin is logically OR'd with
the CAL Bit (Addr: 0h, Bit 15) in the Control Register.
Therefore, both pin and bit must be set low and then
either can be set high to execute an on-command
calibration.
CAL
Calibration Running Indication. This output is logichigh while the calibration sequence is executing. This
output is logic-low while the calibration sequence is not
running.
B5
CalRun
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ADC10D1000QML
Column
ADC10D1000QML
Column
U3
V3
A4
A5
Y3
W4
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Name
Equivalent Circuit
Description
Power Down I- and Q-channel. Setting either input to
logic-high powers down the respective I- or Q-channel
converter. Setting either input to logic-low brings the
respective I- or Q-channel converter to a fully
operational state after a finite time delay. This pin is
active in both ECM and Non-ECM. In the ECM, either
this pin or the PDI and PDQ Bit in the Control Register
can be used to power-down the I- and Q-channel
(Addr: 0h, Bit 11 and Bit 10), respectively.
PDI
PDQ
TPM
Test Pattern Mode. With this input at logic-high, the
device continuously outputs a fixed, repetitive test
pattern at the digital outputs. In the ECM, this input is
ignored and the test pattern mode can only be
activated through the Control Register by the TPM Bit
(Addr: 0h, Bit 12).
NDM
Non-Demuxed Mode. Setting this input to logic-high
causes the digital output bus to be in the 1:1 NonDemuxed Mode. Setting this input to logic-low causes
the digital output bus to be in the 1:2 Demuxed Mode.
This feature is pin-controlled only and remains active
during ECM and Non-ECM.
Full-Scale input Range Select. In Non-ECM, when this
input is set to logic-low or logic-high, the full-scale differential input range for both I- and Q-channel inputs
is set to the lower or higher value, respectively. In the
ECM, this input is ignored and the full-scale range of
the I- and Q-channel inputs is independently determined by the setting of Addr: 3h and Addr: Bh, respectively. Note that the higher and lower FSR value
in Non-ECM does not precisely correspond to the
maximum and minimum available selection in ECM; in
ECM, the selection range is greater.
FSR
DDR Phase Select. This input, when logic-low, selects
the 0-degree Data-to-DCLK phase relationship. When
logic-high, it selects the 90-degree Data-to-DCLK
phase relationship. This pin only has an effect when
the chip is in 1:2 Demuxed Mode, e.g. the NDM pin is
set to logic-low. In ECM, this input is ignored and the
DDR phase is selected through the Control Register
by the DPS Bit (Addr: 0h, Bit 14); the default is 0degree Data-to-DCLK phase relationship.
DDRPh
10
B3
C4
C5
Name
Equivalent Circuit
Description
ECE
Extended Control Enable bar. Extended feature
control through the SPI interface is enabled when this
signal is asserted logic-low. In this case, most of the
direct control pins have no effect. When this signal is
de-asserted, i.e. logic-high, the SPI interface is
disabled and the direct control pins are enabled.
SCS
Serial Chip Select bar. In ECM, when this signal is
asserted logic-low, SCLK is used to clock in serial data
which is present on the SDI input and to source serial
data on the SDO output. When this signal is deasserted, i.e. logic-high, the SDI input is ignored and
the SDO output is in tri-state mode.
Serial Clock. In ECM, serial data is shifted into and out
of the device synchronously to this clock signal. This
clock may be disabled and held logic-low, so long as
timing specifications are not violated when the clock is
enabled or disabled.
SCLK
Serial Data-In. In ECM, serial data is shifted into the
device on this pin while SCS signal is asserted (logiclow).
B4
SDI
Serial Data-Out. In ECM, serial data is shifted out of
the device on this pin while SCS signal is asserted
(logic-low). This output is in tri-state mode when
SCS is de-asserted.
A3
SDO
W3
RSV
Reserved: This pin is used for internal purposes and
should be connected to GND through a 100K Ω
resistor.
NONE
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ADC10D1000QML
Column
ADC10D1000QML
TABLE 3. Power and Ground Pins
Column
A2, A6, B6,
C7, D1, D8,
D9, E1, F1,
H4, N4, R1,
T1, U8, U9,
W6, Y2, Y6
G1, G3, G4,
H2, J3, K3, L3,
M3, N2, P1,
P3, P4, R3, R4
Name
VA
VTC
Equivalent Circuit
NONE
A8, B9, C8,
V8, W9, Y8
VE
NONE
A1, A7, B2,
B7, C2, C6,
D4, D5, E4,
K1, L1, T4, U4,
U5, V4, V5,
W2, W7, Y1,
Y7,
AA2thru AL11
F2, G2, H3,
J2, K4, L4, M2,
N3, P2, R2,
T2, T3, U1
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Analog Power Supply for the Track-and-Hold and
Clock circuitry.
NONE
VDR
F4, L2, M4, U7
Analog Power Supply. This supply is tied to the ESD
ring. Therefore, it must be powered up before or with
any other supply.
NONE
A11, A15,
C18, D11,
D15, D17,
J17, J20, R17,
R20, T17,
U11, U15,
U16, Y11, Y15
D7, E3, J4, K2
Description
Power Supply for the Output Drivers.
VbiasI
VbiasQ
Power Supply for the Digital Encoder.
NONE
Bias Voltage I-channel. This is an externally
decoupled bias voltage for the I-channel. Each pin
should individually be decoupled with a 100nF
capacitor via a low resistance, low inductance path to
GND.
NONE
Bias Voltage Q-channel. This is an externally
decoupled bias voltage for the Q-channel. Each pin
should individually be decoupled with a 100nF
capacitor via a low resistance, low inductance path to
GND.
Analog Ground Return.
GND
GNDTC
NONE
Analog Ground Return for the Track-and-Hold and
Clock circuitry.
NONE
12
Name
Equivalent Circuit
A10, A13,
A17, A20, B10
B18, B19,
B20, C10,
C17, D10,
D13, D16,
E17, F17, F20,
M17, M20,
U10,U13,
U17, V10,
V17, V18,
W10, W18,
W19, W20,
Y10, Y13,
Y17, Y20
GNDDR
NONE
A9, B8, C9,
V9, W8, Y9
GNDE
NONE
ADC10D1000QML
Column
Description
Ground Return for the Output Driver.
Ground Return for the Digital Encoder.
TABLE 4. High-Speed Digital Outputs
Column
K19/K20
L19/L20
K17/K18
L17/L18
Name
Equivalent Circuit
Description
Data Clock Output for the I- and Q-channel data bus.
These differential clock outputs are used to latch the
output data and should always be terminated with a
100Ω differential resistor. Delayed and non-delayed
data outputs are supplied synchronously to this signal.
In 1:2 Demux Mode or Non-Demux Mode, this signal
is at ¼ or ½ the input clock rate, respectively.
DCLKI+/- and DCLKQ+/- are always in phase with
each other, unless one channel is powered down and
do not require a pulse from DCLK_RST+/- to become
synchronized.
DCLKI+/DCLKQ+/-
Out-of-Range Output for the I- and Q-channel. This
differential output is asserted logic-high while the overor under-range condition exists, i.e. the differential
signal at each respective analog input exceeds the fullscale value. Each OR results refers to the current
Data, with which it is clocked out. Each of these
outputs should always be terminated with a 100Ω
differential resistor placed as closely as possible to the
differential receiver.
ORI+/ORQ+/-
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ADC10D1000QML
Column
Name
J18/J19
H19/H20
H17/H18
G19/G20
G17/G18
F18/F19
E19/E20
D19/D20
D18/E18
C19/C20
·
M18/M19
N19/N20
N17/N18
P19/P20
P17/P18
R18/R19
T19/T20
U19/U20
U18/T18
V19/V20
DI9+/DI8+/DI7+/DI6+/DI5+/DI4+/DI3+/DI2+/DI1+/DI0+/·
DQ9+/DQ8+/DQ7+/DQ6+/DQ5+/DQ4+/DQ3+/DQ2+/DQ1+/DQ0+/-
I- and Q-channel Digital Data Outputs. In Non-Demux
Mode, this LVDS data is transmitted at the sampling
clock rate. In Demux Mode, these outputs provide ½
the data at ½ the sampling clock rate, synchronized
with the delayed data, i.e. the other ½ of the data which
was sampled one clock cycle earlier. Compared with
the DId and DQd outputs, these outputs represent the
later time samples. Each of these outputs should
always be terminated with a 100Ω differential resistor
placed as closely as possible to the differential
receiver
A18/A19
B17/C16
A16/B16
B15/C15
C14/D14
A14/B14
B13/C13
C12/D12
A12/B12
B11/C11
·
Y18/Y19
W17/V16
Y16/W16
W15/V15
V14/U14
Y14/W14
W13/V13
V12/U12
Y12/W12
W11/V11
DId9+/DId8+/DId7+/DId6+/DId5+/DId4+/DId3+/DId2+/DId1+/DId0+/·
DQd9+/DQd8+/DQd7+/DQd6+/DQd5+/DQd4+/DQd3+/DQd2+/DQd1+/DQd0+/-
Delayed I- and Q-channel Digital Data Outputs. In
Non-Demux Mode, these outputs are tri-stated. In
Demux Mode, these outputs provide ½ the data at ½
the sampling clock rate, synchronized with the nondelayed data, i.e. the other ½ of the data which was
sampled one clock cycle later. Compared with the DI
and DQ outputs, these outputs represent the earlier
time samples. Each of these outputs should always be
terminated with a 100Ω differential resistor placed as
closely as possible to the differential receiver.
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Equivalent Circuit
Description
14
10.0 Operating Ratings
(Note 1, Note 2)
(Note 1, Note 2)
Supply Voltage (VA, VTC, VDR, VE)
2.2V
Supply Difference
max(VA /TC/DR /E) -min(VA /TC/DR/E)
0V to 100 mV
Voltage on Any Input Pin
−0.15V to (VA +0.15V)
Voltage on VIN+, VIN−0.15V to 2.5V
(Maintaining Common Mode)
Ground Difference
max(GNDTC/DR/E) -min(GNDTC/DR/E)
0V to 100 mV
Input Current at Any Pin (Note 3)
±50 mA
Power Dissipation at TA ≤ 85°C
(Note 3)
ESD Susceptibility (Note 4)
Human Body Model
Charged Device Model
Machine Model
Storage Temperature
Ambient Temperature Range
−55°C ≤ TA ≤ +125°C
Supply Voltage (VA, VTC, VE)
Driver Supply Voltage (VDR)
VIN+, VIN- Voltage Range
(Maintaining Common Mode)
+1.8V to +2.0V
+1.8V to VA
0V to 2.15V
(100% duty cycle)
0V to 2.5V
(10% duty cycle)
Ground Difference
max(GNDTC/DR/E) -min(GNDTC/DR/E)
CLK Pins Voltage Range
Differential CLK Amplitude
3.4 W
8000V
750V
250V
−65°C to +150°C
0V
0V to VA
0.4VP-P to 2.0VP-P
Package Thermal Resistance
Package
θJA
376 Ceramic
10.4°C / W
Column Grid Array
θJB
To Board
3.2°C / W
Solder process specifications in Section 18.9 BOARD
MOUNTING RECOMMENDATION
11.0 Quality Conformance Inspection
MIL-STD-883, Method 5005 - Group A
Subgroup
Description
Temp (°C)
1
Static tests at
+25
2
Static tests at
+125
3
Static tests at
-55
4
Dynamic tests at
+25
5
Dynamic tests at
+125
6
Dynamic tests at
-55
7
Functional tests at
+25
8A
Functional tests at
+125
8B
Functional tests at
-55
9
Switching tests at
+25
10
Switching tests at
+125
11
Switching tests at
-55
12
Setting time at
+25
13
Setting time at
+125
14
Setting time at
-55
15
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ADC10D1000QML
9.0 Absolute Maximum Ratings
ADC10D1000QML
12.0 Converter Electrical Characteristics
(Note 13)
The following specifications apply after calibration for VA = VDR = VTC = VE = +1.9V; I- and Q-channels AC coupled, FSR Pin =
High; CL = 10 pF; Differential AC coupled Sine Wave Input Clock, fCLK = 1 GHz at 0.5 VP-P with 50% duty cycle; VBG = Floating;
Non-extended Control Mode; Rext = Rtrim = 3300 Ω ±0.1%; Analog Signal Source Impedance = 100 Ω Differential; 1:2 Demultiplex
Non-DES Mode; I- and Q-channels; Duty Cycle Stabilizer on. Boldface limits apply for TA = TMIN to TMAX, unless otherwise
noted. All other limits TA = 25°C, unless otherwise noted. (Note 5, Note 6, Note 12)
TABLE 5. Static Converter Characteristics
Symbol
Parameter
Conditions
Notes
Typical
Min
Max
Units
Subgroups
INL
Integral Non-Linearity
(Best fit)
D.C. Coupled, 1 MHz Sine Wave
Over-ranged
±0.7
±1.4
LSB
1, 2, 3
DNL
Differential Non-Linearity D.C. Coupled, 1 MHz Sine Wave
Over-ranged
±0.2
±0.5
LSB
1, 2, 3
10
bits
1, 2, 3
Resolution with No
Missing Codes
VOFF
Offset Error
VOFF_ADJ
Input Offset Adjustment
Range
PFSE
Positive Full-Scale Error
(Note 8)
±28.0
mV
1, 2, 3
NFSE
Negative Full-Scale Error
(Note 8)
±28.0
mV
1, 2, 3
Out of Range Output
Code
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Extended Control Mode
-2.8
LSB
±45
mV
(VIN+) − (VIN−) > + Full Scale
1023
1, 2, 3
(VIN+) − (VIN−) < − Full Scale
0
1, 2, 3
16
Symbol
FPBW
C.E.R.
Parameter
Full Power Bandwidth
Noise Power Ratio
Notes
Typical
Min
Max
Units
Non-DES Mode
2.8
GHz
DES Mode
1.3
GHz
10−18
Error/
Sample
D.C. to 498 MHz
±0.25
dBFS
D.C. to 1.0 GHz
±0.5
dBFS
fc,notch = 325 MHz,
notch width = 25 MHz
47.5
dB
Code Error Rate
Gain Flatness
NPR
Conditions
Subgroups
1:2 Demux Non-DES Mode, Extended Control Mode, FM (14:0) = 7FFFh
ENOB
Effective Number of Bits
fIN = 248 MHz, VIN = -0.5 dBFS,
TA = 25°C to TMax
fIN = 248 MHz, VIN = -0.5 dBFS,
TA = TMIN
fIN = 498 MHz, VIN = -0.5 dBFS,
TA = 25°C to TMax
fIN = 498 MHz, VIN = -0.5 dBFS,
TA = TMIN
SINAD
Signal-to-Noise Plus
Distortion Ratio
fIN = 248 MHz, VIN = -0.5 dBFS,
TA = 25°C to TMax
fIN = 248 MHz, VIN = -0.5 dBFS,
TA = TMIN
fIN = 498 MHz, VIN = -0.5 dBFS,
TA = 25°C to TMax
fIN = 498 MHz, VIN = -0.5 dBFS,
TA = TMIN
SNR
Signal-to-Noise Ratio
fIN = 248 MHz, VIN = -0.5 dBFS,
TA = 25°C to TMax
fIN = 248 MHz, VIN = -0.5 dBFS,
TA = TMIN
fIN = 498 MHz, VIN = -0.5 dBFS,
TA = 25°C to TMax
fIN = 498 MHz, VIN = -0.5 dBFS,
TA = TMIN
THD
Total Harmonic Distortion
fIN = 248 MHz, VIN = -0.5 dBFS,
TA =25°C to TMAX
fIN = 248 MHz, VIN = -0.5 dBFS,
TA = TMIN
fIN = 498 MHz, VIN = -0.5 dBFS,
TA = 25°C to TMAX
fIN = 498 MHz, VIN = -0.5 dBFS,
TA = TMIN
2nd
Harm
Second Harmonic Distortion
3rd
Harm
Third Harmonic Distortion
8.4
bits
4, 5
7.8
bits
6
8.2
bits
4, 5
7.8
bits
6
52.2
dB
4, 5
48.5
dB
6
51.0
dB
4, 5
48.8
dB
6
53.2
dBc
4, 5
49.4
dBc
6
52.0
dBc
4, 5
49.4
dBc
6
-59.0
dBc
4, 5
-56.0
dBc
6
-58.0
dBc
4, 5
-57.0
dBc
6
9.0
8.9
55.8
55.4
56.8
56.1
-68
-61
fIN = 248 MHz, VIN = -0.5 dBFS
−75
dBc
fIN = 498 MHz, VIN = -0.5 dBFS
−68
dBc
fIN = 248 MHz, VIN = -0.5 dBFS
−72
dBc
fIN = 498 MHz, VIN = -0.5 dBFS
−67
dBc
17
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ADC10D1000QML
TABLE 6. Dynamic Converter Characteristics
ADC10D1000QML
Symbol
SFDR
Parameter
Spurious-Free Dynamic
Range
Conditions
fIN = 248 MHz, VIN = -0.5 dBFS,
TA = 25°C to TMax
fIN = 248 MHz, VIN = -0.5 dBFS,
TA = TMIN
fIN = 498 MHz, VIN = -0.5 dBFS,
TA = 25°C to TMax
fIN = 498 MHz, VIN = -0.5 dBFS,
TA = TMIN
Notes
Typical
Units
Subgroups
59.0
dBc
4, 5
53.0
dBc
6
57.5
dBc
4, 5
54.5
dBc
6
8.1
bits
4, 5
7.8
bits
6
8
bits
4, 5
7.7
bits
6
50.3
dB
4, 5
48.5
dB
6
49.8
dB
4, 5
48.0
dB
6
50.9
dBc
4, 5
49.0
dBc
6
50.5
dBc
4, 5
48.5
dBc
6
-59.5
dBc
4, 5
-58.5
dBc
6
-58.5
dBc
4, 5
-58.0
dBc
6
Min
Max
63.0
63.0
1:2 Demux Non-DES Mode, Non-Extended Control Mode, FSR = VA
ENOB
Effective Number of Bits
fIN = 248 MHz, VIN = -0.5 dBFS,
TA = 25°C to TMAX
fIN = 248 MHz, VIN = -0.5 dBFS,
TA = TMIN
fIN = 498 MHz, VIN = -0.5 dBFS,
TA = 25°C to TMAX
fIN = 498 MHz, VIN = -0.5 dBFS,
TA = TMIN
SINAD
Signal-to-Noise Plus
Distortion Ratio
fIN = 248 MHz, VIN = -0.5 dBFS,
TA = 25°C to TMAX
fIN = 248 MHz, VIN = -0.5 dBFS,
TA = TMIN
fIN = 498 MHz, VIN = -0.5 dBFS,
TA = 25°C to TMAX
fIN = 498 MHz, VIN = -0.5 dBFS,
TA = TMIN
SNR
Signal-to-Noise Ratio
fIN = 248 MHz, VIN = -0.5 dBFS,
TA = 25°C to TMAX
fIN = 248 MHz, VIN = -0.5 dBFS,
TA = TMIN
fIN = 498 MHz, VIN = -0.5 dBFS,
TA = 25°C to TMAX
fIN = 498 MHz, VIN = -0.5 dBFS,
TA = TMIN
THD
Total Harmonic Distortion
fIN = 248 MHz, VIN = -0.5 dBFS,
TA = 25°C to TMAX
fIN = 248 MHz, VIN = -0.5 dBFS,
TA = TMIN
fIN = 498 MHz, VIN = -0.5 dBFS,
TA = 25°C to TMAX
fIN = 498 MHz, VIN = -0.5 dBFS,
TA = TMIN
2nd
Harm
Second Harmonic Distortion
3rd
Harm
Third Harmonic Distortion
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8.9
8.9
55.3
55.3
55.6
55.9
-67.0
-64.3
fIN = 248 MHz, VIN = -0.5 dBFS
−75
dBc
fIN = 498 MHz, VIN = -0.5 dBFS
−68
dBc
fIN = 248 MHz, VIN = -0.5 dBFS
−72
dBc
fIN = 498 MHz, VIN = -0.5 dBFS
−68
dBc
18
SFDR
Parameter
Spurious-Free Dynamic
Range
Conditions
fIN = 248 MHz, VIN = -0.5 dBFS,
TA = 25°C to TMAX
fIN = 248 MHz, VIN = -0.5 dBFS,
TA = TMIN
fIN = 498 MHz, VIN = -0.5 dBFS,
TA = 25°C to TMAX
fIN = 498 MHz, VIN = -0.5 dBFS,
TA = TMIN
Notes
Typical
Units
Subgroups
57.5
dBc
4, 5
53.0
dBc
6
57.5
dBc
4, 5
54.5
dBc
6
Min
Max
66.7
66.7
Non-Demux Non-DES Mode, Non-Extended Control Mode, FSR = VA
ENOB
Effective Number of Bits
fIN = 498 MHz, VIN = -0.5 dBFS
9.0
bits
(min)
SINAD
Signal-to-Noise Plus
Distortion Ratio
fIN = 498 MHz, VIN = -0.5 dBFS
56.2
dB
(min)
SNR
Signal-to-Noise Ratio
fIN = 498 MHz, VIN = -0.5 dBFS
56.7
dBc
(min)
THD
Total Harmonic Distortion
fIN = 498 MHz, VIN = -0.5 dBFS
-65.7
dBc
(max)
2nd
Harm
Second Harmonic Distortion
fIN = 498 MHz, VIN = -0.5 dBFS
−75
dBc
3rd
Harm
Third Harmonic Distortion
fIN = 498 MHz, VIN = -0.5 dBFS
−68
dBc
SFDR
Spurious-Free Dynamic
Range
fIN = 498 MHz, VIN = -0.5 dBFS
67.6
dBc
(min)
1:4 Demux DES Mode (Q-channel only), ECM, Offset/Gain Adjusted
ENOB
Effective Number of Bits
fIN = 498 MHz, VIN = -0.5 dBFS
8.7
bits
(min)
SINAD
Signal-to-Noise Plus
Distortion Ratio
fIN = 498 MHz, VIN = -0.5 dBFS
54.2
dB
(min)
SNR
Signal-to-Noise Ratio
fIN = 498 MHz, VIN = -0.5 dBFS
55.3
dBc
(min)
THD
Total Harmonic Distortion
fIN = 498 MHz, VIN = -0.5 dBFS
60.7
dBc
(max)
2nd
Harm
Second Harmonic Distortion
fIN = 498 MHz, VIN = -0.5 dBFS
−78
dBc
3rd
Harm
Third Harmonic Distortion
fIN = 498 MHz, VIN = -0.5 dBFS
−67
dBc
SFDR
Spurious-Free Dynamic
Range
fIN = 498 MHz, VIN = -0.5 dBFS
63.6
dBc
(min)
19
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ADC10D1000QML
Symbol
ADC10D1000QML
TABLE 7. Analog Input/Output and Reference Characteristics
Symbol
VIN_FSR
Parameter
Analog Differential Input
Full Scale Range
Conditions
Notes
FSR Pin Y3 Low
Typical
630
FSR Pin Y3 High
820
Min
Max
560
680
750
890
Units
Subgroups
mVP-P
4, 5, 6
mVP-P
4, 5, 6
mVP-P
4, 5, 6
mVP-P
4, 5, 6
Extended Control Mode
CIN
RIN
VBG
TC_VBG
FM(14:0) = 0000h
600
mVP-P
FM(14:0) = 4000h (default)
790
mVP-P
FM(14:0) = 7FFFh
980
mVP-P
Analog Input Capacitance, Differential
Non-DES Mode
Each input pin to ground
(Note
9, Note
10)
0.02
pF
1.6
pF
Analog Input Capacitance, Differential
DES Mode
Each input pin to ground
(Note
9, Note
10)
0.08
pF
2.2
pF
Differential Input
Resistance
103.5
Bandgap Reference
Output Voltage
IBG = ±100 µA
Bandgap Reference
Voltage Temperature
Coefficient
IBG = ±100µA
1.25
CLOAD VBG Maximum Bandgap
Reference Load
Capacitance
Ω
1, 2, 3
108
Ω
V
1, 2, 3
1.35
V
1, 2, 3
100
1.15
50
ppm/°C
80
pF
1, 2, 3
TABLE 8. Channel-to-Channel Characteristics
Symbol
Parameter
Conditions
Notes
Offset Match
Typical
Min
Max
Units
2
LSB
Zero offset selected in Control
Register
2
LSB
Negative Full-Scale Match Zero offset selected in Control
Register
2
LSB
fIN = 1.0 GHz
<1
Degree
X-TALK
Crosstalk from I-channel
Q-channel (Aggressor) to Q-channel
(Victim)
Aggressor = 498 MHz F.S.
Victim = 100 MHz F.S.
−61
dB
X-TALK
I-channel
Aggressor = 498 MHz F.S.
Victim = 100 MHz F.S.
−61
dB
Positive Full-Scale Match
Phase Matching (I, Q)
Crosstalk from Q-channel
(Aggressor) to I-channel
(Victim)
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20
Subgroups
Symbol
VIN_CLK
Parameter
Differential Clock Input
Level
Conditions
Notes
Sine Wave Clock
0.6
Square Wave Clock
CIN_CLK
RIN_CLK
Sampling Clock Input
Capacitance
Typical
0.6
Differential
(Note
9, Note
10)
Each input to ground
Sampling Clock Input
Resistance
Min
Max
0.4
2.0
0.4
2.0
Units
Subgroups
VP-P
1, 2, 3
VP-P
1, 2, 3
VP-P
1, 2, 3
VP-P
1, 2, 3
0.1
pF
1
pF
100
Ω
TABLE 10. Digital Control and Output Pin Characteristics
Symbol
Parameter
Conditions
Notes
Typical
Min
Max
Units
Subgroups
V
1, 2, 3
V
1, 2, 3
Digital Control Pins, (Cal, PDI, PDQ, TPM, NDM, FSR, DDRPh, ECE, SCLK, SDI, SCS)
VIH
VIL
Logic High Input Voltage
Logic Low Input Voltage
DES, CalDly, CAL, PDI, PDQ,
TPM, NDM, FSR, DDRPh, ECE,
SCLK, SDI, SCS
0.7 x VA
DES, CalDly, CAL, PDI, PDQ,
TPM, NDM, FSR, DDRPh, ECE,
SCLK, SDI, SCS
IT
Input Current
VIN = GND, VIN = VA
CIN_DIG
Input Capacitance
Each input to ground
0.3 x VA
(Note
10,
Note
11)
±1
µA
1.5
pF
Digital Output Pins (Data, DCLKI, DCLKQ, ORI, ORQ)
VOD
LVDS Differential Output
Voltage
VBG = Floating, OVS = VA
520
VBG = Floating, OVS = GND
374
VBG = VA, OVS = VA
568
VBG = VA, OVS = GND
ΔVO DIFF
VOS
ΔVOS
400
Change in LVDS Output
Swing Between Logic
Levels
Output Offset Voltage
Output Short Circuit
Current
ZO
Differential Output
Impedance
VOH
Logic High Output Level
700
160
560
340
760
190
600
mVP-P
1, 2, 3
mVP-P
1, 2, 3
mVP-P
1, 2, 3
mVP-P
1, 2, 3
mVP-P
1, 2, 3
mVP-P
1, 2, 3
mVP-P
1, 2, 3
mVP-P
1, 2, 3
±1
mV
VBG = Floating
0.8
V
VBG = VA
1.2
V
±1
mV
±3.8
mA
100
Ω
Output Offset Voltage
Change Between Logic
Levels
IOS
300
VBG = Floating; D+ and D−
connected to 0.8V
CalRun, SDO IOH = −400 µA
21
(Note
10)
1.65
1.5
V
1, 2, 3
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ADC10D1000QML
TABLE 9. LVDS CLK Input Characteristics
ADC10D1000QML
Symbol
VOL
Parameter
Logic Low Output Level
Conditions
CalRun, SDO IOH = 400 µA
Notes
Typical
(Note
10)
0.15
Min
Max
Units
Subgroups
0.3
V
1, 2, 3
Differential DCLK Reset Pins (DCLK_RST)
VCMI_DRST
DCLK_RST Common
Mode Input Voltage
VID_DRST
Differential DCLK_RST
Input Voltage
RIN_DRST
Differential DCLK_RST
Input Resistance
(Note
10)
1.25
±0.15
V
0.6
VP-P
100
Ω
TABLE 11. Power Supply Characteristics (1:2 Demux Mode)
Symbol
IA
Parameter
Analog Supply Current
Conditions
Notes
IDR
IE
Max
Units
Subgroups
890
951
mA
1, 2, 3
PDI = Low; PDQ = High
505
551
mA
1, 2, 3
PDI = High; PDQ = Low
505
551
mA
1, 2, 3
2
mA
Track-and-Hold and Clock PDI = PDQ = Low
Supply Current
PDI = Low; PDQ = High
358
376
mA
1, 2, 3
220
241
mA
1, 2, 3
PDI = High; PDQ = Low
220
241
mA
1, 2, 3
Output Driver Supply
Current
Digital Encoder Supply
Current
PDI = PDQ = High
1
PDI = PDQ = Low
210
271
mA
1, 2, 3
PDI = Low; PDQ = High
111
141
mA
1, 2, 3
PDI = High; PDQ = Low
111
141
mA
1, 2, 3
PDI = PDQ = High
10
PDI = PDQ = Low
60
101
mA
1, 2, 3
PDI = Low; PDQ = High
30.5
56
mA
1, 2, 3
PDI = High; PDQ = Low
30.5
56
mA
1, 2, 3
PDI = PDQ = High
PC
Min
PDI = PDQ = Low
PDI = PDQ = High
ITC
Typical
Power Consumption
µA
10
µA
PDI = PDQ = Low
2.9
3.22
W
1, 2, 3
PDI = Low; PDQ = High
1.64
1.88
W
1, 2, 3
PDI = High; PDQ = Low
1.64
1.88
W
1, 2, 3
PDI = PDQ = High
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mA
6
22
mW
Symbol
Parameter
Conditions
Notes
Typical
Min
Max
Units
Subgroups
1.0
GHz
9, 10,
11
MHz
9, 10,
11
MHz
9, 10,
11
Input Clock (CLK)
fCLK (max)
Maximum Input Clock
Frequency
fCLK (min)
Minimum Input Clock
Frequency
Non-DES Mode
200
DES Mode
Input Clock Duty Cycle
tCL
Input Clock Low Time
tCH
Input Clock High Time
250
fCLK(min) ≤ fCLK ≤ fCLK (max)
50
%
20
80
%
500
200
ps
(min)
500
200
ps
(min)
DCLK Duty Cycle
% (min)
50
%
(max)
Data Clock (DCLKI, DCLKQ)
tSR
Setup Time DCLK_RST±
45
ps
tHR
Hold Time DCLK_RST±
45
ps
tPWR
Pulse Width DCLK_RST±
5
Input
Clock
Cycles
(min)
tSYNC_DLY
DCLK Synchronization
Delay
90° Mode
4
tLHT
Differential Low-to-High
Transition Time
10% to 90%, CL = 2.5 pF
220
ps
tHLT
Differential High-to-Low
Transition Time
10% to 90%, CL = 2.5 pF
220
ps
tSU
Data-to-DCLK Set-Up Time DDR Mode, 90° DCLK
850
ps
tH
DCLK-to-Data Hold Time
DDR Mode, 90° DCLK
850
ps
tOSK
DCLK-to-Data Output
Skew
50% of DCLK Transition to 50% of
Data Transition
±75
ps
0° Mode
5
23
Input
Clock
Cycles
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ADC10D1000QML
TABLE 12. AC Electrical Characteristics
ADC10D1000QML
Symbol
Parameter
Conditions
Notes
Typical
Min
Max
Units
Subgroups
Data Input to Output
tAD
Sampling (Aperture) Delay Input CLK+ Fall to Acquisition of
Data
tAJ
Aperture Jitter
tOD
Input Clock-to Data Output 50% of Input Clock transition to
Delay (in addition to tLAT)
50% of Data transition
Latency in
DI, DQ Outputs
1:2 Demux Non-DES Mode DId, DQd Outputs
Latency in
1:4 Demux DES Mode
tORR
tWU
ns
0.2
ps
(rms)
2.4
ns
34
(Note
10)
35
DI Outputs
Input
Clock
Cycles
34.5
(Note
10)
35
DQd Outputs
Input
Clock
Cycles
DI Outputs
Latency in
Non-Demux DES Mode
DI Outputs
Over Range Recovery
Time
Differential VIN step from ±1.2V to
0V to get accurate conversion
34
(Note
10)
DQ Outputs
34
34
(Note
10)
DQ Outputs
PD Low to Rated Accuracy Non-DES Mode
Conversion (Wake-Up
DES Mode
Time)
34.5
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
35.5
Latency in
Non-Demux Non-DES
Mode
4, 5, 6
4, 5, 6
34
DQ Outputs
DId Outputs
tLAT
1.1
Input
Clock
Cycles
4, 5, 6
Input
Clock
Cycles
4, 5, 6
1
Input
Clock
Cycle
500
ns
1
µs
15
MHz
4, 5, 6
4, 5, 6
Serial Port Interface
fSCLK
Serial Clock Frequency
Serial Clock Low Time
Serial Clock High Time
30
ns
9, 10,
11
30
ns
9, 10,
11
tSSU
Serial Data to Serial Clock
Rising Setup Time
2.5
ns
(min)
tSH
Serial Data to Serial Clock
Rising Hold Time
1
ns
(min)
tSCS
SCS to Serial Clock Rising
Setup Time
2.5
ns
tHCS
SCS to Serial Clock Falling
Hold Time
1.5
ns
tBSU
Bus Turn-around Time
10
ns
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24
Parameter
Conditions
Notes
Typical
Min
Max
Units
Subgroups
Calibration
tCAL
Calibration Cycle Time
Non-ECM
2.4x107
ECM CSS = 0b
2.3x107
Clock
Cycles
ECM; CSS = 1b
CMS(1:0) = 00b
0.8x107
CMS(1:0) = 01b
1.5x107
CMS(1:0) = 10b (ECM default)
2.4x107
Clock
Cycles
tCAL_L
CAL Pin Low Time
See Figure 10
(Note
10)
1280
Clock
Cycles
9, 10,
11
tCAL_H
CAL Pin High Time
See Figure 10
(Note
10)
1280
Clock
Cycles
9, 10,
11
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no guarantee of operation at the Absolute Maximum
Ratings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications
and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics
may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND = GNDDR = GNDE = GNDTC = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supply limit; (i.e. less than GND or greater than VA), the current at that pin should be limited to 50
mA. In addition, over voltage at a pin must adhere to maximum voltage limits. Simultaneously over voltage at multiple pins require adherence to the maximum
package power dissipation limits.
Note 4: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms. Charged device
model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged.
Note 5: The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.
30071804
Note 6: To guarantee accuracy, it is required that VA, VTC, VE and VDR be well-bypassed. Each supply pin must be decoupled with separate bypass capacitors.
Note 7: Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality
Level).
Note 8: Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for this device,
therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Figure 4. For relationship between Gain Error and Full-Scale Error, see
Specification Definitions for Gain Error.
Note 9: The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.22 pF differential and 1.06 pF each pin to
ground are isolated from the die capacitances by lead and bond wire inductances.
Note 10: This parameter is guaranteed by design and/or characterization and is not tested in production.
Note 11: The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated from the die
capacitances by lead and bond wire inductances.
Note 12: The maximum clock frequency for Non-Demux Mode is 1 GHz.
Note 13: Pre and post irradiation limits are identical to those listed in the “DC ” and “AC" Parameters Electrical Characteristics, except that they are tested at
Room Temperature.
25
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ADC10D1000QML
Symbol
ADC10D1000QML
13.0 Specification Definitions
APERTURE (SAMPLING) DELAY is the amount of delay,
measured from the sampling edge of the CLK input, after
which the signal present at the input pin is sampled inside the
device.
APERTURE JITTER (tAJ) is the variation in aperture delay
from sample-to-sample. Aperture jitter can be effectively considered as noise at the input.
CODE ERROR RATE (C.E.R.) is the probability of error and
is defined as the probable number of word errors on the ADC
output per unit of time divided by the number of words seen
in that amount of time. A C.E.R. of 10-18 corresponds to a
statistical error in one word about every four (4) years.
CLOCK DUTY CYCLE is the ratio of the time that the clock
waveform is at a logic high to the total time of one clock period.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB. It is
measured at sample rate = 500 MSPS with a 1MHz input sine
wave.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion Ratio, or SINAD. ENOB is defined as (SINAD −
1.76) / 6.02 and states that the converter is equivalent to a
perfect ADC of this many (ENOB) number of bits.
FULL POWER BANDWIDTH (FPBW) is a measure of the
frequency at which the reconstructed output fundamental
drops to 3 dB below its low frequency value for a full-scale
input.
GAIN ERROR is the deviation from the ideal slope of the
transfer function. It can be calculated from Offset and FullScale Errors. The Positive Gain Error is the Offset Error minus
the Positive Full-Scale Error. The Negative Gain Error is the
Negative Full-Scale Error minus the Offset Error. The Gain
Error is the Negative Full-Scale Error minus the Positive FullScale Error; it is also equal to the Positive Gain Error plus the
Negative Gain Error.
INTEGRAL NON-LINEARITY (INL) is a measure of worst
case deviation of the ADC transfer function from an ideal
straight line drawn through the ADC transfer function. The
deviation of any given code from this straight line is measured
from the center of that code value step. The best fit method
is used.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
It is defined as the ratio of the power in the second and third
order intermodulation products to the power in one of the
original frequencies. IMD is usually expressed in dBFS.
LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is
30071846
FIGURE 3. LVDS Output Signal Levels
LVDS OUTPUT OFFSET VOLTAGE (VOS) is the midpoint
between the D+ and D- pins output voltage with respect to
ground; i.e., [(VD+) +( VD-)]/2. See Figure 3.
MISSING CODES are those output codes that are skipped
and will never appear at the ADC outputs. These codes cannot be reached with any input value.
MSB (MOST SIGNIFICANT BIT) is the bit that has the largest
value or weight. Its value is one half of full scale.
NEGATIVE FULL-SCALE ERROR (NFSE) is a measure of
how far the first code transition is from the ideal 1/2 LSB above
a differential −VIN/2 with the FSR pin low. For the
ADC10D1000 the reference voltage is assumed to be ideal,
so this error is a combination of full-scale error and reference
voltage error.
NOISE POWER RATIO (NPR) is the ratio of the sum of the
power inside the notched bins to the sum of the power in an
equal number of bins outside the notch, expressed in dB.
OFFSET ERROR (VOFF) is a measure of how far the midscale point is from the ideal zero voltage differential input.
Offset Error = Actual Input causing average of 8k samples to
result in an average code of 511.5.
OUTPUT DELAY (tOD) is the time delay (in addition to
Pipeline Delay) after the falling edge of CLK+ before the data
update is present at the output pins.
OVER-RANGE RECOVERY TIME is the time required after
the differential input voltages goes from ±1.2V to 0V for the
converter to recover and make a conversion with its rated accuracy.
PIPELINE DELAY (LATENCY) is the number of input clock
cycles between initiation of conversion and when that data is
presented to the output driver stage. New data is available at
every clock cycle, but the data lags the conversion by the
Pipeline Delay plus the tOD.
POSITIVE FULL-SCALE ERROR (PFSE) is a measure of
how far the last code transition is from the ideal 1-1/2 LSB
below a differential +VIN/2. For the ADC10D1000 the reference voltage is assumed to be ideal, so this error is a combination of full-scale error and reference voltage error.
POWER SUPPLY REJECTION RATIO (PSRR) PSRR1
(D.C. PSRR) is the ratio of the change in full-scale error that
results from a power supply voltage change from 1.8V to 2.0V.
PSRR is expressed in dB.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal at the output to the rms
value of the sum of all other spectral components below onehalf the sampling frequency, not including harmonics or DC.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or
SINAD) is the ratio, expressed in dB, of the rms value of the
input signal at the output to the rms value of all of the other
spectral components below half the input clock frequency, including harmonics but excluding DC.
VFS / 2N
where VFS is the differential full-scale amplitude VIN as set by
the FSR input and "N" is the ADC resolution in bits, which is
10 for the ADC10D1000.
LOW VOLTAGE DIFFERENTIAL SIGNALING (LVDS)
DIFFERENTIAL OUTPUT VOLTAGE (VID and VOD) is two
times the absolute value of the difference between the VD+
and VD - signals; each measured with respect to Ground.
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26
27
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ADC10D1000QML
where Af1 is the RMS power of the fundamental (output) frequency and Af2 through Af10 are the RMS power of the first 9
harmonic frequencies in the output spectrum.
– Second Harmonic Distortion (2nd Harm) is the difference, expressed in dB, between the RMS power in the input
frequency seen at the output and the power in its 2nd harmonic level at the output.
– Third Harmonic Distortion (3rd Harm) is the difference
expressed in dB between the RMS power in the input frequency seen at the output and the power in its 3rd harmonic
level at the output.
SPURIOUS-FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input
signal at the output and the peak spurious signal, where a
spurious signal is any signal present in the output spectrum
that is not present at the input, excluding DC.
TOTAL HARMONIC DISTORTION (THD) is the ratio expressed in dB, of the rms total of the first nine harmonic levels
at the output to the level of the fundamental at the output. THD
is calculated as
ADC10D1000QML
14.0 Transfer Characteristic
30071822
FIGURE 4. Input / Output Transfer Characteristic
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28
ADC10D1000QML
15.0 Timing Diagrams
30071899
FIGURE 5. Clocking in 1:4 Demux DES Mode
30071859
FIGURE 6. Clocking in 1:2 Demux Non-DES Mode*
29
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ADC10D1000QML
* The timing here is shown for the I-channel only. However, the Q-channel functions precisely the same as the I-channel, with
VinQ+/-, DCLKQ+/-, DQd and DQ instead of VinI+/-, DCLKI+/-, DId and DI. Both I- and Q-channel use the same CLK+/-.
30071860
FIGURE 7. Clocking in Non-Demux Mode Non-DES Mode**
** The timing here is shown for the Q-channel only. However, for the Non-Demux Non-DES Mode, both I- and Q-channels may be
used as input. For this case, the I-channel functions precisely the same as the Q-channel, with VinI+/-, DCLKI+/-, and DI instead
of VinQ+/-, DCLKQ+/-, and DQ. Both I- and Q-channel use the same CLK+/-.
30071896
FIGURE 8. Clocking in Non-Demux Mode DES Mode
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30
ADC10D1000QML
30071820
FIGURE 9. Data Clock Reset Timing
30071825
FIGURE 10. On-Command Calibration Timing
30071819
FIGURE 11. Serial Interface Timing
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ADC10D1000QML
16.0 Typical Performance Plots
VA = VDR = VTC = VE = 1.9V, fCLK = 1000 MHz, fIN = 498 MHz, TA= 25°C, I-channel and Q-channel, unused channel terminated to
AC ground and 1:2 Demux Non-DES Mode (1:1 Demux Mode has similar performance), unless otherwise stated. NPR plots Notch
fC = 325 MHz and Notch width = 25 MHz.
INL vs. CODE
INL vs. TEMPERATURE
30071861
30071862
DNL vs. CODE
DNL vs. TEMPERATURE
30071863
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30071864
32
ADC10D1000QML
ENOB vs. TEMPERATURE
ENOB vs. SUPPLY VOLTAGE
30071865
30071866
ENOB vs. CLOCK FREQUENCY
ENOB vs. INPUT FREQUENCY
30071867
30071868
SNR vs. TEMPERATURE
SNR vs. SUPPLY VOLTAGE
30071869
30071870
33
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ADC10D1000QML
SNR vs. CLOCK FREQUENCY
SNR vs. INPUT FREQUENCY
30071871
30071872
THD vs. TEMPERATURE
THD vs. SUPPLY VOLTAGE
30071873
30071874
THD vs. CLOCK FREQUENCY
THD vs. INPUT FREQUENCY
30071875
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30071876
34
ADC10D1000QML
SFDR vs. TEMPERATURE
SFDR vs. SUPPLY VOLTAGE
30071877
30071878
SFDR vs. CLOCK FREQUENCY
SFDR vs. INPUT FREQUENCY
30071879
30071880
SPECTRAL RESPONSE AT FIN = 248 MHz
SPECTRAL RESPONSE AT FIN = 498 MHz
30071881
30071882
35
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ADC10D1000QML
CROSSTALK vs. SOURCE FREQUENCY
FULL POWER BANDWIDTH
30071883
30071884
POWER CONSUMPTION vs. CLOCK FREQUENCY
GAIN vs. TEMPERATURE FS PERCENT CHANGE
30071885
30071886
GAIN vs. TEMPERATURE ENOB
GAIN vs. TEMPERATURE FS
30071887
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30071888
36
ADC10D1000QML
NPR vs. fC NOTCH
AMPLITUDE vs. FREQUENCY
30071890
30071889
NPR vs. RMS NOISE LOADING LEVEL
30071891
37
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ADC10D1000QML
able configuration and control of the device through the
control pins. The ECM provides additional configuration and
control options through a serial interface and a set of 16 registers.
17.0 Functional Description
The ADC10D1000 is a versatile A/D Converter with an innovative architecture permitting very high speed operation. The
controls available ease the application of the device to circuit
solutions. Optimum performance requires adherence to the
provisions discussed here and in the Applications Information
Section. This section covers an overview and the control
modes; Extended Control Mode (ECM) and Non Extended
Control Mode (Non-ECM).
17.3.1 Non-Extended Control Mode
In Non-extended Control Mode (Non-ECM), the Serial Interface is not active and all available functions are controlled via
various pin settings. Non-ECM is selected by setting ECE (Pin
B3) to logic high. Seven dedicated control pins provide a wide
range of control for the ADC10D1000 and facilitate its operation. These control pins provide Demux Mode selection,
DDR Phase selection, Calibration event initiation, Power
Down I-channel, Power Down Q-channel, Test Pattern Mode
selection, and Full-Scale input Range selection. In addition to
this, a one dual-purpose control pin provides for LVDS output
common-mode voltage selection. See Table 13 for a summary.
17.1 OVERVIEW
The ADC10D1000 uses a calibrated folding and interpolating
architecture that achieves a high 9.0 Effective Number of Bits
(ENOB). The use of folding amplifiers greatly reduces the
number of comparators and power consumption. Interpolation reduces the number of front-end amplifiers required,
minimizing the load on the input signal and further reducing
power requirements. In addition to correcting other non-idealities, on-chip calibration reduces the INL bow often seen
with folding architectures. The result is an extremely fast, high
performance, low power converter. The calibration registers
are radiation hard and will not be upset by a heavy ion strike
up to 120 MeV-cm2/mg.
The analog input signal that is within the converter's input
voltage range is digitized to ten bits at speeds of 200 MHz to
1300 MHz, typical. Differential input voltages below negative
full-scale will cause the output word to consist of all zeroes.
Differential input voltages above positive full-scale will cause
the output word to consist of all ones. Either of these conditions at the I- or Q-channel will cause the Out-of-Range Ichannel or Q-channel output (ORI or ORQ), respectively, to
output a logic-high signal.
The device may be operated in one of two control modes:
Extended Control Mode (ECM) or Non-Extended Control
Mode (Non-ECM). In Non-ECM, the features of the device
may be accessed via simple pin control. In ECM, an expanded
feature set is available via the Serial Interface. Important new
features include AutoSync for mulit-chip synchronization, programmable 15-bit input full-scale range and independant programmable 12-bit plus sign offset adjustment.
Each channel has a selectable output demultiplexer which
feeds two LVDS buses. If the 1:2 Demux Mode is selected,
the output data rate is reduced to half the input sample rate
on each bus. When Non-Demux Mode is selected, the output
data rate on each channel is at the same rate as the input
sample clock and only one 10-bit bus per channel is active.
TABLE 13. Non-ECM Pin Summary
Logic-Low
Logic-High
Floating
NDM
Demux
Mode
Non-demux
Mode
Not allowed
0° Mode
90° Mode
Not allowed
DDRPh
CAL
See Section 17.3.1.3 Calibration
Pin (CAL)
Not allowed
PDI
I-channel
active
Power down
I-channel
Not allowed
PDQ
Q-channel
active
Power down
Q-channel
Not allowed
TPM
Non-Test
Pattern Mode
Test Pattern
Mode
Not allowed
FSR
VBG*
Lower FS input Higher FS input
range
range
Not allowed
Not allowed
Higher LVDS
Lower LVDS
common-mode common-mode
voltage
voltage
*Dual purpose pin.
17.3.1.1 Non-Demultiplexed Mode Pin (NDM)
The Non-Demultiplexed Mode (NDM) Pin selects whether the
ADC10D1000 is in Demux Mode (logic-low) or Non-Demux
Mode (logic-high). In Non-demux Mode, the data from the input is produced at the data-rate at a single 10-bit output bus.
In Demux Mode, the data from the input is produced at half
the data-rate at twice the number of output buses. For NonDES Mode, each I- or Q-channel will produce its data on one
or two buses for Non-demux or Demux Mode, respectively.
For DES Mode, the Q-channel will produce its data on two or
four buses for Non-demux or Demux Mode, respectively.
This feature is pin-controlled only and remains active during
both Non-ECM and ECM. See Table 13 for more information.
17.2 POWER-ON RESET
The ADC10D1000’s power-on reset has been disabled to ensure single effect functional interrupts do not occur during
space operation. Therefore, the calibration routine at poweron is not reliable for the space version of the ADC10D1000.
This means a manual calibration is always required after the
parts is power-on and is stable. Specifically, the part must either be in Non-Extended Control mode or in Extended Control
Mode with the configuration registers reset or written to the
correct values, and then a manual calibration must be run
before the ADC can be used to digitize data correctly. See
section Section 17.4.3 Calibration Feature for more information on Calibration.
17.3.1.2 Dual Data Rate Phase Pin (DDRPh)
The Dual Data Rate Phase (DDRPh) Pin selects whether the
ADC10D1000 is in 0° Mode (logic-low) or 90° Mode (logichigh). In Dual Data Rate (DDR) Mode, the Data may transition
either with the DCLK transition (0° Mode) or halfway between
DCLK transitions (90° Mode). The Data is always in DDR
Mode on the ADC10D1000. The DDRPh Pin selects 0° Mode
or 90° Mode for both the I-channel: DI- and DId-to-DCLKI
17.3 CONTROL MODES
The ADC10D1000 may be operated in one of two control
modes: Non-extended Control Mode (Non-ECM) or Extended
Control Mode (ECM). In the simpler Non-ECM (also sometimes referred to as Pin Control Mode), the user affects availwww.national.com
Pin
Name
38
This pin functions similarly to the PDI pin, except that it applies
to the Q-channel. The PDI and PDQ pins function independently of each other to control whether each I- or Q-channel
is powered down or active.
This pin remains active in ECM. In ECM, either this pin or the
PDQ bit (Addr: 0h; Bit: 10) in the Control Register may be
used to power-down the I-channe. See Section 17.4.4 Power
Down for more information.
17.3.1.3 Calibration Pin (CAL)
The Calibration (CAL) Pin must be used to initiate an oncommand calibration event. The effect of calibration is to
maximize the dynamic performance. To initiate an on-command calibration via the CAL pin, bring the CAL pin high for
a minimum of tCAL_H input clock cycles after it has been low
for a minimum of tCAL_L input clock cycles. The CAL pin should
be held high when not in use to help insure no undesired calibrating in space environment. In ECM mode this pin remains
active and is Logically OR'd with the CAL bit.
To use this feature in ECM, use the CAL bit in the Configuration Register (Addr: 0h; Bit: 15). See Section 17.4.3 Calibration Feature for more information.
17.3.1.6 Test Pattern Mode Pin (TPM)
The Test Pattern Mode (TPM) Pin selects whether the
output of the ADC10D1000 is a test pattern (logic-high) or the
converted input (logic-low). The ADC10D1000 can provide a
test pattern at the four output buses independently of the input
signal to aid in system debug. In TPM, the ADC is disengaged
and a test pattern generator is connected to the outputs, including ORI and ORQ. See Section 17.4.2.6 Test Pattern
Mode for more information.
17.3.1.7 Full-Scale Input Range Pin (FSR)
The Full-Scale Input Range (FSR) Pin selects whether the
full-scale input range for both the I- and Q-channel is higher
(logic-high) or lower (logic-low). The input full-scale range is
specified as VIN in Table 7. In Non-ECM, the full-scale input
range for each I- and Q-channel may not be set independently, but it is possible to do so in ECM. In ECM, the full-scale
input range may be set with 15-bits of precision; see FS_ADJ
in Table 7. The device must be calibrated following a change
in FSR to obtain optimal performance.
To use this feature in ECM, use the Configuration Register
(Addr: 3h and Bh). See Section 17.4.1 Input Control and Adjust for more information.
17.3.1.4 Power Down I-channel Pin (PDI)
The Power Down I-channel (PDI) Pin selects whether the Ichannel is powered down (logic-high) or active (logic-low).
The digital data output pins (both positive and negative) are
put into a high impedance state when the I-channel is powered down. Upon return to the active state, the pipeline will
contain meaningless information and must be flushed. The
supply currents (typicals and limits) are available for the Ichannel powered down or active and may be found in Table
11. It is recommended that the user thoroughly understand
how the PDI feature functions in relationship with the Calibration feature and control them appropriately for his application.
This pin remains active in ECM. In ECM, either this pin or the
PDI bit (Addr: 0h; Bit: 11) in the Control Register may be used
to power-down the I-channel. See Section 17.4.4 Power
Down Power Down for more information.
17.3.1.8 LVDS Output Common-mode Pin (VBG)
The VBG Pin serves a dual purpose and may either provide
the bandgap output voltage or select whether the LVDS output common-mode voltage is higher (logic-high) or lower
(floating). The LVDS output common-mode voltage is specified as VOS and may be found in Table 10. This pin is always
active, in both ECM and Non-ECM. See Section 17.4.2 Output Control and Adjust for more information.
17.3.1.5 Power Down Q-channel Pin (PDQ)
The Power Down Q-channel (PDQ) Pin selects whether the
Q-channel is powered down (logic-high) or active (logic-low).
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ADC10D1000QML
phase relationship and for the Q-channel: DQ- and DQd-toDCLKQ phase relationship.
To use this feature in ECM, use the DPS bit in the Configuration Register (Addr: 0h; Bit: 14). See Configuration Register
1 for more information.
ADC10D1000QML
SCS: Each assertion (logic-low) of this signal starts a new
register access, i.e. the SDI command field must be ready.
The user is required to de-assert this signal after the 24th
clock. If the SCS is de-asserted before the 24th clock, no data
read/write will occur. If the SCS is asserted longer than 24
clocks, data write will occur normally through the SDI input
upon the 24th clock and the SDO output will hold the D0 bit
until SCS is de-asserted. Setup and hold times, tSCS and
tHCS, with respect to the SCLK must be observed.
SCLK: This signal is used to register the input data (SDI) on
the rising edge; and to source the output data (SDO) on the
falling edge. The user may disable the clock and hold it in the
low-state. There is no minimum frequency requirement for
SCLK; see fSCLK in Table 12 for more details.
SDI: Each register access requires a specific 24-bit pattern at
this input, consisting of a command field and a data field.
When in read mode, the data field is high impedance in case
the bidirectional SDI/O option is used. Setup and hold times,
tSH and tSSU, with respect to the SCLK must be observed.
SDO: This output is normally tri-stated and is driven only
when SCS is asserted, the first 8 bits of command data have
been received and it is a READ operation. The data is shifted
out, MSB first, starting with the 8th clock's falling edge. At the
end of the access, when SCS is de-asserted, this output is tristated once again. If an invalid address is accessed, the data
sourced will consist of all zeroes. Setup and hold times, tSH
and tSSU, with respect to the SCLK must be observed. If it is
a READ operation, there will be a bus turnaround time, tBSU,
from when the last bit of the command field was read in until
when the first bit of the data field is written out.
Table 15 shows the Serial Interface bit definitions.
17.3.2 Extended Control Mode
In Extended Control Mode (ECM), all available functions are
controlled via the Serial Interface. In addition to this, several
of the control pins remain active. See Table 16 for details.
ECM is selected by setting ECE (Pin B3) to logic-low.
The space version of the ADC10D1000 does not include a
Power-on Reset. Therefore, when powered up in ECM, the
registers will be in an unknown, random state. There are two
ways to set the ECM registers: toggling the ECEb pin, and
writing the registers. If the device is programmed into NonECM (by setting ECEb logic high), the registers are programmed to their default values. So, if the ECEb pin is set to
logic high, then set to logic low (ECM), the device will be in
ECM and the registers will have their default values. The second method is to simply explicitly write the default (or otherwise desired) values to the register in ECM. This is the
recommended method.
Four pins on the ADC10D1000 control the Serial Interface;
SCS, SCLK, SDI and SDO. This section covers the Serial Interface. The Section 19.0 Register Definitions are located at
the end of the datasheet so that they are easy to locate.
17.3.2.1 The Serial Interface
The ADC10D1000 offers a Serial Interface that allows access
to the sixteen control registers within the device. The Serial
Interface is a generic 4-wire (optionally 3-wire) synchronous
interface that is compatible with SPI type interfaces that are
used on many micro-controllers and DSP controllers. Each
serial interface access cycle is exactly 24 bits long. A registerread or register-write can be accomplished in one cycle. The
signals are defined in such a way that the user can opt to
simply join SDI and SDO signals in his system to accomplish
a single, bidirectional SDI/O signal. A summary of the pins for
this interface may be found in Table 14. See Figure 11 for the
timing diagram and Table 12 for timing specification details.
Control register contents are retained when the device is put
into power-down mode.
TABLE 15. Command and Data Field Definitions
TABLE 14. Serial Interface Pins
Pin
Name
C4
SCS (Serial Chip Select bar)
C5
SCLK (Serial Clock)
B4
SDI (Serial Data In)
A3
SDO (Serial Data Out)
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40
Bit No.
Name
Comments
1
Read/Write (R/W)
1b indicates a read operation
0b indicates a write operation
2-3
Reserved
Bits must be set to 10b
4-7
A<3:0>
16 registers may be addressed.
The order is MSB first
8
X
This is a "don't care" bit
9-24
D<15:0>
Data written to or read from
addressed register
ADC10D1000QML
30071813
FIGURE 12. Serial Interface Timing (Zoom Start)***
***SCSb transition from High to Low must occur tHCS after the falling edge of SCLK, and tSCS before the rising edge of SCLK.
30071814
FIGURE 13. Serial Interface Timing (Zoom End)****
****SCSb transition from Low to High must occur tHCS after the 24th SCLK cycle during a low cycle.
41
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ADC10D1000QML
The serial data protocol is shown for a read and write operation in Figure 14 and Figure 15, respectively.
30071892
FIGURE 14. Serial Data Protocol - Read Operation
30071893
FIGURE 15. Serial Data Protocol - Write Operation
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42
TABLE 16. Features and Modes
Feature
Non-ECM
Control Pin Active in
ECM
ECM
Default ECM State
Input Control and Adjust
Input Full-scale Adjust
Setting
Selected via FSR
(Pin Y3)
No
Selected via the Config
Reg
(Addr: 3h and Bh)
mid FSR value
Input Offset Adjust
Setting
Not Available
Not Applicable
Selected via the Config
Reg
(Addr: 2h and Ah)
Offset = 0mV
LC Filter on Clock
Not Available
Not Applicable
Selected via the Config
Reg
(Addr: Dh)
LC Filter off
Sampling Clock Phase
Adjust
Not Available
Not Applicable
Selected via the Config
Reg
(Addr: Ch and Dh)
Phase adjust disable
DES/Non-DES Mode
Selection
Not Available
No
Selected via DES bit
(Addr: Ch and Dh
Non-DES Mode
No
Selected via DPS in the
Config Reg
(Addr: 0h; Bit: 14)
0° Mode
Not Applicable
Selected via OVS in the
Config Reg
(Addr: 0h; Bit: 13)
Higher amplitude
Output Control and Adjust
DDR Clock Phase
Selection
Selected via DDRPh
(Pin W4)
LVDS Differential Output
Voltage Amplitude
Higher amplitude only
Selection
LVDS Common-Mode
Output Voltage Amplitude
Selection
Selected via VBG
(Pin B1)
Yes
Not available
Higher amplitude
Output Formatting
Selection
Offset Binary only
Not Applicable
Selected via 2SC in the
Config Reg
(Addr: 0h; Bit: 4)
Offset Binary
Test Pattern Mode at
Output
Selected via TPM
(Pin A4)
No
Selected via TPM in the
Config Reg
(Addr: 0h; Bit: 12)
TPM not active
Demux/Non-Demux
Mode Selection
Selected via NDM
(Pin A5)
Yes
Not available
N/A
AutoSync
Not Available
Not Applicable
DCLK RST
Not Available
Not Applicable
Selected via the Config Master Mode, RCOut1/2
Reg (Addr: Eh)
disabled
Select via the Config
Reg (Addr: Eh)
DLCK Reset disabled
Selected via CAL in the
Config Reg
(Addr: 0h; Bit: 15)
N/A
(CAL = 0)
Calibration
On-command Calibration
Event
Selected via CAL
(Pin D6)
Yes
Power-Down
Power down I-channel
Selected via PDI
(Pin U3)
Yes
Selected via PDI in the
Config Reg
(Addr: 0h; Bit: 11)
I-channel operational
Power down Q-channel
Selected via PDQ
(Pin V3)
Yes
Selected via PDQ in the
Config Reg
(Addr: 0h; Bit: 10)
Q-channel operational
43
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ADC10D1000QML
is a summary of the features available, as well as details for
the control mode chosen.
17.4 FEATURES
The ADC10D1000 offers many features to make the device
convenient to use in a wide variety of applications. Table 16
ADC10D1000QML
17.4.1 Input Control and Adjust
There are several features and configurations for the input of
the ADC10D1000. This section covers Input Full Scale Range
adjust, Input Offset adjust, DES/Non-DES Mode, sampling
clock phase adjust, and LC filter on the sampling Clock.
feature in ECM, to optimize DES mode performance. To adjust the I and Q channel offset, measure a histogram of the
digital data and adjust the offset via the control register until
the histogram is centered at code 511/512. Similarly, the full
scale range of each channel may be adjusted for optimal performance.
17.4.1.1 Input Full-Scale Range Adjust
The input full-scale range for the ADC10D1000 may be adjusted via Non-ECM or ECM. In Non-ECM, a control pin
selects a higher or lower value; see Section 17.3.1.7 FullScale Input Range Pin (FSR) . See VIN in Table 7 for electrical
specification details. In ECM, the input full-scale range may
be selected with 15-bits of precision. See FS_ADJ also in
Table 7 for details. Note that the higher and lower full-scale
input range settings in Non-ECM do not correspond to the
maximum and minimum full-scale input range settings in
ECM. It is necessary to execute a manual calibration following
any change of the input full-scale range. See Section 19.0
Register Definitions for information about the registers.
17.4.1.4 Sampling Clock Phase Adjust
The sampling clock (CLK) phase may be delayed internally to
the ADC up to 825 ps in ECM. This feature is intended to help
the system designer remove small imbalances in clock distribution traces at the board level when multiple ADCs are used,
or simplify complex system functions such as beam steering
for phase array antennas. A clock-jitter cleaner is available
only when the CLK phase adjust feature is used. This adjustment delays all clocks, including the DCLKs and output data,
the user is strongly advised to use the minimal amount of adjustment and verify the net benefit of this feature in the system
before relying on it.
17.4.1.5 LC Filter on Input Clock
A LC bandpass filter is available on the ADC10D1000 sampling clock to clean jitter on the incoming clock. This feature
is available when the CLK phase adjust is also used. This
feature was designed to minimize the dynamic performance
degradation resulting from additional clock jitter as much as
possible. This feature is available in ECM via the LCF (LC
Filter) bits in the Control Register (Addr: Dh, Bits 7:0).
If the clock phase adjust feature is enabled, the sampling
clock passes through additional gate delay, which adds jitter
to the clock signal. The LC filter helps to remove this additional
jitter, so it is only available when the clock phase adjust feature is also enabled. To enable both features, use SA (Addr:
Dh, Bit 8). The LCF bits are thermometer encoded and may
be used to set a filter center frequency ranging from 0.8 GHz
to 1.5 GHz; See Table 17.
17.4.1.2 Input Offset Adjust
The input offset adjust for the ADC10D1000 may be adjusted
with 12-bits of precision plus sign via ECM. See Section 19.0
Register Definitions for information about the registers.
17.4.1.3 DES/Non-DES Mode
The ADC10D1000 is available in Dual-Edge Sampling (DES)
or Non-DES Mode. The DES Mode allows for the
ADC10D1000's Q-channel input to be sampled by both channels' ADCs. One ADC samples the input on the rising edge
of the input clock and the other ADC samples the same input
on the falling edge of the input clock. A single input is thus
sampled twice per input clock cycle, resulting in an overall
sample rate of twice the input clock frequency, e.g. 2.0 GSPS
with a 1.0 GHz input clock. SeeSection 17.3.1.1 Non-Demultiplexed Mode Pin (NDM) for information on how to select the
desired mode.
For the DES Mode, only the Q-channel may be used for the
input. This may be selected in ECM by using the DES bit (Addr: 0h, Bit 7) to select the DES Mode and the DESQ bit (Addr:
0h, Bit: 6) to select the Q-channel as input.
In this mode, the outputs must be carefully interleaved in order
to reconstruct the sampled signal. If the device is programmed into the 1:4 Demux DES Mode, the data is effectively demultiplexed by 1:4. If the input clock is 1.0 GHz, the
effective sampling rate is doubled to 2.0 GSPS and each of
the 4 output buses has an output rate of 500 MHz. All data is
available in parallel. To properly reconstruct the sampled
waveform, the four words of parallel data that are output with
each DCLK must be correctly interleaved. The sampling order
is as follows, from the earliest to the latest: DQd, DId, DQ, DI.
See Figure 5. If the device is programmed into the Non-demux
DES Mode, two bytes of parallel data are output with each
edge of the DCLK in the following sampling order, from the
earliest to the latest: DQ, DI. See Figure 8.
The performance of the ADC10D1000 in DES mode depends
on how well the two channels are interleaved, i.e that the clock
samples each channel with precisely a 50% duty cycle, each
channel has the same offset (nominally code 511/512), and
each channel has the same full scale range. The ADC10D1000 also includes an automatic clock phase background adjustment in DES Mode to automatically and
continuously adjust the clock phase of the I- and Q-channels.
This feature removes the need to adjust the clock phase setting manually and provides optimal performance in the DES
Mode. A difference exists in the typical offset between the I
and Q channels, which can be removed via the offset adjust
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TABLE 17. LC Filter Code vs. fC
LCF
(7:0)
LCF(7:0)
fC (GHz)
0
0000 0000b
1.5
1
0000 0001b
1.4
2
0000 0011b
1.3
3
0000 0111b
1.2
4
0000 1111b
1.1
5
0001 1111b
1.0
6
0011 1111b
0.92
7
0111 1111b
0.85
8
1111 1111b
0.8
The LC Filter is a second-order bandpass filter, which has the
following simulated bandwidth for a center frequency, fc at
1GHz, See Table 18
TABLE 18. LC Filter Bandwidth at 1GHz
Bandwidth [dB]
-3
-6
-9
-12
Bandwidth
[MHz]
±135
±235
±360
±525
17.4.2 Output Control and Adjust
There are several features and configurations for the output
of the ADC10D1000 so that it may be used in many different
applications. This section covers DDR clock phase, LVDS
44
(1:4 Demux DES Mode) or not demultiplexed (Non-Demux
DES Mode).
17.4.2.1 DDR Clock Phase
The ADC10D1000 output data is always delivered in Double
Data Rate (DDR). With DDR, the DCLK frequency is half the
data rate and data is sent to the outputs on both edges of
DCLK; see Figure 16. The DCLK-to-Data phase relationship
may be either 0° or 90°. For 0° Mode, the Data transitions on
each edge of the DCLK. Any offset from this timing is tOSK;
see Table 12 for details. For 90° Mode, the DCLK transitions
in the middle of each Data cell. Setup and hold times for this
transition, tSU and tH, may also be found in Table 12. The
DCLK-to-Data phase relationship may be selected via the
DDRPh Pin in Non-ECM (see Section 17.3.1.2 Dual Data
Rate Phase Pin (DDRPh)) or the DPS bit in the Configuration
Register (Addr: 0h; Bit: 14) in ECM.
17.4.2.6 Test Pattern Mode
The ADC10D1000 can provide a test pattern at the four output
buses independently of the input signal to aid in system debug. In Test Pattern Mode, the ADC is disengaged and a test
pattern generator is connected to the outputs, including ORI
and ORQ. The test pattern output is the same in DES Mode
or Non-DES Mode. Each port is given a unique 10-bit word,
alternating between 1's and 0's. When the part is programmed
into the Demux Mode, the test pattern’s order will be as described in Table 19.
TABLE 19. Test Pattern by Output Port in
1:2 Demux Mode
Time
30071894
FIGURE 16. DDR DCLK-to-Data Phase Relationship
17.4.2.2 LVDS Output Differential Voltage
The ADC10D1000 is available with a selectable higher or
lower LVDS output differential voltage. This parameter is
VOD and may be found in Table 10. The desired voltage may
be selected via OVS Bit (Addr: 0h, Bit 13); see Section 19.0
Register Definitions for more information. In non-extended
control mode only higher VOD is available.
Qd
Id
Q
I
ORQ ORI Comments
T0
000h 001h 002h 004h
0b
0b
T1
3FFh 3FEh 3FDh 3FBh
1b
1b
T2
000h 001h 002h 004h
0b
0b
T3
3FFh 3FEh 3FDh 3FBh
1b
1b
T4
000h 001h 002h 004h
0b
0b
T5
000h 001h 002h 004h
0b
0b
T6
3FFh 3FEh 3FDh 3FBh
1b
1b
T7
000h 001h 002h 004h
0b
0b
T8
3FFh 3FEh 3FDh 3FBh
1b
1b
T9
000h 001h 002h 004h
0b
0b
T10 000h 001h 002h 004h
0b
0b
T11 3FFh 3FEh 3FDh 3FBh
1b
1b
T12 000h 001h 002h 004h
0b
0b
T13
...
...
...
...
...
...
Pattern
Sequence
n
Pattern
Sequence
n+1
Pattern
Sequence
n+2
When the part is programmed into the Non-demux Mode, the
test pattern’s order is as described in Table 20.
TABLE 20. Test Pattern by Output Port in
Non-Demux Mode
17.4.2.3 LVDS Output Common-Mode Voltage
The ADC10D1000 is available with a selectable higher or
lower LVDS output common-mode voltage. This parameter is
VOS and may be found in Table 10. See Section 17.3.1.8
LVDS Output Common-mode Pin (VBG) for information on
how to select the desired voltage.
Time
I
Q
ORI
ORQ
T0
001h
000h
0b
0b
T1
001h
000h
0b
0b
T2
3FEh
3FFh
1b
1b
T3
3FEh
3FFh
1b
1b
17.4.2.4 Output Formatting
The formatting at the digital data outputs may be either offset
binary or two's complement. The desired formatting must be
set via the ECM; see Section 19.0 Register Definitions for
more information.
T4
001h
000h
0b
0b
T5
3FEh
3FFh
1b
1b
17.4.2.5 Demux/Non-demux Mode
The ADC10D1000 may be in one of two demultiplex modes:
Demux Mode or Non-Demux Mode (also sometimes referred
to as 1:1 Demux Mode). In Non-demux Mode, the data from
the input is simply output at the sampling rate at which it was
sampled on one 10-bit bus. In Demux Mode, the data from
the input is output at half the sampling rate, on twice the number of buses. See Figure 1. Demux/Non-demux Mode may
only be selected by the NDM pin; see Section 17.3.1.1 NonDemultiplexed Mode Pin (NDM). In Non-DES Mode, the output data from each channel may be demultiplexed by a factor
of 1:2 (1:2 Demux Non-DES Mode). In DES Mode, the output
data from both channels interleaved may be demultiplexed
45
T6
001h
000h
0b
0b
T7
3FEh
3FFh
1b
1b
T8
3FEh
3FFh
1b
1b
T9
3FEh
3FFh
1b
1b
T10
001h
000h
0b
0b
T11
001h
000h
0b
0b
T12
3FEh
3FFh
1b
1b
T13
3FEh
3FFh
1b
1b
T14
...
...
...
...
Comments
Pattern
Sequence
n
Pattern
Sequence
n+1
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ADC10D1000QML
output differential and common-mode voltage, output formatting, Demux/Non-demux Mode, and Test Pattern Mode.
ADC10D1000QML
significantly, relative to the specific system performance requirements.
Due to the nature of the calibration feature, it is recommended
to avoid unnecessary activities on the device while the calibration is taking place. For example, do not read or write to
the Serial Interface or use the DCLK Reset feature while calibrating the ADC. Doing so will impair the performance of the
device until it is re-calibrated correctly. Also, it is recommended to not apply a strong narrow-band signal to the analog
inputs during calibration because this may impair the accuracy of the calibration; broad spectrum noise is acceptable.
17.4.3 Calibration Feature
The ADC10D1000 calibration must be run to achieve specified performance. The calibration procedure is exactly the
same regardless of how it was initiated or when it is run. The
DCLK outputs will be present during all phases of the calibration process. All data and over-range output bits are held
at logic low during calibration. Calibration should be performed in the planned mode of operation. Calibration trims the
analog input differential termination resistor, the CLK input
resistor, and sets internal bias currents which affects the Linearity of the converter. This minimizes full-scale error, offset
error, DNL and INL, resulting in maximizing the dynamic performance as measured by: SNR, THD, SINAD (SNDR) and
ENOB.
17.4.3.4 Calibration Adjust
The calibration event itself may be adjusted, for sequence and
mode. This feature can be used if a shorter calibration time
than the default is required; see tCAL in Table 12. However,
the performance of the device, when using a shorter calibration time than the default setting, is not guaranteed.
The calibration sequence may be adjusted via CSS (Addr: 4h,
Bit 14). The default setting of CSS = 1b executes both RIN and
RIN_CLK Calibration (using Rtrim) and internal linearity Calibration (using Rext). Executing a calibration with CSS = 0b
executes only the internal linearity Calibration. The first time
that Calibration is executed, it must be with CSS = 1b to trim
RIN and RIN_CLK. However, once the device is at its operating
temperature and RIN has been trimmed at least one time, it
will not drift significantly. To save time in subsequent calibrations, trimming RIN and RIN_CLK may be skipped, i.e. by
setting CSS = 0b.
The mode may be changed, to save calibration execution time
for the internal linearity Calibration. See tCAL in Table 12. Adjusting CMS(1:0) will select three different pre-defined calibration times. A larger amount of time will calibrate each
channel more closely to the ideal values, but choosing shorter
times will not significantly impact the performance. The fourth
setting, CMS(1:0) = 11b, is not available.
17.4.3.1 Calibration Pins
Table 21 is a summary of the pins used for calibration. See
Section 8.0 Column Descriptions and Equivalent Circuits for
complete pin information and Figure 10 for the timing diagram.
TABLE 21. Calibration Pins
Pin
Name
Function
D6
CAL
(Calibration)
Initiate calibration event;
see Section 17.3.1.3
Calibration Pin (CAL)
B5
CalRun
(Calibration Running)
Indicates when
calibration is running
C1/D2
C3/D3
Rtrim+/External resistor used to
(Input termination trim calibrate analog and CLK
resistor)
inputs
Rext+/(External Reference
resistor)
External resistor used to
calibrate internal linearity
17.4.3.5 Calibration and Power-Down
If PDI and PDQ are simultaneously asserted during a calibration cycle, the ADC10D1000 will immediately power down.
The calibration cycle will continue when either or both channels are powered back up, but the calibration will be compromised due to the incomplete settling of bias currents directly
after power up. Therefore, a new calibration should be executed upon powering the ADC10D1000 back up. In general,
the ADC10D1000 should be re-calibrated when either or both
channels are powered back up, or after one channel is powered down. For best results, this should be done after the
device has stabilized to its operating temperature.
17.4.3.2 How to Initiate a Calibration Event
The calibration event must be initiated by holding the CAL pin
low for at least tCAL_L clock cycles, and then holding it high for
at least another tCAL_H clock cycles, as defined in Table 12.
The minimum tCAL_L and tCAL_H input clock cycle sequences
are required to ensure that random noise does not cause a
calibration to begin when it is not desired. The time taken by
the calibration procedure is specified as tCAL. In ECM, either
the CAL bit (Addr: 0h; Bit: 15) or the CAL pin may be used to
initiate a calibration event.
17.4.3.3 On-command Calibration
An on-command calibration must be run after power up and
whenever the FSR is changed. It is recommended to execute
an on-command calibration whenever the settings or conditions to the device are altered significantly, in order to obtain
optimal parametric performance. Some examples include:
changing the FSR via either ECM or Non-ECM, power-cycling
either channel, and switching into or out of DES Mode. For
best performance, it is also recommended that an on-command calibration be run 20 seconds or more after application
of power and whenever the operating temperature changes
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17.4.4 Power Down
On the ADC10D1000, the I- and Q-channels may be powered
down individually. This may be accomplished via the control
pins, PDI and PDQ, or via ECM. In ECM, the PDI and PDQ
pins are logically OR'd with the Control Register setting. See
Section 17.3.1.4 Power Down I-channel Pin (PDI) and Section 17.3.1.5 Power Down Q-channel Pin (PDQ) for more
information.
46
18.1 THE ANALOG INPUTS
The ADC10D1000 will continuously convert any signal which
is present at the analog inputs, as long as a CLK signal is also
provided to the device. This section covers important aspects
related to the analog inputs including: acquiring the input, the
reference voltage and FSR, out-of-range indication, AC coupled signals, and single-ended input signals.
18.1.1 Acquiring the Input
Data is acquired at the rising edge of CLK+ in Non-DES Mode
and both the falling and rising edge of CLK+ in DES Mode.
The digital equivalent of that data is available at the digital
outputs a constant number of input clock cycles later for the
DI, DQ, DId and DQd output buses, depending on the demultiplex mode which was chosen. See Pipeline Delay in Table
12. In addition to the Pipeline Delay, there is a constant output
delay, tOD, before the data is available at the outputs. See
tOD in Table 12 and the Timing Diagrams.
For Demux Mode, the signal which is sampled at the input will
appear at the output after a certain latency, as shown in Table
22.
18.1.3 Out-Of-Range Indication
Differential input signals are digitized to 10 bits, based on the
full-scale range. Signal excursions beyond the full-scale
range (greater than +VIN/2 or less than -VIN/2) will be clipped
at the output. An input signal which is above the FSR will result in all 1's at the output and an input signal which is below
the FSR will result in all 0's at the output. When the conversion
result is clipped for the I-channel input, the Out-of-Range Ichannel (ORI) output is activated such that ORI+ goes high
and ORI- goes low for the time that the signal is out of range.
This output is active as long as accurate data on either or both
of the buses would be outside the range of 000h to 3FFh. The
Q-channel has a separate ORQ which functions similarly.
TABLE 22. Input Channel Samples Produced at Data
Outputs in Demultiplexed Mode
Data
Outputs
Non-DES Mode
DES Mode
(Q-channel only)
DI
I-channel sampled
with rise of CLK,
34 cycles earlier.
Q-channel sampled
with rise of CLK,
34 cycles earlier.
DQ
Q-channel sampled
with rise of CLK,
34 cycles earlier.
Q-channel sampled
with fall of CLK,
34.5 cycles earlier.
DId
I-channel sampled
with rise of CLK,
35 cycles earlier.
Q-channel sampled
with rise of CLK,
35 cycles earlier.
DQd
Q-channel sampled
with rise of CLK,
35 cycles earlier.
Q-channel sampled
with fall of CLK,
35.5 cycles earlier.
18.1.4 AC-coupled Input Signals
The AC-coupled analog inputs require a precise commonmode voltage. This voltage, VCMO, is generated on-chip. For
the ADC10D1000 used in a typical application, this may be
accomplished by on-board capacitors shown in Figure 17
As a result, an analog input channel that is not used (e.g. in
DES Mode) should be connected to AC ground, i.e. through
capacitors to ground . Do not connect an unused analog input
directly to ground.
For Non-demux Mode, Table 23 is similarly shown.
TABLE 23. Input Channel Samples Produced at Data
Outputs in Non-Demux Mode
Data
Outputs
Non-DES Mode
DES Mode
(Q-channel only)
DI
I-channel sampled
with rise of CLK,
34 cycles earlier.
Q-channel sampled
with rise of CLK,
34 cycles earlier.
DQ
Q-channel sampled
with rise of CLK,
34 cycles earlier.
Q-channel sampled
with fall of CLK,
34.5 cycles earlier.
DId
No output;
high impedance.
No output;
high impedance.
DQd
No output;
high impedance.
No output;
high impedance.
30071844
FIGURE 17. AC-coupled Differential Input
The analog inputs for the ADC10D1000 are internally
buffered, which simplifies the task of driving these inputs and
the RC pole which is generally used at sampling ADC inputs
is not required. If the user desires to place an amplifier circuit
before the ADC, care should be taken to choose an amplifier
with adequate noise and distortion performance, and adequate gain at the frequencies used for the application.
18.1.2 The Reference Voltage and FSR
The full-scale analog differential input range (VIN_FSR) of the
ADC10D1000 is derived from an internal 1.254V bandgap
reference. In Non-ECM, this full-scale range has two settings
47
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ADC10D1000QML
controlled by the FSR pin; (see Section 17.3.1.7 Full-Scale
Input Range Pin (FSR). The FSR Pin operates on both I- and
Q-channels. In ECM, the full-scale range may be independently set for each channel via Addr: 3h and Bh with 15 bits
of precision; see Section 19.0 Register Definitions. The best
SNR is obtained with a higher full-scale input range, but better
distortion and SFDR are obtained with a lower full-scale input
range. It is not possible to use an external analog reference
voltage to modify the full-scale range, and this adjustment
should only be done digitally, as described.
A buffered version of the internal 1.254V bandgap reference
voltage is made available at the VBG pin for the user. The
VBG pin can drive a load of up to 80 pF and source or sink up
to ±100 μA. It should be buffered if more current than this is
required. The pin remains as a constant reference voltage
regardless of what full-scale range is selected and may be
used for a system reference. VBG is a dual-purpose pin and it
may also be used to select a higher LVDS output commonmode voltage; see Section 17.4.2.3 LVDS Output CommonMode Voltage.
18.0 Applications Information
ADC10D1000QML
sample rates results in higher power consumption and die
temperatures. If the fCLK ≤ 300MHz, enable LFS in control
register (Addr: 0h Bit 8).
18.1.5 Single-Ended Input Signals
It is not possible on the ADC10D1000 to accept single-ended
signals. The best way to handle single-ended signals is to first
convert them to differential signals before presenting them to
the ADC. The easiest way to accomplish single-ended to differential signal conversion is with an appropriate balun-transformer, as shown in Figure 18.
18.2.3 CLK Level
The input clock amplitude is specified as VIN_CLK in Table 9.
Input clock amplitudes above this may result in increased input offset voltage. This would cause the converter to produce
an output code other than the expected 511/512 when both
input pins are at the same potential. Insufficient input clock
levels will result in poor dynamic performance. Both of these
results may be avoided by keeping the clock input amplitude
within the specified limits of VIN_CLK.
18.2.4 CLK Duty Cycle
The duty cycle of the input clock signal can affect the performance of any A/D Converter. The ADC10D1000 features a
duty cycle clock correction circuit which can maintain performance over the 20%-to-80% specified clock duty cycle range.
This feature is enabled by default and provides improved ADC
clocking, especially in the Dual-Edge Sampling (DES) Mode.
30071843
FIGURE 18. Single-Ended to Differential Conversion
Using a Balun
When selecting a balun, it is important to understand the input
architecture of the ADC. The impedance of the analog source
should be matched to the ADC10D1000's on-chip 100Ω differential input termination resistor. The range of this termination resistor is specified as RIN in Table 7.
18.2.5 CLK Jitter
High speed, high performance ADCs such as the ADC10D1000 require a very stable input clock signal with minimum phase noise or jitter. ADC jitter requirements are defined
by the ADC resolution (number of bits), maximum ADC input
frequency and the input signal amplitude relative to the ADC
input full scale range. The maximum jitter (the sum of the jitter
from all sources) allowed to prevent a jitter-induced reduction
in SNR is found to be
18.2 THE CLOCK INPUTS
The ADC10D1000 has a differential clock input, CLK+ and
CLK-, which must be driven with an AC-coupled, differential
clock signal. This provides the level shifting to the clock to be
driven with LVDS, PECL, LVPECL, or CML levels. The clock
inputs are internally terminated to 100Ω differential and selfbiased. This section covers coupling, frequency range, level,
duty-cycle, jitter, and layout considerations.
tJ(MAX) = ( VIN(P-P)/ VFSR) x (1/(2(N+1) x π x fIN))
where tJ(MAX) is the rms total of all jitter sources in seconds,
VIN(P-P) is the peak-to-peak analog input signal, VFSR is the
full-scale range of the ADC, "N" is the ADC resolution in bits
and fIN is the maximum input frequency, in Hertz, at the ADC
analog input.
tJ(MAX) is the square root of the sum of the squares (RSS) sum
of the jitter from all sources, including: the ADC input clock,
system, input signals and the ADC itself. Since the effective
jitter added by the ADC is beyond user control, it is recommended to keep the sum of all other externally added jitter to
a mimimum.
18.2.1 CLK Coupling
The clock inputs of the ADC10D1000 must be capacitively
coupled to the clock pins as indicated in Figure 19.
18.2.6 CLK Layout
The ADC10D1000 clock input is internally terminated with a
trimmed 100Ω resistor. The differential input clock line pair
should have a characteristic impedance of 100Ω and (when
using a balun), be terminated at the clock source in that
(100Ω) characteristic impedance.
It is good practice to keep the ADC input clock line as short
as possible, to keep it well away from any other signals and
to treat it as a transmission line. Otherwise, other signals can
introduce jitter into the input clock signal. Also, the clock signal
can also introduce noise into the analog path if it is not properly isolated.
30071847
FIGURE 19. Differential Input Clock Connection
The choice of capacitor values will depend on the clock frequency, capacitor component characteristics, and other system factors.
18.3 THE LVDS OUTPUTS
The Data, ORI, ORQ, DCLKI and DCLKQ outputs are LVDS.
The electrical specifications of the LVDS outputs are compatible with typical LVDS receivers available on ASIC and
FPGA chips; but they are not IEEE or ANSI communications
standards compliant due to the low +1.9V supply used on this
chip. These outputs should be terminated with a 100Ω differential resister placed as closely to the receiver as possible.
18.2.2 CLK Frequency
Although the ADC10D1000 is tested and its performance is
guaranteed with a differential 1.0 GHz clock, it will typically
function well with input clock frequency range; see fCLK(min)
and fCLK(max) in Table 12. Operation up fCLK(max) is possible
if the maximum ambient temperatures indicated are not exceeded. Operating at sample rates above fCLK(max) for the
given ambient temperature may result in reduced device reliability and product lifetime. This is due to the fact that higher
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DCLK Reset. The AutoSync feature is new and designates
one ADC10D1000 as the Master ADC and other ADC10D1000s in the system as Slave ADCs. The DCLK Reset
feature performs the same function as the AutoSync feature,
but is the first generation solution to synchronizing multiple
ADCs in a system; it is disabled by default. For the application
in which there are multiple Master and Slave ADC10D1000s
in a system, AutoSync may be used to synchronize the Slave
ADC10D1000(s) to each respective Master ADC10D1000
and the DCLK Reset may be used to synchronize the Master
ADC10D1000s with each other.
18.3.1 Common-mode and Differential Voltage
The LVDS outputs have selectable common-mode and differential voltage, VOS and VOD; see Table 10. See Section 17.4.2 Output Control and Adjust for more information.
Selecting the higher VOS will also increase VOD by up to 40mV.
The differential voltage, VOD, may be selected for the higher
or lower value. For short LVDS lines and low noise systems,
satisfactory performance may be realized with the lower
VOD. This will also result in lower power consumption. If the
LVDS lines are long and/or the system in which the ADC10D1000 is used is noisy, it may be necessary to select the
higher VOD.
18.4.1 AutoSync Feature
AutoSync is a new feature which continuously synchronizes
the outputs of multiple ADC10D1000s in a system. It may be
used to synchronize the DCLK and data outputs of one or
more Slave ADC10D1000s to one Master ADC10D1000.
Several advantages of this feature include: no special synchronization pulse required, any upset in synchronization is
recovered upon the next DCLK cycle, and the Master/Slave
ADC10D1000s may be arranged as a binary tree so that any
upset will quickly propagate out of the system.
An example system is shown below in Figure 20 which consists of one Master ADC and two Slave ADCs. For simplicity,
only one DCLK is shown; in reality, there is DCLKI and
DCLKQ, but they are always in phase with one another.
18.3.2 Output Data Rate
The data is produced at the output at the same rate as it is
sampled at the input. The minimum recommended input clock
rate for this device is fCLK(MIN); see Table 12. However, it is
possible to operate the device in 1:2 Demux Mode and capture data from just one 10-bit bus, e.g. just DI (or DId) although
both DI and DId are fully operational. This will decimate the
data by two and effectively halve the data rate.
18.4 SYNCHRONIZING MULTIPLE ADC10D1000S IN A
SYSTEM
The ADC10D1000 has two features to assist the user with
synchronizing multiple ADCs in a system; AutoSync and
30071803
FIGURE 20. AutoSync Example
In order to synchronize the DCLK (and Data) outputs of multiple ADCs, the DCLKs must transition at the same time, as
well as be in phase with one another. The DCLK at each ADC
is generated from the CLK after some latency, plus tOD minus
tAD. Therefore, in order for the DCLKs to transition at the same
time, the CLK signal must reach each ADC at the same time.
To tune out any differences in the CLK path to each ADC, the
tAD adjust feature may be used. However, using the tAD adjust
feature will also affect when the DCLK is produced at the output. If the device is in Demux Mode, then there are four
possible phases which each DCLK may be generated on because the typical CLK = 1GHz and DCLK = 250 MHz for this
case. The RCLK signal controls the phase of the DCLK, so
that each Slave DCLK is on the same phase as the Master
DCLK
The AutoSync feature may only be used via the Control Registers.
18.4.2 DCLK Reset Feature
The DCLK reset feature is available via ECM, but is disabled
by default. DCLKI and DCLKQ are always synchronized, by
design, and do not require a pulse from DCLK_RST to become synchronized.
The DCLK_RST signal must observe certain timing requirements, which are shown in Figure 9 of the Timing Diagrams.
The DCLK_RST pulse must be of a minimum width and its
deassertion edge must observe setup and hold times with respect to the CLK input rising edge. These timing specifications are listed as tPWR, tRS and tRH and may be found in Table
12.
The DCLK_RST signal can be asserted asynchronously to
the input clock. If DCLK_RST is asserted, the DCLK output is
held in a designated state (logic-high) in Demux Mode: in
Non-Demux Mode, the DCLK_RST signal is asserted, there
may be a narrow pulse on the DCLK line during this reset
event. When the DCLK_RST signal is de-asserted, there are
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ADC10D1000QML
This section covers common-mode and differential voltage,
and data rate.
ADC10D1000QML
single source will be split into individual sections of the power
plane, with individual decoupling and connection to the different power supply buses of the ADC. Due to the low voltage
but relatively high supply current requirement, the optimal solution may be to use a switching regulator to provide an
intermediate low voltage, which is then regulated down to the
final ADC supply voltage by a linear regulator. Please refer to
the documentation provided for the ADC10D1000RB for additional details on specific regulators that are recommended
for this configuration
Power for the ADC should be provided through a broad plane
which is located on one layer adjacent to the ground plane(s).
Placing the power and ground planes on adjacent layers will
provide low impedance decoupling of the ADC supplies, especially at higher frequencies. The output of a linear regulator
should feed into the power plane through a low impedance
multi-via connection. The power plane should be split into individual power peninsulas near the ADC. Each peninsula
should feed a particular power bus on the ADC, with decoupling for that power bus connecting the peninsula to the
ground plane near each power/ground pin pair. Using this
technique can be difficult on many printed circuit CAD tools.
To work around this, zero ohm resistors can be used to connect the power source net to the individual nets for the different ADC power buses. As a final step, the zero ohm resistors
can be removed and the plane and peninsulas can be connected manually after all other error checking is completed.
tSYNC_DLY CLK cycles of systematic delay and the next CLK
rising edge synchronizes the DCLK output with those of other
ADC10D1000s in the system. For 90° Mode (DDRPh = logichigh), the synchronizing edge occurs on the rising edge of
CLK, 4 cycles after the first rising edge of CLK after
DCLK_RST is released. For 0° Mode (DDRPh = logic-low),
this is 5 cycles instead. The DCLK output is enabled again
after a constant delay of tOD.
For both Demux and Non-Demux Modes, there is some uncertainty about how DCLK comes out of the reset state for the
first DCLK_RST pulse. For the second (and subsequent)
DCLK_RST pulses, the DCLK will come out of the reset state
in a known way. Therefore, if using the DCLK Reset feature,
it is recommended to apply one “dummy” DCLK_RST pulse
before using the second DCLK_RST pulse to synchronize the
outputs. This recommendation applies each time the device
or channel is powered-on.
When the DCLK_RST function is not going to be used it is
recommended to pull the DCLK+ pin to AGND through a
261Ω resister and to pull the DCLK− pin to VA through a
261Ω resister (See Figure 21). This will provide noise ammunity and prevent false resets.
18.5.1.1 Bypass Capacitors
The general recommendation is to have one 100nF capacitor
for each power/ground pin pair. The capacitors should be
surface mount multi-layer ceramic chip capacitors similar to
Panasonic part number ECJ-0EB1A104K.
18.5.1.1.1 Ground Plane
Grounding should be done using continuous full ground
planes to minimize the impedance for all ground return paths,
and provide the shortest possible image/return path for all
signal traces.
30071806
FIGURE 21. DCLK RST +/18.5.1.1.2 Power Supply Example
The ADC10D1000RB uses continuous ground planes (except
where clear areas are needed to provide appropriate
impedance management for specific signals), see Figure 22.
Power is provided on one plane, with the 1.9V ADC supply
being split into multiple zones or peninsulas for the specific
power buses of the ADC. Decoupling capacitors are connected between these power bus peninsulas and the adjacent
power planes using vias. The capacitors are located as close
to the individual power/ground pin pairs of the ADC as possible. In most cases, this means the capacitors are located on
the opposite side of the PCB to the ADC.
When using DCLK-RST to synchronize multiple ADC10D1000s, it is required that the Select Phase bits in the
Control Register (Addr: Eh, Bits 3,4) be the same for each
Slave ADC10D1000.
18.5 SUPPLY/GROUNDING, LAYOUT AND THERMAL
RECOMMENDATIONS
18.5.1 Power Planes
All supply buses for the ADC should be sourced from a common linear voltage regulator. This ensures that all power
buses to the ADC are turned on and off simultaneously. This
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ADC10D1000QML
30071802
FIGURE 22. Power and Grounding Example
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ADC10D1000QML
resistance. The center columns of the package are attached
to the back of the die through a heat sink. Connecting these
columns to the PCB ground planes with a low thermal resistance path is the best way to remove heat from the ADC.
These pins should also be connected to the ground planes
through low impedance path for electrical purposes.
18.6 THERMAL MANAGEMENT
The Ceramic Column Grid Array (CCGA) package is a modified Ceramic Land Grid Array with an added heat sink. The
signal columns on the outer edge are 1.27mm pitch, while the
columns in the center attached to the heat sink are 1mm. The
smaller pitch for the center columns is to improve the thermal
30071811
FIGURE 23. CCGA Conceptual Drawing
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52
18.8.1 Total Ionizing Dose
Radiation hardness assured (RHA) products are those part
numbers with a total ionizing dose (TID) level specified in the
Ordering Information table on the front page. Testing and
qualification of these products is done on a wafer level according to MIL-STD-883, Test Method 1019. Wafer level TID
data is available with lot shipments.
TABLE 24. Temperature Sensor Recommendation
Number of External
Devices Monitored
Recommended Temperature
Sensor
1
LM95235
2
LM95213
4
LM95214
18.8.2 Single Event Latch-Up and Functional Interrupt
One time single event latch-up (SEL) and single event functional interrupt (SEFI) testing was preformed according to
EIA/JEDEC Standard, EIA/JEDEC57. The linear energy
transfer threshold (LETth) shown in the Key Specifications
table on the front page is the maximum LET tested. A test
report is available upon request.
The LM95235/13/14 is an 11-bit digital temperature sensor
with a 2-wire System Management Bus (SMBus) interface
that can monitor the temperature of one/two/four remote
diodes as well as its own temperature. The LM95235/13/14
can be used to accurately monitor the temperature of up to
one/two/four external devices such as the ADC10D1000, a
FPGA, other system components, and the ambient temperature.
The LM95235/13/14 reports temperature in two different formats for +127.875°C range and 0°/255°C range. The
LM95235/13/14 has a Sigma-Delta ADC core which provides
the first level of noise immunity. For improved performance in
a noise environment, the LM9535/13/14 includes programmable digital filters for Remote Diode temperature readings. When the digital filters are invoked, the resolution for the
Remote Diode readings increases to 0.03125°C. For maximum flexibility and best accuracy, the LM95235/13/14 includes offset registers that allow calibration of other diode
types.
Diode fault detection circuitry in the LM95235/13/14 can detect the absence or fault state of a remote diode: whether D+
is shorted to the power supply, D- or ground, or floating.
In the following typical application, the LM95213 is used to
monitor the temperature of an ADC10D1000 as well as a FPGA. See Figure 24
18.8.3 Single Event Upset
A report on single event upset (SEU) is available upon request.
30071897
FIGURE 24. Typical Temperature Sensor Application
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ADC10D1000QML
18.8 RADIATION ENVIRONMENTS
Careful consideration should be given to environmental conditions when using a product in a radiation environment.
18.7 TEMPERATURE SENSOR DIODE
The ADC10D1000 has an on-die temperature diode connected to pins Tdiode+/- which may be used to monitor the die
temperature. National also provides a family of temperature
sensors for this application which monitor different numbers
of external devices, See Table 24.
ADC10D1000QML
eutectic solder. To much lead increases the effective melting
point of the board side joint and makes it much more difficult
to remove the part if module rework is required.
Cool down rates and methods affect CCGA assemble yield
and reliability. Picking up boards or opening the oven while
solder joints are in molten state can disturb the solder joint.
Boards should not be picked up until the solder joints have
fully solidified. Board warping may potentially cause CCGA
lifting off pads during cooling and this condition can also
cause column cracking when severe. This warping is a result
of a high differential cooling rate between the top and bottom
of the board. Both conditions can be prevented by using even
top and bottom cooling.
18.9 BOARD MOUNTING RECOMMENDATION
Proper thermal profile is required to establish re-flow under
the package and ensure all joints meet profile specifications,
See Table 25.
TABLE 25. Solder Profile Specification
Range Up °C/sec
Peak Temp (Tpk) °C
Max Peak Temp °C
Ramp down °C/sec
≤ 4°C/sec
210°C ≤Tpk ≤ 215°C
≤ 220°C
≤ 5°C/sec
The 220°C peak temperature is driven by the requirement to
limit the dissolution of lead from the high-melt column to the
30071898
FIGURE 25. Landing Pattern Recommendation
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Eight read/write registers provide several control and configuration options in the Extended Control Mode. These registers have
no effect when the device is in the Non-extended Control Mode. The ADC10D1000 does not have a Power-On Reset. The user
can write the registers with the desired values, or in Extended Control Mode set ECEb Logic high setting resisters to the default
values.
TABLE 26. Register Addresses
A3
A2
A1
A0
Hex
Register Addressed
0
0
0
0
0h
Configuration Register 1
0
0
0
1
1h
Res
0
0
1
0
2h
I-channel Offset
0
0
1
1
3h
I-channel FSR
0
1
0
0
4h
Res
0
1
0
1
5h
Res
0
1
1
0
6h
Res
0
1
1
1
7h
Res
1
0
0
0
8h
Res
1
0
0
1
9h
Res
1
0
1
0
Ah
Q-channel Offset
1
0
1
1
Bh
Q-channel FSR
1
1
0
0
Ch
Aperture Delay Coarse Adjust
1
1
0
1
Dh
Aperture Delay Fine Adjust and LC Filter Adjust
1
1
1
0
Eh
AutoSync
1
1
1
1
Fh
Res
Configuration Register 1
Addr: 0h (0000b)
Bit
15
Name CAL
DV
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bits 9
Bits 8
0
Default Values: 2000h
14
13
12
11
10
9
8
DPS
OVS
TPM
PDI
PDQ
Res
LFS
0
1
0
0
0
0
0
7
6
DES DESQ
0
0
5
4
Res
2SC
0
0
3
2
0
0
1
0
0
0
Res
CAL: Calibration Enable. When this bit is set 1b, an on-command calibration cycle is initiated. This bit is not reset
automatically upon completion of the cal cycle. Therefore, the user must reset this bit to 0b and then set it to
1b again to initiate another calibration event. This bit is logically OR'd with the CAL Pin; both bit and pin must be
set to 0b before either is used to execute a calibration.
DPS: DDR Phase Select. Set this bit to 0b to select the 0° Mode DDR Data-to-DCLK phase relationship and to
1b to select the 90° Mode. This bit has no effect when the device is in Non-Demux Mode.
OVS: Output Voltage Select. This bit sets the differential voltage level for the LVDS outputs including Data, OR,
RCOut1, RCOut2 and DCLK. 0b selects the lower level and 1b selects the higher level. See VOD in Table 10 for
details.
TPM: Test Pattern Mode. When this bit is set to 1b, the device will continually output a fixed digital pattern at the
digital Data and OR outputs. When set to 0b, the device will continually output the converted signal, which was
present at the analog inputs. See Section 17.4.2.6 Test Pattern Mode for details about the TPM pattern.
PDI: Power-down I-channel. When this bit is set to 0b, the I-channel is fully operational, but when it is set to
1b, the I-channel is powered-down. The I-channel may be powered-down via this bit or the PDI Pin, which is
active, even in ECM.
PDQ: Power-down Q-channel. When this bit is set to 0b, the Q-channel is fully operational, but when it is set to
1b, the Q-channel is powered-down. The Q-channel may be powered-down via this bit or the PDQ Pin, which is
active, even in ECM.
Reserved. Must be set to 0b.
LFS: Low Frequency Select. If the sampling Clock (CLK) is at or below 300MHz, set this bit to 1b.
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ADC10D1000QML
19.0 Register Definitions
ADC10D1000QML
Bit 7
Bit 6
Bit 5
Bit 4
Bits 3:0
DES: Dual-Edge Sampling Mode select. When this bit is set to 0b, the device will operate in the Non-DES Mode;
when it is set to 1b, the device will operate in the DES Mode. See Section 17.4.1.3 DES/Non-DES Mode for more
information about DES/Non-DES Mode.
DESQ: DES Q-channel select. When the device is in DES Mode, this bit should be set to 1b selecting the Qchannel.
Reserved
2SC: Two's Complement output. For the default setting of 0b, the data is output in Offset Binary format; when
set to 1b, the data is output in Two's Complement format.
Reserved. Must be set to 0b.
Reserved
Addr: 1h (0001b)
Bit
15
Default Values: 2A00h
14
13
12
11
10
9
Bits 15:0
7
6
5
4
3
2
1
0
0
0
0
Reserved
Name
DV
8
0
0
1
0
1
0
1
0
0
0
0
0
0
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
Reserved. Must be set as shown.
I-channel Offset Adjust
Addr: 2h (0010b)
Bit
15
13
Reserved
Name
DV
Default Values: 0000h
14
0
0
12
OS
0
0
OM(11:0)
0
0
Bits 15:13 Reserved. Must be set to 0b.
Bit 12
OS: Offset Sign. The default setting of 0b incurs a positive offset of a magnitude set by Bits 11:0 to the ADC
output. Setting this bet to 1b incurs a negative offset of the set magnitude.
Bits 11:0 OM(11:0): Offset Magnitude. These bits determine the magnitude of the offset set at the ADC output (straight
binary coding). The range is from 0 mV for OM(11:0) = 0d to 45 mV for OM(11:0) = 4095d in steps of ~11 μV.
Monotonicity is guaranteed by design only for the 9MSBs.
Code
Offset [mV]
0000 0000 0000 (default)
0
1000 0000 0000
22.5
1111 1111 1111
45
I-channel Full Scale Range Adjust
Addr: 3h (0011b)
Bit
15
Default Values: 4000h
14
13
12
11
10
9
8
Name Res.
DV
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
FM(14:0)
1
0
0
0
0
0
0
0
Bit 15
Reserved. Must be set to 0b.
Bits 14:0 FM(14:0): FSR Magnitude. These bits increase the ADC full-scale range magnitude (straight binary coding.) The
range is from 630 mV (0d) to 980 mV (32767d) with the default setting at 820 mV (162384d). Monotonicity is
guaranteed by design only for the 9 MSBs. The mid-range (low) setting in ECM corresponds to the nominal (low)
setting in Non-ECM. A greater range of FSR values is available in EC, i.e. FSR values above 820 mV. See Table
7 for characterization details.
Code
FSR [mV]
000 0000 0000 0000
630
100 0000 0000 0000 (default)
820
111 1111 1111 1111
980
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Addr: 4h (0100b)
Default Values: DA7Fh
Bit
15
14
Name
Res
CSS
DV
1
1
13
12
11
10
9
Reserved
0
1
1
8
7
6
5
CMS
0
1
4
3
2
1
0
1
1
1
Reserved
0
0
1
1
1
1
Bits 15
Bit 14
Reserved. Must be set as shown.
CSS: Calibration Sequence Select. The default 1b selects the following calibration sequence: reset all previously
calibrated elements to nominal values, do RIN Calibration, do internal linearity Calibration. Setting CSS = 0b
selects the following calibration sequence: do not reset RIN to its nominal value, skip RIN calibration, do internal
linearity Calibration. The calibration must be completed at least one time with CSS = 1b to calibrate RIN.
Subsequent calibrations may be run with CSS = 0b (skip RIN calibration) or 1b (full RIN and internal linearity
Calibration).
Bits 13:10 Reserved. Must be set as shown.
Bits 9:8
CMS (1:0): Calibration Mode Select. These bits affect the length of time taken to calibrate the internal linearity.
See tCAL in Table 12.
Bits 7:0
Reserved. Must be set as shown
Reserved
Addr: 5h (0101b)
Bit
15
Default Values: XXXXh
14
13
12
11
10
9
DV
Bits 15:0
8
7
6
5
4
3
2
1
0
X
X
X
Reserved
Name
X
X
X
X
X
X
X
X
X
X
X
X
X
8
7
6
5
4
3
2
1
0
0
0
0
Reserved. Do not write.
Reserved
Addr: 6h (0110b)
Bit
Default Values: 1C70h
15
14
13
12
11
10
9
0
0
0
1
1
1
0
0
0
1
1
1
0
10
9
8
7
6
5
4
3
2
1
0
0
0
0
Reserved
Name
DV
Bits 15:0
Reserved. Must be set as shown.
Reserved
Addr: 7h (0111b)
Bit
15
Default Values: 0000h
14
13
12
11
Reserved
Name
DV
Bits 15:0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Reserved. Must be set as shown.
Reserved
Addr: 8h (1000b)
Bit
Default Values: 0000h
15
14
13
12
11
10
9
0
0
0
0
0
0
0
Reserved
Name
DV
Bits 15:0
0
0
Reserved. Must be set as shown.
57
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ADC10D1000QML
Calibration Adjust
ADC10D1000QML
Reserved
Addr: 9h (1001b)
15
Bit
Default Values: 0000h
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
Reserved
Name
0
DV
Bits 15:0
0
0
0
0
0
0
0
0
0
0
0
0
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
Reserved. Must be set as shown.
Q-channel Offset Adjust
Addr: Ah (0110b)
15
Bit
14
Default Values: 0000h
13
Reserved
Name
0
DV
0
12
11
OS
0
0
OM(11:0)
0
0
0
0
0
0
0
Bits 15:13 Reserved. Must be set to 0b.
Bit 12
OS: Offset Sign. The default setting of 0b incurs a positive offset of a magnitude set by Bits 11:0 to the ADC
output. Setting this bet to 1b incurs a negative offset of the set magnitude.
Bits 11:0 OM(11:0): Offset Magnitude. These bits determine the magnitude of the offset set at the ADC output (straight
binary coding). The range is from 0 mV for OM(11:0) = 0d to 45 mV for OM(11:0) = 4095d in steps of -11 μV.
Monotonicity is guaranteed by design only for the 9MSBs.
Code
Offset [mV]
0000 0000 0000 (default)
0
1000 0000 0000
22.5
1111 1111 1111
45
Q-channel Full-Scale Range Adjust
Addr: Bh (0111b)
Bit
15
Name
Res
DV
0
Bit 15
Bits 14:0
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Default Values: 4000h
14
13
12
11
10
9
8
1
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
FM(14:0)
0
Reserved. Must be set to 0b.
FM(14:0): FSR Magnitude. These bits increase the ADC full-scale range magnitude (straight binary coding.) The
range is from 630 mV (0d) to 980 mV (32767d) with the default setting at 820 mV (16384d). Monotonicity is
guaranteed by design only for the 9 MSBs. The mid-range (low) setting in ECM corresponds to the nominal (low)
setting in Non-ECM. A greater range of FSR values is available in ECM, i.e. FSR values above 820 mV. See
Table 7for characterization details.
Code
FSR [mV]
000 0000 0000 0000
630
100 0000 0000 0000 (default)
820
111 1111 1111 1111
980
58
Addr: Ch (1100b)
Bit
Default Values: 0004h
15
14
13
12
11
0
0
0
0
0
Bits 15:4
Bit 3
Bit 2
Bits 1:0
9
8
7
6
5
4
0
0
0
0
0
CAM(11:0)
Name
DV
10
0
0
3
2
STA
DCC
0
1
1
0
Reserved
0
0
CAM(11:0): Coarse Adjust Magnitude. This 12-bit value determines the amount of delay that will be applied to
the input CLK signal. The range is 0 ps delay for CAM(11:0) = 0d to a maximum delay of 825 ps for CAM(11:0)
= 2431d (±95 ps due to PVT variation) in steps of ~340 fs. For code CAM(11:0) = 2432d and above, the delay
saturates and the maximum delay applies. Additional, finer delay steps are available in register Dh. Either STA
(Bit 3) or SA (Addr: Dh, Bit 8) must be selected to enable this function.
STA: Select tAD Adjust. Set this bit to 1b to enable the tAD adjust feature. When using this feature, make sure
that SA (Addr: Dh, Bit 8) is set to 0b.
DCC: Duty Cycle Correct. This bit can be set to 0b to disable the automatic duty-cycle stabilizer feature of the
chip. This feature is enabled by default.
Reserved. Must be set to 0b.
Aperture Delay Fine Adjust and LC Filter Adjust
Addr: Dh (1101b)
Bit
15
14
13
12
11
10
FAM(5:0)
Name
DV
Default Values: 0000h
0
0
0
0
0
0
9
8
Res
SA
0
0
7
6
5
4
3
2
1
0
0
0
0
LCF(7:0)
0
0
0
0
0
Bits 15:10 FAM(5:0): Fine Aperture Adjust Magnitude. This 6-bit value determines the amount of additional delay that will
be applied to the input CLK when the Clock Phase Adjust feature is enabled via STA (Addr: Ch, Bit 3) or SA
(Addr: Dh, Bit 8). The range is straight binary from 0 ps delay for FAM(5:0) = 0d to 2.3 ps delay for FAM(5:0) =
63d (±300 fs due to PVT variation) in steps of ~36 fs.
Bit 9
Reserved. Must be set to 0b.
Bit 8
SA: Select tAD and LC filter Adjust. Set this bit to 1b to enable the tAD and LC filter adjust features. Using this bit
is the same as enabling STA (Addr: Ch, Bit3), but also enables the LC filter to clean the clock jitter.
Bits 7:0
LCF(7:0): LC tank select Frequency. Use these bits to select the center frequency of the LC filter on the Clock
inputs. The range is from 0.8 GHz (255d) to 1.5 GHz (0d). Note that the tuning range is not binary encoded, and
the eight bits are thermometer encoded, i.e. the mid value of 1.1 GHz tuning is achieved with LCF(7:0) = 0000
1111b.
59
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ADC10D1000QML
Aperture Delay Coarse Adjust
ADC10D1000QML
AutoSync
Addr: Eh (1110b)
Bit
Default Values: 0003h
15
14
13
12
0
0
0
0
Bits 15:6
Bit 5
Bits 4:3
Bit 2
Bit 1
Bit 0
10
9
8
7
6
0
0
0
0
DRC(9:0)
Name
DV
11
0
0
5
Res.
0
4
3
SP(1:0)
0
0
2
1
0
ES
DOC
DR
0
1
1
DRC(9:0): Delay Reference Clock (9:0). These bits may be used to increase the delay on the input reference
clock when synchronizing multiple ADCs. The minimum delay is 0s (0d) to 1000 ps (629d). The delay remains
the maximum of 1000 ps for any codes above or equal to 639d.
Reserved. Must be set to 0b.
SP(1:0): Select Phase. These bits select the phase of the reference clock which is latched. The codes correspond
to the following phase shift:
00 = 0°
01 = 90°
10 = 180°
11 = 270°
ES: Enable Slave. Set this bit to 1b to enable the Slave Mode of operation. In this mode, the internal divided
clocks are synchronized with the reference clock coming from the master ADC. The master clock is applied on
the input pins RCLK+/-. If this bit is set to 0b, then the device is in Master Mode.
DOC: Disable Output reference Clocks. Setting this bit to 0b sends a CLK/4 signal on RCOut1 and RCOut2. The
default setting of 1b disables these output drivers. This bit functions as described, regardless of whether the
device is operating in Master or Slave Mode, as determined by ES (Bit 2).
DR: Disable Reset. The default setting of 0b leaves the DCLK_RST functionality disabled. Set this bit to 1b to
enable DCLK_RST functionality.
Reserved
Addr: Fh (1111b)
Bit
15
14
Default Values: XXXXh
13
12
11
10
9
Bits 15:0
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7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
Reserved
Name
DV
8
X
X
X
X
X
X
X
X
Reserved. Do not write.
60
X
Date Released
Revision
Section
Changes
02/11/09
A
Initial Release
New Product Data Sheet Release
(ECN SENT FOR APPROVAL 02/05/09 - Edit #:
16)
03/18/09
B
Connection Diagram, Table 3. Section 8.0 Following Pin names corrected VA, GND and
- DCLK_RST+/- diagram, Section 18.0,
GNDDR. Section 8.0 - Update DCLK_RST+/paragraph 18.4.2.
diagram, Section 18.0 - paragraph added to 18.4.2
and new figure. Revision A will be Archived.
4/20/09
C
Features, Key Specifications, Table 10
Electricals.
05/28/09
D
Absolute Maximum Ratings and Operating Absolute Maximum Ratings added Voltage on VIN
+, V -. Operating Ratings changed V +, V Ratings, Electrical Section Table 12,
IN
IN
IN
Section 19 Reserved Addr: Fh
Voltage Range. Range. Remove Note 10
reference from Table 12 tOSK, Correction to
Reserved Addr: Fh. Revision C will be Archived.
09/11/09
E
Electrical Section Table 12 Calibration
(Tcal), 17.0 Section, 19.0 Section (top
register 4h) Addr: 4h (0100b) POR state:
DA7Fh
05/10/2010
F
Ordering Information Table, Table 6, Table Added reference to MPR and CVAL NSPN. Table
10 Electrical Section. Sections 15.0, 17.0, 6 section 1:2 Demux Non-DES Mode, Extended
17.4.3, 19.0 Configuration Register 1 Bit 6 Control Mode, FM (14:0) = 7FFFh SNR Limit and
1:2 Demux Non-DES Mode, Non-Extended
Control Mode, FSR = VA. Table 10 Digital Control
Pins. Update Figure 11, Added New Figure 12 and
13, Renumbered previous Figure 12 and 13 to
Figure 14 and 15 etc. Changed paragraph 17.4.3.
Configuration Register 1– Bit 6 paragraph.
Revision E will be Archived.
61
Moved reference to radiation to Features from Key
Specifications. Table 10 Electricals: VOH typo limit
move to Min., Added parameters VCMI_DRST,
VID_DRST, RIN_DRST. Revision B will be Archived.
Added Conditions to Tcal parameter, 17.0 Section
New paragraph 17.4.3.4 and renumbered,
Changed table 4h and title from Reserved to
Calibration Adjust in 19.0 Section. Revision D will
be Archived.
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ADC10D1000QML
20.0 Revision History
ADC10D1000QML
21.0 Physical Dimensions inches (millimeters) unless otherwise noted
NOTES: UNLESS OTHERWISE SPECIFIED
REFERENCE JEDEC REGISTRATION MS-034, VARIATION BAL-2.
376 Ceramic Column Grid Array Package
NS Package Number CCC376A
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62
ADC10D1000QML
Notes
63
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ADC10D1000QML Low Power, 10-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/D Converter
Notes
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