CD4015BM/CD4015BC Dual 4-Bit Static Shift Register General Description Features The CD4015BM/CD4015BC contains two identical, 4-stage, serial-input/parallel-output registers with independent ‘‘Data’’, ‘‘Clock,’’ and ‘‘Reset’’ inputs. The logic level present at the input of each stage is transferred to the output of that stage at each positive-going clock transition. A logic high on the ‘‘Reset’’ input resets all four stages covered by that input. All inputs are protected from static discharge by a series resistor and diode clamps to VDD and VSS. Y Y Y Y Y Wide supply voltage range High noise immunity Low power TTL compatibility Medium speed operation Fully static design 3.0V to 18V 0.45 VDD (typ.) Fan out of 2 driving 74L or 1 driving 74LS 8 MHz (typ.) clock rate @V DD b VSS e 10V Applications Y Y Y Serial-input/parallel-output data queueing Serial to parallel data conversion General purpose register Connection Diagram and Truth Table Dual-In-Line Package TL/F/5948 – 1 CL U D R Q1 Qn L L K X 0 1 X X 0 0 0 1 0 1 Q1 0 Qnb1 Qnb1 Qn 0 (No change) U Level change X e Don’t care case Order Number CD4015B C1996 National Semiconductor Corporation TL/F/5948 RRD-B30M76/Printed in U. S. A. http://www.national.com CD4015BM/CD4015BC Dual 4-Bit Static Shift Register June 1996 Absolute Maximum Ratings (Notes 1 & 2) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. DC Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering, 10 seconds) DC Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) CD4015BM CD4015BC b 0.5 to a 18 VDC b 0.5 to VDD a 0.5 VDC b 65§ C to a 150§ C a 3 to a 15 VDC 0 to VDD VDC b 55§ C to a 125§ C b 40§ C to a 85§ C 700 mW 500 mW 260§ C DC Electrical Characteristics CD4015BM (Note 2) Symbol Parameter b 55§ C Conditions Min Max a 25§ C Min a 125§ C Min Units Typ Max Max 5 10 20 0.005 0.010 0.015 5 10 20 150 300 600 mA mA mA 0.05 0.05 0.05 0 0 0 0.05 0.05 0.05 0.05 0.05 0.05 V V V IDD Quiescent Device Current VDD e 5V, VIN e VDD or VSS VDD e 10V, VIN e VDD or VSS VDD e 15V, VIN e VDD or VSS VOL Low Level Output Voltage VDD e 5V VDD e 10V VDD e 15V High Level Output Voltage VDD e 5V VDD e 10V VDD e 15V VIL Low Level Input Voltage VDD e 5V, VO e 0.5V or 4.5V VDD e 10V, VO e 1.0V or 9.0V VDD e 15V, VO e 1.5V or 13.5V VIH High Level Input Voltage VDD e 5V, VO e 0.5V or 4.5V VDD e 10V, VO e 1.0V or 9.0V VDD e 15V, VO e 1.5V or 13.5V 3.5 7.0 11.0 3.5 7.0 11.0 2.75 5.50 8.25 3.5 7.0 11.0 V V V IOL Low Level Output Current (Note 3) VDD e 5V, VO e 0.4V VDD e 10V, VO e 0.5V VDD e 15V, VO e 1.5V 0.64 1.6 4.2 0.51 1.3 3.4 0.88 2.25 8.8 0.36 0.9 2.4 mA mA mA IOH High Level Output Current (Note 3) VDD e 5V, VO e 4.6V VDD e 10V, VO e 9.5V VDD e 15V, VO e 13.5V b 0.64 b 1.6 b 4.2 b 0.51 b 1.3 b 3.4 b 0.88 b 2.25 b 8.8 b 0.36 b 0.9 b 2.4 mA mA mA IIN Input Current VDD e 15V, VIN e 0V VDD e 15V, VIN e 15V VOH ( (l l lIOl k 1 mA 4.95 9.95 14.95 IO k 1 mA 4.95 9.95 14.95 1.5 3.0 4.0 5 10 15 2.25 4.50 6.75 4.95 9.95 14.95 1.5 3.0 4.0 V V V 1.5 3.0 4.0 b 0.1 b 10 b 5 b 0.1 b 1.0 0.1 10b5 0.1 1.0 V V V mA mA Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices should be operated at these limits. The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for actual device operation. Note 2: VSS e 0V unless otherwise specified. Note 3: IOH and IOL are tested one output at a time. http://www.national.com 2 DC Electrical Characteristics CD4015BC (Note 2) Symbol Parameter b 55§ C Conditions Min Max a 25§ C Min a 125§ C Min Units Typ Max Max 20 40 80 0.005 0.010 0.015 20 40 80 150 300 600 mA mA mA 0.05 0.05 0.05 0 0 0 0.05 0.05 0.05 0.05 0.05 0.05 V V V IDD Quiescent Device Current VDD e 5V, VIN e VDD or VSS VDD e 10V, VIN e VDD or VSS VDD e 15V, VIN e VDD or VSS VOL Low Level Output Voltage VDD e 5V VDD e 10V VDD e 15V VOH High Level Output Voltage VDD e 5V VDD e 10V VDD e 15V VIL Low Level Input Voltage VDD e 5V, VO e 0.5V or 4.5V VDD e 10V, VO e 1.0V or 9.0V VDD e 15V, VO e 1.5V or 13.5V VIH High Level Input Voltage VDD e 5V, VO e 0.5V or 4.5V VDD e 10V, VO e 1.0V or 9.0V VDD e 15V, VO e 1.5V or 13.5V 3.5 7.0 11.0 3.5 7.0 11.0 2.75 5.50 8.25 3.5 7.0 11.0 V V V IOL Low Level Output Current (Note 3) VDD e 5V, VO e 0.4V VDD e 10V, VO e 0.5V VDD e 15V, VO e 1.5V 0.52 1.3 3.6 0.44 1.1 3.0 0.88 2.25 8.8 0.36 0.9 2.4 mA mA mA IOH High Level Output Current (Note 3) VDD e 5V, VO e 4.6V VDD e 10V, VO e 9.5V VDD e 15V, VO e 13.5V b 0.52 b 1.3 b 3.6 b 0.44 b 1.1 b 3.0 b 0.88 b 2.25 b 8.8 b 0.36 b 0.9 b 2.4 mA mA mA IIN Input Current VDD e 15V, VIN e 0V VDD e 15V, VIN e 15V 4.95 9.95 14.95 4.95 9.95 14.95 1.5 3.0 4.0 5 10 15 2.25 4.50 6.75 4.95 9.95 14.95 1.5 3.0 4.0 V V V 1.5 3.0 4.0 b 0.3 b 10 b 5 b 0.3 b 1.0 0.3 10b5 0.3 1.0 V V V mA mA Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices should be operated at these limits. The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for actual device operation. Note 2: VSS e 0V unless otherwise specified. Note 3: IOH and IOL are tested one output at a time. 3 http://www.national.com AC Electrical Characteristics* TA e 25§ C, CL e 50 pF, RL e 200k, tr e tf e 20 ns, unless otherwise specified Symbol Parameter Conditions tPHL, tPLH Propagation Delay Time tTHL, tTLH Min Typ Max Units VDD e 5V VDD e 10V VDD e 15V 230 80 60 350 160 120 ns ns ns Transition Time VDD e 5V VDD e 10V VDD e 15V 100 50 40 200 100 80 ns ns ns tWL, tWM Minimum Clock Pulse-Width VDD e 5V VDD e 10V VDD e 15V 160 60 50 250 110 85 ns ns ns trCL, tfCL Clock Rise and Fall Time VDD e 5V VDD e 10V VDD e 15V 15 15 15 ms ms ms tSU Minimum Data Set-Up Time VDD e 5V VDD e 10V VDD e 15V 100 40 30 ms ms ms fCL Maximum Clock Frequency VDD e 5V VDD e 10V VDD e 15V CIN Input Capacitance Clock Input Other Inputs 7.5 5 10 7.5 pF pF CLOCK OPERATION 50 20 15 2 4.5 6 3.5 8 11 MHz MHz MHz RESET OPERATION tPHL(R) Propagation Delay Time VDD e 5V VDD e 10V VDD e 15V 200 100 80 400 200 160 ns ns ns tWH(R) Minimum Reset Pulse Width VDD e 5V VDD e 10V VDD e 15V 135 40 30 250 80 60 ns ns ns *AC Parameters are guaranteed by DC correlated testing. Logic Diagrams TL/F/5948 – 2 http://www.national.com 4 Logic Diagrams (Continued) Terminal No. 16 e VDD Terminal No. 8 e GND TL/F/5948 – 3 Physical Dimensions inches (millimeters) unless otherwise noted Ceramic Dual-In-Line Package (J) Order Number CD4015BMJ or CD4015BCJ NS Package Number J16A 5 http://www.national.com CD4015BM/CD4015BC Dual 4-Bit Static Shift Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Molded Dual-In-Line Package (N) Order Number CD4015BMN or CD4015BCN NS Package Number N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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