NSC ADC10030CIVT

ADC10030
10-Bit, 30 MSPS, 125 mW A/D Converter with Internal
Sample and Hold
General Description
Features
The ADC10030 is a low power, high performance CMOS
analog-to-digital converter that digitizes signals to 10 bits
resolution at sampling rates up to 30 Msps while consuming
a typical 125 mW from a single 5V supply. Reference force
and sense pins allow the user to connect an external reference buffer amplifier to ensure optimal accuracy. No missing
codes is guaranteed over the full operating temperature
range. The unique two-stage architecture achieves 9.1 Effective Bits with a 15 MHz input signal and a 30 MHz clock
frequency. Output formatting is straight binary coding.
To ease interfacing to 3V systems, the digital I/O power pins
of the ADC10030 can be tied to a 3V power source, making
the outputs 3V compatible. When not converting, power consumption can be reduced by pulling the PD (Power Down)
pin high, placing the converter into a low power standby
state, where it typically consumes less than 4 mW. The
ADC10030’s speed, resolution and single supply operation
makes it well suited for a variety of applications in video, imaging, communications, multimedia and high speed data acquisition. Low power, single supply operation ideally suit the
ADC10030 for high speed portable applications, and its
speed and resolution are ideal for charge coupled device
(CCD) input systems.
The ADC10030 comes in a space saving 32-pin TQFP and
operates over the industrial (−40˚C ≤ TA ≤ +85˚C) temperature range.
n
n
n
n
n
n
Internal Sample-and-Hold
Single +5V Operation
Low Power Standby Mode
Guaranteed No Missing Codes
TRI-STATE ® Outputs
TTL/CMOS or 3V Logic Input/Output Compatible
Key Specifications
n Resolution
n Conversion Rate
n ENOB @ 15 MHz Input
10 Bits
30 Msps
9.1 Bits (typ)
n DNL
0.40 LSB (typ)
n Conversion Latency
2 Clock Cycles
n PSRR
56 dB
n Power Consumption
n Low Power Standby Mode
125 mW (typ)
< 3.5 mW (typ)
Applications
n
n
n
n
n
n
n
Digital Video
Communications
Document Scanners
Medical Imaging
Electro-Optics
Plain Paper Copiers
CCD Imaging
Connection Diagram
DS101064-1
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation
DS101064
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ADC10030 10-Bit, 30 MSPS, 125 mW A/D Converter with Internal Sample and Hold
January 2000
ADC10030
Ordering Information
Commercial Temperature Range
(−40˚C ≤ TA ≤ +85˚C)
NS Package
ADC10030CIVT
TQFP
Block Diagram
DS101064-2
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2
ADC10030
Pin Descriptions and Equivalent Circuits
Pin
No.
Symbol
Equivalent Circuit
Description
30
VIN
Analog Input signal to be converted. Conversion
range is VREF+ S to VREF− S.
31
VREF+ F
Analog input that goes to the high side of the
reference ladder of the ADC. This voltage should
force VREF+ S to be in the range of 2.6V to 3.8V.
32
VREF+ S
Analog output used to sense the voltage at the top
of the ADC reference ladder.
2
VREF− F
Analog input that goes to the low side of the
reference ladder of the ADC. This voltage should
force VREF− S to be in the range of 1.7V to 2.8V.
1
VREF− S
Analog output used to sense the voltage at the
bottom of the ADC reference ladder.
9
CLK
Converter digital clock input. VIN is sampled on the
falling edge of CLK input.
8
PD
Power Down input. When this pin is high, the
converter is in the Power Down mode and the data
output pins are in a high impedance state.
OE
Output Enable pin. When this pin and the PD pin
are low, the output data pins are active. When this
pin or the PD pin is high, the data output pins are in
a high impedance state.
D0–D9
Digital Output pins providing the 10-bit conversion
results. D0 is the LSB, D9 is the MSB. Data is
acquired on the falling edge of the CLK input and
valid data is present 2.0 clock cycles plus tOD later.
VA
Positive analog supply pins. These pins should be
connected to a clean, quiet voltage source of +5V.
VA and VD should have a common supply and be
separately bypassed with 10 µF to 50 µF capacitors
in parallel with 0.1 µF capacitors.
VD
Positive digital supply pins. These pins should be
connected to a clean, quiet voltage source of +5V.
VA and VD should have a common supply and be
separately bypassed with 10 µF to 50 µF capacitors
in parallel with 0.1 µF capacitors.
26
14
thru
19
and
22
thru
25
3, 7,
28
5, 10
3
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ADC10030
Pin Descriptions and Equivalent Circuits
Pin
No.
Symbol
Equivalent Circuit
(Continued)
Description
12, 21
VD I/O
Positive supply pins for the digital output drivers.
These pins should be connected to a clean, quiet
voltage source of +3V to +5V and be separately
bypassed with 10 µF to 50 µF capacitors.
4, 27,
29
AGND
The ground return for the analog supply. AGND and
DGND should be connected together close to the
ADC10030 package.
6, 11
DGND
The ground return for the digital supply. AGND and
DGND should be connected together close to the
ADC10030 package.
13, 20
DGND I/O
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The ground return of the digital output drivers.
4
Soldering Temp., Infrared, 10 sec. (Note 6)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature
Positive Supply Voltage (V = VA = VD)
Voltage on Any Pin
300˚C
−65˚C to +150˚C
Operating Ratings (Notes 1, 2)
6.5V
Operating Temperature Range
−40˚C ≤ TA ≤ +85˚C
−0.3V to (VA or VD +0.3V)
VA, VD Supply Voltage
+4.75V to +5.5V
± 25 mA
± 50 mA
VD I/O Supply Voltage
+2.7V to 5.5V
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Package Dissipation at TA = 25˚C
See (Note 4)
ESD Susceptibility (Note 5)
Human Body Model
1500V
Machine Model
VIN Voltage Range
1.7V to (VA−1.2V)
VREF+ Voltage Range
2.6V to (VA−1.2V)
VREF− Voltage Range
1.7V to 2.8V
PD, CLK, OE Voltage Range
−0.3V to +5.5V
200V
Converter Electrical Characteristics
The following specifications apply for VA = +5.0VDC, VD = 5.0VDC, VD I/O = +5.0VDC, VREF+ = +3.5VDC, VREF− = +1.75VDC,
CL = 20 pF, fCLK = 27 MHz, RS = 50Ω. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C (Note 7)
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 9)
± 0.45
± 0.40
± 1.0
± 0.95
LSB(max)
10
Bits
Units
Static Converter Characteristics
INL
Integral Non-Linearity
DNL
Differential-Non-Linearity
Resolution with No Missing
Codes
LSB(max)
Zero Scale Offset Error
−4
mV
Full-Scale Offset Error
+3
mV
fIN = 1.0 MHz
fIN = 4.43 MHz
fIN = 13.5 MHz
fIN = 4.43 MHz, fCLK = 30 MHz
fIN = 15.0 MHz, fCLK = 30 MHz
fIN = 1.0 MHz
9.6
Bits
= 4.43 MHz
= 13.5 MHz
= 4.43 MHz, fCLK = 30 MHz
= 15.0 MHz, fCLK = 30 MHz
= 1.0 MHz
59
Dynamic Converter Characteristics
ENOB
S/(N+D)
Effective Number of Bits
Signal-to-Noise Plus
Distortion Ratio
fIN
fIN
fIN
fIN
SNR
THD
SFDR
Signal-to-Noise Ratio
Total Harmonic Distortion
Spurious Free Dynamic
Range
Overrange Output Code
fIN
fIN = 4.43 MHz
fIN = 13.5 MHz
fIN = 4.43 MHz, fCLK = 30 MHz
fIN = 15.0 MHz, fCLK = 30 MHz
fIN = 1.0 MHz
9.4
9.4
Bits
9.3
Bits
9.1
Bits
60
dB
58
dB
53.5
dB
58
dB
57
dB
60
dB
59
59
dB
54
59
dB
dB
58
dB
−72
dB
fIN = 4.43 MHz
fIN = 13.5 MHz
fIN = 4.43 MHz, fCLK = 30 MHz
fIN = 15.0 MHz, fCLK = 30 MHz
fIN = 1.0 MHz
−69
fIN = 4.43 MHz
fIN = 13.5 MHz
fIN = 4.43 MHz, fCLK = 30 MHz
fIN = 15.0 MHz, fCLK = 30 MHz
VIN > VREF+
Bits
8.6
−66
dB
−61
dB
−64
dB
−61
dB
73
dB
71
dB
68
dB
66
dB
62
dB
1023
5
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ADC10030
Absolute Maximum Ratings (Notes 1, 2)
ADC10030
Converter Electrical Characteristics
(Continued)
The following specifications apply for VA = +5.0VDC, VD = 5.0VDC, VD I/O = +5.0VDC, VREF+ = +3.5VDC, VREF− = +1.75VDC,
CL = 20 pF, fCLK = 27 MHz, RS = 50Ω. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C (Note 7)
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 9)
Units
Dynamic Converter Characteristics
Underrange Output Code
BW
Full Power Bandwidth
PSRR
Power Supply Rejection
Ratio
VIN < VREF−
Change in Full Scale with 4.5V to
5.5V Supply Change
150
MHz
56
dB
Reference, DC, and Logic Electrical Characteristics
The following specifications apply for VA = +5.0VDC, VD = +5.0VDC, VD I/O = +5.0VDC, VREF+ = +3.5VDC, VREF− =
+1.75VDC, CL = 20 pF, fCLK = 27 MHz, RS = 50Ω. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C
(Note 7)
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 9)
Units
1.75
3.5
1.6
3.8
V(min)
V(max)
Reference and Analog Input Characteristics
VIN
Analog Input Range
CIN
Analog VIN Input
Capacitance
5
IIN
Input Leakage Current
10
RREF
Reference Ladder
Resistance
VREF+
pF
µA
1000
850
1150
Ω(min)
Ω(max)
Positive Reference Voltage
3.5
3.8
V(max)
VREF−
Negative Reference
Voltage
1.75
1.6
V(min)
(VREF+) −
(VREF−)
Total Reference Voltage
1.75
1.0
2.2
V(min)
V(max)
CLK, OE, PD, Digital Input Characteristics
Logical “1” Input Current
VD = 5.5V
VD = 4.5V
VIH = VD
10
µA
Logical “0” Input Current
VIL = DGND
−10
µA
VIH
Logical “1” Input Voltage
VIL
Logical “0” Input Voltage
IIH
IIL
2.0
V(min)
1.0
V(max)
DB0–DB9 Digital Output Characteristics
VOH
Logical “1” Output Voltage
VOL
Logical “0” Output Voltage
IOZ
TRI-STATE Output Current
IOS
Output Short Circuit
Current
VD I/O =
VD I/O =
VD I/O =
VD I/O =
+4.5V, IOUT = −0.5 mA
+2.7V, IOUT = −0.5 mA
+4.5V, IOUT = −1.6 mA
+2.7V, IOUT = −1.6 mA
VOUT = DGND
VOUT = VD
VD I/O = 3V
VD I/O = 5V
4.0
2.4
V(min)
V(min)
0.4
0.4
V(max)
V(max)
−10
10
µA
µA
± 12
± 25
mA
17.6
0.5
mA(max)
mA
6.6
0.2
mA(max)
mA
mA
Power Supply Characteristics
IA
Analog Supply Current
ID +
ID I/O
Digital Supply Current
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PD = LOW, Ladder Current not
included
PD = HIGH, Ladder Current not
included
PD = LOW, Ladder Current not
included
PD = HIGH, Ladder Current not
included
6
(Continued)
The following specifications apply for VA = +5.0VDC, VD = +5.0VDC, VD I/O = +5.0VDC, VREF+ = +3.5VDC, VREF− =
+1.75VDC, CL = 20 pF, fCLK = 27 MHz, RS = 50Ω. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C
(Note 7)
Symbol
Typical
(Note 8)
Limits
(Note 9)
Units
PD = LOW
121
130
mW(max)
PD = HIGH
3.5
PD = LOW, fCLK = 30 MHz
125
Parameter
Conditions
Power Supply Characteristics
PD
Power Consumption
mW
AC Electrical Characteristics
The following specifications apply for VA = +5.0VDC, VD = +5.0VDC, VD I/O = 5.0VDC, VREF+ = +3.5VDC, VREF− =
+1.75VDC, CL = 20 pF, fCLK = 27 MHz, RS = 50Ω. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C
(Note 7)
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 9)
Units
(Limits)
30
MHz
fCLK1
Maximum Clock Frequency
27
fCLK2
Minimum Clock Frequency
1
tCH
Clock High Time
16.5
ns(min)
tCL
Clock Low Time
16.5
ns(min)
45
55
%(min)
%(max)
2.0
Clock Cycles
4
ns(max)
25
ns(max)
Duty Cycle
50
Pipeliine Delay (Latency)
MHz
trc, tfc
Clock Input Rise and Fall Time
tr, tf
Output Rise and Fall Times
10
tOD
Fall of CLK to Data Valid
20
tOH
Output Data Hold Time
12
ns
From Output High,
2 kΩ to Ground
25
ns
tDIS
Rising Edge of OE to
TRI-STATE
From Output Low, 2
kΩ to VD I/O
18
ns
1 kΩ to VCC
25
ns
27
ns
tEN
Falling Edge of OE to Valid
Data
tVALID
Data Valid Time
tAJ
Aperture Jitter
tWU
ns
< 30
ps
Full Scale Step Response
tr = 10 ns
1
conversion
Overrange Recovery Time
VIN Step from
(VREF+ +100 mV) to
(VREF−)
1
conversion
700
ns
PD Low to 1⁄2 LSB Accurate
Conversion (Wake-Up Time)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (VIN < GND or VIN > VA or VD), the current at that pin should be limited to 25 mA. The 50 mA
maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.
Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA)/θJA. In the 32-pin
TQFP, θJA is 69˚C/W, so PDMAX = 1,811 mW at 25˚C and 942 mW at the maximum operating ambient temperature of 85˚C. Note that the power dissipation of this
device under normal operation will typically be about 137 mW (125 mW quiescent power + 2 mW reference ladder power +10 mW due to 1 TTL load on each digital
output). The values for maximum power dissipation listed above will be reached only when the ADC10030 is operated in a severe fault condition (e.g. when input or
output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ω.
Note 6: See AN450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount” found in any post 1986 National
Semiconductor Linear Data Book, for other methods of soldering surface mount devices.
Note 7: The inputs are protected as shown below. Input voltage magnitudes up to 300 mV beyond the supply rails will not damage this device. However, errors in
the A/D conversion can occur if the input goes above VA or below AGND by more than 300 mV.
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ADC10030
Reference, DC, and Logic Electrical Characteristics
ADC10030
AC Electrical Characteristics
(Continued)
DS101064-24
DS101064-12
DS101064-11
Note 8: Typical figures are at TJ = 25˚C, and represent most likely parametric norms.
Note 9: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 10: When the input signal is between VREF+ and (VA + 300 mV), the output code will be 3FFh, or all 1s. When the input signal is between −300 mV and VREF−,
the output code will be 000h, or all 0s.
Typical Performance Characteristics
VA = VD = VD I/O = 5V, TA = 25˚C, fIN = 4.4 MHz, fCLK = 27
MHz, unless otherwise specified.
Typical INL
INL vs fCLK
INL vs VA
DS101064-42
DS101064-41
INL vs Clock Duty Cycle
Typical DNL
DNL vs fCLK
DS101064-44
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DS101064-43
DS101064-45
8
DS101064-46
VA = VD = VD I/O = 5V, TA = 25˚C, fIN = 4.4 MHz, fCLK = 27
MHz, unless otherwise specified.. (Continued)
DNL vs VA
DNL vs Clock Duty Cycle
DS101064-47
SINAD & ENOB vs
Temperature and fIN
DS101064-48
DS101064-49
SINAD & ENOB vs VA
IA + ID vs Temparature
DS101064-50
Spectral Response at 30 MSPS
Spectral Response at 27 MSPS
DS101064-53
DS101064-52
Dynamics at 27 MSPS
DS101064-54
Dynamics at 30 MSPS
DS101064-55
DS101064-56
fCLK. The input frequency at which the output is −3 dB relative to the 1 MHz input signal is the full power bandwidth.
FULL SCALE (FS) INPUT RANGE of the ADC is the input
range of voltages over which the ADC will digitize that input.
For VREF+ = 3.5V and VREF− = 1.5V, FS = (VREF+) −
(VREF−) = 2.0V.
FULL SCALE OFFSET ERROR is a measure of how far the
last code transition is from the ideal 11⁄2 LSB below VREF+
and is defined as V1023 +1.5 LSB − VREF+, where V1023 is
the voltage at which the transition from code 1022 to 1023
occurs.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from negative full scale (1⁄2 LSB below the first code transition) through
Specification Definitions
APERTURE JITTER is the variation in aperture delay from
sample to sample. Aperture jitter shows up as input noise.
APERTURE DELAY See Sampling Delay.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise plus
Distortion Ratio (S/N+D or SINAD). ENOB is defined as (SINAD −1.76) / 6.02.
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its 1 MHz value for a full scale input. The test is performed with fIN equal to 100 kHz plus integral multiples of
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ADC10030
Typical Performance Characteristics
ADC10030
Specification Definitions
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the RMS value of the input signal to the RMS value of
other spectral components below half the clock frequency,
not including harmonics or dc.
(Continued)
positive full scale (11⁄2 LSB above the last code transition).
The deviation of any given code from this straight line is
measured from the center of that code value.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or
SINAD) is the ratio, expressed in dB, of the RMS value of the
input signal to the RMS value of all of the other spectral components below half the clock frequency, including harmonics
but excluding dc.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB or dBc, between the RMS value of the
input signal and the peak spurious signal, where a spurious
signal is any signal present in the output spectrum that is not
present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the RMS total of the first six harmonic components, to the RMS value of the input signal.
ZERO SCALE OFFSET ERROR is the difference between
the ideal input voltage (1⁄2 LSB) and the actual input voltage
that just causes a transition from an output code of zero to
an output code of one.
OUTPUT DELAY is the time delay after the fall of the input
clock before the data update is present at the output pins.
OUTPUT HOLD TIME is the length of time that the output
data is valid after the fall of the input clock.
PIPELINE DELAY (LATENCY) is the number of clock cycles
between initiation of conversion and when that data is presented to the output driver stage. Data for any given sample
is available by the Pipeline Delay plus the Output Delay after
that sample is taken. New data is available at every clock
cycle, but the data lags the conversion by the Pipeline Delay
plus the Output Delay.
PSRR (POWER SUPPLY REJECTION RATIO) is the ratio
of the change in dc power supply voltage to the resulting
change in Full Scale Error, expressed in dB.
SAMPLING (APERTURE) DELAY or APERTURE TIME is
that time required after the fall of the clock input for the sampling switch to open. The sample is effectively taken this
amount of time after the fall of the clock input.
Timing Diagram
DS101064-15
FIGURE 1. ADC10030 Timing Diagram
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10
ADC10030
Timing Diagram
(Continued)
DS101064-16
FIGURE 3. tEN, tDIS Test Circuit
DS101064-17
FIGURE 2. AC Test Circuit
Functional Description
The ADC10030 maintains excellent dynamic performance
for input signals up to and exceeding half the clock frequency. The use of an internal sample-and-hold amplifier
(SHA) enables sustained dynamic performance for signals of
input frequency beyond the clock rate, lowers the converter’s
input capacitance and reduces the number of external components required.
The analog signal at VIN that is within the voltage range set
by VREF+ S and VREF− S are digitized to ten bits at up to
30 MSPS. Input voltages below VREF− S will cause the output word to consist of all zeroes. Input voltages above
VREF+ S will cause the output word to consist of all ones.
VREF+ S has a range of 2.6V to 3.8V, while VREF− S has a
range of 1.7V to 2.8V. VREF+ S should always be at least
1.0V more positive than VREF− S.
Data is acquired at the falling edge of the clock and the digital equivalent of that data is available at the digital outputs
2.0 clock cycles plus tOD later. The ADC10030 will convert as
long as the clock signal is present at pin 9 and the PD pin is
low. The Output Enable pin (OE), when low, enables the output pins. The digital outputs are in the high impedance state
when the OE pin or the PD pin is high.
minimal Differential Gain and Differential Phase. The
CLC409 performs best with a feedback resistor of about
100Ω.
Care should be taken to keep digital noise out of the analog
input circuitry to maintain highest noise performance.
2.0 REFERENCE INPUTS
Note: Throughout this data sheet reference is made to VREF+ and to VREF−.
These refer to the internal voltage across the reference ladder and are,
nominally, VREF+ S and VREF− S, respectively.
Figure 4 shows a simple reference biasing scheme with
minimal components. While this circuit might suffice for
some applications, it does suffer from thermal drift because
the external will have a different temperature coefficient than
the on-chip resistors. Also, the on-chip resistors, while well
matched to each other, will have a large tolerance compared
with any external resistors, causing the value of VREF+ and
VREF− to be somewhat variable.
The VREF+ F and VREF− F pins should each be bypassed to
AGND with 10 µF tantalum or electrolytic capacitors and
0.1 µF ceramic capacitors.
The circuit of Figure 5 is an improvement over the circuit of
Figure 4 in that the positive end of the reference ladder is defined with a reference voltage. This reduces problems of
high reference variability and thermal drift.
In addition to the usual VREF+F and VREF−F reference inputs, the ADC10030 has two sense outputs for precision
control of the ladder voltages. These sense outputs (VREF+
S and VREF− S) compensate for errors due to IR drops between the source of the reference voltages and the ends of
the reference ladder itself.
With the addition of two op-amps, the voltages at the top and
bottom of the reference ladder can be forced to the exact
value desired, as shown in Figure 6.
Applications Information
1.0 THE ANALOG INPUT
The analog input of the ADC10030 is a switch (transmission
gate) followed by a switched capacitor amplifier. The capacitance seen at the input changes with the clock level, appearing as about 3 pF when the clock is low, and about 5 pF
when the clock is high. This small change in capacitance can
be reasonably assumed to be a fixed capacitance. Care
should be taken to avoid driving the input beyond the supply
rails, even momentarily, as during power-up.
The CLC409 has been found to be a good device to drive the
ADC10030 because of its wide bandwidth, low distortion and
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ADC10030
Applications Information
(Continued)
DS101064-18
FIGURE 4. Simple, Low Component Count Reference Biasing
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12
ADC10030
Applications Information
(Continued)
DS101064-19
FIGURE 5. Improved Low Component Count Reference Biasing
The circuit of Figure 6 may be used if it is desired to obtain
precise reference voltages. The LMC6082 in this circuit was
chosen for its low offset voltage, low voltage rail-to-rail capability and low cost.
Since the current flowing through the sense lines (those lines
associated with VREF+ S and VREF− S) is essentially zero,
there is negligible voltage drop across any resistance in series with these sense pins and the voltage at the inverting input of the op-amp accurately represents the voltage at the
top (or bottom) of the ladder. The op-amp drives the force input, forcing the voltage at the ends of the ladder to equal the
voltage at the op-amp’s non-inverting input, plus any offset
voltage. For this reason, op-amps with low VOS, such as the
LMC6081 and LMC6082, should be used for this application.
Voltages at the reference sense pins (VREF+ S and VREF− S)
should be within the range specified in the Operating Ratings
table (2.6V to 3.8V for VREF+ and 1.7V to VA - 1.2V for
VREF−). Any device used to drive the reference pins should
be able to source sufficient current into the VREF+ F pin and
sink sufficient current from the VREF− F pin when the ladder
is at its minimum value of 850Ω.
The reference voltage at the top of the ladder (VREF+) may
take on values as low as 1.0V above the voltage at the bottom of the ladder (VREF−) and as high as (VA − 1.2V). The
voltage at the bottom of the ladder (VREF−) may take on values as low as 1.7V and as high as 2.8V. However, to minimize noise effects and ensure accurate conversions, the total reference voltage range (VREF+ − VREF−) should be a
minimum of 1.0V and a maximum of 2.2V.
13
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ADC10030
Applications Information
(Continued)
DS101064-20
FIGURE 6. Setting Precision Reference Voltages
circuits driving the CLK, PD, OE, analog input and reference
pins do not come up any faster than does the voltage at the
ADC10030 power pins.
3.0 POWER SUPPLY CONSIDERATIONS
A/D converters draw sufficient transient current to corrupt
their own power supplies if not adequately bypassed. A
10 µF to 50 µF tantalum or aluminum electrolytic capacitor
should be placed within an inch (2.5 centimeters) of the A/D
power pins, with a 0.1 µF ceramic chip capacitor placed as
close as possible to each of the converter’s power supply
pins. Leadless chip capacitors are preferred because they
have low lead inductance.
While a single voltage source should be used for the analog
and digital supplies of the ADC10030, these supply pins
should be well isolated from each other to prevent any digital
noise from being coupled to the analog power pins. A choke
or ferrite bead is recommended between the analog and
digital supply lines, with a ceramic capacitor close to the
analog supply pin.
The converter digital supply should not be the supply that is
used for other digital circuitry on the board. It should be the
same supply used for the ADC10030 analog supply.
As is the case with all high-speed converters, the ADC10030
should be assumed to have little high frequency power supply rejection. A clean analog power source should be used.
No pin should ever have a voltage on it that is more than
300 mV in excess of the supply voltages or below ground,
not even on a transient basis. This can be a problem upon
application of power to a circuit. Be sure that the supplies to
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4.0 THE ADC10030 CLOCK
Although the ADC10030 is tested and its performance is
guaranteed with a 27 MHz clock, it typically will function with
clock frequencies from 1 MHz to 30 MHz. Performance is
best if the clock rise and fall times are 4 ns or less and if the
clock line is terminated with a series RC of about 100Ω and
47 pF near the clock input pin, as shown in Figure 6.
5.0 LAYOUT AND GROUNDING
Proper routing of all signals and proper ground techniques
are essential to ensure accurate conversion. Separate analog and digital ground planes are required to meet data sheet
limits. The analog ground plane should be low impedance
and free of noise from other parts of the system.
Each bypass capacitor should be located as close to the appropriate converter pin as possible and connected to the pin
and the appropriate ground plane with short traces. The analog input should be isolated from noisy signal traces to avoid
coupling of spurious signals into the input. Any external component (e.g., a filter capacitor) connected between the converter’s input and ground should be connected to a very
clean point in the analog ground return.
14
Digital and analog signal lines should never run parallel to
each other in close proximity with each other. They should
only cross each other when absolutely necessary, and then
only at 90˚ angles. Violating this rule can result in digital
noise getting into the input, which degrades accuracy and
dynamic performance (THD, SNR, SINAD).
(Continued)
Figure 7 gives an example of a suitable layout, ground plane
separation, and bypass capacitor placement. All analog circuitry (input amplifiers, filters, reference components, etc.)
should be placed on or over the analog ground plane. All
digital circuitry and I/O lines should be over the digital ground
plane.
DS101064-21
FIGURE 7. An Acceptable Layout Pattern for the ADC10030
15
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ADC10030
Applications Information
ADC10030
Applications Information
(e.g., 74F and 74AC devices) to exhibit undershoot that goes
more than a volt below ground. A resistor of 50Ω to 100Ω in
series with the offending digital input will usually eliminate
the problem.
(Continued)
6.0 DYNAMIC PERFORMANCE
The ADC10030 is ac tested and its dynamic performance is
guaranteed. To meet the published specifications, the clock
source driving the CLK input must be free of jitter. For best
ac performance, isolating the ADC clock from any digital circuitry should be done with adequate buffers, as with a clock
tree. See Figure 8.
Meeting dynamic specifications is also dependent upon
keeping digital noise out of the input, as mentioned in Sections 1.0 and 5.0.
Care should be taken not to overdrive the inputs of the
ADC10030 (or any device) with a device that is powered
from supplies outside the range of the ADC10030 supply.
Such practice may lead to conversion inaccuracies and even
to device damage.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers has to charge for
each conversion, the more instantaneous digital current is
required from VD I/O and DGND I/O. These large charging
current spikes can couple into the analog section, degrading
dynamic performance. Adequate bypassing and maintaining
separate analog and digital ground planes will reduce this
problem on the board. Buffering the digital data outputs (with
an 74F541, for example) may be necessary if the data bus to
be driven is heavily loaded. Dynamic performance can also
be improved by adding series resistors of 47Ω at each digital
output.
Driving the VREF+ F pin or the VREF− F pin with devices
that can not source or sink the current required by the
ladder. As mentioned in section 2.0, be careful to see that
any driving devices can source sufficient current into the
VREF+ F pin and sink sufficient current from the VREF− F pin.
If these pins are not driven with devices than can handle the
required current, they will not be held stable and the converter output will exhibit excessive noise.
Using a clock source with excessive jitter. This will cause
the sampling interval to vary, causing excessive output noise
and a reduction in SNR performance. The use of simple
gates with RC timing is generally inadequate.
Using the same voltage source for VD and digital logic.
As mentioned in section 3.0, VD should use the same power
source used by VA, but should be decoupled from VA.
DS101064-22
FIGURE 8. Isolating the ADC Clock
from Digital Circuitry
7.0 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, all inputs should not go
more than 300 mV beyond the supply pins. Exceeding these
limits on even a transient basis can cause faulty or erratic
operation. It is not uncommon for high speed digital circuits
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16
inches (millimeters) unless otherwise noted
32-Lead TQFP Package
Ordering Number ADC10030CIVT
NS Package Number VBE32A
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ADC10030 10-Bit, 30 MSPS, 125 mW A/D Converter with Internal Sample and Hold
Physical Dimensions