ADC1175-50 8-Bit, 50 MSPS, 125 mW A/D Converter General Description The ADC1175-50 is a low power, 50 MSPS analog-to-digital converter that digitizes signals to 8 bits while consuming just 125 mW (typ). The ADC1175-50 uses a unique architecture that achieves 6.8 Effective Bits and 25 MHz input and 50 MHz clock frequency. Output formatting is straight binary coding. The excellent DC and AC characteristics of this device, together with its low power consumption and +5V single supply operation, make it ideally suited for many video and imaging applications, including use in portable equipment. Furthermore, the ADC1175-50 is resistant to latch-up and the outputs are short-circuit proof. The top and bottom of the ADC1175-50’s reference ladder is available for connections, enabling a wide range of input possibilities. The low input capacitance (7 pF, typical) makes this device easier to drive than conventional flash converters and the power down mode reduces power consumption to less than 5 mW. The ADC1175-50 is offered in SOIC (EIAJ) and TSSOP. It is designed to operate over the commercial temperature range of −20˚C to +75˚C. Features n Internal Track-and-Hold function n Single +5V operation n Internal reference bias resistors n Industry standard pinout n Power-down mode ( < 5 mW) Key Specifications n n n n n n n n n Resolution 8 Bits Maximum Sampling Frequency 50 MSPS (min) THD 54 dB (typ) DNL 0.7 LSB (typ) ENOB @ fIN = 25 MHz 6.8 Bits (typ) Guaranteed No Missing Codes Differential Phase 0.5˚ (typ) Differential Gain 1.0% (typ) Power Consumption 125 mW (typ), 190 mW (max) (Excluding Reference Current) Applications n n n n n n n n Digital Still Cameras CCD Imaging Electro-Optics Medical Imaging Communications Video Digitization Digital Television Multimedia Connection Diagram DS100896-1 Ordering Information ADC1175-50CIJM SOIC (EIAJ) ADC1175-50CIJMX SOIC (EIAJ) (tape and reel) ADC1175-50CIMT TSSOP ADC1175-50CIMTX TSSOP (tape and reel) TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 2000 National Semiconductor Corporation DS100896 www.national.com ADC1175-50 8-Bit, 50 MSPS, 125 mW A/D Converter January 2000 ADC1175-50 Block Diagram DS100896-2 Pin Descriptions and Equivalent Circuits Pin No. Symbol 19 VIN Analog signal input. Conversion range is VRT to VRB. 16 VRTS Reference Top Bias with internal pull up resistor. Short this pin to VRT to self-bias the reference ladder. VRT Analog input that is the high (top) side of the reference ladder of the ADC. Nominal range is 1.0V to AVDD, optimized value of 2.6V. Voltages on VRT and VRB inputs define the VIN conversion range. Bypass well. See Section 2.0 for more information. VRB Analog input that is the low (bottom) side of the reference ladder of the ADC. Nominal range is 0.0V to 4.0V, with optimized value of 0.6V. Voltage on VRT and VRB inputs define the VIN conversion range. Bypass well. See Section 2.0 for more information. 17 23 www.national.com Equivalent Circuit Description 2 Pin No. 22 Symbol Equivalent Circuit ADC1175-50 Pin Descriptions and Equivalent Circuits (Continued) Description Reference Bottom Bias with internal pull down resistor. Short to VRB to self-bias the reference ladder. Bypass well if not grounded. See Section 2.0 for more information. VRBS 1 PD CMOS/TTL compatible Digital input that, when high, puts the ADC1175-50 into a power-down mode where total power consumption is typically less than 5 mW. With this pin low, the device is in the normal operating mode. 12 CLK CMOS/TTL compatible digital clock input. VIN is sampled on the falling edge of CLK input. 3 thru 10 Conversion data digital Output pins. D0 is the LSB, D7 is the MSB. Valid data is output just after the rising edge of the CLK input. These pins are in a high impedance mode when the PD pin is low. D0–D7 11, 13, 14 DVDD Positive digital supply pin. Connect to a clean, quiet voltage source of +5V. AVDD and DVDD should have a common source and be separately bypassed with a 10 µF capacitor and a 0.1 µF ceramic chip capacitor. See Section 4.0 for more information. 2, 24 DVSS The ground return for the digital supply. AVSS and DVSS should be connected together close to the ADC1175-50. 3 www.national.com ADC1175-50 Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit (Continued) Description 15, 18 AVDD Positive analog supply pin. Connect to a clean, quiet voltage source of +5V. AVDD and DVDD should have a common source and be separately bypassed with a 10 µF capacitor and a 0.1 µF ceramic chip capacitor. See Section 4.0 for more information. 20, 21 AVSS The ground return for the analog supply. AVSS and DVSS should be connected together close to the ADC1175-50 package. www.national.com 4 ESD Susceptibility (Note 5) Human Body Model Machine Model Soldering Temperature, Infrared, (10 sec.) (Note 6) Storage Temperature Short Circuit Duration (Single High Output to Ground) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (AVDD, DVDD) Voltage on Any Input or Output Pin Reference Voltage (VRT, VRB) CLK, PD Voltage Range Digital Output Voltage (VOH, VOL) Input Current at Any Pin (Note 3) Package Input Current (Note 3) Power Dissipation at TA = 25˚C 6.5V −0.3V to +6.5V AVDD to VSS −0.5 to (AVDD +0.5V) VDD to VSS ± 25 mA ± 50 mA See (Note 4) 2000V 250V 300˚C −65˚C to +150˚C 1 Second Operating Ratings (Notes 1, 2) −20˚C ≤ TA ≤ +75˚C +4.75V to +5.25V < 0.5V 0V to 100 mV 1.0V to VDD 0V to 4.0V VRB to VRT Operating Temperature Range Supply Voltage (AVDD, DVDD) AVDD − DVDD Ground Difference |DVSS–AVSS| Upper Reference Voltage (VRT) Lower Reference Voltage (VRB) VIN Voltage Range Converter Electrical Characteristics The following specifications apply for AVDD = DVDD = +5.0 VDC, PD = 0V, VRT = +2.6V, VRB = 0.6V, CL = 20 pF, fCLK = 50 MHz at 50% duty cycle. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25˚C (Notes 7, 8). Symbol Parameter Conditions Typical (Note 9) Limits (Note 9) Units (Limits) ± 0.8 ± 1.95 LSB (max) +0.7 +1.75 LSB (max) −0.7 −1.0 LSB (min) 8 Bits DC ACCURACY INL DNL Integral Non Linearity Error Differential Non-Linearity VIN = 0.6V to 2.6V VIN = 0.6V to 2.6V Resolution for No Missing Codes EOT Top Offset Voltage −12 mV EOB Bottom Offset Voltage +10 mV VIDEO ACCURACY DP Differential Phase Error fIN = 4.43 MHz Modulated Ramp 0.5 deg DG Differential Gain Error fIN = 4.43 MHz Modulated Ramp 1.0 % ANALOG INPUT AND REFERENCE CHARACTERISTICS VRB V (min) VRT V (max) VIN Input Range CIN VIN Input Capacitance RIN RIN Input Resistance >1 MΩ BW Full Power Bandwidth 120 MHz RRT Top Reference Resistor 320 Ω RREF Reference Ladder Resistance RRB Bottom Reference Resistor IREF 2.0 VIN = 1.5V +0.7 Vrms (CLK LOW) 4 pF (CLK HIGH) 7 pF VRT to VRB 270 200 350 Ω (min) Ω (max) 5.4 mA (min) 10.8 mA (max) Ω 80 VRT = VRTS, VRB = VRBS 7 VRT = VRTS, VRB = AVSS 8 Reference Ladder Current VRT Reference Top Self Bias Voltage VRT Connected to VRTS, VRB Connected to VRBS 2.6 VRB Reference Bottom Self Bias Voltage VRT Connected to VRTS, VRB Connected to VRBS 0.6 5 6.1 mA (min) 12.3 mA (max) V (min) V (max) 0.55 0.70 V (min) V (max) www.national.com ADC1175-50 Absolute Maximum Ratings (Notes 1, 2) ADC1175-50 Converter Electrical Characteristics (Continued) The following specifications apply for AVDD = DVDD = +5.0 VDC, PD = 0V, VRT = +2.6V, VRB = 0.6V, CL = 20 pF, fCLK = 50 MHz at 50% duty cycle. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25˚C (Notes 7, 8). Symbol Typical (Note 9) Limits (Note 9) Units (Limits) VRT Connected to VRTS, VRB Connected to VRBS 2 1.89 2.20 (V (min) V (max) VRT Connected to VRTS, VRB Connected to VRBS 2.3 Parameter Conditions ANALOG INPUT AND REFERENCE CHARACTERISTICS VRTS–VRBS Self Bias Voltage Delta VRT–VRB V 2 1.0 2.8 V (min) V (max) fIN = 4.4 MHz, fCLK = 40 MHz fIN = 19.9 MHz, fCLK = 40 MHz fIN = 1.3 MHz, fCLK = 50 MHz 7.2 6.7 Bits (min) 7.0 6.4 Bits (min) 7.3 Bits fIN = 4.4 MHz, fCLK = 50 MHz fIN = 24.9 MHz, fCLK = 50 MHz fIN = 4.4 MHz, fCLK = 40 MHz 7.2 Bits fIN = 19.9 MHz, fCLK = 40 MHz fIN = 1.3 MHz, fCLK = 50 MHz fIN = 4.4 MHz, fCLK = 50 MHz Reference Voltage Differential CONVERTER DYNAMIC CHARACTERISTICS ENOB SINAD Effective Number of Bits Signal-to-Noise & Distortion fIN = 24.9 MHz, fCLK = 50 MHz fIN = 4.4 MHz, fCLK = 40 MHz fIN = 19.9 MHz, fCLK = 40 MHz SNR SFDR THD Signal-to-Noise Ratio Spurious Free Dynamic Range Total Harmonic Distortion 6.8 6.1 Bits (min) 45 42 dB (min) 44 40 dB (min) 46 dB 45 dB 43 38.4 dB (min) 46 42.5 dB (min) 44 41 dB (min) fIN = 1.3 MHz, fCLK = 50 MHz fIN = 4.4 MHz, fCLK = 50 MHz fIN = 24.9 MHz, fCLK = 50 MHz 48 fIN = 1.3 MHz fIN = 4.4 MHz fIN = 24.9 MHz fIN = 1.3 MHz 57 dB 56 dB 51 dB dB 45 44 dB 40 dB (min) −55 dB fIN = 4.4 MHz fIN = 24.9 MHz −54 dB −51 dB POWER SUPPLY CHARACTERISTICS IADD Analog Supply Current DVDD = AVDD = 5.25V 13 mA IDDD Digital Supply Current DVDD = AVDD = 5.25V 11 mA DVDD = AVDD = 5.25V, fCLK = 50 MHz 25 DVDD = AVDD = 5.25V, CLK Inactive (low) 14 IADD + IDDD Total Operating Current Power Consumption PD pin low 125 Power Consumption PD pin high < 5 mW 36 mA (max) mA 190 mW (max) mW CLK, PD DIGITAL INPUT CHARACTERISTICS VIH Logical High Input Voltage VIL Logical Low Input Voltage IIH Logical High Input Current IIL Logical Low Input Current CIN Digital Input Capacitance 2.0 VIH = DVDD = AVDD = +5.25V VIL = 0V, DVDD = AVDD = +5.25V V (min) 0.8 V (max) ±5 ±5 µA (max) 4 µA (max) pF DIGITAL OUTPUT CHARACTERISTICS IOH Output Current, Logic HIGH DVDD = 4.75V, VOH = 4.0V −1.1 mA (min) IOL Output Current, Logic LOW DVDD = 4.75V, VOL = 0.4V 1.8 mA (min) www.national.com 6 (Continued) The following specifications apply for AVDD = DVDD = +5.0 VDC, PD = 0V, VRT = +2.6V, VRB = 0.6V, CL = 20 pF, fCLK = 50 MHz at 50% duty cycle. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25˚C (Notes 7, 8). Symbol Parameter Typical (Note 9) Conditions Limits (Note 9) Units (Limits) DIGITAL OUTPUT CHARACTERISTICS IOZH, IOZL TRI-STATE ® Output Current DVDD = 5.25V, PD = DVDD, VOL = DVDD, or VOL = 0V ± 20 µA AC ELECTRICAL CHARACTERISTICS fC1 Maximum Conversion Rate 55 fC2 Minimum Conversion Rate 1 tOD Output Delay CLK high to data valid 14 Pipeline Delay (Latency) tDS Sampline (Aperture) Delay tAJ Aperture Jitter tOH Output Hold Time tEN PD Low to Data Valid 50 MHz 5 ns (min) 20 ns (max) 2.5 CLK low to acquisition of data MHz (min) Clock Cycles 3 ns 10 ps rms CLK high to data invalid 10 ns Loaded as in Figure 2 140 ns Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND = AVSS = DVSS = 0V, unless otherwise specified. Note 3: When the input voltage at any pin exceeds the power supplies (that is, less than AVSS or DVSS, or greater than AVDD or DVDD), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two. Note 4: The absolute maximum junction temperature (TJ max) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJ max, the junction-to-ambient thermal resistance (θJA) and the ambient temperature (TA), and can be calculated using the formula PD max = (TJ max–TA)/θJA. In the 24-pin TSSOP, θJA is 92˚C/W, so PD max = 1,358 mW at 25˚C and 815 mW at the maximum operating ambient temperature of 75˚C. (Typical thermal resistance, θJA, of this part is 98˚C/W for the EIAJ SOIC.) Note that the power dissipation of this device under normal operation will typically be about 258 mW (210 mW quiescent power +38 mW reference ladder power +10 mW due to 1 TTL load on each digital output. The values for maximum power dissipation listed above will be reached only when the ADC1175-50 is operated in a severe fault condition (e.g., when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω. Note 6: See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount” found in any post 1986 National Semiconductor Linear Data Book for other methods of soldering surface mount devices. Note 7: The analog inputs are protected as shown below. Input voltage magnitudes up to 6.5V or 500 mV below GND will not damage this device. However, errors in the A/D conversion can occur if the input goes above VDD or below GND by more than 50 mV. As an example, if AVDD is 4.75 VDC, the full-scale input voltage must be ≤4.80 VDC to ensure accurate conversions. DS100896-10 Note 8: To guarantee accuracy, it is required that AVDD and DVDD be well bypassed. Each VDD pin must be decoupled with separate bypass capacitors. Note 9: Typical figures are at TJ = 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). 7 www.national.com ADC1175-50 Converter Electrical Characteristics ADC1175-50 Typical Performance Characteristics INL Plot AVDD = DVDD = 5V, fCLK = 50 MHz, unless otherwise stated. DNL Plot INL vs Temperature DS100896-12 DS100896-11 DNL vs Temperature SNR vs Temp & fIN DS100896-14 SINAD & ENOB vs Temp & fIN DS100896-13 THD vs Temp & fIN DS100896-16 DS100896-15 SINAD & ENOB vs Clock Duty Cycle SFDR vs Temp & fIN DS100896-17 DS100896-19 DS100896-18 tOD vs Temperature Power Supply Current vs fCLK DS100896-20 www.national.com DS100896-21 8 Spectral Response DS100896-22 ANALOG INPUT BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. The test is performed with fIN equal to 100 kHz plus integer multiples of fCLK. The input frequency at which the output is −3 dB relative to the low frequency input signal is the full power bandwidth. APERTURE JITTER is the time uncertainty of the sampling point (tDS), or the range of variation in the sampling delay. BOTTOM OFFSET is the difference between the input voltage that just causes the output code to transition to the first code and the negative reference voltage. Bottom Offset is defined as EOB = VZT − VRB, where VZT is the first code transition input voltage. Note that this is different from the normal Zero Scale Error. DIFFERENTIAL GAIN ERROR is the percentage difference between the output amplitudes of a high frequency reconstructed sine wave at two different dc levels. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. DNL is measured at the rated clock frequency with a ramp input. DIFFERENTIAL PHASE ERROR is the difference in the output phase of a reconstructed small signal sine wave at two different dc levels. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion Ratio, or SINAD. ENOB is defined as (SINAD − 1.76)/6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual codes from a line drawn from zero scale (1/2 LSB below the first code transition) through positive full scale (1/2 LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. The end point test method is used. INL is measured at rated clock frequency with a ramp input. OUTPUT DELAY is the time delay after the rising edge of the input clock before the data update is present at the output pins. PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that data is presented to the output stage. Data for any given sample is available the Pipeline Delay plus the Output Delay after that sample is taken. New data is available at every clock cycle, but the data lags the conversion by the pipeline delay. SAMPLING (APERTURE) DELAY, or tDS, is the time required after the falling edge of the clock for the sampling switch to open (in other words, for the Sample/Hold circuit to go from the “sample” mode into the “hold” mode). The Sample/Hold circuit effectively stops capturing the input signal and goes into the “hold” mode tDS after the clock goes low. SIGNAL TO NOISE RATIO (SNR) is the ratio of the rms value of the input signal to the rms value of the other spectral components below one-half the sampling frequency, not including harmonics or dc. SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding dc. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input. TOP OFFSET is the difference between the positive reference voltage and the input voltage that just causes the output code to transition to full scale and is defined as EOT = VFT − VRT. Where VFT is the full scale transition input voltage. Note that this is different from the normal Full Scale Error. TOTAL HARMONIC DISTORTION (THD) is the ratio of the rms total of the first six harmonic components to the rms value of the input signal. 9 www.national.com ADC1175-50 OUTPUT HOLD TIME is the length of time that the output data is valid after the rise of the input clock. Specification Definitions ADC1175-50 Timing Diagram DS100896-23 FIGURE 1. ADC1175-50 Timing Diagram DS100896-24 FIGURE 2. tEN, tDIS Test Circuit are 2.6V and 0.6V, respectively. If VRT and VRTS are connected together and VRB is grounded, the nominal value of VRT is 2.3V. Data is acquired at the falling edge of the clock and the digital equivalent of that data is available at the digital outputs 2.5 clock cycles plus tOD later. The ADC1175-50 will convert as long as the clock signal is present at pin 12. The Power Down pin (PD), when high, puts the ADC1175-50 into a power down mode where power consumption is typically less than 5 mW. When the part is powered down, the digital output pins are in a high impedance TRI-STATE. It takes about 140 ns for the part to become active upon coming out of the power down mode. Functional Description The ADC1175-50 maintains superior dynamic performance with input frequencies up to 1/2 the clock frequency, achieving 6.8 effective bits with a 50 MHz sampling rate and 25 MHz input frequency. The analog signal at VIN that is within the voltage range set by VRT and VRB are digitized to eight bits at up to 55 MSPS. Input voltages below VRB will cause the output word to consist of all zeroes. Input voltages above VRT will cause the output word to consist of all ones. While the ADC1175-50 is optimized for top and bottom reference voltages (VRT and VRB) or 2.6V and 0.6V, respectively, and will give best performance at these values, VRT has a range of 1.0V to the analog supply voltage, AVDD, while VRB has a range of 0V to 4.0V. VRT should always be at least 1.0V more positive than VRB. With VRT voltages above 2.8V, it is necessary to reduce the clock frequency to maintain SINAD performance. If VRT and VRTS are connected together and VRB and VRBS are connected together, the nominal values of VRT and VRB www.national.com Applications Information 1.0 THE ANALOG INPUT The analog input of the ADC1175-50 is a switch followed by an integrator. The capacitance seen at the input changes with the clock level, appearing as 4 pF when the clock is low, 10 CLC409 has been found to be an excellent device for driving the ADC1175-50. Do not drive the input beyond the supply rails. Figure 3 gives an example of driving circuitry. (Continued) and 7 pF when the clock is high. Since a dynamic capacitance is more difficult to drive than is a fixed capacitance, choose an amplifier that can drive this type of load. The DS100896-25 FIGURE 3. Driving the ADC1175-50. Choose an op-amp that can drive a dynamic capacitance. 2.0 REFERENCE INPUTS The reference inputs VRT (Reference Top) and VRB (Reference Bottom) are the top and bottom of the reference ladder. Input signals between these two voltages will be digitized to 8 bits. External voltages applied to the reference input pins should be within the range specified in the Electrical Characteristics table (1.0V to AVDD for VRT and 0V to (AVDD − 1.0V) for VRB). Any device used to drive the reference pins should be able to source sufficient current into the VRT pin and sink sufficient current from the VRB pin. The reference ladder can be self-biased by connecting VRT to VRTS and connecting the VRB to VRBS to provide top and bottom reference voltages of approximately 2.6V and 0.6V, respectively, with VCC = 5.0V. This connection is shown in Figure 3. If VRT and VRTS are tied together, but VRB is tied to analog ground, a top reference voltage of approximately 2.3V is generated. The top and bottom of the ladder should be bypassed with 10 µF tantalum capacitors located close to the reference pins. The reference self-bias circuit of Figure 3 is very simple and the performance is adequate for many applications. Better linearity performance can generally be achieved by driving the reference pins with a low impedance source. By forcing a little current into or out of the top and bottom of the ladder, as shown in Figure 4, the top and bottom reference voltages can be trimmed and performance improved over the self-bias method of Figure 3. The resistive divider at the amplifier inputs can be replaced with potentiometers, if desired. The LMC662 amplifier shown was chosen for its low offset voltage and low cost. Note that a negative power supply is needed for these amplifiers as the lower one may be required to go slightly negative to force the required reference voltage. If reference voltages are desired that are more than a few tens of millivolts from the self-bias values, the circuit of Figure 5 will allow forcing the reference voltages to whatever levels are desired. This circuit provides the best performance because of the low source impedance of the transistors. Note that the VRTS and VRBS pins are left floating. To minimize noise effects and ensure accurate conversions, the total reference voltage range (VRT − VRB) should be a minimum of 1.0V and a maximum of about 2.8V. The ADC1175-50 is designed to operate with top and bottom references of 2.6V and 0.6V, respectively. However, it will function with reduced performance with a top reference voltage as high as AVDD. 11 www.national.com ADC1175-50 Applications Information ADC1175-50 Applications Information (Continued) DS100896-26 FIGURE 4. Better Defining the ADC Reference Voltage. Self bias is still used, but the reference voltages are trimmed by providing a small trim current with the operational amplifiers. www.national.com 12 ADC1175-50 Applications Information (Continued) DS100896-27 FIGURE 5. Driving the Reference to Force Desired Values requires driving with a low impedance source, provided by the transistors. Note that pins 16 and 22 are not connected. 3.0 OUTPUT DATA TIMING The Output Delay (tOD) of the ADC1175-50 can be very close to one half clock cycle. Because of this, the output data transition occurs very near the falling edge of the ADC clock. To avoid clocking errors, you should use the rising edge of the ADC clock to latch the output data of the ADC1175-50 and not use the falling edge. As with all high speed converters, the ADC1175-50 should be assumed to have little a.c. power supply rejection, especially when self biasing is used by connecting VRT and VRTS together. No pin should ever have a voltage on it that is in excess of the supply voltage or below ground, not even on a transient basis. This can be a problem upon application of power to a circuit. Be sure that the supplies to circuits driving the CLK, PD, analog input and reference pins do not come up any faster than does the voltage at the ADC1175-50 power pins. 4.0 POWER SUPPLY CONSIDERATIONS Many A/D converters draw sufficient transient current to corrupt their own power supplies if not adequately bypassed. A 10 µF tantalum or aluminum electrolytic capacitor should be placed within an inch (2.5 centimeters) of the A/D power pins, with a 0.1 µF ceramic chip capacitor placed as close as possible to the converter’s power supply pins. Leadless chip capacitors are preferred because they have low lead inductance. While a single voltage source should be used for the analog and digital supplies of the ADC1175-50, these supply pins should be isolated from each other to prevent any digital noise from being coupled to the analog power pins. We recommended a choke be used between the analog and digital supply lines, with a ceramic capacitor close to the analog supply pin. If a resistor is used in place of the choke, a maximum of 10Ω should be used. The converter digital supply should not be the supply that is used for other digital circuitry on the board. It should be the same supply used for the A/D analog supply. 5.0 THE ADC1175-50 CLOCK Although the ADC1175-50 is tested and its performance is guaranteed with a 50 MHz clock, it typically will function with clock frequencies from 1 MHz to 55 MHz. The clock should be one of low jitter and close to 50% duty cycle. 6.0 LAYOUT AND GROUNDING Proper grounding and proper routing of all signals is essential to ensure accurate conversion. Separate analog and digital ground planes that are connected beneath the ADC1175-50 are required to meet data sheet limits. The analog and digital grounds may be in the same layer, but should be separated from each other and should never overlap each other. Capacitive coupling between the typically noisy digital ground plane and the sensitive analog circuitry can lead to poor performance that may seem impossible to isolate and 13 www.national.com ADC1175-50 Applications Information (Continued) remedy. The solution is to keep the analog circuitry well separated from the digital circuitry and from the digital ground plane. Digital circuits create substantial supply and ground current transients. The logic noise thus generated could have significant impact upon system noise performance. The best logic family to use in systems with A/D converters is one which employs non-saturating transistor designs, or has low noise characteristics, such as the 74HC(T) and 74AC(T)Q families. The worst noise generators are logic families that draw the largest supply current transients during clock or signal edges, like the 74F and the 74AC(T) families. In general, slower logic families, such as 74LS and 74HC(T) will produce less high frequency noise than do high speed logic families, such as the 74F and 74AC(T) families. Since digital switching transients are composed largely of high frequency components, total ground plane copper weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area is more important than is total ground plane volume. An effective way to control ground noise is by connecting the analog and digital ground planes together beneath the ADC with a copper trace that is very narrow (about 1/16 inch) compared with the rest of the ground plane. This narrowing beneath the converter provides a fairly high impedance to the high frequency components of the digital switching currents, directing them away from the analog pins. The relatively lower frequency analog ground currents do not see a significant impedance across this narrow ground connection. Generally, analog and digital lines should cross each other at 90˚ to avoid getting digital noise into the analog path. In high frequency systems, however, avoid crossing analog and digital lines altogether. Clock lines should be isolated from ALL other lines, analog AND digital. Even the generally accepted 90˚ crossing should be avoided as even a little coupling can cause problems at high frequencies. Best performance at high frequencies and at high resolution is obtained with a straight signal path. Be especially careful with the layout of inductors. Mutual inductance can change the characteristics of the circuit in which they are used. Inductors should not be placed side by side with each other, not even with just a small part of their bodies beside each other. DS100896-28 FIGURE 6. Layout Example Showing Separate Analog and Digital Ground Planes Connected below the ADC1175-50 Figure 6 gives an example of a suitable layout. All analog circuitry (input amplifiers, filters, reference components, etc.) should be placed on or over the analog ground plane. All digital circuitry and I/O lines should be placed over the digital ground plane. 7.0 DYNAMIC PERFORMANCE The ADC1175-50 is ac tested and its dynamic performance is guaranteed. To meet the published specifications, the clock source driving the CLK input must be free of jitter. For best ac performance, isolating the ADC clock from any digital circuitry should be done with adequate buffers, as with a clock tree. See Figure 7. The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input. Any external component (e.g., a filter capacitor) connected between the converter’s input and ground should be connected to a very clean point in the analog ground plane. DS100896-29 FIGURE 7. Isolating the ADC Clock from Digital Circuitry It is good practice to keep the ADC clock line as short as possible and to keep it well away from any other signals. Other signals can introduce jitter into the clock signal. 8.0 COMMON APPLICATION PITFALLS Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should not go more than 50 mV below the ground pins or 50 mV above the www.national.com 14 are not driven with devices than can handle the required current, these reference pins will not be stable, resulting in a reduction of dynamic performance. (Continued) supply pins. Exceeding these limits on even a transient basis may cause faulty or erratic operation. It is not uncommon for high speed digital circuits (e.g., 74F and 74AC devices) to exhibit undershoot that goes more than a volt below ground. A resistor of about 50Ω to 100Ω in series with the offending digital input will usually eliminate the problem. Care should be taken not to overdrive the inputs of the ADC1175-50. Such practice may lead to conversion inaccuracies and even to device damage. Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers have to charge for each conversion, the more instantaneous digital current is required from DVDD and DGND. These large charging current spikes can couple into the analog section, degrading dynamic performance. Buffering the digital data outputs (with a 74ACQ541, for example) may be necessary if the data bus to be driven is heavily loaded. Dynamic performance can also be improved by adding 47Ω series resistors at each digital output, reducing the energy coupled back into the converter output pins. Using a clock source with excessive jitter, using excessively long clock signal trace, or having other signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive output noise and a reduction in SNR performance. Simple gates with RC timing is generally inadequate as a clock source. Input test signal contains harmonic distortion that interferes with the measurement of dynamic signal to noise ratio. Harmonic and other interfering signals can be removed by inserting a filter at the signal input. Suitable filters are shown in Figure 8 and Figure 9. The circuit of Figure 8 has a cutoff of about 5.5 MHz and is suitable for input frequencies of 1 MHz to 5 MHz. The circuit of Figure 9 has a cutoff of about 11 MHz and is suitable for input frequencies of 5 MHz to 10 MHz. These filters should be driven by a generator of 75Ω source impedance and terminated with a 75Ω resistor. Not considering the effect on a driven CMOS digital circuit(s) when the ADC1175-50 is in the power down mode. Because the ADC1175 output goes into a high impedance state when in the power down mode, any CMOS device connected to these outputs will have their inputs floating. Should the inputs float to a level near 2.5V, the CMOS device could exhibit relative large currents through its input stage. The solution is to use pull-down resistors. The value of these resistors is not critical, as long as they do not cause excessive currents in the outputs of the ADC1175-50. These currents could result in degraded SNR and SINAD performance of the ADC1175-50. Values between 5 kΩ and 100 kΩ should work well. Using an inadequate amplifier to drive the analog input. As explained in Section 1.0, the capacitance seen at the input alternates between 4 pF and 7 pF with the clock. This dynamic capacitance is more difficult to drive than is a fixed capacitance, and should be considered when choosing a driving device. The CLC409 has been found to be an excellent device for driving the ADC1175-50. Driving the VRT pin or the VRB pin with devices that can not source or sink the current required by the ladder. As mentioned in Section 2.0, care should be taken to see that any driving devices can source sufficient current into the VRT pin and sink sufficient current from the VRB pin. If these pins DS100896-30 FIGURE 8. 5.5 MHz Low Pass filter to eliminate harmonics at the signal input. Use at input frequencies of 1 MHz to 5 MHz. DS100896-31 FIGURE 9. 11 MHz Low Pass filter to eliminate harmonics at the signal input. Use at input frequencies of 5 MHz to 10 MHz 15 www.national.com ADC1175-50 Applications Information ADC1175-50 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Package JM Order Number ADC1175-50CIJM NS Package Number M24D www.national.com 16 ADC1175-50 8-Bit, 50 MSPS, 125 mW A/D Converter Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Package TC Order Number ADC1175-50CIMT NS Package Number MTC24 LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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