LM3671 2MHz , 600mA Step-Down DC-DC Converter in SOT23-5 General Description The LM3671 step-down DC-DC converter is optimized for powering ultra-low voltage circuits from a single Li-Ion cell or 3 cell NiMH/NiCd batteries. It provides up to 600mA load current, over an input voltage range from 2.8V to 5.5V. There are several different fixed voltage output options available as well as an adjustable output voltage version. The device offers superior features and performance for mobile phones and similar portable applications with complex power management systems. Automatic intelligent switching between PWM low-noise and PFM low-current mode offers improved system control. During full-power operation, a fixed-frequency 2 MHz (typ). PWM mode drives loads from ∼70 mA to 600 mA max. Hysteretic PFM mode extends the battery life through reduction of the quiescent current to 16 µA (typ) at light loads and system standby. Internal synchronous rectification provides high efficiency. In shutdown mode (Enable pin pulled low) the device turns off and reduces battery consumption to 0.01 µA (typ). The LM3671 is available in a SOT23-5 package with Pb and No Pb (Lead free) versions. A high switching frequency - 2 MHz (typ) - allows use of tiny surface-mount components. Only three external surface-mount components, an inductor and two ceramic capacitors, are required. 2 MHz PWM fixed switching frequency (typ) Automatic PFM/PWM mode switching Available in fixed output voltages and adjustable version SOT23-5 package Internal synchronous rectification for high efficiency Internal soft start 0.01 µA typical shutdown current Operates from a single Li-Ion cell or 3 cell NiMH/NiCd batteries n Only three tiny surface-mount external components required (one inductor, two ceramic capacitors) n Current overload and Thermal shutdown protection n n n n n n n n Applications n n n n n n n Mobile phones PDAs MP3 players W-LAN Portable instruments Digital still cameras Portable Hard disk drives Features n 16 µA typical quiescent current n 600 mA maximum load capability Typical Application Circuits 20108401 FIGURE 1. Typical Application Circuit © 2004 National Semiconductor Corporation DS201084 www.national.com LM3671 2MHz , 600mA Step-Down DC-DC Converter in SOT23-5 November 2004 LM3671 Typical Application Circuits (Continued) 20108431 FIGURE 2. Typical Application Circuit for ADJ version Connection Diagram and Package Mark Information SOT23-5 Package NS Package Number MF05A 20108402 Note: The actual physical placement of the package marking will vary from part to part. FIGURE 3. Top View Pin Description Pin # Name 1 VIN 2 GND 3 EN Enable pin. The device is in shutdown mode when voltage to this pin is < 0.4V and enabled when > 1.0V. Do not leave this pin floating. 4 FB Feedback analog input. Connect directly to the output filter capacitor for fixed voltage versions. For adjustable version external resistor dividers are required. The internal resistor dividers are disabled for the adjustable version. 5 SW Switching node connection to the internal PFET switch and NFET synchronous rectifier. www.national.com Description Power supply input. Connect to the input filter capacitor (Figure 1). Ground pin. 2 LM3671 Ordering Information Voltage Option ADJ* Order Number Spec LM3671MF-ADJ NOPB LM3671MFX-ADJ NOPB Package Marking SBTB LM3671MF-ADJ LM3671MFX-ADJ 1.2* 3000 units, Tape-and-Reel 1000 units, Tape-and-Reel LM3671MFX-1.2 NOPB 3000 units, Tape-and-Reel SBPB 3000 units, Tape-and-Reel NOPB 1000 units, Tape-and-Reel LM3671MFX-1.25 NOPB 3000 units, Tape-and-Reel SDRB LM3671MFX-1.25 LM3671MF-1.375 NOPB LM3671MFX-1.375 NOPB 1000 units, Tape-and-Reel SEDB LM3671MFX-1.375 NOPB 1000 units, Tape-and-Reel LM3671MFX-1.5 NOPB 1000 units, Tape-and-Reel SBRB LM3671MFX-1.5 3000 units, Tape-and-Reel 1000 units, Tape-and-Reel 3000 units, Tape-and-Reel LM3671MF-1.6 NOPB 1000 units, Tape-and-Reel LM3671MFX-1.6 NOPB 3000 units, Tape-and-Reel SDUB LM3671MF-1.6 LM3671MFX-1.6 1000 units, Tape-and-Reel 3000 units, Tape-and-Reel LM3671MF-1.8 NOPB 1000 units, Tape-and-Reel LM3671MFX-1.8 NOPB 3000 units, Tape-and-Reel SBSB LM3671MF-1.8 LM3671MFX-1.8 1.875 3000 units, Tape-and-Reel 3000 units, Tape-and-Reel LM3671MF-1.5 LM3671MF-1.5 1.8 1000 units, Tape-and-Reel 3000 units, Tape-and-Reel LM3671MF-1.375 1.6 1000 units, Tape-and-Reel LM3671MF-1.25 LM3671MF-1.25 1.5 1000 units, Tape-and-Reel NOPB LM3671MFX-1.2 1.375 3000 units, Tape-and-Reel LM3671MF-1.2 LM3671MF-1.2 1.25* Supplied As 1000 units, Tape-and-Reel 1000 units, Tape-and-Reel 3000 units, Tape-and-Reel LM3671MF-1.875 NOPB 1000 units, Tape-and-Reel LM3671MFX-1.875 NOPB 3000 units, Tape-and-Reel SDVB LM3671MF-1.875 LM3671MFX-1.875 1000 units, Tape-and-Reel 3000 units, Tape-and-Reel * ADJ, 1.2 and 1.25V to be released soon.Samples available now. 3 www.national.com LM3671 Absolute Maximum Ratings (Note 1) Human Body Model: EN 500V If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Machine Model: All Pins 200V VIN Pin: Voltage to GND Operating Ratings (Notes 1, 2) −0.2V to 6.0V FB, SW, EN Pin: Input Voltage Range (GND−0.2V) to (VIN + 0.2V) Continuous Power Dissipation (Note 3) Junction Temperature (TJ-MAX) 0mA to 600 mA Junction Temperature (TJ) Range Internally Limited −25˚C to +125˚C Ambient Temperature (TA) Range (Note 5) −25˚C to +85˚C +125˚C Storage Temperature Range −65˚C to +150˚C Maximum Lead Temperature (Soldering, 10 sec.) 260˚C Thermal Properties Junction-to-Ambient Thermal Resistance (θJA) (SOT23-5) (Note 6) ESD Rating (Note 4) Human Body Model: VIN,GND,SW,FB 2.8V to 5.5V Recommended Load Current 250˚C/W 2.0 kV Electrical Characteristics (Notes 2, 9, 10) Limits in standard typeface are for TJ = 25˚C. Limits in boldface type apply over the full operating junction temperature range (−25˚C ≤ TJ ≤ +125˚C). Unless otherwise noted, specifications apply to the LM3671 Typical Application Circuit (Figure. 1) with VIN = EN = 3.6V, VOUT = 1.5V Symbol Parameter Condition Min Typ Max Units VIN Input Voltage Range (Note 11) 2.8 5.5 V VOUT Output Voltage IO = 0 mA −2 +4 % IO = 100 mA −4 Line Regulation 2.8V ≤ VIN ≤ 5.5V IO = 10 mA 0.045 %/V Load Regulation 100 mA ≤ IO ≤ 300 mA VIN = 3.6V 0.0031 %/mA +4 % VREF Internal Reference Voltage (Note 7) 0.5 ISHDN Shutdown Supply Current EN = 0V 0.01 1 µA IQ_PFM DC Bias Current into VIN No load, device is not switching (FB forced higher than programmed output voltage) 16 35 µA RDSON (P) Pin-Pin Resistance for PFET VIN = VGS = 3.6V 380 500 mΩ RDSON (N) Pin-Pin Resistance for NFET VIN = VGS = 3.6V 250 400 mΩ ILIM Switch Peak Current Limit Open Loop (Note 8) 1020 1150 mA VIH Logic High Input VIL Logic Low Input IEN Enable (EN) Input Current FOSC Internal Oscillator Frequency 830 V 1.0 PWM Mode 1.6 V 0.4 V 0.01 1 µA 2 2.6 MHz Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: All voltages are with respect to the potential at the GND pin. Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 150˚C (typ.) and disengages at TJ = 130˚C (typ.). Note 4: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each pin. MIL-STD-883 3015.7 Note 5: In Applications where high power dissipation and/or poor package resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX), the maximum power dissipation of the device in the application (PD-MAX) and the junction to ambient thermal resistance of the package (θJA) in the application, as given by the following equation:TA-MAX = TJ-MAX− (θJAx PD-MAX). Refer to Dissipation rating table for PD-MAX values at different ambient temperatures. Note 6: Junction to ambient thermal resistance is highly application and board layout dependent. In applications where high power dissipation exists, special care must be given to thermal dissipation issues in board design. Value specified here 250 ˚C/W is based on measurement results using a 2 layer, 4" x 3", 2 oz Cu board as per JEDEC standards. The (θJA) can be as low as 140 ˚C/W if a 4 layer, 4" x 3", 2/1/1/2 oz. Cu board as per JEDEC standards is used. Note 7: For the ADJ version the resistor dividers should be selected such that at the desired output voltage,the voltage at the FB pin is 0.5V. www.national.com 4 Note 8: Refer to datasheet curves for closed loop data and its variation with regards to supply voltage and temperature. Electrical Characteristic table reflects open loop data (FB=0V and current drawn from SW pin ramped up until cycle by cycle current limit is activated). Closed loop current limit is the peak inductor current measured in the application circuit by increasing output current until output voltage drops by 10%. Note 9: Min and Max limits are guaranteed by design, test or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm. Note 10: The parameters in the electrical characteristic table are tested at VIN = 3.6V unless otherwise specified. For performance over the input voltage range refer to datasheet curves. Note 11: Input voltage range for all voltage options is 2.8V to 5.5V. The voltage range recommended (Fixed Voltage parts) for ideal applications performance with 500mA or higher output current is given below. VIN = 2.8V to 4.5V for VOUT = 1.2V, 1.25V, 1.375V, 1.5V and 1.6V. VIN = 3.0V to 4.5V for VOUT = 1.8V and 1.875V. Dissipation Rating Table θJA TA≤ 25˚C Power Rating TA = 60˚C Power Rating TA = 85˚C Power Rating 250˚C/W 400mW 260mW 160mW 5 www.national.com LM3671 Electrical Characteristics (Notes 2, 9, 10) Limits in standard typeface are for TJ = 25˚C. Limits in boldface type apply over the full operating junction temperature range (−25˚C ≤ TJ ≤ +125˚C). Unless otherwise noted, specifications apply to the LM3671 Typical Application Circuit (Figure. 1) with VIN = EN = 3.6V, VOUT = 1.5V (Continued) LM3671 20108418 FIGURE 4. Simplified Functional Diagram www.national.com 6 LM3671 Typical Performance Characteristics LM3671MF, Circuit of Figure 1, VIN = 3.6V, TA = 25˚C, unless otherwise noted. Quiescent Supply Current vs. Supply Voltage Shutdown Current vs. Temp 20108405 20108404 Output Voltage vs. Temperature (VOUT = 1.5V) Output Voltage vs. Supply Voltage (VOUT = 1.5V) 20108429 20108406 Output Voltage vs. Output Current (VOUT = 1.5V) RDS(ON) vs. Temperature 20108407 20108433 7 www.national.com LM3671 Typical Performance Characteristics (Continued) Efficiency vs. Output Current (VOUT = 1.8V, L= 2.2 µH) Efficiency vs. Output Current (VOUT = 1.5V, L= 2.2 µH) 20108408 20108409 Switching Frequency vs. Temperature Open/Closed Loop Current Limit vs. Temperature 20108410 20108430 Line Transient Response (PWM Mode) Load Transient Response (PWM Mode) 20108412 www.national.com 20108413 8 LM3671 Typical Performance Characteristics (Continued) Load Transient Response (PFM Mode 0.5mA to 50mA) Load Transient Response (PFM Mode 50mA to 0.5mA) 20108414 20108415 Mode Change by Load Transients (PFM to PWM) Mode Change by Load Transients (PWM to PFM) 20108420 20108421 Start Up into PWM Mode (Output Current= 300mA) Start Up into PFM Mode (Output Current= 1mA) 20108424 20108419 9 www.national.com LM3671 The current limit comparator can also turn off the switch in case the current limit of the PFET is exceeded. Then the NFET switch is turned on and the inductor current ramps down. The next cycle is initiated by the clock turning off the NFET and turning on the PFET. Operation Description DEVICE INFORMATION The LM3671, a high efficiency step down DC-DC switching buck converter, delivers a constant voltage from either a single Li-Ion or three cell NiMH/NiCd battery to portable devices such as cell phones and PDAs. Using a voltage mode architecture with synchronous rectification, the LM3671 has the ability to deliver up to 600 mA depending on the input voltage,output voltage, ambient temperature and the inductor chosen. There are three modes of operation depending on the current required - PWM, PFM, and shutdown. The device operates in PWM mode at load currents of approximately 80 mA or higher, having voltage tolerance of ± 4% with 90% efficiency or better. Lighter load currents cause the device to automatically switch into PFM for reduced current consumption (IQ = 16 µA typ) and a longer battery life. Shutdown mode turns off the device, offering the lowest current consumption (IQ, SHUTDOWN = 0.01 µA typ). Additional features include soft-start, under voltage protection, current overload protection, and thermal shutdown protection. As shown in Figure 1, only three external power components are required for implementation. The part uses an internal reference voltage of 0.5V. It is recommended to keep the part in shutdown until the input voltage is 2.8V or higher. 20108423 FIGURE 5. Typical PWM Operation Internal Synchronous Rectification While in PWM mode, the LM3671 uses an internal NFET as a synchronous rectifier to reduce rectifier forward voltage drop and associated power loss. Synchronous rectification provides a significant improvement in efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier diode. CIRCUIT OPERATION The LM3671 operates as follows. During the first portion of each switching cycle, the control block in the LM3671 turns on the internal PFET switch. This allows current to flow from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a ramp with a slope of (VIN–VOUT)/L, by storing energy in a magnetic field. During the second portion of each cycle, the controller turns the PFET switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor draws current from ground through the NFET to the output filter capacitor and load, which ramps the inductor current down with a slope of - VOUT/L. The output filter stores charge when the inductor current is high, and releases it when inductor current is low, smoothing the voltage across the load. The output voltage is regulated by modulating the PFET switch on time to control the average current sent to the load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and synchronous rectifier at the SW pin to a low-pass filter formed by the inductor and output filter capacitor. The output voltage is equal to the average voltage at the SW pin. Current Limiting A current limit feature allows the LM3671 to protect itself and external components during overload conditions. PWM mode implements current limiting using an internal comparator that trips at 1020 mA (typ). If the output is shorted to ground the device enters a timed current limit mode where the NFET is turned on for a longer duration until the inductor current falls below a low threshold, ensuring inductor current has more time to decay, thereby preventing runaway. PFM OPERATION At very light loads, the converter enters PFM mode and operates with reduced switching frequency and supply current to maintain high efficiency. The part will automatically transition into PFM mode when either of two conditions occurs for a duration of 32 or more clock cycles: A. The inductor current becomes discontinuous. B. The peak PMOS switch current drops below the IMODE level, (Typically IMODE < 30mA + VIN/42 Ω ). PWM OPERATION During PWM operation the converter operates as a voltagemode controller with input voltage feed forward. This allows the converter to achieve good load and line regulation. The DC gain of the power stage is proportional to the input voltage. To eliminate this dependence, feed forward inversely proportional to the input voltage is introduced. While in PWM (Pulse Width Modulation) mode, the output voltage is regulated by switching at a constant frequency and then modulating the energy per cycle to control power to the load. At the beginning of each clock cycle the PFET switch is turned on and the inductor current ramps up until the comparator trips and the control logic turns off the switch. www.national.com 10 switch is turned on. It remains on until the output voltage reaches the ‘high’ PFM threshold or the peak current exceeds the IPFM level set for PFM mode. The typical peak current in PFM mode is: IPFM = 112mA + VIN/27Ω . Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output voltage is below the ‘high’ PFM comparator threshold (see Figure 7), the PMOS switch is again turned on and the cycle is repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output switches are turned off and the part enters an extremely low power mode. Quiescent supply current during this ‘sleep’ mode is 16µA (typ), which allows the part to achieve high efficiencies under extremely light load conditions. When the output drops below the ‘low’ PFM threshold, the cycle repeats to restore the output voltage (average voltage in pfm mode) to ∼1.15% above the nominal PWM output voltage. If the load current should increase during PFM mode (see Figure 7) causing the output voltage to fall below the ‘low2’ PFM threshold, the part will automatically transition into fixed-frequency PWM mode. When VIN =2.8V the part transitions from PWM to PFM mode at ~35mA output current and from PFM to PWM mode at ~85mA , when VIN=3.6V, PWM to PFM transition happens at ~50mA and PFM to PWM transition happens at ~100mA, when VIN =4.5V, PWM to PFM transition happens at ~65mA and PFM to PWM transition happens at ~115mA. (Continued) 20108422 FIGURE 6. Typical PFM Operation During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output FETs such that the output voltage ramps between ~0.6% and ~1.7% above the nominal PWM output voltage. If the output voltage is below the ‘high’ PFM comparator threshold, the PMOS power 20108403 FIGURE 7. Operation in PFM Mode and Transfer to PWM Mode operation. While turning on the device with EN, soft start is activated. It is recommended to set EN pin low to turn off the LM3671 during system power up and undervoltage condi- SHUTDOWN MODE Setting the EN input pin low ( < 0.4V) places the LM3671 in shutdown mode. During shutdown the PFET switch, NFET switch, reference, control and bias circuitry of the LM3671 are turned off. Setting EN high ( > 1.0V) enables normal 11 www.national.com LM3671 Operation Description LM3671 Operation Description • R2: feedback resistor from FB to GND For any output voltage greater than or equal to 0.8V a zero must be added around 45 kHz for stability. The formula for calculation of C1 is: (Continued) tions when the supply is less than 2.8V. Do not leave the EN pin floating. Do not tie EN pin to VIN when powering up LM3671-ADJ (VOUT ≥ 2.5V) with a slow input supply ramp. SOFT START The LM3671 has a soft-start circuit that limits in-rush current during start-up. During start-up the switch current limit is increased in steps. Soft start is activated only if EN goes from logic low to logic high after Vin reaches 2.8V. Soft start is implemented by increasing switch current limit in steps of 70mA, 140mA, 280mA and 1020mA (typ. switch current limit). The start-up time thereby depends on the output capacitor and load current demanded at start-up. Typical start-up times with 22µF output capacitor and 300mA load current is 400 µs and with 1mA load current its 275µs. For output voltages between 0.7 and 0.8V and output voltages higher than 2.5V a pole must be placed at 45 kHz as well. The lowest output voltage possible is 0.7V. At low output voltages the duty cycle is very small; in addition as the input voltage increases the duty cycle decreases even further. Since the duty cycle is so low it is very susceptible to noise. C1 and C2 act as noise filters at this point rather than frequency poles and zeroes. If the pole and zero are at the same frequency the formula for calculation of C2 is: LDO - LOW DROP OUT OPERATION The LM3671-ADJ can operate at 100% duty cycle (no switching, PMOS switch completely on) for low drop out support of the output voltage. In this way the output voltage will be controlled down to the lowest possible input voltage. The minimum input voltage needed to support the output voltage is VIN, MIN = ILOAD * (RDSON, PFET + RINDUCTOR) + VOUT • ILOAD • RDSON, PFET Load current • RINDUCTOR Inductor resistance The formula for location of zero and pole frequency created by adding C1,C2 are given below. It can be seen that by adding C1, a zero as well as a higher frequency pole is introduced. Drain to source resistance of PFET switch in the triode region Application Information OUTPUT VOLTAGE SELECTION FOR LM3671-ADJ The output voltage of the adjustable parts can be programmed through the resistor network connected from VOUT to FB then to GND. VOUT will be adjusted to make the voltage at FB equal to 0.5V. The resistor from FB to GND (R2) should be 200 kΩ to keep the current drawn through this network well below the 16 µA quiescent current level (PFM mode) but large enough that it is not susceptible to noise. If R2 is 200 kΩ, and given the VFB is 0.5V, the current through the resistor feedback network will be 2.5 µA. The formula for output voltage selection is: See the "LM3671-ADJ configurations for various VOUT" table.These values are subject to change when the LM3671ADJ part is released. • VOUT: output voltage (volts) • VFB : feedback voltage = 0.5V • R1: feedback resistor from VOUT to FB www.national.com 12 LM3671 Application Information (Continued) LM3671-ADJ configurations for various VOUT VOUT(V) R1(kΩ) R2 (kΩ) C1 (pF) C2 (pF) L (µH) CIN (µF) COUT(µF) 0.7 54.9 137 68 27 2.2 10 22 0.8 118 196 33 none 2.2 10 22 0.9 162 200 22 none 2.2 10 22 1.0 200 200 18 none 2.2 10 22 1.1 191 158 18 none 2.2 10 22 1.2 280 200 12 none 2.2 10 22 1.5 360 180 10 none 2.2 10 22 1.6 442 200 8.2 none 2.2 10 22 1.7 432 180 8.2 none 2.2 10 22 1.875 523 191 6.8 none 2.2 10 22 2.5 402 100 8.2 none 2.2 10 22 3.3 562 100 6.8 33 2.2 10 22 INDUCTOR SELECTION tor’s resistance should be less than 0.3Ω for good efficiency. Table 1 lists suggested inductors and suppliers. For low-cost applications, an unshielded bobbin inductor could be considered. For noise critical applications, a toroidal or shieldedbobbin inductor should be used. A good practice is to lay out the board with overlapping footprints of both types for design flexibility. This allows substitution of a low-noise shielded inductor, in the event that noise from low-cost bobbin models is unacceptable. There are two main considerations when choosing an inductor; the inductor should not saturate, and the inductor current ripple is small enough to achieve the desired output voltage ripple. Different saturation current rating specs are followed by different manufacturers so attention must be given to details. Saturation current ratings are typically specified at 25˚C so ratings at max ambient temperature of application should be requested from manufacturer. There are two methods to choose the inductor saturation current rating. Method 1: The saturation current is greater than the sum of the maximum load current and the worst case average to peak inductor current. This can be written as • • • • INPUT CAPACITOR SELECTION A ceramic input capacitor of 10 µF, 6.3V is sufficient for most applications. Place the input capacitor as close as possible to the VIN pin of the device. A larger value may be used for improved input voltage filtering. Use X7R or X5R types, do not use Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. The input filter capacitor supplies current to the PFET switch of the LM3671 in the first half of each cycle and reduces voltage ripple imposed on the input power source. A ceramic capacitor’s low ESR provides the best noise filtering of the input voltage spikes due to this rapidly changing current. Select a capacitor with sufficient ripple current rating. The input current ripple can be calculated as: IRIPPLE: average to peak inductor current IOUTMAX: maximum load current (600mA) VIN: maximum input voltage in application L : min inductor value including worst case tolerances (30% drop can be considered for method 1) • f : minimum switching frequency (1.6Mhz) • VOUT: output voltage Method 2: A more conservative and recommended approach is to choose an inductor that has saturation current rating greater than the max current limit of 1150mA. A 2.2 µH inductor with a saturation current rating of at least 1150 mA is recommended for most applications.The induc- 13 www.national.com LM3671 Application Information (Continued) TABLE 1. Suggested Inductors and Their Suppliers Model Vendor Dimensions LxWxH(mm) D.C.R (max) DO3314-222MX Coilcraft 3.3 x 3.3 x 1.4 200 mΩ LPO3310-222MX Coilcraft 3.3 x 3.3 x 1.0 150 mΩ ELL5GM2R2N Panasonic 5.2 x 5.2 x 1.5 53 mΩ CDRH2D14-2R2 Sumida 3.2 x 3.2 x 1.55 94 mΩ OUTPUT CAPACITOR SELECTION Because these two components are out of phase the rms value can be used to get an approximate value of peak-topeak ripple. Use a 22 µF, 6.3V ceramic capacitor. Use X7R or X5R types, do not use Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. DC bias characteristics vary from manufacturer to manufacturer and dc bias curves should be requested from them as part of the capacitor selection process. The LM3671 has been evaluated with 22 µF, 6.3V, 0805 with worst case tolerances including dc bias effects. The use of two 10 µF, 6.3V, 0805 caps will give an overall higher capacitance value when dc bias is considered. Voltage peak-to-peak ripple, root mean squared can be expressed as follows Note that the output voltage ripple is dependent on the inductor current ripple and the equivalent series resistance of the output capacitor (RESR). The RESR is frequency dependent (as well as temperature dependent); make sure the value used for calculations is at the switching frequency of the part. The output filter capacitor smoothes out current flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR to perform these functions. The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its RESR and can be calculated as: Voltage peak-to-peak ripple due to capacitance can be expressed as follows Voltage peak-to-peak ripple due to ESR can be expressed as follows VPP-ESR = (2 * IRIPPLE) * RESR TABLE 2. Suggested Capacitors and Their Suppliers Type Vendor Voltage Rating Case Size Inch (mm) GRM21BR60J226K Ceramic, X5R Murata 6.3V 0805 (2012) C2012X5R0J226K Ceramic, X5R TDK 6.3V 0805 (2012) JMK212BJ226K Ceramic, X5R Taiyo-Yuden 6.3V 0805 (2012) 0805 (2012) Model 22 µF for COUT 10 µF for CIN GRM21BR60J106K Ceramic, X5R Murata 6.3V JMK212BJ106K Ceramic, X5R Taiyo-Yuden 6.3V 0805 (2012) C2012X5R0J106K Ceramic, X5R TDK 6.3V 0805 (2012) BOARD LAYOUT CONSIDERATIONS PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to www.national.com EMI, ground bounce, and resistive voltage loss in the traces. These can send erroneous signals to the DC-DC converter IC, resulting in poor regulation or instability. 14 LM3671 Application Information (Continued) 20108416 FIGURE 8. Board Layout Design Rules for the LM3671 Good layout for the LM3671 can be implemented by following a few simple design rules, as illustrated in Figure 8. 1. Place the LM3671, inductor and filter capacitors close together and make the traces short. The traces between these components carry relatively high switching currents and act as antennas. Following this rule reduces radiated noise. Special care must be given to place the input filter capacitor very close to the VIN and GND pin. 2. Arrange the components so that the switching current loops curl in the same direction. During the first half of each cycle, current flows from the input filter capacitor through the LM3671 and inductor to the output filter capacitor and back through ground, forming a current loop. In the second half of each cycle, current is pulled up from ground through the LM3671 by the inductor to the output filter capacitor and then back through ground forming a second current loop. Routing these loops so the current curls in the same direction prevents magnetic field reversal between the two half-cycles and reduces radiated noise. 3. Connect the ground pins of the LM3671 and filter capacitors together using generous component-side copper fill as a pseudo-ground plane. Then, connect this to the ground-plane (if one is used) with several vias. This reduces ground-plane noise by preventing the switching currents from circulating through the ground plane. It also reduces ground bounce at the LM3671 by giving it a low-impedance ground connection. 4. Use wide traces between the power components and for power connections to the DC-DC converter circuit. This reduces voltage errors caused by resistive losses across the traces. 5. Route noise sensitive traces, such as the voltage feedback path, away from noisy traces between the power components. The voltage feedback trace must remain close to the LM3671 circuit and should be direct but should be routed opposite to noisy components. This reduces EMI radiated onto the DC-DC converter’s own voltage feedback trace. A good approach is to route the feedback trace on another layer and to have a ground plane between the top layer and layer on which the feedback trace is routed. In the same manner for the adjustable part it is desired to have the feedback dividers on the bottom layer. 6. Place noise sensitive circuitry, such as radio IF blocks, away from the DC-DC converter, CMOS digital blocks and other noisy circuitry. Interference with noisesensitive circuitry in the system can be reduced through distance. In mobile phones, for example, a common practice is to place the DC-DC converter on one corner of the board, arrange the CMOS digital circuitry around it (since this also generates noise), and then place sensitive preamplifiers and IF stages on the diagonally opposing corner. Often, the sensitive circuitry is shielded with a metal pan and power to it is post-regulated to reduce conducted noise, using lowdropout linear regulators. 15 www.national.com LM3671 2MHz , 600mA Step-Down DC-DC Converter in SOT23-5 Physical Dimensions inches (millimeters) unless otherwise noted 5-Lead SOT23-5 Package NS Package Number MF05A National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. 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