ADC12062
12-Bit, 1 MHz, 75 mW A/D Converter
with Input Multiplexer and Sample/Hold
General Description
Features
Using an innovative multistep conversion technique, the
12-bit ADC12062 CMOS analog-to-digital converter digitizes
signals at a 1 MHz sampling rate while consuming a maximum of only 75 mW on a single a 5V supply. The
ADC12062 performs a 12-bit conversion in three lower-resolution ‘‘flash’’ conversions, yielding a fast A/D without the
cost and power dissipation associated with true flash approaches.
The analog input voltage to the ADC12062 is tracked and
held by an internal sampling circuit, allowing high frequency
input signals to be accurately digitized without the need for
an external sample-and-hold circuit. The multiplexer output
is available to the user in order to perform additional external signal processing before the signal is digitized.
When the converter is not digitizing signals, it can be placed
in the Standby mode; typical power consumption in this
mode is 100 mW.
Y
Y
Y
Y
Built-in sample-and-hold
Single a 5V supply
Single channel or 2 channel multiplexer operation
Low Power Standby mode
Key Specifications
Y
Y
Y
Y
Y
Sampling rate
Conversion time
Signal-to-Noise Ratio, fIN e 100 kHz
Power dissipation (fs e 1 MHz)
No missing codes over temperature
1 MHz (min)
740 ns (typ)
69.5 dB (min)
75 mW (max)
Guaranteed
Applications
Y
Y
Y
Y
Y
Digital signal processor front ends
Instrumentation
Disk drives
Mobile telecommunications
Waveform digitizers
Block Diagram
TL/H/11490 – 1
Ordering Information
Industrial (b40§ C s TA s a 85§ )
Package
ADC12062BIV
V44 Plastic Leaded Chip Carrier
ADC12062BIVF
VGZ44A Plastic Quad Flat Package
ADC12062CIV
V44 Plastic Leaded Chip Carrier
ADC12062CIVF
VGZ44A Plastic Quad Flat Package
ADC12062EVAL
Evaluation Board
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation
TL/H/11490
RRD-B30M75/Printed in U. S. A.
ADC12062 12-Bit, 1 MHz, 75 mW A/D Converter
with Input Multiplexer and Sample/Hold
December 1994
Absolute Maximum Ratings (Notes 1, 2)
Soldering Information (Note 6)
V Package, Infrared, 15 seconds
VF Package
Vapor Phase (60 seconds)
Infrared (15 seconds)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VCC e DVCC e AVCC)
Voltage at Any Input or Output
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Power Dissipation (Note 4)
ESD Susceptibility (Note 5)
b 0.3V to a 6V
b 0.3V to VCC a 0.3V
a 300§ C
a 215§ C
a 220§ C
b 65§ C to a 150§ C
Storage Temperature Range
Maximum Junction Temperature (TJMAX)
150§ C
25 mA
50 mA
875 mW
2000V
Operating Ratings (Notes 1, 2)
Temperature Range
TMIN s TA s TMAX
ADC12062BIV, ADC12062CIV,
ADC12062BIVF, ADC12062CIVF b40§ C s TA s a 85§ C
Supply Voltage Range (DVCC e AVCC)
4.5V to 5.5V
Converter Characteristics
The following specifications apply for DVCC e AVCC e a 5V, VREF a (SENSE) e
a 4.096V, VREF b (SENSE) e AGND, and fs e 1 MHz, unless otherwise specified. Boldface limits apply for TA e TJ from
TMIN to TMAX; all other limits TA e TJ e a 25§ C.
Symbol
Parameter
Conditions
Typ
(Note 7)
Limit
(Note 8)
12
Bits
g 0.8
Resolution
Units
(Limit)
Differential Linearity Error
TA e 25§ C
TMIN to TMAX
g 0.4
g 0.95
LSB (max)
LSB (max)
Integral Linearity Error
(Note 9)
TMIN to TMAX (BIV Suffix)
g 0.4
g 1.0
LSB (max)
TA e a 25§ C (CIV Suffix)
TMIN to TMAX (CIV Suffix)
g 0.4
g 1.0
g 1.5
LSB (max)
LSB (max)
Offset Error
Full Scale Error
Power Supply Sensitivity
(Note 15)
TMIN to TMAX (BIV Suffix)
g 0.3
g 1.25
LSB (max)
TA e a 25§ C (CIV Suffix)
TMIN to TMAX (CIV Suffix)
g 0.3
g 1.25
g 2.0
LSB (max)
LSB (max)
TMIN to TMAX (BIV Suffix)
g 0.2
g 1.0
LSB (max)
TA e a 25§ C (CIV Suffix)
TMIN to TMAX (CIV Suffix)
g 0.2
g 1.0
g 1.5
LSB (max)
LSB (max)
g 1.0
LSB (max)
500
1000
X (min)
X (max)
DVCC e AVCC e 5V g 10%
RREF
Reference Resistance
VREF( a )
VREF a (SENSE) Input Voltage
AVCC
V (max)
VREF(b)
VREFb(SENSE) Input Voltage
AGND
V (min)
AVCC a 0.05V
AGND b 0.05V
V (max)
V (min)
3
mA (max)
VIN
CADC
CMUX
750
Input Voltage Range
To VIN1, VIN2, or ADC IN
ADC IN Input Leakage
AGND to AVCC b 0.3V
0.1
MUX On-Channel Leakage
AGND to AVCC b 0.3V
0.1
3
mA (max)
MUX Off-Channel Leakage
AGND to AVCC b 0.3V
0.1
3
mA (max)
ADC IN Input Capacitance
25
Multiplexer Input Cap
MUX Off Isolation
fIN e 100 kHz
2
pF
7
pF
92
dB
Dynamic Characteristics (Note 10) The following specifications apply for DVCC e AVCC e a 5V,
VREF a (SENSE) e a 4.096V, VREFb(SENSE) e AGND, RS e 25X, fIN e 100 kHz, 0 dB from fullscale, and fs e 1 MHz, unless
otherwise specified. Boldface limits apply for TA e TJ from TMIN to TMAX; all other limits TA e TJ e a 25§ C.
Symbol
Parameter
Conditions
Typ
(Note 7)
Limit
(Note 8)
Units
(Limit)
SINAD
Signal-to-Noise Plus
Distortion Ratio
TMIN to TMAX
71
68.0
dB (min)
SNR
Signal-to-Noise Ratio
(Note 11)
TMIN to TMAX
72
69.5
dB (min)
THD
Total Harmonic Distortion
(Note 12)
TA e a 25§ C
TMIN to TMAX
b 82
b 74
b 70
dBc (max)
dBc (max)
ENOB
Effective Number of Bits
(Note 13)
TMIN to TMAX
11.5
11.0
Bits (min)
IMD
Intermodulation Distortion
fIN e 102.3 kHz, 102.7 kHz
b 80
dBc
DC Electrical Characteristics The following specifications apply for DVCC e AVCC e a 5V,
VREF a (SENSE) e a 4.096V, VREFb(SENSE) e AGND, and fs e 1 MHz, unless otherwise specified. Boldface limits apply
for TA e TJ from TMIN to TMAX; all other limits TA e TJ e a 25§ C.
Symbol
Parameter
Conditions
Typ
(Note 7)
Limit
(Note 8)
Units
(Limit)
VIN(1)
Logical ‘‘1’’ Input Voltage
DVCC e AVCC e a 5.5V
2.0
V (min)
VIN(0)
Logical ‘‘0’’ Input Voltage
DVCC e AVCC e a 4.5V
0.8
V (max)
IIN(1)
Logical ‘‘1’’ Input Current
0.1
1.0
mA (max)
IIN(0)
Logical ‘‘0’’ Input Current
0.1
1.0
mA (max)
VOUT(1)
Logical ‘‘1’’ Output Voltage
2.4
4.25
V (min)
V (min)
0.4
V (max)
3
mA (max)
DVCC e AVCC e a 4.5V,
IOUT e b360 mA
IOUT e b100 mA
VOUT(0)
Logical ‘‘0’’ Output Voltage
DVCC e AVCC e a 4.5V,
IOUT e 1.6 mA
IOUT
TRI-STATEÉ Output
Leakage Current
Pins DB0 – DB11
COUT
TRI-STATE Output Capacitance
Pins DB0 – DB11
5
pF
CIN
Digital Input Capacitance
4
pF
DICC
DVCC Supply Current
2
3
mA (max)
AICC
AVCC Supply Current
10
12
mA (max)
ISTANDBY
Standby Current (DICC a AICC)
PD e 0V
3
0.1
20
mA
AC Electrical Characteristics The following specifications apply for DVCC e AVCC e a 5V,
VREF a (SENSE) e a 4.096V, VREFb(SENSE) e AGND, and fs e 1 MHz, unless otherwise specified. Boldface limits apply
for TA e TJ from TMIN to TMAX; all other limits TA e TJ e a 25§ C.
Symbol
Parameter
fs
Maximum Sampling Rate
(1/tTHROUGHPUT)
tCONV
Conversion Time
(S/H Low to EOC High)
tAD
Aperture Delay
(S/H Low to Input Voltage Held)
tS/H
S/H Pulse Width
tEOC
S/H Low to EOC Low
tACC
Access Time
(RD Low or OE High to Data Valid)
t1H, t0H
Conditions
Typ
(Note 7)
740
Limit
(Note 8)
Units
(Limits)
1
MHz (min)
600
980
ns (min)
ns (max)
20
ns
5
550
ns (min)
ns (max)
95
60
125
ns (min)
ns (max)
CL e 100 pF
10
20
ns (max)
TRI-STATE Control
(RD High or OE Low to Databus TRI-STATE)
RL e 1k, CL e 10 pF
25
40
ns (max)
tINTH
Delay from RD Low to INT High
CL e 100 pF
35
60
ns (max)
tINTL
Delay from EOC High to INT Low
CL e 100 pF
b 25
b 35
b 10
ns (min)
ns (max)
tUPDATE
EOC High to New Data Valid
5
15
ns (max)
tMS
Multiplexer Address Setup Time
(MUX Address Valid to EOC Low)
50
ns (min)
tMH
Multiplexer Address Hold Time
(EOC Low to MUX Address Invalid)
50
ns (min)
tCSS
CS Setup Time
(CS Low to RD Low, S/H Low, or OE High)
20
ns (min)
tCSH
CS Hold Time
(CS High after RD High, S/H High, or OE Low)
20
ns (min)
tWU
Wake-Up Time
(PD High to First S/H Low)
1
ms
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional. These ratings do not guarantee specific performance limits, however. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under
the listed test conditions.
Note 2: All voltages are measured with respect to GND (GND e AGND e DGND), unless otherwise specified.
Note 3: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN k GND or VIN l VCC) the absolute value of current at that pin should be
limited to 25 mA or less. The 50 mA package input current limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to
two.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, iJA and the ambient temperature TA. The maximum
allowable power dissipation at any temperature is PD e (TJMAX b TA)/iJA or the number given in the Absolute Maximum Ratings, whichever is lower. iJA for the V
(PLCC) package is 55§ C/W. iJA for the VF (PQFP) package is 62§ C/W. In most cases the maximum derated power dissipation will be reached only during fault
conditions.
4
Note 5: Human body model, 100 pF discharged through a 1.5 kX resistor. Machine model ESD rating is 200V.
Note 6: See AN-450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ or the section titled ‘‘Surface Mount’’ found in a current National
Semiconductor Linear Data Book for other methods of soldering surface mount devices.
Note 7: Typicals are at a 25§ C and represent most likely parametric norm.
Note 8: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 9: Integral Linearity Error is the maximum deviation from a straight line between the measured offset and full scale endpoints.
Note 10: Dynamic testing of the ADC12062 is done using the ADC IN input. The input multiplexer adds harmonic distortion at high frequencies. See the graph in the
Typical Performance Characteristics section for a typical graph of THD performance vs input frequency with and without the input multiplexer.
Note 11: The signal-to-noise ratio is the ratio of the signal amplitude to the background noise level. Harmonics of the input signal are not included in its calculation.
Note 12: The contributions from the first nine harmonics are used in the calculation of the THD.
Note 13: Effective Number of Bits (ENOB) is calculated from the measured signal-to-noise plus distortion ratio (SINAD) using the equation ENOB e (SINAD b
1.76)/6.02.
Note 14: The digital power supply current takes up to 10 seconds to decay to its final value after PD is pulled low. This prohibits production testing of the standby
current. Some parts may exhibit significantly higher standby currents than the 20 mA typical.
Note 15: Power Supply Sensitivity is defined as the change in the Offset Error or the Full Scale Error due to a change in the supply voltage.
TRI-STATE Test Circuit and Waveforms
TL/H/11490 – 2
TL/H/11490 – 3
TL/H/11490 – 4
TL/H/11490 – 5
5
Typical Performance Characteristics
Offset and Fullscale
Error Change vs
Reference Voltage
Linearity Error Change
vs Reference Voltage
Mux ON Resistance vs
Input Voltage
Digital Supply Current
vs Temperature
Analog Supply Current
vs Temperature
Current Consumption in
Standby Mode vs Voltage
on Digital Input Pins
Conversion Time (tCONV)
vs Temperature
EOC Delay Time (tEOC)
vs Temperature
Spectral Response
SINAD vs Input Frequency
(ADC IN)
SNR vs Input Frequency
(ADC IN)
THD vs Input Frequency
(ADC IN)
TL/H/11490 – 27
6
Typical Performance Characteristics
SINAD vs Input Frequency
(Through Mux)
(Continued)
SNR vs Input Frequency
(Through Mux)
SNR and THD vs Source
Impedance
THD vs Input Frequency
(Through Mux)
SNR and THD vs
Reference Voltage
TL/H/11490 – 28
Timing Diagrams
TL/H/11490 – 9
FIGURE 1. Interrupt Interface Timing (MODE e 1, OE e 1)
7
Timing Diagrams (Continued)
TL/H/11490 – 10
FIGURE 2. High Speed Interface Timing (MODE e 1, OE e 1, CS e 0, RD e 0)
TL/H/11490 – 11
FIGURE 3. CS Setup and Hold Timing for S/H, RD, and OE
Connection Diagrams
TL/H/11490–13
TL/H/11490 – 29
Top View
Top View
8
Pin Descriptions
AVCC
DVCC
AGND,
DGND1,
DGND2
DB0 – DB11
VIN1, VIN2
MUX OUT
ADC IN
S0
These are the two positive analog supply
inputs. They should always be connected
to the same voltage source, but are
brought out separately to allow for separate bypass capacitors. Each supply pin
should be bypassed to AGND with a
0.1 mF ceramic capacitor in parallel with a
10 mF tantalum capacitor.
This is the positive digital supply input. It
should always be connected to the same
voltage as the analog supply, AVCC. It
should be bypassed to DGND2 with a
0.1 mF ceramic capacitor in parallel with a
10 mF tantalum capacitor.
These are the power supply ground pins.
There are separate analog and digital
ground pins for separate bypassing of the
analog and digital supplies. The ground
pins should be connected to a stable,
noise-free system ground. All of the
ground pins should be returned to the
same potential. AGND is the analog
ground for the converter. DGND1 is the
ground pin for the digital control lines.
DGND2 is the ground return for the output
databus. See Section 6.0 LAYOUT AND
GROUNDING for more information.
These are the TRI-STATE output pins, enabled by RD, CS, and OE.
These are the analog input pins to the multiplexer. For accurate conversions, no input pin (even one that is not selected)
should be driven more than 50 mV below
ground or 50 mV above VCC.
This is the output of the on-board analog
input multiplexer.
This is the direct input to the 12-bit sampling A/D converter. For accurate conversions, this pin should not be driven more
than 50 mV below AGND or 50 mV above
AVCC.
This pin selects the analog input that will
be connected to the ADC12062 during the
conversion. The input is selected based on
the state of S0 when EOC makes its highto-low transition. Low selects VIN1, high
selects VIN2.
MODE
This pin should be tied to DVCC.
CS
This is the active low Chip Select control
input. When low, this pin enables the RD,
S/H, and OE inputs. This pin can be tied
low.
INT
This is the active low Interrupt output.
When using the Interrupt Interface Mode
(Figure 1), this output goes low when a
conversion has been completed and indicates that the conversion result is available in the output latches. This output is
always high when RD is held low (Figure
2).
EOC
This is the End-of-Conversion control output. This output is low during a conversion.
RD
This is the active low Read control input.
When RD is low (and CS is low), the INT
output is reset and (if OE is high) data appears on the data bus. This pin can be tied
low.
This is the active high Output Enable control input. This pin can be thought of as an
inverted version of the RD input (see Figure 6 ). Data output pins DB0 – DB11 are
TRI-STATE when OE is low. Data appears
on DB0 – DB11 only when OE is high and
CS and RD are both low. This pin can be
tied high.
OE
S/H
This is the Sample/Hold control input. The
analog input signal is held and a new conversion is initiated by the falling edge of
this control input (when CS is low).
PD
This is the Power Down control input. This
pin should be held high for normal operation. When this pin is pulled low, the device
goes into a low power standby mode.
VREF a (FORCE), These are the positive and negative voltVREFb(FORCE) age reference force inputs, respectively.
See Section 4, REFERENCE INPUTS, for
more information.
VREF a (SENSE), These are the positive and negative voltVREFb(SENSE) age reference sense pins, respectively.
See Section 4, REFERENCE INPUTS, for
more information.
VREF/16
This pin should be bypassed to AGND with
a 0.1 mF ceramic capacitor.
TEST
This pin should be tied to DVCC.
9
Functional Description
The ADC12062 performs a 12-bit analog-to-digital conversion using a 3 step flash technique. The first flash determines the six most significant bits, the second flash generates four more bits, and the final flash resolves the two least
significant bits. Figure 4 shows the major functional blocks
of the converter. It consists of a 2(/2-bit Voltage Estimator, a
resistor ladder with two different resolution voltage spans, a
sample/hold capacitor, a 4-bit flash converter with front end
multiplexer, a digitally corrected DAC, and a capacitive voltage divider.
The resistor string near the center of the block diagram in
Figure 4 generates the 6-bit and 10-bit reference voltages
for the first two conversions. Each of the 16 resistors at the
bottom of the string is equal to (/1024 of the total string resistance. These resistors form the LSB Ladder* and have a
voltage drop of (/1024 of the total reference voltage (VREF a
b VREF b ) across each of them. The remaining resistors
form the MSB Ladder. It is comprised of eight groups of
eight resistors each connected in series (the lowest MSB
ladder resistor is actually the entire LSB ladder). Each MSB
Ladder section has (/8 of the total reference voltage across
it. Within a given MSB ladder section, each of the eight MSB
resistors has (/64 of the total reference voltage across it. Tap
points are found between all of the resistors in both the
MSB and LSB ladders. The Comparator MultipIexer can
connect any of these tap points, in two adjacent groups of
eight, to the sixteen comparators shown at the right of
Figure 4. This function provides the necessary reference
voltages to the comparators during the first two flash conversions.
The six comparators, seven-resistor string (Estimator DAC
ladder), and Estimator Decoder at the left of Figure 4 form
the Voltage Estimator. The Estimator DAC, connected between VREF a and VREFb, generates the reference voltages for the six Voltage Estimator comparators. The comparators perform a very low resoIution A/D conversion to
obtain an ‘‘estimate’’ of the input voltage. This estimate is
used to control the placement of the Comparator Multiplexer, connecting the appropriate MSB ladder section to the
sixteen flash comparators. A total of only 22 comparators (6
in the Voltage Estimator and 16 in the flash converter) is
required to quantize the input to 6 bits, instead of the 64 that
would be required using a traditional 6-bit flash.
Prior to a conversion, the Sample/Hold switch is closed,
allowing the voltage on the S/H capacitor to track the input
voItage. Switch 1 is in position 1. A conversion begins by
opening the Sample/Hold switch and latching the output of
the Voltage Estimator. The estimator decoder then selects
two adjacent banks of tap points aIong the MSB ladder.
These sixteen tap points are then connected to the sixteen
flash converters. For exampIe, if the input voltage is between ±/16 and -/16 of VREF (VREF e VREF a b VREFb), the
estimator decoder instructs the comparator multiplexer to
select the sixteen tap points between )/8 and %/8 (%/16 and
`/16) of VREF and connects them to the sixteen comparators.
The first flash conversion is now performed, producing the
first 6 MSBs of data.
At this point, Voltage Estimator errors as large as (/16 of
VREF will be corrected since the comparators are connected to ladder voltages that extend beyond the range specified by the Voltage Estimator. For example, if (-/16)VREF
k VIN k ('/16)VREF, the Voltage Estimator’s comparators
tied to the tap points below ('/16)VREF will output ‘‘1’’s
(000111). This is decoded by the estimator decoder to ‘‘10’’.
The 16 comparators will be placed on the MSB ladder
*Note: The weight of each resistor on the LSB ladder is actually equivalent
to four 12-bit LSBs. It is called the LSB ladder because it has the
highest resolution of all the ladders in the converter.
TL/H/11490 – 14
FIGURE 4. Functional Block Diagram
10
Functional Description (Continued)
tap points between (*/8)VREF and (±/8)VREF. This overlap of
((/16)VREF will automatically cancel a Voltage Estimator error of up to 256 LSBs. If the first flash conversion determines that the input voltage is between (*/8)VREF and
((%/8)VREF b LSB/2), the Voltage Estimator’s output code
will be corrected by subtracting ‘‘1’’, resulting in a corrected
value of ‘‘01’’ for the first two MSBs. If the first flash conversion determines that the input voltage is between (%/8)VREF
b LSB/2) and (±/8)VREF, the voltage estimator’s output
code is unchanged.
The results of the first flash and the Voltage Estimator’s
output are given to the factory-programmed on-chip
EEPROM which returns a correction code corresponding to
the error of the MSB ladder at that tap. This code is converted to a voltage by the Correction DAC. To generate the next
four bits, SW1 is moved to position 2, so the ladder voltage
and the correction voltage are subtracted from the input
voltage. The remainder is applied to the sixteen flash converters and compared with the 16 tap points from the LSB
ladder.
The result of this second conversion is accurate to 10 bits
and describes the input remainder as a voltage between two
tap points (VH and VL) on the LSB ladder. To resolve the
last two bits, the voltage across the ladder resistor (between
VH and VL) is divided up into 4 equal parts by the capacitive
voltage divider, shown in Figure 5. The divider also creates
6 LSBs below VL and 6 LSBs above VH to provide overlap
used by the digital error correction. SW1 is moved to position 3, and the remainder is compared with these 16 new
voltages. The output is combined with the results of the
Voltage Estimator, first flash, and second flash to yield the
final 12-bit result.
By using the same sixteen comparators for all three flash
conversions, the number of comparators needed by the
multi-step converter is significantly reduced when compared
to standard multi-step techniques.
Applications Information
1.0 MODES OF OPERATION
The ADC12062 has two interface modes: An interrupt/read
mode and a high speed mode. Figures 1 and 2 show the
timing diagrams for these interfaces.
In order to clearly show the relationship between S/H, CS,
RD, and OE, the control logic decoding section of the
ADC12062 is shown in Figure 6 .
Interrupt Interface
As shown in Figure 1, the falling edge of S/H holds the input
voltage and initiates a conversion. At the end of the conversion, the EOC output goes high and the INT output goes
low, indicating that the conversion results are latched and
may be read by pulling RD low. The falling edge of RD resets the INT line. Note that CS must be low to enable S/H
or RD.
High Speed Interface
This is the fastest interface, shown in Figure 2. Here the
output data is always present on the databus, and the INT to
RD delay is eliminated.
TL/H/11490 – 15
FIGURE 5. The Capacitive Voltage Divider
11
Applications Information (Continued)
TL/H/11490 – 16
FIGURE 6. ADC Control Logic
For maximum performance, the impedance of the source
driving the ADC12062 should be made as small as possible.
A source impedance of 100X or less is recommended. A
plot of dynamic performance vs. source impedance is given
in the Typical Performance Characteristics section.
If the signal source has a high output impedance, its output
should be buffered with an operational amplifier capable of
driving a switched 25 pF/100X load. Any ringing or instabilities at the op amp’s output during the sampling period can
result in conversion errors. The LM6361 high speed op amp
is a good choice for this application due to its speed and its
ability to drive large capacitive loads. Figure 8 shows the
LM6361 driving the ADC IN input of an ADC12062. The
100 pF capacitor at the input of the converter absorbs some
of the high frequency transients generated by the S/H
switching, reducing the op amp transient response requirements. The 100 pF capacitor should only be used with high
speed op amps that are unconditionally stable driving capacitive loads.
2.0 THE ANALOG INPUT
The analog input of the ADC12062 can be modeled as two
small resistances in series with the capacitance of the input
hold capacitor (CIN), as shown in Figure 7 . The S/H switch
is closed during the Sample period, and open during Hold.
The source has to charge CIN to the input voltage within the
sample period. Note that the source impedance of the input
voltage (RSOURCE) has a direct effect on the time it takes to
charge CIN. If RSOURCE is too large, the voltage across CIN
will not settle to within 0.5 LSBs of VSOURCE before the
conversion begins, and the conversion results will be incorrect. From a dynamic performance viewpoint, the combination of RSOURCE, RMUX, RSW, and CIN form a low pass
filter. Minimizing RSOURCE will increase the frequency response of the input stage of the converter.
Typical values for the components shown in Figure 7 are:
RMUX e 100X, RSW e 100X, and CIN e 25 pF. The settling time to n bits is:
tSETTLE e (RSOURCE a RMUX a RSW) * CIN * n * ln (2).
The bandwidth of the input circuit is:
fb3dB e 1/(2 * 3.14 * (RSOURCE a RMUX a RSW) * CIN)
TL/H/11490 – 17
FIGURE 7. Simplified ADC12062 Input Stage
12
Applications Information (Continued)
TL/H/11490 – 18
FIGURE 8. Buffering the Input with an LM6361 High Speed Op Amp
Another benefit of using a high speed buffer is improved
THD performance when using the multiplexer of the
ADC12062. The MUX on-resistance is somewhat non-linear
over input voltage, causing the RC time constant formed by
CIN, RMUX, and RSW to vary depending on the input voltage.
This results in increasing THD with increasing frequency.
Inserting the buffer between the MUX OUT and the ADC IN
terminals as shown in Figure 8 will eliminate the loading on
RMUX, significantly reducing the THD of the multiplexed system.
Correct converter operation will be obtained for input voltages greater than AGND b 50 mV and less than AVCC a
50 mV. Avoid driving the signal source more than 300 mV
higher than AVCC, or more than 300 mV below AGND. If an
analog input pin is forced beyond these voltages, the current flowing through that pin should be limited to 25 mA or
less to avoid permanent damage to the IC. The sum of all
the overdrive currents into all pins must be less than 50 mA.
When the input signal is expected to extend more than
300 mV beyond the power supply limits for any reason (unknown/uncontrollable input voltage range, power-on transients, fault conditions, etc.) some form of input protection,
such as that shown in Figure 9, should be used.
TL/H/11490 – 19
FIGURE 9. Input Protection
13
Applications Information (Continued)
signal is returned to the ADC IN input and digitized. If no
additional signal processing is required, the MUX OUT pin
should be tied directly to the ADC IN pin.
See Section 9.0 (APPLICATIONS) for a simple circuit that
will alternate between the two inputs while converting at full
speed.
3.0 ANALOG MULTIPLEXER
The ADC12062 has an input multiplexer that is controlled by
the logic level on pin S0 when EOC goes low, as shown in
Figures 1 and 2. Multiplexer setup and hold times with respect to the S/H input can be determined by these two
equations:
tMS (wrt S/H) e tMS b tEOC (min) e 50 b 60 e b10 ns
tMH (wrt S/H) e tMH a tEOC (max) e 50 a 125 e 175 ns
Note that tMS (wrt S/H) is a negative number; this indicates
that the data on S0 must become valid within 10 ns after
S/H goes low in order to meet the setup time requirements.
S0 must be valid for a length of
(tMH a tEOC (max)) b (tMS b tEOC (min)) e 185 ns.
4.0 REFERENCE INPUTS
In addition to the fully differential VREF a and VREFb reference inputs used on most National Semiconductor ADCs,
the ADC12062 has two sense outputs for precision control
of the ladder voltage. These sense inputs compensate for
errors due to IR drops between the reference source and
the ladder itself. The resistance of the reference ladder is
typically 750X. The parasitic resistance (RP) of the package
leads, bond wires, PCB traces, etc. can easily be 0.5X to
1.0X or more. This may not be significant at 8-bit or 10-bit
resolutions, but at 12 bits it can introduce voltage drops
causing offset and gain errors as large as 6 LSBs.
The ADC12062 provides a means to eliminate this error by
bringing out two additional pins that sense the exact voltage
at the top and bottom of the ladder. With the addition of two
op amps, the voltages on these internal nodes can be
forced to the exact value desired, as shown in Figure 10.
Table I shows how the input channels are assigned:
TABLE I. ADC12062 Input
Multiplexer Programming
S0
Channel
0
1
VIN1
VIN2
The output of the multiplexer is available to the user via the
MUX OUT pin. This output allows the user to perform additional signal processing, such as filtering or gain, before the
TL/H/11490 – 20
FIGURE 10. Reference Ladder Force and Sense Inputs
14
Applications Information (Continued)
The reference inputs are fully differential and define the
zero to full-scale range of the input signal. They can be
configured to span up to 5V (VREFb e 0V, VREF a e 5V),
or they can be connected to different voltages (within the
0V to 5V limits) when other input spans are required. The
ADC12062 is tested at VREFb (SENSE) e 0V, VREF a
(SENSE) e 4.096V. Reducing the reference voltage span to
less than 4V increases the sensitivity (reduces the LSB size)
of the converter; however noise performance degrades
when lower reference voltages are used. A plot of dynamic
performance vs reference voltage is given in the Typical
Performance Characteristics section.
If the converter will be used in an application where DC
accuracy is secondary to dynamic performance, then a simpler reference circuit may suffice. The circuit shown in Figure 11 will introduce several LSBs of offset and gain error,
but INL, DNL, and all dynamic specifications will be unaffected.
All bypass capacitors should be located as close to the
ADC12062 as possible to minimize noise on the reference
ladder. The VREF/16 output should be bypassed to analog
ground with a 0.1 mF ceramic capacitor.
The LM4040 shunt voltage reference is available with a
4.096V output voltage. With initial accuracies as low as
g 0.1%, it makes an excellent reference for the ADC12062.
Since the current flowing through the SENSE lines is essentially zero, there is negligible voltage drop across RS and the
1 kX resistor, so the voltage at the inverting input of the op
amp accurately represents the voltage at the top (or bottom) of the ladder. The op amp drives the FORCE input and
forces the voltage at the ends of the ladder to equal the
voltage at the op amps’s non-inverting input, plus or minus
its input offset voltage. For this reason op amps with low
VOS, such as the LM627 or LM607, should be used for this
application. When used in this configuration, the ADC12062
typically has less than 0.5 LSB of offset and gain error without any user adjustments.
The 0.1 mF and 10 mF capacitors on the force inputs provide high frequency decoupling of the reference ladder. The
500X force resistors isolate the op amps from this large
capacitive load. The 0.01 mF/1 kX network provides zero
phase shift at high frequencies to ensure stability. Note that
the op amp supplies in this example must be g 10V to
g 15V to meet the input/output voltage range requirements
of the LM627 and supply the sub-zero voltage to the
VREFb (FORCE) pin. The VREF/16 output should be bypassed to analog ground with a 0.1 mF ceramic capacitor.
TL/H/11490 – 21
FIGURE 11. Using the VREF Force Pins Only
15
Applications Information (Continued)
5.0 POWER SUPPLY CONSIDERATIONS
The ADC12062 is designed to operate from a single a 5V
power supply. There are two analog supply pins (AVCC) and
one digital supply pin (DVCC). These pins allow separate
external bypass capacitors for the analog and digital portions of the circuit. To guarantee proper operation of the
converter, all three supply pins should be connected to the
same voltage source. In systems with separate analog and
digital supplies, the converter should be powered from the
analog supply.
The ground pins are AGND (analog ground), DGND1 (digital
input ground), and DGND2 (digital output ground). These
pins allow for three separate ground planes for these sections of the chip. Isolating the analog section from the two
digital sections reduces digital interference in the analog circuitry, improving the dynamic performance of the converter.
Separating the digital outputs from the digital inputs (particularly the S/H input) reduces the possibility of ground bounce
from the 12 data lines causing jitter on the S/H input. The
analog ground plane should be connected to the Digital2
ground plane at the ground return for the power supply. The
Digital1 ground plane should be tied to the Digital2 ground
plane at the DGND1 and DGND2 pins.
Both AVCC pins should be bypassed to the AGND ground
plane with 0.1 mF ceramic capacitors. One of the two AVCC
pins should also be bypassed with a 10 mF tantalum capacitor. DVCC should be bypassed to the DGND2 ground pIane
with a 0.1 mF capacitor in parallel with a 10 mF tantalum
capacitor.
TL/H/11490 – 22
FIGURE 12. PC Board Layout
7.0 DYNAMIC PERFORMANCE
The ADC12062 is AC tested and its dynamic performance is
guaranteed. In order to meet these specifications, the clock
source driving the S/H input must be free of jitter. For the
best AC performance, a crystal oscillator is recommended.
For operation at or near the ADC12062’s 1 MHz maximum
sampling rate, a 1 MHz squarewave will provide a good signal for the S/H input. As long as the duty cycle is near 50%,
the waveform will be low for about 500 ns, which is within
the 550 ns limit. When operating the ADC12062 at a sample
rate of 910 kHz or below, the pulse width of the S/H signal
must be smaller than half the sample period.
6.0 LAYOUT AND GROUNDING
In order to ensure fast, accurate conversions from the
ADC12062, it is necessary to use appropriate circuit board
layout techniques. Separate analog and digital ground
planes are required to meet datasheet AC and DC limits.
The analog ground plane should be low-impedance and free
of noise from other parts of the system.
All bypass capacitors should be located as close to the converter as possible and should connect to the converter and
to ground with short traces. The analog input should be isolated from noisy signal traces to avoid having spurious signals couple to the input. Any external component (e.g., a
filter capacitor) connected across the converter’s input
should be connected to a very clean analog ground return
point. Grounding the component at the wrong point will result in increased noise and reduced conversion accuracy.
Figure 12 gives an example of a suitable layout, including
power supply routing, ground plane separation, and bypass
capacitor placement. All analog circuitry (input amplifiers,
filters, reference components, etc.) should be placed on the
analog ground plane. All digital circuitry and I/O lines (excluding the S/H input) should use the digital2 ground plane
as ground. The digital1 ground plane should only be used
for the S/H signal generation.
TL/H/11490 – 23
FIGURE 13. Crystal Clock Source
Figure 13 is an example of a low jitter S/H pulse generator
that can be used with the ADC12062 and allow operation at
sampling rates from DC to 1 MHz. A standard 4-pin DIP
crystal oscillator provides a stable 1 MHz squarewave.
Since most DIP oscillators have TTL outputs, a 4.7k pullup
resistor is used to raise the output high voltage to CMOS
input levels. The output is fed to the trigger input (falling
16
Applications Information (Continued)
converter is turned off, but other devices connected to it (op
amps, microprocessors) still have power. Note that if there
is no power to the converter, DGND e AGND e DVCC e
AVCC e 0V, so all inputs should be within g 300 mV of
AGND and DGND.
Driving a high capacitance digital data bus. The more
capacitance the data bus has to charge for each conversion, the more instantaneous digital current required from
DVCC and DGND. These large current spikes can couple
back to the analog section, decreasing the SNR of the converter. While adequate supply bypassing and separate analog and digital ground planes will reduce this problem, buffering the digital data outputs (with a pair of MM74HC541s,
for example) may be necessary if the converter must drive a
heavily loaded databus.
edge) of an MM74HC4538 one-shot. The 1k resistor and 12
pF capacitor set the pulse length to approximately 100 ns.
The S/H pulse stream for the converter appears on the Q
output of the HC4538. This is the S/H clock generator used
on the ADC12062EVAL evaluation board. For lower power,
a CMOS inverter-based crystal oscillator can be used in
place of the DIP crystal oscillator. See Application Note
AN-340 in the National Semiconductor CMOS Logic Databook for more information on CMOS crystal oscillators.
8.0 COMMON APPLICATION PITFALLS
Driving inputs (analog or digital) outside power supply
rails. The Absolute Maximum Ratings state that all inputs
must be between GND b 300 mV and VCC a 300 mV. This
rule is most often broken when the power supply to the
9.0 APPLICATIONS
2’s Complement Output
TL/H/11490 – 24
Ping-Ponging between VIN1 and VIN2
TL/H/11490 – 25
17
Applications Information (Continued)
AC Coupling Bipolar Inputs
TL/H/11490 – 26
18
Physical Dimensions inches (millimeters)
Plastic Leaded Chip Carrier (V)
Order Number ADC12062BIV, ADC12062CIV
NS Package Number V44A
19
ADC12062 12-Bit, 1 MHz, 75 mW A/D Converter
with Input Multiplexer and Sample/Hold
Physical Dimensions inches (millimeters) (Continued)
Plastic Quad Flat Package (VF)
Order Number ADC12062BIVF, ADC12062CIVF
NS Package Number VGZ44A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
National Semiconductor
Corporation
2900 Semiconductor Drive
P.O. Box 58090
Santa Clara, CA 95052-8090
Tel: 1(800) 272-9959
TWX: (910) 339-9240
National Semiconductor
GmbH
Livry-Gargan-Str. 10
D-82256 F4urstenfeldbruck
Germany
Tel: (81-41) 35-0
Telex: 527649
Fax: (81-41) 35-1
National Semiconductor
Japan Ltd.
Sumitomo Chemical
Engineering Center
Bldg. 7F
1-7-1, Nakase, Mihama-Ku
Chiba-City,
Ciba Prefecture 261
Tel: (043) 299-2300
Fax: (043) 299-2500
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
National Semiconductor
Hong Kong Ltd.
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
Hong Kong
Tel: (852) 2737-1600
Fax: (852) 2736-9960
National Semiconductores
Do Brazil Ltda.
Rue Deputado Lacorda Franco
120-3A
Sao Paulo-SP
Brazil 05418-000
Tel: (55-11) 212-5066
Telex: 391-1131931 NSBR BR
Fax: (55-11) 212-1181
National Semiconductor
(Australia) Pty, Ltd.
Building 16
Business Park Drive
Monash Business Park
Nottinghill, Melbourne
Victoria 3168 Australia
Tel: (3) 558-9999
Fax: (3) 558-9998
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.