SCANSTA112 7-port Multidrop IEEE 1149.1 (JTAG) Multiplexer General Description The SCANSTA112 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a multidrop approach over a single serial scan chain is improved test throughput and the ability to remove a board from the system and retain test access to the remaining modules. Each SCANSTA112 supports up to 7 local IEEE1149.1 scan chains which can be accessed individually or combined serially. Addressing is accomplished by loading the instruction register with a value matching that of the Slot inputs. Backplane and inter-board testing can easily be accomplished by parking the local TAP Controllers in one of the stable TAP Controller states via a Park instruction. The 32-bit TCK counter enables built in self test operations to be performed on one port while other scan chains are simultaneously tested. The STA112 has a unique feature in that the backplane port and the LSP0 port are bidirectional. They can be configured to alternatively act as the master or slave port so an alternate test master can take control of the entire scan chain network from the LSP0 port while the backplane port becomes a slave. Features n 7 IEEE 1149.1-compatible configurable local scan ports n Bi-directional Backplane and LSP0 ports are interchangeable slave ports n Capable of ignoring TRST of the backplane port when it becomes the slave. n Stitcher Mode bypasses level 1 and 2 protocols n Mode Register0 allows local TAPs to be bypassed, selected for insertion into the scan chain individually, or serially in groups of two or three n Transparent Mode can be enabled with a single instruction to conveniently buffer the backplane IEEE 1149.1 pins to those on a single local scan port n General purpose local port passthrough bits are useful for delivering write pulses for Flash programming or monitoring device status. n Known Power-up state n TRST on all local scan ports n 32-bit TCK counter n 16-bit LFSR Signature Compactor n Local TAPs can become TRI-STATE via the OE input to allow an alternate test master to take control of the local TAPs (LSP0-3 have a TRI-STATE notification output) n 3.0-3.6V VCC Supply Operation n Supports live insertion/withdrawal n True IEEE 1149.1 hierarchical and multidrop addressable capability n The 8 address inputs support up to 249 unique slot addresses, an Interrogation Address, Broadcast Address, and 4 Multi-cast Group Addresses (address 000000 is reserved) 20051250 FIGURE 1. Typical use of SCANSTA112 for board-level management of multiple scan chains. © 2004 National Semiconductor Corporation DS200512 www.national.com SCANSTA112 7-port Multidrop IEEE 1149.1 (JTAG) Multiplexer May 2004 SCANSTA112 20051251 FIGURE 2. Example of SCANSTA112 in a multidrop addressable backplane. Introduction Architecture The SCANSTA112 is the third device in a series that enable multi-drop address and multiplexing of IEEE-1149.1 scan chains. The SCANSTA112 is a superset of its predecessors - the SCANPSC110 and the SCANSTA111. The STA112 has all features and functionality of these two previous devices. The STA112 is essentially a support device for the IEEE 1149.1 standard. It is primarily used to partition scan chains into managable sizes, or to isolate specific devices onto a seperate chain (Figure 1). The benefits of multiple scan chains are improved fault isolation, faster test times, faster programiing times, and smaller vector sets. In addition to scan chain partitioning, the device is also addressable for use in a multidrop backplane environment (Figure 2). In this configuration, multiple IEEE-1149.1 accessible cards with an STA112 on board can utilize the same backplane test bus for system-level IEEE-1149.1 access. This approach facilitates a system-wide commitment to structural test and programming throughout the entire system life sycle. Figure 3 shows the basic architecture of the ’STA112. The device’s major functional blocks are illustrated here. www.national.com The TAP Controller, a 16-state state machine, is the central control for the device. The instruction register and various test data registers can be scanned to exercise the various functions of the ’STA112 (these registers behave as defined in IEEE Std. 1149.1). The ’STA112 selection controller provides the functionality that allows the 1149.1 protocol to be used in a multi-drop environment. It primarily compares the address input to the slot identification and enables the ’STA112 for subsequent scan operations. The Local Scan Port Network (LSPN) contains multiplexing logic used to select different port configurations. The LSPN control block contains the Local Scan Port Controllers (LSPC) for each Local Scan Port (LSP0, LSP1 ... LSPn). This control block receives input from the ’STA112 instruction register, mode registers, and the TAP controller. Each local port contains all four boundary scan signals needed to interface with the local TAPs plus the optional Test Reset signal (TRST). The TDI/TDO Crossover Master/Slave logic is used to define the bidirectional B0 and B1 ports in a Master/Slave configuration. 2 SCANSTA112 20051202 FIGURE 3. SCANSTA112 Block Diagram 3 www.national.com SCANSTA112 Connection Diagrams 20051201 (BGA Top view) www.national.com 4 SCANSTA112 Connection Diagrams (Continued) 20051260 TQFP pinout 5 www.national.com SCANSTA112 TABLE 1. Pin Descriptions No. Pins I/O VCC 10 N/A Power GND 10 N/A Ground Pin Name Description RESET 1 I RESET Input: will force a reset of the device regardless of the current state. ADDMASK 1 I ADDRESS MASK input: Allows masking of lower slot input pins. MPselB1/B0 1 I MASTER PORT SELECTION: Controls selection of LSPB0 or LSPB1 as the backplane port. The unselected port becomes LSP00. A value of "0" will select LSPB0 as the master port. SB/S 1 I Selects ScanBridge or Stitcher Mode. 7 I In Stitcher Mode these inputs define which LSP’s are to be included in the scan chain TRANS 1 I Transparent Mode enable input: The value of this pin is loaded into the TRANSENABLE bit of the control register at power-up. This value is used to control the presence of registers and pad-bits in the scan chain while in the stitcher mode. TLR_TRST 1 I Sets the driven value of TRST0-5 when LSP TAPs are in TLR and the device is not being reset. During RESET = "0" or TRSTB = "0" (IgnoreReset = "0") TRSTn = "0". This pin is to be tied low to match the function of the SCANSTA111 TLR_TRST6 1 I This pin affects TRST of LSP6 only. This pin is to be tied low to match the function of the SCANSTA111 TDIB0, TDIB1 2 I BACKPLANE TEST DATA INPUT: All backplane scan data is supplied to the ’STA112 through this input pin. MPselB1/B0 determines which port is the master backplane port and which is LSP00. This input has a 25KΩ internal pull-up resistor and no ESD clamp diode (ESD is controlled with an alternate method). When the device is power-off (VDD floating), this input appears to be a capacitive load to ground (Note 1). When VDD = 0V (i.e.; not floating but tied to VSS) this input appears to be a capacitive load with the pull-up to ground. TMSB0, TMSB1 2 I/O BACKPLANE TEST MODE SELECT: Controls sequencing through the TAP Controller of the ’STA112. Also controls sequencing of the TAPs which are on the local scan chains. MPselB1/B0 determines which port is the master backplane port and which is LSP00. This bidirectional TRISTATE pin has 24mA of drive current, with a 25KΩ internal pull-up resistor and no ESD clamp diode (ESD is controlled with an alternate method). When the device is power-off (VDD floating), this input appears to be a capacitive load to ground (Note 1). When VDD = 0V (i.e.; not floating but tied to VSS) this input appears to be a capacitive load with the pull-up to ground. TDOB0, TDOB1 2 I/O BACKPLANE TEST DATA OUTPUT: This output drives test data from the ’STA112 and the local TAPs, back toward the scan master controller. This bidirectional TRISTATE pin has 12mA of drive current. MPselB1/B0 determines which port is the master backplane port and which is LSP00. Output is sampled during interrogation addressing. When the device is power-off (VDD = 0V or floating), this output appears to be a capacitive load (Note 1). TCKB0, TCKB1 2 I/O TEST CLOCK INPUT FROM THE BACKPLANE: This is the master clock signal that controls all scan operations of the ’STA112 and of the local scan ports. MPselB1/B0 determines which port is the master backplane port and which is LSP00. These bidirectional TRISTATE pins have 24mA of drive current with hysterisis. This input has no pull-up resistor and no ESD clamp diode (ESD is controlled with an alternate method). When the device is power-off (VDD floating), this input appears to be a capacitive load to ground (Note 1). When VDD = 0V (i.e.; not floating but tied to VSS) this input appears to be a capacitive load to ground. TRSTB0, TRSTB1 2 I/O TEST RESET: An asynchronous reset signal (active low) which initializes the ’STA112 logic. MPselB1/B0 determines which port is the master backplane port and which is LSP00. This bidirectional TRISTATE pin has 24mA of drive current, with a 25KΩ internal pull-up resistor and no ESD clamp diode (ESD is controlled with an alternate method). When the device is power-off (VDD floating), this pin appears to be a capacitive load to ground (Note 1). When VDD = 0V (i.e.; not floating but tied to VSS) this input appears to be a capacitive load with the pull-up to ground. LSPsel (0-6) www.national.com 6 SCANSTA112 TABLE 1. Pin Descriptions (Continued) Pin Name No. Pins I/O Description TRISTB0, TRISTB1 2 O BACKPLANE TRI-STATE NOTIFICATION OUTPUT: This signal is high when the backplane scan port is TRI-STATEd. This pin is used for backplane physical layer changes (i.e.; TTL to LVDS). This TRISTATE output has 12mA of drive current. MPselB1/B0 determines which port is the master backplane port and which is LSP00. A0B0, A1B0, A0B1, A1B1 4 I BACKPLANE PASS-THROUGH INPUT: A general purpose input which is driven to the Yn of a single selected LSP. (Not available when multiple LSPs are selected). This input has a 25KΩ internal pull-up resistor. MPselB1/B0 determines which port is the master backplane port and which is LSP00. Y0B0, Y1B0, Y0B1, Y1B1 4 O BACKPLANE PASS-THROUGH OUTPUT: A general purpose output which is driven from the An of a single selected LSP. (Not available when multiple LSPs are selected). This TRISTATE output has 12mA of drive current. MPselB1/B0 determines which port is the master backplane port and which is LSP00. S(0-7) 8 I SLOT IDENTIFICATION: The configuration of these pins is used to identify (assign a unique address to) each ’STA112 on the system backplane OE 1 I OUTPUT ENABLE for the Local Scan Ports, active low. When high, this active-low control signal TRI-STATEs all local scan ports on the ’STA112, to enable an alternate resource to access one or more of the local scan chains. TDO(01-06) 6 O TEST DATA OUTPUTS: Individual output for each of the local scan ports . These TRISTATE outputs have 12mA of drive current. TDI(01-06) 6 I TEST DATA INPUTS: Individual scan data input for each of the local scan ports. This input has a 25KΩ internal pull-up resistor. TMS(01-06) 6 O TEST MODE SELECT OUTPUTS: Individual output for each of the local scan ports. TMSn does not provide a pull-up resistor (which is assumed to be present on a connected TMS input, per the IEEE 1149.1 requirement) . These TRISTATE outputs have 24mA of drive current. TCK(01-06) 6 O LOCAL TEST CLOCK OUTPUTS: Individual output for each of the local scan ports. These are buffered versions of TCKB . These TRISTATE outputs have 24mA of drive current. TRST(01-06) 6 O LOCAL TEST RESETS: A gated version of TRSTB. These TRISTATE outputs have 24mA of drive current. A001, A101 2 I LOCAL PASS-THROUGH INPUTS: General purpose inputs which can be driven to the backplane pin YB. (Only on LSP0 and LSP1. Only available when a single LSP is selected) . These inputs have a 25KΩ internal pull-up resistor. Y001, Y101 2 O LOCAL PASS-THROUGH OUTPUT: General purpose outputs which can be driven from the backplane pin AB. (Only on LSP0 and LSP1. Only available when a single LSP is selected) . These TRISTATE outputs have 12mA of drive current. TRIST(01-03) 3 O LOCAL TRI-STATE NOTIFICATION OUTPUTS: This signal is high when the local scan ports are TRI-STATEd . These pins are used for backplane physical layer changes (i.e.; TTL to LVDS). These TRISTATE outputs have 12mA of drive current. Note 1: Refer to the IBIS model on our website for I/O characteristics. capability. First, a test controller can select individual ’STA112s, specific sets of ’STA112s (multi-cast groups), or all ’STA112s (broadcast). This ’STA112-selection process is supported by a Level-1 communication protocol. Second, within each selected ’STA112, a test controller can select one or more of the chip’s seven local scan-ports. That is, individual local ports can be selected for inclusion in the (single) scan-chain which a ’STA112 presents to the test controller. This mechanism allows a controller to select specific scan-chains within the overall scan network. The portselection process is supported by a Level-2 protocol. HIERARCHICAL SUPPORT - Multiple SCANSTA112’s can be used to assemble a hierarchical boundary-scan tree. In Application Overview ADDRESSING SCHEME - The SCANSTA112 architecture extends the functionality of the IEEE 1149.1 Standard by supplementing that protocol with an addressing scheme which allows a test controller to communicate with specific ’STA112s within a network of ’STA112s. That network can include both multi-drop and hierarchical connectivity. In effect, the ’STA112 architecture allows a test controller to dynamically select specific portions of such a network for participation in scan operations. This allows a complex system to be partitioned into smaller blocks for testing purposes. The ’STA112 provides two levels of test-network partitioning 7 www.national.com SCANSTA112 Application Overview refers to the required actions to address/select the desired ScanBridge. Level 2 protocol is required to configuring the mux’ing function and enable the connection (UNPARK) between the local scan chain and the backplane bus via an LSP. Upon completion of level 1 and 2 protocols the ScanBridge is prepared for its operational mode. This is where scan vectors are moved from the backplane bus to the desired local scan chain(s). STITCHER MODE - Stitcher Mode is a method of skipping level 1 and 2 protocol of the ScanBridge mode of operation. This is accomplished via external pins. When in stitcher mode the SCANSTA112 will go directly to the operational mode. (Continued) such a configuration, the system tester can configure the local ports of a set of ’STA112s so as to connect a specific set of local scan-chains to the active scan chain. Using this capability, the tester can selectively communicate with specific portions of a target system. The tester’s scan port is connected to the backplane scan port of a root layer of ’STA112s, each of which can be selected using multi-drop addressing. A second tier of ’STA112s can be connected to this root layer, by connecting a local port (LSP) of a rootlayer ’STA112 to the backplane port of a second-tier ’STA112. This process can be continued to construct a multilevel scan hierarchy. ’STA112 local ports which are not cascaded into higher-level ’STA112s can be thought of as the terminal leaves of a scan tree. The test master can select one or more target leaves by selecting and configuring the local ports of an appropriate set of ’STA112s in the test tree. STANDARD SCANBRIDGE MODE - ScanBridge mode refers to functionality and protocol that has been used by National since the introduction of the PSC110 in 1993. This functionality consists of a multidrop addressable IEEE1149.1 switch. This enables one (or more) device to be selected from many that are connected to a parallel IEEE1149.1 bus or backplane. The second function that ScanBridge mode accomplishes is to act as a mux for multiple IEEE1149.1 local scan chains. The Local Scan Ports (LSP) of the device creates a connection between one or more of the local scan chains to the backplane bus. To accomplish this functionality the ScanBridge has two levels of protocol and an operational mode. Level 1 protocol www.national.com TRANSPARENT MODE - Transparent mode refers to a condition of operation in which there are no pad-bits or SCANSTA112 registers in the scan chain. The Transparent mode of operation is available in both ScanBridge and Stitcher modes. Only the activation method differs. Once transparent mode has been activated there is no difference in operation. Transparent mode allows for the use of vectors that have been generated for a chain where these bits were not included. Check with your ATPG tool vendor to ensure support of these features. For details regarding the internal operation of the SCANSTA112 device, refer to applications note AN-1259 SCANSTA112 Designers Reference. 8 Supply Voltage (VCC) −0.3V to +4.0V 100L FBGA 35˚C/W 100L TQFP 59.1˚C/W Package Derating above +25˚C DC Input Diode Current (IIK) VI = −0.5V −20 mA DC Input Voltage (VI) −0.5V to +3.9V −20 mA DC Output Voltage (VO) −0.3V to +3.9V DC VCC or Ground Current per Output Pin Junction Temperature (Plastic) ’STA112 +150˚C Storage Temperature 2500V Supply Voltage (VCC) ± 300 mA DC Latchup Source or Sink Current 16.92mW/˚C Recommended Operating Conditions ± 50 mA ± 50 mA DC Output Source/Sink Current (IO) 28.57mW/˚C 100L TQFP ESD Last Passing Voltage (HBM Min) DC Output Diode Current (IOK) VO = −0.5V 100L FBGA −65˚C to +150˚C Lead Temperature (Solder, 4sec) 3.0V to 3.6V Input Voltage (VI) 0V to VCC Output Voltage (VO) 0V to VCC Operating Temperature (TA) 100L FBGA 220˚C 100L TQFP 220˚C Industrial Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of SCAN STA products outside of recommended operation conditions. Max Package Power Capacity @ 25˚C 100L FBGA 3.57W 100L TQFP 2.11W −40˚C to +85˚C Thermal Resistance (θJA) DC Electrical Characteristics Over recommended operating supply voltage and temperature ranges unless otherwise specified Symbol VIH Parameter Conditions Minimum High Input Voltage VOUT = 0.1V or Min Max 2.1 Units V VCC −0.1V VIL Maximum Low Input Voltage VOUT = 0.1V or VOH Minimum High Output Voltage IOUT = −100 µA All Outputs and I/O Pins VIN = VIH or VIL 0.8 V VCC −0.1V VOH VOH Minimum High Output Voltage IOUT = −12 mA TDOB0, TDOB1, TRISTB0, TRISTB1, Y0B0, Y1B0, Y0B1, Y1B1, TDO(01-06), Y001, Y101, TRIST(01-03) All Outputs Loaded Minimum High Output Voltage IOUT = −24mA VCC - 0.2v V 2.4 V 2.2 V TMSB0, TMSB1, TCKB0, TCKB1, TRSTB0, TRSTB1, TMS(01-06), TCK(01-06), TRST(01-06) VOL VOL Maximum Low Output Voltage IOUT = +100 µA All Outputs and I/O Pins VIN = VIH or VIL 0.2 V Maximum Low Output Voltage IOUT = +12 mA 0.4 V IOUT = +24mA 0.55 V Maximum Input Clamp Diode Voltage IIK = -18mA -1.2 V Maximum Input Leakage Current VIN = VCC or GND ± 5.0 µA TDOB0, TDOB1, TRISTB0, TRISTB1, Y0B0, Y1B0, Y0B1, Y1B1, TDO(01-06), Y001, Y101, TRIST(01-03) VOL Maximum Low Output Voltage TMSB0, TMSB1, TCKB0, TCKB1, TRSTB0, TRSTB1, TMS(01-06), TCK(01-06), TRST(01-06) VIKL IIN (non-resistor input pins) 9 www.national.com SCANSTA112 Absolute Maximum Ratings (Note 2) SCANSTA112 DC Electrical Characteristics (Continued) Over recommended operating supply voltage and temperature ranges unless otherwise specified Symbol IILR Parameter Conditions Input Current Low VIN = GND Min Max Units -45 -200 µA 5.0 µA ± 5.0 µA ± 200 ± 5.0 µA (Input and I/O pins with pull-up resistors: TDIB0, TDIB1, TMSB0, TMSB1, TRSTB0, TRSTB1, A0B0, A1B0, A0B1, A1B1, TDI(01-06), A001, A101) IIH Input High Current (Input and I/O pins with pull-up resistors: TDIB0, TDIB1, TMSB0, TMSB1, TRSTB0, TRSTB1, A0B0, A1B0, A0B1, A1B1, TDI(01-06), A001, A101) VIN = VCC IOFF Power-off Leakage Current Outputs and I/O pins without pull-up resistors VCC = 0V, VIN = 3.6V (Note 3) Outputs and I/O pins with pull-up resistors IOZ Maximum TRI-STATE Leakage Current µA Outputs and I/O pins without pull-up resistors ICC Maximum Quiescent Supply Current VIN = VCC or GND 3.8 mA ICCD Maximum Dynamic Supply Current VIN = VCC or GND, Input Freq = 25MHz 68 mA Typ Max Units 8.5 13.5 ns 8.5 14.0 ns 7.5 12.5 ns 7.5 13.0 ns 8.0 12.0 ns 8.0 12.0 ns 8.0 12.0 ns 8.0 12.0 ns 8.0 12.0 ns 8.0 12.0 ns 7.5 12.0 ns 7.5 12.0 ns 11.5 18.0 ns 11.5 18.0 ns Note 3: Guaranteed by equivalent test method. AC Electrical Characteristics: Scan Bridge Mode Over recommended operating supply voltage and temperature ranges unless otherwise specified (Note 5). Symbol Parameter tPHL, Propagation Delay tPLH TCKB0 to TDOB0 or TDOB1 tPHL, Propagation Delay tPLH TCKB1 to TDOB0 or TDOB1 tPHL, Propagation Delay tPLH TCKB0 to TDO(01-06) tPHL, Propagation Delay tPLH TCKB1 to TDO(01-06) tPHL, Propagation Delay tPLH TMSB0 to TMSB1 tPHL, Propagation Delay tPLH TMSB1 to TMSB0 tPHL, Propagation Delay tPLH TMSB0 to TMS(01-06) tPHL, Propagation Delay tPLH TMSB1 to TMS(01-06) tPHL, Propagation Delay tPLH TCKB0 to TCKB1 tPHL, Propagation Delay tPLH TCKB1 to TCKB0 tPHL, Propagation Delay tPLH TCKB0 to TCK(01-06) tPHL, Propagation Delay tPLH TCKB1 to TCK(01-06) tPHL, Propagation Delay tPLH TCKB0 to TRSTB1 tPHL, Propagation Delay tPLH TCKB1 to TRSTB0 www.national.com Conditions 10 (Continued) Over recommended operating supply voltage and temperature ranges unless otherwise specified (Note 5). Symbol Parameter tPHL, Propagation Delay tPLH TCKB0 to TRST(01-06) tPHL, Propagation Delay tPLH TCKB1 to TRST(01-06) tPHL Propagation Delay Conditions Typ Max Units 12.0 18.5 ns 12.0 18.5 ns 8.5 12.5 ns 8.0 12.0 ns 9.0 14.5 ns 6.0 9.0 ns Max Units TCKBn to TRISTBn tPHL Propagation Delay TCKBn to TRIST(01-03) tPZL, Propagation Delay tPZH TCKBn to TDOBn or TDO(01-06) tPHL, Propagation Delay tPLH An to Yn AC Timing Characteristics: Scan Bridge Mode Over recommended operating supply voltage and temperature ranges unless otherwise specified (Notes 4, 5). Symbol tS Parameter Conditions Setup Time Min 2.5 ns 1.5 ns 3.0 ns 2.0 ns 1.0 ns 3.5 ns 1.0 ns tR/tF = 1.0ns 10.0 ns tR/tF = 1.0ns 2.5 ns tR/tF = 1.0ns 25 MHz TMSBn to TCKBn tH Hold Time TMSBn to TCKBn tS Setup Time TDIBn to TCKBn tH Hold Time TDIBn to TCKBn tS Setup Time TDI(01-06) to TCKBn tH Hold Time TDI(01-06) to TCKBn tREC Recovery Time TCKBn from TRSTBn tW Clock Pulse Width TCKBn(H or L) tWL Reset Pulse Width TRSTBn(L) FMAX Maximum Clock Frequency (Note 6) Note 4: Guaranteed by Design (GBD) by statistical analysis Note 5: RL = 500Ω to GND, CL = 50pF to GND, tR/tF = 2.5ns, Frequency = 25MHz, VM = 1.5V Note 6: When sending vectors one-way to a target device on an LSP (such as in FPGA/PLD configuration/programming), the clock frequency may be increased above this specification. In Scan Mode (expecting to capture returning data at the LSP), the FMAX must be limited to the above specification. 11 www.national.com SCANSTA112 AC Electrical Characteristics: Scan Bridge Mode SCANSTA112 AC Electrical Characteristics: Stitcher Transparent Mode Over recommended operating supply voltage and temperature ranges unless otherwise specified (Note 5). Symbol Parameter tPHL, Propagation Delay tPLH TDIB0 to TDOB1, TDIB1 to TDOB0 tPHL, Propagation Delay tPLH TDIB0 to TDO01, TDIB1 to TDO01 tPHL, Propagation Delay tPLH TDILSPn to TDOLSPn+1 tPHL, Propagation Delay tPLH TMSB0 to TMSB1, TMSB1 to TMSB0 tPHL, Propagation Delay tPLH TMSB0 to TMS(01-06), TMSB1 to TMS(01-06) tPHL, Propagation Delay tPLH TRSTB0 to TRSTB1, TRSTB1 to TRSTB0 tPHL, Propagation Delay tPLH TRSTB0 to TRST(01-06), TRSTB1 to TRST(01-06) Conditions Typ Timing Diagrams 20051236 Waveforms for an Unparked STA112 in the Shift-DR (IR) TAP Controller State www.national.com 12 Max Units 12.5 ns 12.5 ns 12.5 ns 12.5 ns 12.5 ns 12.5 ns 12.5 ns SCANSTA112 Timing Diagrams (Continued) 20051238 Reset Waveforms 20051239 Output Enable Waveforms Capacitance & I/O Characteristics Refer to National’s website for IBIS models at http://www.national.com/scan 13 www.national.com SCANSTA112 Physical Dimensions inches (millimeters) unless otherwise noted 100-Pin BGA NS Package Number SLC100a Ordering Code SCANSTA112SM 100-Pin TQFP NS Package Number VJD100a Ordering Code SCANSTA112VS www.national.com 14 SCANSTA112 7-port Multidrop IEEE 1149.1 (JTAG) Multiplexer Notes LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. National Semiconductor Americas Customer Support Center Email: [email protected] Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: [email protected] National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: [email protected] Tel: 81-3-5639-7560 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.