LM1771
Low-Voltage Synchronous Buck Controller with
Precision Enable and No External Compensation
General Description
Features
The LM1771 is an efficient synchronous buck switching controller with a precision enable requiring no external compensation. The constant on-time control scheme provides a
simple design free of compensation components, allowing
minimal component count and board space. The precision
enable pin allows flexibility in sequencing multiple rails and
setting UVLO. The LM1771 also incorporates a unique input
feed-forward to maintain a constant frequency independent
of the input voltage. The LM1771 is optimized for a low
voltage input range of 2.8V to 5.5V and can provide an
adjustable output as low as 0.8V. Driving an external high
side PFET and low side NFET it can provide efficiencies as
high as 95%.
Three versions of the LM1771 are available depending on
the switching frequency desired for the application. Nominal
switching frequencies are in the range of 100kHz to
1000kHz.
n
n
n
n
n
n
n
n
n
Input voltage range of 2.8V to 5.5V
0.8V reference voltage
Precision enable
No compensation required
Constant frequency across input range
Low quiescent current of 400 µA
Internal soft-start
Short circuit protection
Tiny LLP-6 package and MSOP-8 package
Applications
n Simple To Design, High Efficiency Step Down Switching
Regulators
n FPGAs, DSPs, and ASIC Power Supplies
n Set-Top Boxes
n Cable Modems
n Printers
n Digital Video Recorders
n Servers
n Graphic Cards
Typical Application Circuit
20189001
© 2006 National Semiconductor Corporation
DS201890
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LM1771 Low-Voltage Synchronous Buck Controller with Precision Enable and No External
Compensation
June 2006
LM1771
Connection Diagrams
Top View
Top View
20189040
MSOP-8
NS Package Number MUA08A
20189002
6-Lead LLP (3mm x 3mm)
NS Package Number SDE06A
Ordering Information
Order Number
LM1771SSD
LM1771SSDX
LM1771TSD
LM1771TSDX
LM1771USD
LM1771USDX
Order Number
LM1771SMM
LM1771SMMX
LM1771TMM
LM1771TMMX
LM1771UMM
LM1771UMMX
Timing Option
NSC Package
Drawing
Package Type
500ns
1000ns
6-Lead LLP
SDE06A
2000ns
Timing Option
Top Mark
Supplied As
1771S
1000 units Tape and Reel
1771S
4500 units Tape and Reel
1771T
1000 units Tape and Reel
1771T
4500 units Tape and Reel
1771U
1000 units Tape and Reel
1771U
4500 units Tape and Reel
Package Type
NSC Package Drawing
Supplied As
MSOP-8
MUA08A
Available Soon
500ns
1000ns
2000ns
Pin Descriptions
Pin #
Name
1
FB
2
GND
3
HG
PFET Gate Drive
4
LG
NFET Gate Drive
5
VIN
Input supply
6
EN
Enable Pin
DAP
-
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Function
Feedback Pin
Ground
Die Attach Pad is internally connected to GND, but it cannot be
used as the primary GND connection
2
Junction Temperature
150˚C
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Lead Temperature
260˚C
VIN
-0.3V to 6V
EN, FB, HG, LG
-0.3V to VIN
Storage Temperature Range
(soldering, 10sec)
ESD Rating
2kV
Operating Ratings
VIN to GND
−65˚C to 150˚C
2.8V to 5.5V
Junction Temperature Range (TJ)
−40˚C to +125˚C
Electrical Characteristics Specifications with standard typeface are for TJ = 25˚C, and those in bold face
type apply over the full Junction Temperature Range (−40˚C to +125˚C). Minimum and Maximum limits are guaranteed
through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25˚C and are
provided for reference purposes only. Unless otherwise specified VIN = 3.3V.
Symbol
VFB
IQ
TON
TOFF_MIN
TD
VIH_EN
VEN_HYS
IFB
VUVLO
Parameter
Conditions
Feedback pin voltage
Quiescent current
Switch On-Time
Minimum Off-Time
Min
0.782
VFB = 0.9V
V
700
µA
0.5
0.6
1.0
1.2
LM1771U - (2000ns)
1.6
2.0
2.4
LM1771S - (500ns)
150
250
LM1771T - (1000ns)
135
225
LM1771U - (2000ns)
120
220
70
Feedback pin bias current
VFB = 0.9V
Under-voltage lock out
VIN Rising Edge
Feedback pin Short Circuit Latch
Threshold
0.818
0.8
EN Pin Hysteresis
VSC_TH
0.8
0.4
1.15
µs
ns
ns
1.2
1.25
V
50
200
mV
50
2.65
nA
2.8
50
0.42
Unit
400
LM1771T - (1000ns)
EN Pin Rising Threshold
Under-voltage lock out hysteresis
Max
LM1771S - (500ns)
Gate Drive Dead-Time
VUVLO_HYS
Typ
0.55
V
mV
0.65
V
RDS(ON) 1
HG FET driver pull-up On resistance
IHG = 20 mA
4
Ω
RDS(ON) 2
HG FET driver pull-down On resistance IHG = 20 mA
6
Ω
RDS(ON) 3
LG FET driver pull-up On resistance
ILG = 20 mA
4
Ω
RDS(ON) 4
LG FET driver pull-down On resistance ILG = 20 mA
6
Ω
Note 1: Absolute Maximum Ratings indicate limits beyond which damage may occur to the device. Operating Ratings indicate conditions for which the device is
intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications, see Electrical Characteristics.
3
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LM1771
Absolute Maximum Ratings (Note 1)
LM1771
Typical Performance Characteristics All curves taken at VIN = 3.3V with configuration in typical application circuit shown in Application Information section of this datasheet. TJ = 25˚C, unless otherwise specified.
TON vs VIN (LM1771S)
TON vs VIN (LM1771T)
20189007
20189009
TON vs VIN (LM1771U)
TON vs Temperature (LM1771S)
20189011
20189008
TON vs Temperature (LM1771T)
TON vs Temperature (LM1771U)
20189010
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20189012
4
TOFF vs Temperature (LM1771S)
TOFF vs Temperature (LM1771T)
20189013
20189041
TOFF vs Temperature (LM1771U)
Feedback Voltage vs Temperature
20189042
20189017
VEN Threshold vs Temperature
Short Circuit Threshold vs Temperature
20189014
20189018
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LM1771
Typical Performance Characteristics All curves taken at VIN = 3.3V with configuration in typical
application circuit shown in Application Information section of this datasheet. TJ = 25˚C, unless otherwise
specified. (Continued)
LM1771
Typical Performance Characteristics All curves taken at VIN = 3.3V with configuration in typical
application circuit shown in Application Information section of this datasheet. TJ = 25˚C, unless otherwise
specified. (Continued)
Quiescent Current vs Temperature
Deadtime vs Temperature
20189016
20189015
Efficiency vs IOUT (LM1771U)
(VIN = 5V, VOUT = 2.5V, FSW = 379kHz)
Efficiency vs IOUT (LM1771T)
(VIN = 5V, VOUT = 1.8V, FSW = 545kHz)
20189004
20189003
Efficiency vs IOUT (LM1771S)
(VIN = 5V, VOUT = 1.2V, FSW = 727kHz)
Efficiency vs IOUT (LM1771U)
(VIN = 5V, VOUT = 3.3V, FSW = 500kHz)
20189005
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20189006
6
LM1771
Block Diagram
20189019
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LM1771
Application Information
THEORY OF APPLICATION
The LM1771 synchronous buck controller has a control
scheme that is referred to as adaptive on-time control. This
topology relies on a fixed switch on-time to regulate the
output voltage. This on-time is internally set by EEPROM
and is available with three different set-points to allow for
different frequency options. The LM1771 automatically adjusts the on-time during operation inversely with the input
voltage (VIN) to maintain a constant frequency. Therefore
the switching frequency during continuous conduction mode
is independent of the inductor and capacitor size unlike
hysteretic switchers.
where,
α = VIN x TON
To maintain a set frequency in an application, α is always
held constant by varying TON inversely with VIN. The three
versions of the LM1771 are identified by the on times at a
VIN of 3.3V for consistency. For clarification see the table
below:
At the beginning of the cycle the LM1771 turns on the high
side PFET for a fixed duration. This on-time is predetermined
(internally set by EEPROM and adjusted by VIN) and the
switch will not turn off until the timer has completed its
period. The PFET will then turn off for a minimum predetermined time period. This minimum TOFF of 150ns is
internally set and cannot be adjusted. This is to prevent false
triggering from occurring on the comparator due to noise
from the SW node transition. After the minimum TOFF period
has expired, the PFET will remain off until the comparator
trip-point has been reached. Upon passing this trip-point (set
at 0.8V at the feedback pin), the PFET will turn back on and
the process will repeat, thus regulating the output.
Product ID
TON @ 3.3V
α (V µs)
LM1771S
0.5µs
1.65
LM1771T
1.0µs
3.3
LM1771U
2.0µs
6.6
The variation of TON versus VIN can also be expressed
graphically. These graphs can be found in the typical curves
section of the datasheet.
With α being a constant regardless of the version of the
LM1771 used, equation [6] shows that the only dependent
variable remaining is VOUT. Since VOUT will be a constant in
any application, the frequency will also remain constant. The
switching frequency at which the application runs depends
upon the VOUT desired and the LM1771 version chosen. For
any VOUT, three frequency options (LM1771 versions) can
be selected. This can be seen in the table below. The recommended frequency range of operation is 100kHz to
1000kHz.
The NFET control is complementary to the PFET control with
the exception of a short dead-time to prevent shoot through
from occurring.
DEVICE OPERATION
Timing Options
Timing Opinion
Three versions of the LM1771 are available each with a
predetermined TON set internally by EEPROM. This TON
setting will determine the switching frequency for the application. Derivation and calculation of the switching frequency’s dependence on VIN and TON can be seen in the following section.
In a PWM buck switcher the following equations can be
manipulated to obtain the switching frequency. The first
equation shows the standard duty-cycle equation given by
the volts-seconds balance on the inductor with the following
equations defining standard relationships:
500ns
1000ns
2000ns
0.8
485
242
121
1
606
303
152
1.2
727
364
182
1.5
909
455
227
1.8
1091
545
273
2.5
1515
758
379
3.3
2000
1000
500
Switching Frequency (kHz) of LM1771 based on output voltage and timing
option.
SHORT-CIRCUIT PROTECTION
The LM1771 has an internal short circuit comparator that
constantly monitors the feedback node (except during softstart). If the feedback voltage drops below 0.55V (equivalent
to the output voltage dropping below 68% of nominal), the
comparator will trip causing the part to latch off. The LM1771
will not resume switching until the input voltage is taken
below the UVLO threshold and then brought back into its
normal operating range, or the part is disabled then reenabled through the enable pin. The purpose of this function
is to prevent a severe short circuit from causing damage to
the application. Due to the fast transient response of the
LM1771 a severe short on the output causing the feedback
to drop would only occur if the load applied had an effective
resistance that approaches the PMOS RDS(ON).
TON = D x TP
Using these equations and solving for duty-cycle:
D = fSW x TON
Frequency can now be expressed as:
PRECISION ENABLE
The LM1771 features a precision enable circuit. If the voltage on the EN pin is 1.2V or greater, the part is enabled and
switching will occur. If the enable voltage falls below 1.2V,
Or simply written as:
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VOUT
8
frequency at that instant. When viewed on an oscilloscope
this can be seen as a jitter in the switch node. The change in
feedback voltage or output voltage, however, is almost indistinguishable.
(Continued)
the part will be placed into a shutdown state and the drivers
will be tri-stated. This allows the LM1771 to be easily sequenced using a resistive divider from the output of another
regulator, or the working input voltage range of the LM1771
to be set using a resistive divider on VIN. There is no internal
pull-up connected to the EN pin, so an external signal is
required to initiate switching. It should be noted that when
power is first applied to the LM1771, there is a slight delay
before the enable comparator is functional. During this delay,
typically on the order of 400 µs, the part will be disabled
regardless of the voltage on the EN pin. The falling enable
threshold features 50 mV of hysteresis
Design Guide
The following section walks the designer through the steps
necessary to select the external components to build a fully
functional power supply. As with any DC-DC converter numerous trade-offs are possible to optimize the design for
efficiency, size or performance. These will be taken into
account and highlighted throughout this discussion.
The first equation to calculate for any buck converter is
duty-cycle. Ignoring conduction losses associated with the
FETs and parasitic resistances it can be approximated by:
SOFT-START
To limit in-rush current and allow for a controlled startup the
LM1771 incorporates an internal soft-start scheme. Every
time the enable voltage rises rises above 1.2V while VIN is
greater than the UVLO threshold, the LM1771 goes through
an adaptive soft-start that limits the on-time and expands the
minimum off-time. In addition the part will only activate the
PMOS allowing a discontinuous mode of operation enabling
a pre-biased startup. The time spent in soft-start will depend
on the load applied to the output, but is usually close to a set
time that is dependent on the timing option. The approximate
soft-start time can be seen below for each timing option.
Product ID
Timing
TSS
LM1771S
0.5 µs
1 ms
LM1771T
1.0 µs
1.2 ms
LM1771U
2.0 µs
1.8 ms
A more accurate calculation for duty-cycle can be used that
takes into account the voltage drops across the FETs. This
equation can be used to determine the slight load dependency on switch frequency if needed. Otherwise the simplified equation works well for component calculation.
FREQUENCY SELECTION
The LM1771 is available with three preset timing options that
select the on-time and hence determine the switching frequency of the application. Increasing the switching frequency has the effect of reducing the inductor size needed
for the application while requiring a slight trade-off in efficiency. The table below shows the same frequency table as
shown earlier, with the exception that the recommended
timing option for each VOUT is highlighted. It is not recommended to use a high switching frequency with VOUT equal
to or greater than 2.5V due to the maximum duty-cycle
limitations of the device coupled with the internal startup.
It should be noted that as soon as soft-start terminates the
short-circuit protection is enabled. This means that if the
output voltage does not reach at least 68% of its final value
the part will latch off. Therefore, if the input supply is extremely slow rising such that at the end of soft-start the input
voltage is still near the UVLO threshold, a timing option
should be chosen to ensure that maximum duty-cycle permits the output to meet the minimum condition. As a general
recommendation it is advisable to use the 2000 ns option
(LM1771U) in conditions where the output voltage is 2.5V or
greater to avoid false latch offs when there is concern regarding the input supply slew rate.
In some situations, the internal soft-start routine can create a
slight overshoot on the output voltage. If this must be
avoided, the use of a feed-forward capacitor as detailed in
the feed-forward capacitor section of this datasheet is recommended.
Timing Options
JITTER
The LM1771 utilizes an adaptive on-time control scheme
that relies on the output voltage ripple to provide a consistent
switching frequency. Under certain conditions, excessive
noise can couple onto the feedback pin causing the switch
node to appear to have a slight amount of jitter. This is not
indicative of an unstable design. The output voltage will still
regulate to the exact same value. Careful component selection and layout should minimize any external influence.
In addition to any external noise that can add to the jitter
seen on the switch node, the LM1771 will always have a
slight amount of switch jitter. This is because the LM1771
makes a small alteration in the reference voltage every 128
cycles to improve its accuracy and long term performance.
This has the effect of causing a change in the switching
VOUT
500 ns
1000 ns
2000 ns
0.8
485
242
-
1
606
303
-
1.2
727
364
-
1.5
909
455
227
1.8
-
545
273
2.5
-
-
379
3.3
-
-
500
Recommended switching frequency (kHz) based on output voltage and
timing option.
INDUCTOR SELECTION
The inductor selection is an iterative process likely requiring
several passes before settling on a final value. The reason
for this is because it influences the amount of ripple seen at
the output, a critical component to ensure general stability of
an adaptive on-time circuit. For the first pass at inductor
selection the value can be obtained by targeting a maximum
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LM1771
Application Information
LM1771
Design Guide
If the output voltage is fairly high, causing significant attenuation through the feedback resistors, a feed-forward capacitor can be used. This is actually recommended for most
circuits as it improves performance. See the feed-forward
capacitor section for more details.
(Continued)
peak-to-peak ripple current equal to 30% of the maximum
load current. The inductor current ripple (∆IL) can be calculated by:
The second criteria is to ensure that there is sufficient ripple
at the output that is in-phase with the switch. The problem
exists that there is actually ripple caused by the capacitor
charging and discharging, not only the ESR ripple. Since
these are effectively out of phase, problems can exist. To
avoid this issue it is recommended that the ratio of the two
ripples (β) is always greater than 5. To calculate the minimum ESR value needed, the following equation can be
used.
Therefore, L can be initially set to the following by applying
the 30% rule:
The other features of the inductor that can be selected
besides inductance value are saturation current and core
material. Because the LM1771 does not have a current limit,
it is recommended to have a saturation current higher than
the maximum output current to handle any ripple or momentary over-current events. The core material also influences
the saturation characteristics as ferrite materials have a hard
saturation curve and care should be taken such that they
never saturate during normal use. A shielded inductor or low
profile unshielded inductor is recommended to reduce EMI.
This also helps prevent any spurious noise from picking up
on the feedback node resulting in unexpected tripping of the
feedback comparator.
In general the best capacitors to use are chemistries that
have a known and consistent ESR across the entire operating temperature range. Tantalum capacitors or similar chemistries such as Niobium Oxide perform well along with certain
families of Aluminum Electrolytics. Small value POSCAPs
and SP CAPs also work as they have sufficient ESR. When
used in conjunction with a low value inductor it is possible to
have an extremely stable design. The only capacitors that
require modification to the circuit are ceramic capacitors.
Ceramic capacitors cause problems meeting both criteria
because they have low ESR and low capacitance. Therefore, if they are to be used, an external ESR resistor (RSNS)
should be added. This can be seen below in the following
circuit.
OUTPUT CAPACITOR
One of the most important components to select with the
LM1771 is the output capacitor. This is because its size and
ESR have a direct effect on the stability of the loop. A
constant on-time control scheme works by sensing the output voltage ripple and switching the FETs appropriately. The
output voltage ripple on a buck converter can be approximated by stating that the AC inductor ripple flows entirely
into the output capacitor and is created by the ESR of the
capacitor. This can be expressed in the following equation:
∆VOUT = ∆IL x RESR
To ensure stability, two constraints need to be met. The first
is that there is sufficient ESR to create enough voltage ripple
at the feedback pin. The recommendation is to have at least
10mV of ripple seen at the feedback pin. This can be calculated by multiplying the output voltage ripple by the gain
seen through the feedback resistors. This gain, H, can be
calculated below:
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LM1771
Design Guide
(Continued)
20189029
This circuit implementation utilizing the feed-forward capacitor begins to experience limitations when the output voltage
is small. Previously the circuit relied on the CFF for all the
ripple at the feedback node by assuming that the resistor
divider was negligible. As VOUT decreases this can not be
assumed. The resistor divider contributes a larger amount of
ripple which is problematic as it is also out of phase. Therefore the resistor location should be changed to be in series
with the output capacitor. This can be viewed as adding an
effective ESR to the output capacitor.
This circuit uses an additional resistor in series with the
inductor to add ripple at the output. It is placed in this location
and used in combination with the feed-forward capacitor
(CFF) to provide ripple to the feedback pin, without adding
ripple or a DC offset to the output. The benefit of using a
ceramic capacitor is still obtained with this technique. Because the addition of the resistor results in power loss, this
circuit implementation is only recommended for low currents
(2A and below). The power loss and rating of the resistor
should be taken into account when selecting this component.
20189030
FEED-FORWARD CAPACITOR
The feed-forward capacitor is used across the top feedback
resistor to provide a lower impedance path for the high
frequency ripple without degrading the DC accuracy. Typically the value for this capacitor should be small enough to
prevent load transient errors because of the discharging
time, but large enough to prevent attenuation of the ripple
voltage. In general a small ceramic capacitor in the range of
1nF to 10nF is sufficient.
If CFF is used then it can be assumed that the ripple voltage
seen at the feedback pin is the same as the ripple voltage at
the output. The attenuation factor H no longer needs to be
used. However, in these conditions, it is recommended to
have a minimum of 20mV ripple at the feedback pin. The use
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LM1771
Design Guide
GATE CHARGE
(Continued)
Because the LM1771 utilizes a fixed dead-time scheme to
prevent cross conduction, the FET transitions must occur in
this time. The rise and fall time of the FETs gate can be
influenced by several factors including the gate capacitance.
Therefore the total gate charge of both FETs should be
limited to less than 20nC at 4.5V VGS. The lower the number
the faster the FETs should switch and the better the efficiency.
of a CFF capacitor is recommended as it improves the regulation and stability of the design. However, its benefit is
diminished as VOUT starts approaching VREF , therefore it is
not needed in this situation.
INPUT CAPACITOR
The dominating factor that usually sets an input capacitors’
size is the current handling ability. This is usually determined
by the package size and ESR of the capacitor. If these two
criteria are met then there usually should be enough capacitance to prevent impedance interactions with the source. In
general it is recommended to use a ceramic capacitor for the
input as they provide a low impedance and small footprint.
One important note is to use a good dielectric for the ceramic
capacitor such as X5R or X7R. These provide better over
temperature performance and also minimize the DC voltage
derating that occurs on Y5V capacitors. To calculate the
input capacitor RMS current, the equation below can be
used:
RISE / FALL TIMES
A better indication of the actual switching times of the FETs
can be found in their electrical characteristics table. The rise
and fall time should be specified and selected to be at a
minimum. This helps improve efficiency and ensuring that
shoot through does not occur.
GATE CHARGE RATIO
Another consideration in selecting the FETs is to pay attention to the Qgd / Qgs ratio. The reason for this is that proper
selection can prevent spurious turn on. If we look at the
NFET for example, when the FET is turning off, the gate
signal will pull to ground. Conversely the PFET will be turning on, causing the SW node to rise towards VIN. The gate to
drain capacitance of the NFET couples the SW node to the
gate and will cause it to rise. If this voltage is excessive, then
it could weakly turn on the low side FET causing an efficiency loss. However, this coupling is mitigated by having a
large gate to source capacitance of the FET, which helps to
hold the gate voltage down. Ideally, a very low Qgd / Qgs
would be ideal, but in practice it is common to find the
number around 1. As a general rule, the lower the ratio, the
better.
If the above selection criteria have been met it is useful to
generate a figure of merit to allow comparison between the
FETs. One such method is to multiply the RDS(ON) of the FET
by the total gate charge. This allows an easy comparison of
the different FETs available. Once again, the lower the product, the better.
which can be approximated by,
MOSFET Selection
The two FETs used in the LM1771 requires attention to
selection of parameters to ensure optimal performance of
the power supply. The high side FET should be a PFET and
the low side an NFET. These can be integrated in one
package or as two separate packages. The criteria that
matter in selection are listed below:
FEEDBACK RESISTORS
The feedback resistors are used to scale the output voltage
to the internal reference value such that the loop can be
regulated. The feedback resistors should not be made arbitrarily large as this creates a high impedance node at the
feedback pin that is more susceptible to noise. A combined
value of 50kΩ for the two resistors is adequate. To calculate
the resistor values use the equation below. Typically the low
side resistor is initially set to a pre-determined value such as
10 kΩ.
VDS VOLTAGE RATING
The first selection criteria is to select FETs that have sufficient VDS voltage ratings to handle the maximum voltage
seen at the input plus any transient spikes that can occur
from parasitic ringing. In general most FETs available for this
application will have ratings from 8V to 20V. If a larger
voltage rating is used then the performance will most likely
be degraded because of higher gate capacitance.
RDSON
The RDS(ON) specification is important as it determines several attributes of the FET and the overall power supply. The
first is that it sets the maximum current of the FET for a given
package. A lower RDS(ON) will permit a higher allowable
current and reduce conduction losses, however, it will increase the gate capacitance and the switching losses.
VFB is the internal reference voltage that can be found in the
electrical characteristics table or approximated by 0.8V.
The output voltage value can be set in a precise manner by
taking into account the fact that the reference voltage is
regulating the bottom of the output ripple as opposed to the
average value. This relationship is shown in the figure below.
GATE DRIVE
The next step is to ensure that the FETs are capable of
switching at the low Vin supplies used by the LM1771. The
FET should have the Rdson specified at either 1.8V or 2.5V
to ensure that it can switch effectively as soon as the
LM1771 starts up.
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LM1771
MOSFET Selection
(Continued)
20189034
It can be seen that the average output voltage (VOUT_ACTUAL) is higher than the output voltage (VOUT_SET) that was
calculated by the earlier equation by exactly half the output
voltage ripple. The output voltage that is targeted for regulation may then be appended according to the voltage ripple.
This can be seen below:
VOUT_ACTUAL= VOUT_SET + 1⁄2∆VOUT = VOUT_SET + 1⁄2∆IL x
RESR
TRANSITIONAL LOSS
The last FET power loss is the transitional loss. This is
caused by switching the PMOS while it is conducting current.
This approach only models the PMOS transition, the NMOS
loss is considered negligible because it has minimal drain to
source voltage when it switches due to the conduction of the
body diode. Therefore the transitional loss of the PMOS can
be modeled by:
PP_TRANSITIONAL = 0.5 x VIN x IOUT x fSW x (tr + tf)
tr and tf are the rise and fall times of the FET and can be
found in their corresponding datasheet. Typically these numbers are simulated using a 6Ω drive, which corresponds well
to the LM1771. Given this, no adjustment is needed.
Efficiency Calculations
One of the most important parameters to calculate during the
design stage is the expected efficiency of the system. This
can help determine optimal FET selection and can be used
to calculate expected temperature rise of the individual components. The individual losses of each component are broken down and the equations are listed below:
DCR LOSS
The last source of power loss in the system that needs to be
calculated is the loss associated with the inductor resistance
(DCR) which can be calculated by:
PDCR = RDCR x IOUT2
QUIESCENT CURRENT
The quiescent current consumed by the LM1771 is one of
the major sources of loss within the controller. However, from
a system standpoint this is usually less than 0.5% of the
overall efficiency. Therefore, it could easily be omitted but is
shown for completeness:
PIQ = VIN x IQ
EFFICIENCY
The efficiency, η, can then be calculated by summing all the
power losses and then using the equation below:
CONDUCTION LOSS
There are three losses associated with the external FETs.
From the DC standpoint there is the I-squared R loss,
caused by the on resistance of the FET. This can be modeled for the PMOS by:
PP_COND = D x RDSON_PMOS x IOUT2
and the NMOS by:
PN_COND = (1 - D) x RDSON_NMOS x IOUT2
Thermals
By breaking down the individual power loss in each component it makes it easy to determine the temperature rise of
each component. Generally the expected temperature rise
of the LM1771 is extremely low as it is not in the power path.
Therefore the only two items of concern are the PMOS and
the NMOS. The power loss in the PMOS is the sum of the
conduction loss and transitional loss, while the NMOS only
has conduction loss. It is assumed that any loss associated
with the body diode conduction during the dead-time is
negligible.
For completeness of design it is important to watch out for
the temperature rise of the inductor. Assuming the inductor is
kept out of saturation the predominant loss will be the DC
copper resistance. At higher frequencies, depending on the
core material, the core loss could approach or exceed the
DCR losses. Consult with the inductor manufacturer for appropriate temp curves based on current.
SWITCHING LOSS
The next loss is the switching loss that is caused by the need
to charge and discharge the gate capacitance of the FETs
every cycle. This can be approximated by:
PP_SWITCH = VIN x Qg_PMOS x fSW
for the PMOS, and the same approach can be adapted for
the NMOS:
PN_SWITCH = VIN x Qg_NMOS x fSW
13
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LM1771
3.
Locate the feedback resistors close to the IC and keep
the feedback trace as short as possible. Do not run any
feedback traces near the switch node.
4. Keep the gate traces short and keep them away from the
switch node as much as possible.
5. If a small bypass capacitor is used on VIN (0.1µF) place
it as close to the pin, with the ground connection as
close to the chip ground as possible.
Layout
The LM1771, like all switching regulators, requires careful
attention to layout to ensure optimal performance. The following steps should be taken to aid in the layout. For more
information refer to Application Note AN-1299.
1. Ensure that the ground connections of the input capacitor, output capacitor and NMOS are as close as possible. Ideally these should all be grounded together in
close proximity on the component side of the board.
2. Keep the switch node small to minimize EMI without
degrading thermal cooling of the FETs.
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14
LM1771
Typical Application Circuit
20189043
Example Circuit Schematic
Bill of Materials (5V to 1.8V Conversion, fSW = 1090kHz, IOUT = 2A)
Designator
Quantity
Vendor
U1
LM1771, 500ns
LM1771S
1
National Semiconductor
Q1
PMOS
Si3867DV
1
Siliconix
Q2
NMOS
Si3460DV
1
Siliconix
CIN
22µF Capacitor, 0805
GRM21BR60J226ME39
1
Murata
COUT
100µF Capacitor, 6.3V, 100mΩ
TPSY107M006R0100
1
AVX
RFB1
12.4kΩ Resistor, 0603
CRCW06031242F
1
Vishay
RFB2
10kΩ Resistor, 0603
CRCW06031002F
1
Vishay
CFF
1nF Capacitor, 0603
VJ0603102KXXA
1
Vishay
3.3µH Inductor
MSS7341-332NLB
1
Coilcraft
L
Description
Part Number
Bill of Materials (5V to 3.3V Conversion, fSW = 500kHz, IOUT = 5A)
Designator
Description
Part Number
Quantity
Vendor
1
National Semiconductor
U1
LM1771, 200ns
LM1771U
Q1
PMOS
Si9433BDY
1
Siliconix
Q2
NMOS
Si4894DY
1
Siliconix
CIN
100µF Capacitor, 1812
GRM43SR60J107ME20B
1
Murata
COUT
150µF Capacitor, 6.3V, 70mΩ
NOSD157M006R0070
1
AVX
RFB1
29.4kΩ Resistor, 0805
CRCW08052942F
1
Vishay
RFB2
10kΩ Resistor, 0805
CRCW08051002F
1
Vishay
CFF
1nF Capacitor, 0805
VJ0805102KXXA
1
Vishay
2.2µH Inductor
DO3316P-222
1
Coilcraft
L
15
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LM1771
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16
LM1771
Physical Dimensions
inches (millimeters) unless otherwise noted
LLP-6 Package
NS Package Number SDE06A
MSOP-8 Package
NS Package Number MUA08A
17
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LM1771 Low-Voltage Synchronous Buck Controller with Precision Enable and No External
Compensation
Notes
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