LM2631 Synchronous Step-Down Power Supply Controller General Description Features The LM2631 controller provides all the active functions for step-down (buck) switching converters. These dc-to-dc converters provide core CPU power in battery-operated systems. High efficiency is achieved by using synchronous rectification and pulse-skipping mode operation at light load. Inexpensive N-channel MOSFETs are used to reduce system cost. Bootstrap circuit is used to drive the high-side N-channel MOSFET. Current mode control scheme is used to improve line regulation and transient response, also provides cycle-by-cycle current limiting. The operating frequency is adjustable between 200 kHz and 400 kHz. An external shutdown pin can be used to disable the device and reduce the quiescent current to 0.1 µA. In low noise applications, bringing the FPWM pin high can force the device to operate in constant frequency mode. Other features include the external synchronization pin, and the PGOOD pin to indicate the state of the output voltage. Protection circuitry includes thermal shutdown, undervoltage and overvoltage shutdown protection, soft-start capability, and two levels of current limits: The first level simply limits the load current directly; at the second level, if the load pulls the output voltage down below 80% of the regulated value, the chip will shut down. This operation is disabled during startup, but an internal timer will enable it if the output does not come up in the preset time. n n n n n n n n n n n n n n n 4.5V to 30V input range Adjustable output (1.5V to 7V) 200 kHz to 400 kHz adjustable operating frequency Externally synchronizable On-board power good function Precision 1.24V reference output 0.8 mA typical quiescent current 0.1 µA shutdown current Thermal shutdown Direct current limit protection Input undervoltage lockout Output undervoltage shutdown protection Output overvoltage shutdown protection Programmable soft-start function Tiny TSSOP package Applications n n n n Notebook and subnotebook computers Cellular phones Portable instruments Battery-powered digital devices Typical Application Circuit DS100937-1 © 1999 National Semiconductor Corporation DS100937 www.national.com LM2631 Synchronous Step-Down Power Supply Controller April 1999 Absolute Maximum Ratings (Note 1) Storage Temperature Range If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Soldering Dwell Time, Temperature (Note 3) Wave Voltages from the indicated pins to GND and PGND: VIN −0.3V to 32V CBOOT −0.3V to 37V SD −0.3V to 32V SW −0.3V to 32V CSH, CSL 10 sec, 240˚C Vapor Phase 75 sec, 219˚C 1.5 kV Operating Ratings VIN −0.3V to 10V Power Dissipation (TA = 70˚C), (Note 2) 4 sec, 260˚C Infrared ESD Rating (Note 4) −0.3V to 8V FPWM, SYNC −65˚C to +150˚C 4.5V to 30V Junction Temperature −25˚C to +125˚C 720mW Electrical Characteristics Specifications in standard type face are for Tj = 25˚C and those with boldface type apply over full operating junction temperature range. VIN = 10V, GND = PGND = 0V,unless otherwise stated. (Notes 5, 6) Symbol Parameter Conditions Typical Limit Units System VIN Input Supply Voltage 4.5 30 V(min) V(max) VOUT Output Voltage Adjustment Range 1.5 7.0 V(min) V(max) ∆VOUT/ VOUT Load Regulation 0 mV ≤ (CSH-CSL) ≤ 75 mV ∆VOUT/ VOUT Line Regulation 4.5 ≤ VIN ≤ 30V IIN Input Supply Current with the Switching Controller ON VFB = 1V, VCSH = 2.15V, VCSL = 2.1V Input Supply Current with the Switching Controller ON (Internal Rail is Supplied from CSL Pin) VFB = 1V, VCSH = 5.15V, VCSL = 5V 0.15 Input Supply Current with the IC Shut Down VSD = 0V, VIN = 30V 0.1 Soft Start Source Current Soft Start Sink Current VCL Current Limit Voltage (Voltage from CSH to CSL) VIN Undervoltage Shutdown Latch Threshold % 0.002 %/V 0.8 VSS = 1.5V µA Rising Edge µA 5 µA(min) 13 µA(max) 20 µA 110 mV 90/80 mV(min) 130/140 mV(max) 2.6 V(min) 72/70 % VOUT(min) 89/90 %VOUT(max) 113/110 % VOUT(min) 129/130 % VOUT(max) 3.5 80 VOUT Overvoltage Shutdown Latch Threshold (Note 8) 120 2 µA(max) V 10 VSS = 1.5V VFB = 1V, VCSL = 1.8V mA(max) mA 3 VOUT Undervoltage Shutdown Latch Threshold (Note 8) www.national.com mA 1.2/1.4 3 (Note 7) Minimum Output Voltage for CSL Providing the Internal Rail ISS 0.3 V % VOUT % VOUT Electrical Characteristics (Continued) Specifications in standard type face are for Tj = 25˚C and those with boldface type apply over full operating junction temperature range. VIN = 10V, GND = PGND = 0V,unless otherwise stated. (Notes 5, 6) Symbol Parameter Conditions Typical Limit Units System VOUT Low Regulation Comparator Enable Threshold 97 % VOUT Hysteresis of Low Regulation Comparator 2 % VOUT Regulator Window Detector Thresholds (PGOOD from High to Low) 91 or 109 % VOUT Regulator Window Detector Thresholds (PGOOD from Low to High) % VOUT 97 or 103 Gate Drive VBOOT IBOOT Bootstrap Voltage (Voltage from CBOOT to SW) CBOOT Sourcing 100 µA 4.5 V CBOOT Leakage Current VCBOOT = 7V VHDRV = 0V, VCBOOT = 5V 100 nA High Drive Source Current 0.3 A High Drive Sink Current HDRV Forced to 5V 0.45 A Low Drive Source Current LDRV Forced to 0V 0.35 A Low Drive Sink Current LDRV Forced to 5V 4.0 V(min) 0.55 A High-Side FET On-Resistance HDRV or LDRV 8 Ω Low-Side FET On-Resistance HDRV or LDRV 4 Ω Oscillator FOSC Oscillator Frequency Oscillator Frequency FADJ Open 200 FADJ Sourcing 2.94 µA (Note 9) VFADJ Voltage at FADJ pin DMAX Maximum Duty Cycle FADJ Open Maximum Frequency of Synchronization Low-Going 200 ns Wide Rectangular Pulses Applied at 400 kHz at the SYNC Input Minimum Pulse Width of the SYNC Signal SYNC Pulses are Low-Going kHz 172/162 kHz(min) 228/230 kHz(max) 255 kHz(min) 345 kHz(max) 300 kHz 1.03 V 96 % 92 %(min) 400 kHz(min) 200 ns(min) Error Amplifier IFB ICOMP Feedback Input Bias Current VFB = 1.3V, VCSH = 5.15V, VCSL = 5V COMP Output Source Current VCOMP = 0.2V, VFB = 1V VCOMP = 1.2V, VFB = 1.4V COMP Output Sink Current 100 nA 50 µA 50 µA Voltage Reference VREF Reference Voltage (Nominal)) IREF = 0µA 1.238 3 V 1.219/1.219 V(min) 1.251/1.262 V(max) www.national.com Electrical Characteristics (Continued) Specifications in standard type face are for Tj = 25˚C and those with boldface type apply over full operating junction temperature range. VIN = 10V, GND = PGND = 0V,unless otherwise stated. (Notes 5, 6) Symbol Parameter Conditions Typical Limit Units 1.219/1.219 V(min) 1.251/1.262 V(max) 1.219/1.219 V(min) 1.251/1.262 V(max) Voltage Reference VREF Reference Voltage (Line Regulation) 4.5V < VIN < 30V Reference Voltage (Load Regulation) 0 µA < IREF < 50 µA 1.238 V 1.238 V Logic Inputs and Outputs VIH Minimum High Level Input Voltage (SD, FPWM and SYNC) 2.4 V(min) VIL Maximum Low Level Input Voltage (FPWM and SYNC) 0.8 V(max) 0.5 Maximum Low Level Input Voltage (SD) VOH VOL Maximum Input Leakage Curren1t (SD , FPWM and SYNC) Logic Input Voltage 0V or 5V PGOOD High Level Output Voltage PGOOD Sourcing 50 µA PGOOD Low Level Output Voltage PGOOD Sinking 50 µA ± 0.1 V(max) µA 2.7 V 2.4 V(min) 0.5 V(max) 0 V Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Electrical specifications do not apply when operating the device outside of its rated operating conditions. Note 2: The maximum allowable power dissipation is calculated by using PDmax = (TJmax - TA)/θJA , where TJmax is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction-to-ambient thermal resistance of the specified package. The 720 mW rating results from using 160˚C, 70˚C, and 125˚C/W for TJmax, TA, and θJA respectively. A θJA of 125˚C/W represents the worst-case condition of no heat sinking of the 20-pin TSSOP. Heat sinking allows the safe dissipation of more power. The Absolute Maximum power dissipation must be derated by 8 mW per ˚C above 70˚C ambient. The LM263 actively limits its junction temperature to about 160˚C. Note 3: For detailed information on soldering plastic small-outline packages, refer to the Packaging Databook available from National Semiconductor Corporation. Note 4: For testing purposes, ESD was applied using the human-body model, a 100 pF capacitor discharged through a 1.5 kΩ resistor. Note 5: A typical is the center of characterization data taken with TA = TJ = 25˚C. Typicals are not guaranteed. Note 6: All limits are guaranteed. All electrical characteristics having room-temperature limits are tested during production with TA = TJ = 25˚C. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Note 7: This limit is guaranteed by design. Note 8: Percentage limits are determined by measuring the shutdown latch threshold at the FB pin, and dividing it by the nominal reference voltage. Note 9: Pulling 2.94 µA out of FADJ pin simulates adjusting the oscillator frequency with a 350 kΩ resistor connected from FADJ to GND. Typical Performance Characteristics Efficiency vs Load Current (FPWM = Low, VOUT = 3.3V) Efficiency (FPWM = High, Input Voltage = 16V VOUT = 2.9V) DS100937-11 www.national.com DS100937-12 4 Typical Performance Characteristics (Continued) Quiscent Supply Current vs Supply Voltage (Not Switching, FPWM = Low, VOUT = 2.0V) Quiscent Supply Current vs Supply Voltage (FPWM = Low, VOUT = 3.3V) DS100937-15 Supply Current vs Oscillator Frequency (FPWM = High) DS100937-16 Oscillator Frequency vs Adjusting Resistor DS100937-18 DS100937-17 Oscillator Frequency vs Junction Temperature Reference Voltage vs Junction Temperature DS100937-13 DS100937-14 5 www.national.com Connection Diagram and Ordering Information 20-Lead TSSOP (MTC) DS100937-2 Top View Order Number LM2631MTC-ADJ See NS Package Number MTC20 Pin Description Pin Name Function 1 SD 2 SYNC Oscillator synchronization input. Connect this pin to ground if not used. 3 PGOOD A constant monitor on the output voltage. PGOOD will go low if the output voltage exceeds ± 9% of its nominal value. Once PGOOD goes low, it will go high if the output moves within ± 3% of its nominal value. 4 SS The soft-start control pin. A capacitor connected from this pin to ground sets the ramp time to full current output. 5 COMP Compensation network connection (connected to the output of the voltage error amplifier). 6 FB Output voltage feedback input (connected to the center of the external resistor divider). 7 FADJ Frequency adjustment input. 8 VREF The output of the precision reference. 9 GND Low-noise analog ground. 10 CSH Current-sense positive input. 11 CSL Current-sense negative input. 12 NC No internal connection. 13 VIN Main power supply pin. 14 NC No internal connection. 15 FPWM When FPWM is high, pulse-skipping mode operation at light load is disabled. The converter is forced to operate in constant frequency mode. 16 PGND Power ground. 17 LDRV Low-side gate-drive output. 18 CBOOT Bootstrap capacitor connection for high-side gate drive. 19 SW Switched-node connection, which is connected with the source of the high-side MOSFET. 20 HDRV High-side gate-drive output. HDRV is a floating drive output that rides on SW voltage. www.national.com Shutdown control input, active low. 6 Block Diagram DS100937-3 FIGURE 1. LM2631 Block Diagram reaches the control level set by the error amplifier, the PWM comparator reset the driver logic to turn off the high-side switch; the low-side switch is turned on after certain delay (the voltage at the SW pin is sensed and the low-side switch is turned on once the SW pin voltage reaches zero. A preset maximum delay is 100 ns). The low-side switch stays on until the end of the cycle or until the inductor current reaches zero; when this occurs, the zero cross detector will disable the low-side driver to turn off the low-side switch. The zero cross detector is disabled in FPWM mode. For any peak current mode step-down converter, a compensation ramp is needed to avoid subharmonic oscillations Operation Basic Operation of the Current Mode Controlled Switching Regulator The main control loop includes the error amplifier, the current amplifier and PWM comparator (as shown in Figure 1). During heavy load or any load with FPWM mode enabled, the controller is in constant frequency current mode operation: the high-side switch is turned on at the beginning of each clock cycle, and the output of the error amplifier is compared with the sensed inductor current ramp; once the ramp 7 www.national.com Operation Frequency Control Pin (FADJ) and SYNC Pin With the FADJ pin open, the switching frequency is 200 kHz. The frequency can be increased by connecting a resistor between FADJ and ground. The device can also be synchronized with an external CMOS or TTL logic clock in the range from 200 kHz to 400 kHz. It is recommended to connect the SYNC pin to ground if not used. (Continued) when the duty cycle is higher than 50%. For the LM2631, this compensation ramp is internally set to equal the maximum down slope of the current amplifier output: Protections The current limit comparator provides the cycle-by-cycle current limit function by turning off the high-side MOSFET whenever the sensed current reaches 110 mV. Note that, the current limit voltage will increase when output voltage is less than 1.5V. A second level of current limit is accomplished by the 80% low voltage detector: if the load pulls the output voltage down below 80% of the nominal value, the device will turn off the high-side MOSFET and turn on the low-side MOSFET. The overvoltage protection comparator will turn on the low-side switch when the output voltage exceeds 120% of the nominal value. Both protection features are disabled during start-up. All latched conditions can be reset by shutting the device down and then powering it up. Built-in undervoltage lockout circuit will keep most of the internal function blocks off until the input voltage rises to about 3.5V. Where n = 5 is the gain of the current sense amplifier. The maximum output voltage equals 6V. Also, a 10 µH inductor and a 0.025Ω sense resistor are assumed to determine the internal compensation ramp. Different values of inductor and sense resistor can be used as long as the resulted MDOWN ( = n x RSEN x VOUT/L) is less than MC. Pulse-Skipping Mode at Light Load Pulse-skipping mode can be enabled by pulling PFWM pin low. This mode decreases switching frequency at light loads to reduce the switching frequency related losses. If PFWM is set at low, the controller goes into the pulse-skipping mode when the sensed inductor current goes below the 25 mV threshold set by the pulse-skipping comparator. In the pulse-skipping mode, the high-side switch only turns on at the beginning of a clock cycle when the voltage at the feedback pin falls below the reference voltage. Once the switch is on, it stays on until the sensed current rises to the 25 mV threshold Soft Start A capacitor at the SS pin provides the soft start feature. When the regulator is first powered up, or when the SD pin goes high, a 10µA current source charges up the SS capacitor from the 0.6V clamping voltage. The switch duty cycle starts with narrow pulses and gradually get wider as the SS pin voltage ramps up to about 1.3V, above which the duty cycle will be controlled by the maximum current limit until the output voltage rises to the nominal value and the regulator starts to operate in the normal current mode PWM control. The LM2631 use a digital counter, referenced to the oscillator frequency, to set the soft start timeout. The timeout is dependent on the switching frequency (timeout = 4096/FS). If the output voltage doesn’t move within the ± 3% window of the nominal value during this period, the device will latch itself off. Fast Transient Response When the output voltage fails to exceed 97% of the nominal level, the low voltage regulation(LREG) comparator will set the PWM logic to turn the high-side switch on at maximum duty cycle. This improves transient response since it bypasses the error amplifier and PWM comparator. During start-up, the LREG is disabled. Boost High-Side Gate Drive A flying capacitor is used to bootstrap the power supply for the high-side driver as illustrated in Figure 1. The boost capacitor is charged from an internal voltage rail (about 5.5V) through an internal diode when the synchronous rectifier (low-side MOSFET) is on, and then boosts up the high-side gate voltage to turn high-side MOSFET on at the beginning of next cycle. The internal diode connecting between the VIN pin and the CBOOT pin reduces the count of external components. For low input voltage application (Vin < 5V), some external charge pump circuitry can be used to boost the gate voltage in order to reduce conduction loss. Details will be discussed in the Application Circuits Section. Power Good The LM2631 provides a power good signal by monitoring the voltage at the FB pin and compared the feedback voltage with the VREF voltage. Once the output voltage exceeds the ± 9% window of the nominal value, the PGOOD pin goes low, and stays low until the output voltage returns to the ± 3% window of the nominal value. Design Procedure Supply Voltage for the LM2631 Guidelines for selecting external components are discussed in this section. When 5V is available, it is recommended to connect LM2631 VIN (pin13) to 5V. This can improve efficiency (see the second figure in Typical Performance Characteristics), and also reduce power dissipation inside the IC. Since the 5V supply is only used to power the LM2631 (including the gate charge for the external MOSFETs), it only requires a small amount of current. Inductor Selection The most critical parameters for the inductor are the inductance, peak current and the dc resistance. The inductance is related to the switching frequency and the ripple current: Reference The 1.238V reference is of ± 2.4% accuracy over temperature. A 220 pF capacitor is recommended between the VREF pin and ground. The load at the VREF pin should not exceed 100µA. www.national.com Higher switching frequency allows smaller inductor, but reduces the efficiency. A higher value of ripple current reduces inductance, but increase the conductance loss, core loss, 8 Design Procedure ward voltage of D1 is less than the body diode, efficiency can be improved. The breakdown voltage rating of D1 is preferred to be 25% higher than the maximum input voltage. Since D1 is only on for a short period of time (about 200 ns each cycle), the average current rating for D1 only requires to be higher than 30% of the maximum output current. It is important to place D1 very close to the drain and source of Q2, extra parasitic inductance in the parallel loop will slow the turn-on of D1 and direct the current through the body diode of Q2. (Continued) current stress for the inductor and switch devices, and requires a bigger output capacitor for the same output voltage ripple requirement. A reasonable value is setting the ripple current to be 30% of the dc output current. Since the ripple current increase with the input voltage, the maximum input voltage is always used to determine the inductance. The dc resistance of the inductor is a key parameter for the efficiency. Lower dc resistance is available with a bigger winding area. A good tradeoff between the efficiency and the core size is letting the inductor copper loss equal to 2% of the output power. R1 and R2 (Programming Output Voltage) Use the following formula to select the appropriate resistor values: VOUT = VREF(1 + R1/R2) where VREF = 1.238V Input Capacitor A low ESR aluminum or tantalum capacitor is needed between the drain of the high-side MOSFET and ground to prevent large voltage transients from appearing at the input. The capacitor is selected based on the RMS current and voltage requirements. The RMS current is given by: Select a value for R2 between 10kΩ and 100kΩ. (Use 1% or higher accuracy metal film resistors). Current sense resistor The value of the sense resistor is determined by the minimum current limit voltage and the maximum peak current. It can be calculated as follows: The RMS current reaches its maximum (IOUT/2) when VIN equals 2VOUT. A parallel of several capacitors may be required to meet the RMS current rating. For an aluminum capacitor, the voltage rating should be at least 25% higher than the maximum input voltage. If a tantalum capacitor is used, the voltage rating should be about twice the maximum input voltage. The tantalum capacitor should also be surge current tested by the manufacturer. It is also recommended to put a small ceramic capacitor (0.1 µF) between the VIN pin and ground. where TF is the tolerance factor of the sense resistor. PCB Layout Considerations Layout is critical to reduce noises and ensure specified performance. The important guidelines are listed as follows: 1. Minimize the parasitic inductance in the loop of input capacitors and MOSFETS: Q1, Q2 by using wide and short traces. This is important because the rapidly switching current, together with wiring inductance can generate large voltage spikes which can cause noise problems. 2. Always minimize the high-current ground traces: such as the traces from PGND pin to the source of Q2, then to the negative terminals of the output capacitors. 3. Use dedicated (Kelvin sense) and short traces from CSH, CSL pins to the sense resistor, R3. Keep these traces away from noise traces (such as SW trace, and gate traces). Output Capacitor The selection of COUT is driven by the maximum allowable output voltage ripple. The output ripple in FPWM mode is approximated by: The ESR term plays the dominant role in determining the voltage ripple. Low ESR aluminum electrolytic or tantalum capacitors (such as Nichicon PL series, Sanyo OS-CON, Sprague 593D, 594D, and AVX TPS) are recommended. Electrolytic capacitors are not recommended for temperature below −25˚C since their ESR rises dramatically at cold temperature. Tantalum capacitors have a much better ESR specification at cold temperatures and are preferred for low temperature applications. 4. 5. 6. Power MOSFETs Two N-channel logic-level MOSFETs are required for this application. MOSFETs with low on-resistance and total gate charge are recommended to achieve high efficiency. The drain-source breakdown voltage ratings are recommended to be 1.2 times the maximum input voltage. Minimize the traces connecting Q2 and the Schottky diode. Any parasitic inductance in the loop can delay the turn-on of the Schottky diode, which diminishes the efficiency gain from adding D1. Minimize the traces from drivers (HDRV pin and LDRV pin) to the MOSFETs gates. Minimize the trace from the center of the output resistor divider to the FB pin and keep it away from noise sources to avoid noise pickup. A dedicated sense trace (separated from the power trace) can be used to connect the top of the resistor divider to the output. The sense trace ensures tight regulation at the output. Application Circuits Schottky Diode D1 A typical application circuit is shown in Figure 2, with some of the components values shown in Table 1. The Schottky diode D1 is used to prevent the intrinsic body diode of the low-side MOSFET Q2 from conducting during the dead time when both MOSFETs are off. Since the for- 9 www.national.com Application Circuits (Continued) DS100937-4 FIGURE 2. The Typical 2.5V Application Circuit TABLE 1. Components for Typical 2.5V, 300kHz Application Circuits Input Voltage 4.75V to 24V Output Current 4A 10A Application Notebook Desktop Q1 and Q2 Fairchild FDS6680; Siliconix Si4410DY; or International Rectifier IRF7805 Fairchild FDB7030L; or Motorola MTB75N03HDL Inductor L1 Sumida CDRH127-7R6: 7.6 µH, 5.9A Pulse PE-53681: 2.5 µH, 11.4A Input Capacitors 2 x 22µF, 35V Sprague 593D or TPS 2 x 220 µF, 10V Sanyo OS-CON SA Output Capacitors 2 x 220µF, 10V Sprague 593D or TPS 3 x 330 µF, 6.3V Sanyo OS-CON SA Rectifier D1 Motorola MBRS140T3 Motorola MBRS340T3 Sensing Resistor R3 15 mΩ IRC R8 = 3.3 KΩ, C8 = 1 nF 3 x 20 mΩ IRC R8 = 4 KΩ, C8 = 1nF Compensation components C8 and R8 4.5V to 6V can be added to double the CBOOT pin voltage (see Figure 3). It can also be added to the VIN pin to increase the gate drive voltage at both high-side and low-side MOSFETs. When the input voltage is low (less than 5V), the bootstrap function cannot deliver enough gate voltage to fully drive the high-side MOSFET on, which increases Rdson, and consequently reduces efficiency. An external charge-pump doubler www.national.com 10 Application Circuits (Continued) DS100937-5 FIGURE 3. High Efficiency, 300 kHz, 5V to 2.5V Converter. Efficiency is 94% (typ) at 1A load. 11 www.national.com LM2631 Synchronous Step-Down Power Supply Controller Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead TSSOP (MTC) Order Number LM2631MTC-ADJ NS Package Number MTC20 LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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