NSC DP83907VF

November 1995
DP83907 AT/LANTIC TM II
General Description
Features
The DP83907 Twisted-Pair Enhanced Coaxial Network Interface Controller is a CMOS VLSI device designed for easy
implementation of CSMA/CD local area networks.
Unique to the DP83907 is the integration of the entire bus
interface for PCAT ISA (Industry Standard Architecture) bus
based systems. Hardware and software selectable options
allow the DP83907’s bus interface to be configured in the
same manner as an NE2000 Architecture. All bus drivers
and control logic are integrated to reduce board cost and
area.
Supported network interfaces include 10BASE5 or
10BASE2 Ethernet via an external transceiver connected to
its AUl port, and Twisted-pair EthernetÉ (10BASE-T) using
the on-board transceiver. The DP83907 provides the Ethernet Media Access Control (MAC), Encode-Decode (ENDEC)
with an AUl interface, and 10BASE-T transceiver functions
in accordance with the lEEE 802.3 standards.
The DP83907’s integrated 10BASE-T transceiver fully complies with the IEEE standard. This functional block incorporates the receiver, transmitter, collision, heartbeat, loopback, jabber, and link integrity blocks as defined in the standard. The transceiver when combined with equalization resistors, transmit/receive filters, and pulse transformers provides a complete physical interface from the DP83907’s
ENDEC module and the twisted pair medium.
(continued)
Controller and integrated bus interface solution for IEEE
802.3, 10BASE5, 10BASE2, and 10BASE-T
Y Software compatible with industry standard Ethernet
Adapters: NovellÉ’s NE2000
Y No external bus logic or drivers needed
Y Supports jumpered or jumperless configuration
Y Provides EEPROM interface for non-volatile storage of
configuration data, user-defined data and Ethernet
Physical Address
Y Allows in-situ programming of EEPROM
Y Integrated controller, ENDEC, and transceiver
Y Full IEEE 802.3 compliant AUI interface
Y Single 5V supply
10BASE-T TRANSCEIVER MODULE:
Y Integrates transceiver functionality
Y Transmitter and receiver functions
Y Collision detect, heartbeat and jabber
Y Selectable link integrity test or link disable
Y Polarity Detection/Correction
Y Auto switch
Y On chip filter
ENDEC MODULE:
Y 10 Mbit/s Manchester encoding/decoding
Y Squelch on receive and collision pairs
MAC/CONTROLLER MODULE:
Y Software compatible with DP8390, DP83901, DP83902
Y Efficient buffer management implementation
IN-CIRCUIT TEST
Y
1.0 System Diagram
TL/F/12082 – 1
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
AT/LANTICTM is a trademark of National Semiconductor Corporation.
EthernetÉ is a registered trademark of Xerox Corporation.
NetWareTM is a trademark of Novell Incorporated.
NovellÉ is a registered trademark of Novell Incorporated.
C1995 National Semiconductor Corporation
TL/F/12082
RRD-B30M115/Printed in U. S. A.
DP83907 AT/LANTIC II
PRELIMINARY
General Description (Continued)
TabIe Of Contents
The integrated ENDEC module allows Manchester encoding and decoding via a differential transceiver and phase
lock loop decoder at 10 Mbit/sec. Also included are a collision detect translator and diagnostic loopback capability.
The ENDEC module interfaces directly to the transceiver
module, and also provides a fully IEEE compliant AUI (Attachment Unit Interface) for connection to other media
transceivers.
The Media Access Control function which is provided by the
Network Interface Control module (NIC) provides simple
and efficient packet transmission and reception control by
means of off-board memory which can be accessed through
an I/O port.
The DP83907 provides a comprehensive solution for
10BASE-T IEEE 802.3 networks. Due to the inherent constraints of CMOS processing, isolation is required at the AUI
differential signal interface for 10BASE5 and 10BASE2 applications.
1.0 SYSTEM DIAGRAM
1.1 Connection Diagram
2.0 PIN DESCRIPTION
3.0 SIMPLIFIED APPLICATION DIAGRAM
4.0 FUNCTIONAL DESCRIPTION
4.1 Bus Interface Block
4.2 Power on RESET Operation
4.3 EEPROM OperatIon
4.4 Jumperless Operation Support
4.5 Ethernet Cable Configuratlon
4.6 Interrupt AND LED OperatIon
4.7 Boot PROM OperatIon
4.8 DP8390 Core (Network interface Controller)
4.9 Twisted Pair Interface Module
4.10 Encoder/Decoder (ENDEC) Module
5.0 REGISTER DESCRIPTIONS
5.1 Configuration Registers
5.2 NIC Core Registers
5.3 DP8390 Core DMA Registers
6.0 OPERATION OF DP83907
6.1 Transmit/Receive Packet Encapsulation/Decapsulation
6.2 Buffer Memory Access Control (DMA)
6.3 Packet Reception
6.4 Packet TransmissIon
6.5 Loopback DIagnostics
6.6 Memory Arbitration and Bus Operation
6.7 Functional Bus TimIng
7.0 IN-CIRCUIT TEST (ICT) DESCRIPTION
2
Connection Diagram
TL/F/12082 – 2
Order Number DP83907VF
See NS Package Number VF132A
3
2.0 Pin Description
Pin No.
Pin Name
Type
Description
ISA BUS INTERFACE PINS
119 – 127,
132
SA0–SA9
I
TTL
LATCHED ADDRESS BUS: Low-order 10 bits of the system’s latched 20-bit address
bus. These bits are used to decode accesses to the DP83907’s I/O map.
1–7
SA13–SA19
I
TTL
LATCHED ADDRESS BUS: 7 bits of the system’s latched 20-bit address bus that are
used to decode accesses to the DP83907’s boot PROM.
10, 11
SMRD,
SMWR
I
TTL
BOOT PROM STROBES: These inputs are used to access the BOOT PROM.
15, 16, 18
19, 21, 22
24, 25, 98
99, 101, 102,
104, 105, 107,
108
SD0–SD7
SD8–SD15
I/O
3ST
SYSTEM DATA BUS: 16-bit system data bus. Used to transfer data between the
system and the DP83907.
118
IOCS16
O
OCH
16 BIT I/O TRANSFER: This signal indicates that the DP83907 is responding to a 16bit I/O access by driving 16 bits of data on the bus.
9
IOWR
I
TTL
I/O WRITE STROBE: Strobe from system to write to the DP83907’s I/O map.
8
IORD
I
TTL
I/O READ STROBE: Strobe from system to read from the DP83907’s I/O map.
30
RESET
I
TTL
RESET: This signal is output by the system to reset all devices on the bus.
13
CHRDY
O
OCH
CHANNEL READY: This signal is used to insert wait states into system accesses.
12
AEN
I
TTL
DMA ACTIVE: This signal indicates that the systems DMA has control of the bus.
29, 111,
112, 114,
115, 128
129, 130
IRQ3, 4, 5, 9, 10,
11, 12, 15
O
3ST
INTERRUPT REQUEST: The operation of these outputs is determined by
Configuration Register A.
Note: Driver Types are: I e Input, O e Output, I/O e Bi-directional Output, OCH e Open Collector, 3ST e TRI-STATEÉ Output, TTL e TTL Compatible,
AUI e Attachment Unit Interface, TPI e Twisted Pair Interface, LED e LED Drive, MOS e CMOS Level Compatible, XTAL e Crystal.
4
2.0 Pin Description (Continued)
Pin No.
Pin Name
Type
Description
NETWORK INTERFACE PINS
44 – 47
TxOd a , TXOb,
TXO a TXOdb
O
TPI
TWISTED PAIR TRANSMIT OUTPUTS: These high drive CMOS level outputs are
resistively combined external to the chip to produce a differential output signal with
equalization to compensate for Intersymbol Interference (ISI) on the twisted pair medium.
42, 43
RXI a , RXIb
I
TPI
TWISTED PAIR RECEIVE INPUTS: These inputs feed a differential amplifier which passes
valid data to the ENDEC module.
33, 34
TXb
TX a
O
AUI
AUI TRANSMIT OUTPUT: Differential driver which sends the encoded data to the
transceiver.
36, 37
RXb
RX a
I
AUI
AUI RECEIVE INPUT: Differential receive input pair from the transceiver.
38, 39
CDb
CD a
I
AUI
AUI COLLISION INPUT: Differential collision pair input from the transceiver.
55
ACTÐled
O
LED
ACTIVITY: An open-drain active low output. It is asserted for approximately 50 ms
whenever the DP83907 transmits or receives data in either AUI or TPI modes.
56
COLÐled
O
LED
COLLISION: An open-drain active low output. It is asserted for approximately 50 ms
whenever the DP83907 detects a collision in either either AUI or TPI modes.
54
GDLNKÐled
O
LED
GOOD LINK: An open-drain active low output. This pin operates as an output to display link
integrity status if this function has not been disabled by the GDLNK bit in Configuratioin
Register B.
This output is off if the DP83907 is in AUI mode or if link testing is enabled and the link
integrity is bad (i.e., the twisted pair link has been broken).
This output is on if the DP83907 is in Twisted Pair interface (TPI) mode, link integrity
checking is enabled and the link integrity is good (i.e., the twisted pair link has not been
broken) or if the link testing is disabled.
53
REQ
I
EQUALIZATION RESISTOR: A resistor can be connected from this pin to GND or VCC to
change the equalization of the TP output.
52
RTX
I
TRANSMIT LEVEL RESISTOR: A resistor can be connected from this pin to GND or VCC to
change the TP output amplitude level.
59
X1 (OSCIN)
I
XTAL
CRYSTAL ON EXTERNAL OSCILLATOR INPUT
58
X2 (OSCOUT)
O
XTAL
CRYSTAL FEEDBACK OUTPUT: Used in crystal connections only. Should be left
unconnected when using an oscillator module.
31
THIN
O
DCDC
THIN CABLE: This output is high if DP83907 is configured for thin cable. It can be used to
enable the DC-DC converter required by the thin Ethernet configuration.
Note: Driver Types are: I e Input, O e Output, I/O e Bi-directional Output, OCH e Open Collector, 3ST e TRI-STATE Output, TTL e TTL Compatible,
AUI e Attachment Unit Interface, TPI e Twisted Pair Interface, LED e LED Drive, MOS e CMOS Level Compatible, XTAL e Crystal.
5
2.0 Pin Description (Continued)
Pin No.
Pin Name
Type
Description
EXTERNAL MEMORY SUPPORT
87 – 94
MSD0 – 7 or
CA0 – 7 or
DO, DI, SK
I/O – I– O
MOS
77 – 82
85, 86
MSD8 – 15 or
CB0 – 7
I/O – I
MOS
MEMORY SUPPORT DATA BUSÐCONFIGURATION REGISTER B INPUT:
MSD8–15: When RESET is inactive these pins are used to access external memory.
CB0–7: When RESET is active Configuration Register B is loaded with the data value on
these pins. If the user puts an external pull-up on any of these pins then the corresponding
register bit is set to a 1. If the pin is left unconnected then the register bit is 0.
60 – 67
MSA1 – 8 or
CC0 – 7
O–I
MOS
MEMORY SUPPORT ADDRESS BUSÐCONFIGURATION REGISTER C INPUT:
MSA1–8: When RESET is inactive these pins drive the memory support address bus.
CC0–7: When RESET is active Configuration Register C is loaded with the data value on
these pins. If the user puts an external pull-up on any of these pins then the corresponding
register bit is set to a 1. If the pin is left unconnected then the register bit is 0.
68, 69
71 – 73
MSA9 – 13 or
DWID,
EECONFIG
and SIG 5–7
O–I
MOS
MEMORY SUPPORT ADDRESS BUSÐDWID, EECONFIG AND SIGNATURE REGISTER:
MSA9–13: When RESET is inactive these pins drive the memory support address bus.
DWID (MSA9): When RESET is active this input specifies whether the DP83907 is interfacing
to an 8-bit or 16-bit ISA bus. If the user puts an external pull-up on this pin then the bus is
considered to be 16-bit. If the pin is left unconnected then the bus is considered to be 8-bit.
EECONFIG(MSA10): When RESET is active this input specifies whether the DP83907 loads
the configuration from an EEPROM or from the MSD0 – 15 and MSA1 – 8 pins. If the user puts
an external pull-up on this pin then configuration data is loaded from the EEPROM. If the pin
is left unconnected then configuration data is loaded from the memory support bus.
SIG 5–7(MSA11–13): When RESET is active the most significant 3 bits of the signature
register are loaded with the data value on these pins. If the user puts an external pull-up on
any of these pins then the corresponding register bit is set to a 1. If the pin is left
unconnected then the register bit is 0.
76
MSRD
O
MOS
MEMORY SUPPORT BUS READ: Strobes data from the external RAM into the DP83907 via
the memory support data bus.
74
MSWR
O
MOS
MEMORY SUPPORT BUS WRITE: Strobes data from the DP83907 into the external RAM
via the memory support data bus.
MEMORY SUPPORT DATA BUSÐCONFIGURATION REGISTER A INPUT: EEPROM
SIGNALS:
MSD0–7: When RESET is inactive these pins are used to access external memory and boot
PROM.
CA0–7: When RESET is active Configuration Register A is loaded with the data value on
these pins. If the user puts an external pull-up on any of these pins then the corresponding
register bit is set to a 1. If the pin is left unconnected then the register bit is 0.
DO, DI, SK: When RESET goes from an active to an inactive level DP83907 will read the
contents of a serial EEPROM, using these signals, and load the contents into internal
registers. These internal registers are mapped into the space taken up by the PROM in the
NE2000 Architecture. After the EEPROM read operation has completed these pins will revert
to MSD0–2 (D0 e MSD0, DI e MSD1, SK e MSD2).
Note: Driver Types are: I e Input, O e Output, I/O e Bi-directional Output, OCH e Open Collector, 3ST e TRI-STATE Output, TTL e TTL Compatible,
AUI e Attachment Unit Interface, TPI e Twisted Pair Interface, LED e LED Drive, MOS e CMOS Level Compatible, XTAL e Crystal.
6
2.0 Pin Description (Continued)
Pin No.
Pin Name
Type
Description
EXTERNAL MEMORY SUPPORT (Continued)
95
RCS
O
MOS
RAM CHIP SELECT: Drives the chip select of the external RAM.
97
BPCS
O
MOS
BOOT PROM CHIP SELECT: Selects the boot PROM on the memory support data bus.
This is for READ only.
96
EECS
O
MOS
EEPROM CHIP SELECT: Strobes data from the EEPROM onto the memory support
data bus.
POWER SUPPLY PINS
40
AVCC
ANALOG 5V SUPPLY PIN: This pin supplies 5V to the DP83907’s analog circuitry. To
maximize data recovery it is recommended that analog layout and decoupling rules be
applied between this pin and AGND.
41
AGND
ANALOG NEGATIVE (GROUND) SUPPLY PIN.
35, 48
XVCC, TPVCC
PHYSICAL MEDIA 5V SUPPLY PINS: This pin supplies 5V to the DP83907’s analog
physical media interface circuitry.
32, 49
XGND, TPGND
PHYSICAL MEDIA NEGATIVE (GROUND) SUPPLY PINS: This pin is the ground to the
DP83907’s analog physical media interface circuitry.
26, 109
coreVCC
POSITIVE 5V SUPPLY PINS: These pins suppy power to the DP83907.
27, 110
coreGND
NEGATIVE (GROUND) SUPPLY PINS: These are the supply pins for the DP83907. It is
suggested that decoupling capacitors be connected between the VCC and GND pins. It
is essential to provide a path to ground for the GND pins with the lowest possible
impedance.
20, 70, 103
VCC
POSITIVE 5V SUPPLY PINS: These pins supply power to the DP83907 Output Drivers
e.g., SD, MSD, MSA, Chip selects.
14, 17, 23,
28, 57, 75,
100, 106,113,
116, 131
GND
NEGATIVE (GROUND) SUPPLY PINS: These are the supply pins for the DP83907
Drivers. It is suggested that decoupling capacitors be connected between the VCC and
GND pins. It is essential to provide a path to ground for the GND pins with the lowest
possible impedance.
Note: Driver Types are: I e Input, O e Output, I/O e Bi-directional Output, OCH e Open Collector, 3ST e TRI-STATE Output, TTL e TTL Compatible,
AUI e Attachment Unit Interface, TPI e Twisted Pair Interface, LED e LED Drive, MOS e CMOS Level Compatible, XTAL e Crystal.
7
3.0 Simplified Application Diagram
TL/F/12082 – 3
8
3.0 Simplified Application Diagram (Continued)
TL/F/12082 – 4
FIGURE 1. Block Diagram of DP83907
4.0 Functional Description
Bus. The bus interface provides an NE2000 Architecture
compatible I/O port architecture, supporting both 8-bit and
16-bit wide ISA Bus slots.
The DP83907 is a highly integrated and configurable Ethernet controller making it suitable for most Ethernet applications. The DP83907 integrates the functions of the following
blocks:
1. ISA Bus Interface containing all logic required to connect
the DP8390 core to a packet buffer RAM and the ISA
bus.
2. DP8390 Ethernet Controller Core and Media Access
Control logic.
3. Media Interface which includes a TPI transceiver.
DETERMINING 8-BIT OR 16-BIT WIDE DATA
DP83907 can treat the system data bus and all internal data
busses as 8 bits or 16 bits wide. 8-bit or 16-bit mode is
determined by MSA9 at reset. For an adapter card this pin
can be used to automatically detect if the card has been
plugged into an 8-bit or 16-bit slot by connecting MSA9 via a
10 kX pull-up resistor to a VDD on the upper connector. It
will be pulled high when plugged into a 16-bit slot, enabling
16-bit mode, and floating when plugged into an 8-bit slot.
When floating the internal pull-down resistor will enable 8-bit
mode.
4.1 BUS INTERFACE BLOCK
The DP83907’s Bus interface block provides the circuitry to
interface the Ethernet controller logic and the external packet buffer RAM to an ISA (Industry Standard Architecture)
9
4.0 Functional Description (Continued)
The DP83907 register space within this area are 8 bits wide,
but the data transfer port is 16 bits wide. The DP83907’s
registers can be programmed to control the passing of data
between its internal memory and the data transfer port. By
accessing the data transfer port (using I/O instructions) the
user can transfer data to or from the DP83907’s internal
memory. The DP83907’s internal memory map is as shown
below.
D15
0000h
D0
00
001Fh
PROM
Aliased PROM
4000h
FIGURE 2. I/O Port
The DP83907’s internal memory map is accessed one byte
or word at a time, via a port within the systems I/O space.
DP83907 is programmed by the user to control the transfers
between its internal memory and the I/O port. The
DP83907’s internal registers and the memory access port
are accessed within the system’s I/O map. The address
within this I/O map is, set by Configuration Register A.
8000h
Aliased PROM
C000h
Aliased
Buffer RAM
FFFh
16-BIT I/O PORT COMPATIBLE MODE I/O ADDRESS
MAPPING
This mode is compatible with Novell’s NE2000 Architecture.
The base I/O address of DP83907 is configured by Configuration Register A (either upon power up or by software writing to this register). At the base I/O address the following
stwcture appears.
(a)
D15
D0
001Eh
00
57h
001Ch
00
57h
Base a 00h
DP8390
Core
Register
Base a 0Fh
Base a 10h
Base a 17h
8k x 16
Buffer RAM
7FFFh
TL/F/12082–5
Data Transfer
Port
#
#
00
RESERVED
#
#
00Ah
00
E’net Address 5
0008h
00
E’net Address 4
0006h
00
E’net Address 3
0004h
00
E’net Address 2
0002h
00
E’net Address 1
0000h
00
E’net Address 0
(b)
FIGURE 4. a) NIC Core’s 16-Bit Memory Map
b) 16-Bit PROM Map
DP83907 has a 64k address range but only does partial
decoding through this space. The PROM data is mirrored
from all decodes up to 4000H and the entire map is repeated at 8000H. To access either the PROM or the RAM the
user must initiate a Remote DMA transfer between the I/O
port and memory.
Base a 18h
Reset Port
Base a 1Fh
FIGURE 3. I/O Port Mode Register I/O Map
10
4.0 Functional Description (Continued)
On a remote read the DP83907 moves data from its internal
memory map to the I/O port and the host system reads it by
using an ‘‘INW’’ or ‘‘INSW’’ instruction from the I/O address
of the data transfer port. If the system attempts to read the
port before DP83907 has written the next word of data to it
DP83907 will insert wait states into the system cycle using
the CHRDY line. DP83907 will not begin the next memory
read until the previous word of data has been read.
On a remote write the system writes data to the I/O port,
using an ‘‘OUTW’’ or ‘‘OUTSW’’ instruction, and DP83907
moves it to its buffer memory. If the system attempts to
write to the port before DP83907 has moved the data to
memory, DP83907 will insert wait states into the system cycle using the CHRDY line. DP83907 will not begin the next
memory write until a new word has been written to the I/O
port.
Addresses 00H to 1FH are specified as the PROM space
for compatibility with the NE2000 Architecture. This is actually an array of 8-bit registers which are loaded from an
external EEPROM after DP83907 is initialized by an ISA RESET. They should contain the same data as the PROM did
in the NE2000 Architecture and in the same format. To
transfer the data out the user must initiate a 16-bit DMA
read transfer and discard the most significant byte of data
on each transfer.
At address 00H of the PROM is a six byte Ethernet address
for this node. The upper two addresses of the PROM store
contain bytes which identify whether the DP83907 is in 8-bit
or 16-bit mode. For 16-bit mode these bytes both contain
the value 57H, for 8-bit mode they both contain 42H.
0000h
0020h
PROM
Aliased PROM
4000h
8k x 8 BUFFER RAM
6000h
RESERVED
7FFFh
(a)
D15
8-BIT I/O PORT COMPATIBLE MODE
This mode is compatible with the 8-bit mode offered by Novells NE2000 Architecture. The NE2000 automatically detects whether it is in an 8-bit or 16-bit slot and configures
itself appropriately. As explained in the previous paragraphs, the user can determine whether the board is in 8-bit
or 16-bit mode by reading the PROM. In 8-bit mode only
8 Kbytes of RAM are addressable, as in the 8-bit mode of
the NE2000 Architecture. The I/O map is the same as the
16-bit mode, the memory map is shown in Figure 5 . Again
the PROM has only a partial decode, so is mirrored at all
addresses up to 4000H. The PROM still occupies 32 bytes
of address space, although it only has 16 bytes of data, as
the data at all odd address locations is merely a mirror of
the data at the previous even address location.
A low cost card, using only one 8 Kbyte RAM, can be designed. If the function on MSA9 is left unconnected, then
the DP83907 will always operate in 8-bit mode, regardless
of the slot the board is in.
D0
1Eh
42h
42h
1Ch
42h
42h
#
#
RESERVED
RESERVED
#
#
0Ah
E’net Address 5
E’net Address 5
08h
E’net Address 4
E’net Address 4
06h
E’net Address 3
E’net Address 3
04h
E’net Address 2
E’net Address 2
02h
E’net Address 1
E’net Address 1
00h
E’net Address 0
E’net Address 0
(b)
FIGURE 5. a) 8-Bit NIC Core’s Memory Map
b) 8-Bit PROM Map
4.2 POWER ON RESET OPERATION
The DP83907 configures itself after a Reset signal is applied. To be recognized as a valid Power-On-Reset the Reset signal must be active for at least 415 ms. Figure 6 shows
how the RESET circuitry operates.
TL/F/12082 – 6
FIGURE 6. RESET Operation
11
4.0 Functional Description (Continued)
The ISA standard determines that within 500 ns of RESET
going active all devices should enter the appropriate reset
condition. The DP83907 will generate the internal signal
IOinactive after RESET has been active for 400 ns, which
will disable all outputs and cause RESET to be the only
input monitored. The DP83907 will not respond to a RESET
pulse of shorter duration than this. An internal timer continues to monitor the amount of time RESET is active. After
415 ms it is considered a valid Power-On-Reset and an internal signal called RegLoad is generated.
When a Power-On-Reset occurs the DP83907 latches in the
values on the configuration pins and uses these to configure
the internal registers and options. Internally these pins contain pull-down resistors, which are enabled when IOinactive
goes active. If any pins are unconnected they default to a
logic zero. The intemal pull-down resistor has a high resistance to allow the external pull-up resistors to be of a high
value. This limits the current taken by the memory support
bus. The suggested external resistor value is 10 kX. The
configuration registers are loaded from the memory support
bus when RESET goes inactive if RegLoad is active. The
internal pull-down resistors are enabled onto the bus until
RegLoad has gone inactive.
A Power-On-Reset also causes the DP83907 to load the
internal PROM space from the EEPROM, which can take up
to 320 ms. This occurs after RegLoad has gone inactive.
The DP83907 will be inaccessible during this time. If
EECONFIG is held high the configuration data loaded on
the falling edge of RESET will be overwritten with data read
from the serial EEPROM. Regardless of the level on
EECONFIG, the PROM space will always be loaded with
data from the serial EEPROM during the time specified
as EELoad.
Mapping EEPROM into PROM Space
Data is read from the EEPROM at boot time and stored in
registers within the DP83907. While this operation takes
place the DP83907 can not be accessed by the system.
These registers are mapped into the space traditionally occupied by the PROM in the NE2000
The user should program the EEPROM to contain the Ethernet address in the first six bytes and whatever is required in
the next 8 bytes. The user should then program 5757H and
4242H into address 07h and 08h respectively. The
DP83907 device driver may determine that this is a 16-bit
board by checking this value.
The DP83907 reads the first 8 words from the EEPROM and
maps them into the memory map at the appropriate address.
In Circuit ProgrammIng the EEPROM
If the upper byte of address 0Fh in the EEPROM does not
contain 073H then the DP83907 enters a mode that allows
the EEPROM contents to be programmed. This can be used
in production to program the EEPROM in-situ. By programming 073H into the uppermost byte the EEPROM is protected from future adaptation, except for configuration data
which can always be modified.
If the EEPR bit of the Signature Register is low the
EEPROM program mode may be entered. The EEPR bit is
low if the EEPROM code is not programmed as 73H. In this
mode, if the EELOAD bit of Configuration Register B is set
the user can directly control the EEPROM signals by writing
to the Data Transfer Port. The user can write to the Data
Transfer Port and the value on the SD3, SD2 and SD1 pins
will be driven onto the EECS, SK and DI outputs. These
outputs will be latched. The user can generate a clock on
SK by repetitively writing 1 then 0 to the appropriate bit. This
can be used to generate the EEPROM signals, as per the
NM93C06 data sheet.
When the EEPROM has been programmed the user must
give the DP83907 a reset signal to return to normal operation and to read in the new data.
4.3 EEPROM OPERATION
The DP83907 uses an NMC93C06, or another serial
EEPROM with compatible timings. The NMC93C06 is a 256bit device, arranged as 16 words by 16 bits wide. The programmed contents of the EEPROM is shown in Figure 7 .
D15
D0
0Fh
EEPROM Code
Config. C
0Eh
Config. B
Config. A
#
#
#
#
#
#
08h
42h
42h
07h
57h
57h
#
#
#
#
#
#
03h
Reserved
Reserved
02h
E’net Address 5
E’net Address 4
01h
E’net Address 3
E’net Address 2
E’net Address 1
E’net Address 0
00h
Storing and Loading Configuration from EEPROM
If the EECONFIG function on MSA10 is high during boot up
the DP83907’s configuration is read from the EEPROM, before the PROM data is read. The configuration data is stored
within the upper two words of the EEPROM’s address
space. Configuration Registers A and B are located in the
lower of these words, Register C in the lower byte of the
upper word, as shown in Figure 7 .
To write this configuration into the EEPROM the user must
follow the routine specified in the pseudo code below. If the
EEPROM code byte in the EEPROM is programmed as 73H
the Configuration Registers may be written to in the
EPROM. This operation will work regardless of the level on
EECONFIG. The EELOAD bit of Configuration Register B
being set starts the EEPROM write process. Care should be
taken not to accidentally set the GDLlNK bit and therefore
disable link integrity checking. The next 3 writes to this register load the values that will be stored in the configuration
register (note that the last 2 of these writes do not have to
follow the normal practice of preceding a write to this register with a read to this address). The DP83907 will then commence the EEPROM write. The write has been completed
when the EELOAD bit goes to zero. This loading proce-
FIGURE 7. EEPROM Programming Map
12
4.0 Functional Description (Continued)
type of cabling used is controlled by Configuration Register
B. DP83907 also supplies a THIN output signal which can
be used to disable/enable an external DC-DC converter
which is required for 10BASE2.
dure should be followed exactly and interrupts should be
disabled until it has completed, to prevent any accidental
accesses to the DP83907.
EEPROM LOAD()
4.6 INTERRUPT AND LED OPERATION
The DP83907 has only one Interrupt Mode. There are 8
possible interrupts. Configuration Register A controls which
of the 8 interrupt lines are driven, the others are TRI-STATE.
The interrupt outputs should be connected to the following ISA Interrupt lines, In the order given, to maintain NE2000 Architecture compatibility: 3, 4, 5, 9, 10, 11,
12, 15.
À
DISABLE INTERRUPTS();
value 4 READ(CONFIG B);
value 4 value AND ! GDLINK;
value 4 value OR EELOAD;
WRITE(CONFIG B, value);
READ(CONFIG B);
WRITE(CONFIG B, config for A);
WRITE(CONFIG B, config for B);
WRITE(CONFIG B, config for C);
while (value AND EELOAD)
4.7 BOOT PROM OPERATION
The DP83907 supports an optional boot PROM, the address and size of which can be set in Configuration Register
C. This boot PROM can be any 8-bit wide storage device
implemented with a non-volatile technology. Write cycles to
this device can be enabled and disabled by programming
Configuration Register B. This can be used to prevent unwanted write cycles to certain devices, such as a Flash
EEPROM. The DP83907 supplies the chip select to the device and buffers the data on to and from the ISA bus, so the
memory support data bus should be connected to the boot
PROM’s data pins.
À
value 4 READ(CONFIG B);
WAIT();
Ó
ENABLE INTERRUPTS();
Ó
4.8 DP8390 CORE (NETWORK INTERFACE CONTROLLER)
The DP8390 Core logic, Figure 12 , contains the Serializer/
Deserializer which is controlled by the Protocol PLA, DMA
Control, FIFO, Address Comparator and Multicast Hashing
Register. The DP8390 core implements all of the IEEE
802.3 Media access control functions for the DP83907 and
interfaces to the internal ENDEC (on the left of the block
diagram) and to the Bus Interface and memory support bus
via a number of address, data and control signals (the right
side of the block diagram). The following sections describe
the functions of the DP8390 core.
4.4 JUMPERLESS OPERATION SUPPORT
One of the biggest problems in installing new adapters in a
PC is not knowing the available resources within that machine. DP83907’s software configuration overcomes that
problem. The conflicts possible in the I/O base selection
can be overcome by a special mode for software configuration of the I/O base address. By using this mode, and by
using the configuration storage capability of the EEPROM, a
fully software configurable design on the ISA bus can be
realized without address conflict problems.
This mode is invoked by having the DP83907 default to
jumperless software configuration option in the I/O base
selection. This mode enables configuration register A to be
mapped to address location 278H which is defined to be a
printer port’s data register. If software writes to this location
four consecutive times, on the fourth write the DP83907 will
load the data written into the I/O address bits of Configuration Register A. This data should set the I/O base address
to a known conflict-free value. The DP83907 can now be
configured and operated at the desired base I/O address. If
desired, the configuration software could change the
EEPROM content to the new values eliminating the need to
reconfigure upon each power up. Alternately the software
could leave the EEPROM alone and execute the configuration using the printer port’s data register upon each power
up. This configuration scheme will only work once after
each power-up. Therefore the user can not enable the
DP83907 from reserved mode, change it back into reserved
mode and enable it again. A power-on reset must occur
between the first time it is enabled from the reserved mode
and the second.
Receive Deseriallzer
The Receive Deserializer is activated when the input signal
Carrier Sense is asserted to allow incoming bits to be shifted into the shift register by the receive clock. The serial
receive data is also routed to the CRC generator/checker.
The Receive Deserializer includes a synch detector which
detects the SFD (Start of Frame Delimiter) to establish
where byte boundaries within the serial bit stream are located. After every eight receive clocks, the byte wide data is
transferred to the 16-byte FIFO and the Receive Byte Count
is incremented. The first six bytes after the SFD are
checked for valid comparison by the Address Recognition
Logic. If the Address Recognition Logic does not recognize
the packet, the FlFO is cleared.
CRC Generator/Checker
During transmission, the CRC logic generates a local CRC
field for the transmitted bit sequence. The CRC encodes all
fields after the SFD. The CRC is shifted out MSB first follow-
4.5 ETHERNET CABLE CONFIGURATION
DP83907 offers the choice of all the possible Ethernet cabling options, that is Ethernet (10BASE5), Thin Ethernet
(10BASE2) and Twisted-pair Ethernet (10BASE-T). The
13
4.0 Functional Description (Continued)
TL/F/12082 – 7
FIGURE 12. DP8390 Core Simplified Block Diagram
If any one of the six bytes does not match the pre-programmed physical address, the Protocol Control Logic rejects the packet. All multicast destination addresses are filtered using a hashing technique. (See register description.)
If the multicast address indexes a bit that has been set in
the filter bit array of the Multicast Address Register Array
the packet is accepted, otherwise it is rejected by the Protocol Control Logic. Each destination address is also checked
for all 1’s which is the reserved broadcast address.
ing the last transmit byte. During reception the CRC logic
generates a CRC field from the incoming packet. This local
CRC is serially compared to the incoming CRC appended to
the end of the packet by the transmitting node. If the local
and received CRC match, a specific pattern will be generated and decoded to indicate no data errors. Transmission
errors result in different pattern and are detected, resulting
in rejection of a packet.
Transmit Serializer
The Transmit Serializer reads parallel data from the FIFO
and serializes it for transmission. The serializer is clocked by
the transmit clock generated internally. The serial data is
also shifted into the CRC generator/checker. At the beginning of each transmission, the Preamble and SFD Generator append 62 bits of 1,0 preamble and a 1,1 synch pattern.
After the last data byte of the packet has been serialized the
32-bit FCS (Frame Check Sequence) field is shifted directly
out of the CRC generator. In the event of a collision the
Preamble and SFD generator is used to generate a 32-bit
JAM pattern of all 1’s.
FIFO and Packet Data Operations
OVERVIEW
To accommodate the different rates at which data comes
from (or goes to) the network and goes to (or comes from)
the packet buffer memory, the DP83907 contains a 16-byte
FIFO for buffering data between the media and the buffer
RAM located on the memory support bus. The FIFO threshold is programmable. When the FIFO has filled to its programmed threshold, the local DMA channel transfers these
bytes (or words) into local memory (via the memory bus). It
is crucial that the local DMA is given access to the bus
within a minimum bus latency time; otherwise a FIFO underrun (or overrun) occurs.
Comparator-Address Recognition Logic
The address recognition logic compares the Destination Address Field (first 6 bytes of the received packet) to the Physical address registers stored in the Address Register Array.
14
4.0 Functional Description (Continued)
mine whether the packet matches its Physical Address Registers or maps to one of its Multicast Registers. This causes
the FIFO to accumulate 8 bytes. Furthermore, there are
some synchronization delays in the DMA PLA. Thus, the
actual time that a request to access the buffer RAM is asserted from the time the Start of Frame Delimiter (SFD) is
detected is 7.8 ms. This operation affects the bus latencies
at 2 and 4 byte thresholds during the first receive request
since the FIFO must be filled to 8 bytes (or 4 words) before
issuing a request to the buffer RAM.
FIFO underruns or overruns are caused when a local DMA
request is issued while an ISA bus access is current and the
ISA cycle takes longer to complete than the local DMA’s
tolerable latency. This tolerable latency depends on the
FIFO threshold, whether it is in byte or word wide mode and
the speed of the DMA clock (BSCLK frequency). Note that
this refers to standard ISA cycles, NOT those where the
CHRDY is deasserted extending the cycle.
FIFO THRESHOLD DETECTION
To assure that no overwriting of data in the FIFO, the FIFO
logic flags a FIFO overrun as the 13th byte is written into the
FIFO, effectively shortening the FIFO to 13 bytes. The FIFO
logic also operates differently in Byte Mode and in Word
Mode. In Byte Mode, a threshold is indicated when the n a 1
byte has entered the FIFO; thus, with an 8 byte threshold,
the DP83907 issues a request to the buffer RAM when the
9th byte has entered the FIFO, making the effective threshold 9 bytes. For Word Mode, the request is not generated
until the n a 2 bytes have entered the FIFO. Thus, with a 4
word threshold (equivalent to 8 byte threshold), a request to
the buffer RAM is issued when the 10th byte has entered
the FIFO, making the effective threshold 10 bytes.
END OF RECEIVE
When the end of a packet is detected by the ENDEC module, the DP83907 enters its end of packet processing sequence, emptying its FIFO and writing the status information
at the beginning of the 1st buffer. The DP83907 holds onto
the memory bus for the entire sequence. The longest time
that local DMA will hold the buffer RAM occurs when a
packet ends just as the DP83907 performs its last FIFO
burst. The DP83907, in this case, performs a programmed
burst transfer followed by flushing the remaining bytes in the
FIFO, and completed by writing the header information to
the buffer memory. The following steps occur during this
sequence.
1. DP83907 issues request to access the RAM because the
FIFO threshold has been reached.
2. During the burst, the packet ends, resulting in the request being extended.
3. DP83907 flushes remaining bytes from FIFO.
4. DP83907 performs internal processing to prepare for
writing the header.
5. DP83907 writes 4-byte (2-word) header
6. DP83907 de-asserts access to the buffer RAM.
TOLERABLE LATENCY CALCULATION
To prevent a FIFO overrun a byte (or word) of data must be
removed from the FIFO before the 13th byte is written.
Therefore the worst case tolerable latency is the time from
the effective threshold being reached to the time the 13th
byte is written minus the time taken to load the first byte (or
word) of data to the FIFO during a local DMA burst (8
BSCLKs).
tolerable latency e ((overrun b effective) threshold
c time to transfer byte on network)
b time to fill 1st FIFO location
BEGINNING OF TRANSMIT
Before transmitting, the DP83907 performs a prefetch from
memory to load the FIFO. The number of bytes prefetched
is the programmed FIFO threshold. The next request to the
buffer RAM is not issued until after the DP83907 actually
begins transmitting data, i.e., after SFD.
For the case of a 4 word threshold using a 20 MHz BSCLK:
tolerable latency e ((13 b 10) c 800) b (8 c 50) ns
e 2 ms
To prevent a FIFO underrun a byte (or word) of data must
be added to the FIFO before the last byte is removed.
Therefore the worst case tolerable latency is the time from
the effective threshold being reached to the time the last
byte is removed minus the time taken to load the first byte
(or word) of data to the FIFO during a local DMA burst (8
BSCLKs).
tolerable latency e (threshold
READING THE FIFO
If the FIFO is read during normal operation the DP83907 will
‘‘hang’’ the ISA bus by deasserting CHRDY and never asserting it. The FIFO should only be read during loopback
diagnostics.
PROTOCOL PLA
The protocol PLA is responsible for implementing the IEEE
802.3 protocol, including collision recovery with random
backoff. The Protocol PLA also formats packets during
transmission and strips preamble and synch during reception.
c time to transfer byte on network)
b time to fill 1st FIFO location
For the case of a 4 word threshold using a 20 MHz BSCLK:
tolerable latency e (4 c 800) b (8 c 50) ns
e 2.8 ms
The worst case latency, either overrun or underrun, ultimately limits the overall latency that the DP83907 can tolerate. If the standard ISA cycles are shorter than the worst
case latency, then no FIFO overruns or underruns will occur.
DMA AND BUFFER CONTROL LOGIC
The DMA and Buffer Control Logic is used to control two
16-bit DMA channels. During reception, the Local DMA
stores packets in a receive buffer ring, located in buffer
memory. During transmission the Local DMA uses programmed pointer and length registers to transfer a packet
from local buffer memory to the FIFO.
BEGINNING OF RECEIVE
At the beginning or reception, the DP83907 stores the entire
Address field of each incoming packet in the FIFO to deter-
15
4.0 Functional Description (Continued)
TL/F/12082 – 8
FIGURE 13. Twisted Pair Interface Module Block Diagram
b) The Collision function checks for simultaneous transmission and reception of data on the TXO g and RXI g pins.
A second DMA channel (Remote DMA) is used as a slave
DMA to transfer data between the local buffer memory and
the host system. The Local DMA and Remote DMA are internally arbitrated, with the Local DMA channel having highest priority. Both DMA channels use a common external bus
clock to generate all required bus timing. External arbitration
is performed with a standard bus request, bus acknowledge
handshake protocol.
c) The Link Detector/Generator checks the integrity of the
cable connecting the two twisted pair MAUs.
d) The Jabber disables the transmitter if it attempts to
transmit a longer than legal packet.
e) The TX Driver and Pre-emphasis transmits Manchester
encoded data to the twisted pair network via the summing resistors and transformer/filter.
4.9 TWISTED PAIR INTERFACE MODULE
The TPI consists of five main logical functions:
a) The Receiver/Smart Squelch, responsible for determining when valid data is present on the differential receive
inputs (RXI g ) and receiving the data.
16
4.0 Functional Description (Continued)
Collision
Receiver and Smart Squelch
The DP83907 implements an intelligent receive squelch on
the RXI g differential inputs to ensure that impulse noise on
the receive inputs will not be mistaken for a valid signal.
The squelch circuitry employs a combination of amplitude
and timing measurements to determine the validity of data
on the twisted pair inputs. There are two voltage level options for the smart squelch. One mode, 10BASE-T mode,
uses levels that meet the 10BASE-T specification. The second mode, reduced squelch mode, uses a lower squelch
threshold level, and can be used in longer cable applications where due to attenuation smaller signal levels may be
present. The squelch level mode can be selected in the
DP83907 configuration registers.
A collision is detected by the TPI module when the receive
and transmit channels are active simultaneously. If the TPI
is receiving when a collision is detected it is reported to the
controller immediately. If, however, the TPI is transmitting
when a collision is detected the collision is not reported until
seven bits have been received while in the collision state.
This prevents a collision being reported incorrectly due to
noise on the network. The signal to the controller remains
for the duration of the collision.
Approximately 1 msec after the transmission of each packet
a signal called the Signal Quality Error (SQE) consisting of
typically 10 cycles of 10 MHz is generated. This 10 MHz
signal, also called the Heartbeat, ensures the continued
functioning of the collision circuitry.
Figure 14 shows the operation of the smart squelch in
10BASE-T mode.
The signal at the start of packet is checked by the smart
squelch and any pulses not exceeding the squelch level
(either positive or negative, depending upon polarity) will be
rejected. Once this first squelch level is overcome correctly
the opposite squelch level must then be exceeded within
150 ns later. Finally the signal must exceed the original
squelch level within a further 150 ns to ensure that the input
waveform will not be rejected. The checking procedure results in the loss of typically three bits at the beginning of
each packet.
Only after all these conditions have been satisfied will a
control signal be generated to indicate to the remainder of
the circuitry that valid data is present. At this time the smart
squelch circuitry is reset.
In the reduced squelch mode the operation is identical except that the lower squelch levels shown in the figure are
used.
Valid data is considered to be present until either squelch
level has not been generated for a time longer than 150 ns,
indicating End of Packet. Once good data has been detected the squelch levels are reduced to minimize the effect of
noise causing premature End of Packet detection.
Link Detector/Generator
The link generator is a timer circuit that generates a link
pulse as defined by the 10 Base-T specification that will be
generated by the transmitter section. The pulse which is 100
ns wide is transmitted on the TXO a output, every 16 ms, in
the absence of transmit data.
The pulse is used to check the integrity of the connection to
the remote MAU. The link detection circuit checks for valid
pulses from the remote MAU and if valid link pulses are not
received the link detector will disable the transmit, receive
and collision detection functions.
The GDLNK output can directly drive a LED to show that
there is a good twisted pair link. For normal conditions the
LED will be on. The link integrity function can be disabled by
setting the GDLNK bit of Configuration Register B.
Jabber
The jabber timer monitors the transmitter and disables the
transmission if the transmitter is active for greater than 26
ms. The transmitter is then disabled for the whole time that
the Endec module’s internal transmit enable is asserted.
This signal has to be deasserted for approximately 750 ms
(the unjab time) before the Jabber re-enables the transmit
outputs.
TL/F/12082 – 9
FIGURE 14. Twisted Pair Squelch Waveform
17
4.0 Functional Description (Continued)
Transmitter
The transmitter consists of four signals, the true and compliment Manchester encoded data (TXO g ) and these signals
delayed by 50 ns (TXOd g ).
These four signals are resistively combined TXO a with
TXOdb and TXOb with TXOd a . This is known as digital
pre-emphasis and is required to compensate for the twisted
pair cable which acts like a low pass filter causing greater
attenuation to the 10 MHz (50 ns) pulses of the Manchester
encoded waveform than the 5 MHz (100 ns) pulses.
An example of how these signals are combined is shown in
the following diagram.
TL/F/12082 – 10
FIGURE 15. Typical Summed Transmit Waveform
The signal with pre-emphasis shown above is generated by
resistively combining TXO a and TXOdb. This signal along
with its compliment is passed to the transmit filter.
TL/F/12082 – 11
FIGURE 16a. Circuitry to Connect DP83907 to Twisted Pair Cable with External Filter
18
4.0 Functional Description (Continued)
TL/F/12082 – 52
FIGURE 16b. Circuitry to Connect DP83907 to Twisted Pair Cable with Internal Filter
On-Chip Filters
The on-chip filters are enabled via an external pull-up resistors on MSDk12l at configuration. Only an isolation transformer and impedance matching resistors are needed for
the transmit and receive twisted pair interface.
UTP/STP Function
The TPI transceiver supports both shielded and unshielded
twisted pair cable. UTP is default but STP can be enabled
during configuration by a pull-up on MSAk7l or by setting
bit D6 of configuration register C. In UTP mode TXO a and
TXOD a are driven and TXOb and TXODb are TRI-STATED. In STP mode, TXOb and TXODb are driven and
TXO a and TXOD a are TRI-STATED.
TL/F/12082 – 12
FIGURE 17. Typical DP83907 LED Connection
Status Information
Status information is provided by the DP83907 on the
ACTÐled, COLÐled and GDLNKÐled outputs as described in the pin description table. These outputs are suitable for driving status LED’s as shown in Figure 17 . All outputs are open drain.
Recommended Transformers for Internal Filter mode:
Auto-Switch Function
When an auto-switch function is enabled at configuration by
a pull-up on MSAk5l or by setting bit D4 of the configuration register C, it allows the transceiver to switch between
TP and AUI outputs. If there is an absence of link pulses,
the transceiver will switch to AUI mode. Similarly, when the
transceiver starts detecting link pulses it will switch to TP
mode. The switching from one mode to the next is only
done after the current package has been transmitted or received. If the twisted pair output is jabbering and gets into
link fail state, then the switch to AUI mode is only done after
the jabbering is done, including the time it takes to unjab
(unjab time). When auto-switching is enabled the THIN output is automatically generated if AUI is selected.
1)
2)
3)
4)
5)
6)
19
Valor PT4160
Pulse PE-68029
PCA EPE6087A
Delta THX16B02
Belfus A553-3899-06
Kappa TP3036
4.0 Functional Description (Continued)
TL/F/12082 – 13
FIGURE 18. Encoder/Decode Block Diagram
counter a higher than expected board yield loss due to the
oscillator not starting. The DP83907’s oscillator circuit
clocks the Encoder-Decoder logic. The DP83907’s oscillator also clocks the twisted pair interface block. If the oscillator does not start, the DP83907 will not be able to transmit
or receive.
4.10 ENCODER/DECODER (ENDEC) MODULE
The ENDEC consists of four main logical blocks:
a) The oscillator generates the 10 MHz transmit clock signal for system timing.
b) The Manchester encoder accepts NRZ data from the
controller, encodes the data to Manchester, and transmits the data differentially to the transceiver, through the
differential transmit driver.
c) The Manchester decoder receives Manchester data from
the transceiver, converts it to NRZ data and clock pulses, and sends it to the controller.
d) The collision translator indicates to the controller the
presence of a valid 10 MHz collision signal to the PLL.
Oscillator
The oscillator is controlled by a 20 MHz parallel resonant
crystal connected between X1 and X2 or by an external
clock on X1. The 20 MHz output of the oscillator is divided
by 2 to generate the 10 MHz transmit clock for the controller. The oscillator also provides internal clock signals to the
encoding and decoding circuits.
CRYSTAL OPERATION
If the crystal used with the internal oscillator circuit is not
properly selected, the DP83907 oscillator may not reliably
start oscillation under all conditions.
If this occurs, it could be deceiving to a designer, since his
prototypes may work fine. However, when the designer
does qualification testing or starts production, he may en-
TL/F/12082 – 14
FIGURE 19. Crystal Connection to DP83907
(see text for component values)
20
4.0 Functional Description (Continued)
If a crystal is connected to the DP83907, it is recommended
that the circuit shown in Figure 19 be used and that the
components used meet the following:
Crystal XT1: AT cut parallel resonant crystal
Series Resistance: s 25X
Specified Load Capacitance: s 20 pF
Accuracy: 0.005% (50 ppm)
Typical Load: 50 mW – 75 mW
The recommended values for capacitors C1 and C2 should
be 26 pF minus the board capacitance on that pin. Therefore if both X1 and X2 have 4 pF of board capacitance then
a 22 pF capacitor should be used.
According to the IEEE 802.3 standard, the entire oscillator
circuit (crystal and amplifier) must be accurate to 0.01%.
When using a crystal, the X2 pin is not guaranteed to provide a TTL compatible logic output, and should not be used
to drive external standard logic. If additional logic needs to
be driven, then an external oscillator should be used, as
described in the following section.
FIGURE 20. DP83907 Connection for Oscillator Module
Oscillator Module Operation
If the designer wishes to use a crystal clock oscillator, one
that provides the following should be employed:
1) TTL or CMOS output with a 0.01% frequency tolerance
2) 40 – 60% duty cycle
The circuit is shown in Figure 20 . When using a clock oscillator it is recommended that the designer connect the oscillator output to the X1 pin and leave the X2 pin floating.
Manchester Encoder and DIfferential Driver
The differential transmit pair, on the secondary of the employed transformer, drives up to 50 meters of twisted pair
AUI cable.
The DP83907 allows full-step to be compatible with IEEE
802.3. Transmit a and Transmitb are equal in the idle
state, providing zero differential voltage to operate with
transformer coupled loads.
TL/F/12082 – 15
TL/F/12082 – 16
FIGURE 21. Connection from DP83907’s AUI Port to a AUI Connector
21
4.0 Functional Description (Continued)
Manchester Decoder
AVCC Power Supply Consideration
The decoder consists of a differential receiver and a PLL to
separate a Manchester encoded data stream into internal
clock signals and data. The differential input must be externally terminated with two 39X resistors connected in series
if the standard 78X transceiver drop cable is used. In thin
Ethernet applications, these resistors are optional. To prevent noise from falsely triggering the decoder, a squelch
circuit at the input rejects signals with levels less than
b 175 mV. Signals more negative than b 300 mV. Data becomes valid typically within 6-bit times. The DP83907 may
tolerate bit jitter up to 20 ns in the received data. The decoder detects the end of a frame when no more mid-bit transitions are detected.
The AVCC pin is the a 5V power supply for the phase lock
loop (PLL) of the ENDEC unit. Since this is an analog circuit,
excessive noise on the AVCC pin can affect the performance of the PLL. This noise, if in the 10 KHz – 400 KHz
range, can reduce the jitter performance of the ENDEC, resulting in missing packets or CRC errors.
If the power supply noise is causing significant packet reception error, a low pass filter could be added to reduce the
power supply noise and hence improve the jitter performance. Standard analog design techniques should be utilized
when laying out the power supply traces on the board. If the
digital power supply is used, it may be desirable to add a
one pole RC filter (designed to have a cut-off frequency of
1 KHz) as shown in Figure 22 to improve the jitter performance. The AVCC draws 3 mA – 4 mA so the voltage across
the resister is less than 90 mV, which will not affect the
PLL’s operation.
Collision Translator
When in AUI Mode, the Ethernet transceiver (DP8392 CTI)
detects a collision, it generates a 10 MHz signal to the differential collision inputs (CD g ) of the DP83907. When
these inputs are detected active, the DP83907 uses this
signal to back off its current transmission and reschedule
another one.
In this mode the COLÐled output will indicate when the
CD a lines are active during activity on the network. This
means it will correctly indicate any collision on the network,
but will not be lit for heartbeat or if there is no cable connected.
The collision differential inputs are terminated the same way
as the differential receive inputs. The squelch circuitry is
also similar, rejecting pulses levels less than b175 mV.
TL/F/12082 – 17
FIGURE 22. Filtering Power Supply Noise
22
5.0 Register Descriptions
5.1 CONFIGURATION REGISTERS
These registers are used to configure the operation of the DP83907 typically after power up. These registers control the
configuration of bus interface, setting options like interrupt selection, I/O base address, and other specific modes.
MODE CONFIGURATION REGISTER A
To prevent any accidental writes of this register it is ‘‘hidden’’ behind a previously unused register. Register 0AH in the
DP83907’s Page 0 of registers was previously reserved on a read. Now Configuration Register A can be read at that address
and can be written to by following a read to 0AH with a write to 0AH. If any other DP83907 register accesses take place between
the read and the write then the write to 0AH will access the Remote Byte Count Register 0.
Bit
Symbol
0–2
IOAD0–IOAD2
7
6
5
4
3
2
1
0
RES
FRd/Wr
INT2
INT1
INT0
IOAD2
IOAD1
IOAD0
Function
I/O ADDRESS: These three bits determine the base I/O address of the DP83907 within the system’s
I/O map. The DP83907 occupies 20H bytes of the system’s address space.
Bit 2 1 0
000
001
010
011
100
101
110
111
0300H
Software (Note 1)
0240H
0280H
02C0H
0320H
0340H
0360H
Note 1: When 001 is selected the DP83907 will not respond to any I/O Addresses, but will allow 4 consecutive writes to 278H to
write these three bits of this register. This sequence will only operate once after a power-on reset. This mode allows the DP83907
to be configured via software without conflicting with other peripherals.
3–5
INT0–INT2
6
FRd/WR
7
RES
INTERRUPT LINE USED:
Bit 5 4 3
IRQ
000
3
001
4
010
5
011
9
100
10
101
11
110
12
111
15
FAST RD/WR: When this bit is set high the DP83907, in I/O mode, will begin the next port fetch
before the current IORD/IOWR has completed. In slow ISA systems this may cause the data in the
port to be overwritten before the ISA cycle has been completed.
RESERVED: This bit must be set low for normal operation.
23
5.0 Register Descriptions (Continued)
MODE CONFIGURATION REGISTER B
To prevent any accidental writes of this register it is ‘‘hidden’’ behind a previously unused register. Register 0BH in the
DP83907’s Page 0 of registers was previously reserved on a read. Now Configuration Register B can be read at that address
and can be written to by following a read to 0BH with a write to 0BH. If any other DP83907 register accesses take place between
the read and the write then the write to 0BH will access the Remote Byte Count Register 1. Care should be taken when
writing to this register as GDLINK and BE are not simple read/write bits. e.g., the user can not change the physical layer by
reading B, or-ing the returned value with the bits to be set and writing this value to B. This could inadvertently disable link
integrity generation and clear a bus error indication before it was noted.
7
6
5
4
3
2
1
0
EELOAD
BPWR
BE
RES
IO16CON
GDLINK
PHYS1
PHYS0
Bit
Symbol
Function
0–1
PHYS0 –
PHYS1
PHYSICAL LAYER INTERFACE: These 2 bits determine which type of physical interface the DP83907 is
using. The 2 TPI interfaces use twisted pair outputs and inputs, while the other 2 interfaces use the AUI
outputs and inputs. In 10BASE5 mode the THICK/THIN output pin is driven low, in 10BASE2 mode it is
driven high. This can be used to enable the DC-DC converter required by the 10BASE2 specification to
provide electrical isolation. The Non spec TPI mode is a twisted pair mode with reduced receive squelch
levels. This allows the use of longer cable lengths than specified in the twisted pair specification, or the use
of cable with higher losses.
Bit 1 0
00
01
10
11
2
GDLINK
TPI (10BASE-T Compatible Squelch Level)
Thin Ethernet (10BASE2)
Thick Ethernet (10BASE5) (AUI Port)
TPI (Reduced Squelch Level)
GOOD LINK: When a 1 is written to this bit the link test pulse generation and integrity checking is disabled.
When this bit is read it will indicate the link status, reflecting the value shown on the LED output. It is 0 if the
DP83907 is in AUI mode or if link testing is enabled and the link integrity is bad (i.e., the twisted pair link has
been broken). It is 1 if the DP83907 is in TPI mode, link integrity checking is enabled and the link integrity is
good (i.e., the twisted pair link has not been broken) or if the link testing is disabled.
3
IO16CON
4
RES
5
BE
6
BPWR
7
EELOAD
IO16 CONTROL: When this bit is set high the DP83907 generates IO16 after IORD or IOWR go active. If
low this output is generated only on address decode.
RESERVED: This bit must be set low for normal operation.
BUS ERROR: This bit shows that the DP83907 has detected a bus error condition. This will go high if the
DP83907 attempts to insert wait states into a system access and the system terminates the cycle without
inserting the wait states. Writing a one to this bit clears it to zero. Writing a zero has no effect.
BOOT PROM WRITE: When this bit is low no write cycles are generated to the boot PROM.
EEPROM LOAD: Writing a 1 to this bit enables the EEPROM load algorithm as detailed in Section 4. This
bit should not be configured to be high, either from switches or an EEPROM.
24
5.0 Register Descriptions (Continued)
HARDWARE CONFIGURATION REGISTER C
This register is configured during a RESET and can be accessed by 3rd consecutive read config register A.
Bit
Symbol
0–3
BPS0– 3
7
6
5
4
3
2
1
0
SOFEN
RES
RES
RES
BPS3
BPS2
BPS1
BPS0
Function
BOOT PROM SELECT: Selects address at which boot PROM begins and the size. When the system reads
within the selected memory area DP83907 reads the data in through MSD0 – 7 and drives it onto the system
data bus. The following are valid addresses and sizes:
Bit 3
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bit 2
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Bit 1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Bit 0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Address
X
0C000H
0C400H
0C800H
0CC00H
0D000H
0D400H
0D800H
0DC00H
0C000H
0C800H
0D000H
0D800H
0C000H
0D000H
Size
No Boot PROM
8K
8K
8K
8K
8K
8K
8K
8K
32K
32K
32K
32K
64K
64K
4
RES
RESERVED: This bit must be set low for normal operation.
5
RES
RESERVED: This bit must be set high for normal operation.
6
RES
RESERVED: This bit must be set low for normal operation.
7
SOFEN
SOFTWARE ENABLE: If this bit is set low then the user can program configuration registers A and B in
software. If this bit is set high then the configuration registers are not accessible. If EECONFIG is high the
configuration from the switches will be overwritten by the configuration from the EEPROM even if this bit is
pulled high.
25
5.0 Register Descriptions (Continued)
SIGNATURE REGISTER
This register is intended to allow the software programmer to determine which of the DP83907 family of devices and what board
configuration is being used. This register is ‘‘hidden’’ behind a used register. Register 01H in the DP83907’s Page 1 of registers
is Physical Address Register 0, which is read/write. Now the Signature Register can be read at that address by following a read
to 01H, on Page 1, with another read to 01H. If any other DP83907 register accesses take place between the two reads then the
second read will access Physical Address Register 0. All writes are to Physical Address Register 0. The user can determine if
the Signature Register exists by writing, while in Page 1, a known value to the Physical Address Register 0 then reading it back
twice. The first read will be the known value. If the second read is not equal to the value written then the Signature Register
exists. This operation should only be attempted while the DP83907 is in STOP mode (STP bit in the Command Register
set high).
Bit
Symbol
0–3
REV0 – 3
7
6
5
4
3
2
1
0
SIG7
SIG6
SIG5
EEPR
REV3
REV2
REV1
REV0
Function
DP83907 FAMILY REVISION: Shows that this is an DP83907 by holding the value:
Rev 3
1
4
0–3
EEPR
SIG5 – 7
(MSA11 – 13)
Rev 2
0
Rev 1
0
Rev 0
0
EEPROM PROGRAMMED: If the upper byte of the EEPROM contains 073H when loaded into the
DP83907 this bit will be high.
BOARD REVISION: Shows that this board uses an NE2000 Architecture compatible interrupt structure:
Sig 7
0
Sig 6
0
Sig 5
0
26
5.0 Register Descriptions (Continued)
5.2 NIC CORE REGISTERS
All registers are 8-bit wide and mapped into two pages which are selected in the Command Register (PS0, PS1). Pins RA0 – RA3
are used to address registers within each page. Page 0 registers are those registers which are commonly accessed during
DP83907 operation while page 1 registers are used primarily for initialization. The registers are partitioned to avoid having to
perform two write/read cycles to access commonly used registers.
TL/F/12082 – 18
FIGURE 23. NIC Core Register Mapping
Register Assignments
Page 0 Address Assignments
RA0–RA3
RD
(PS1 e 0, PS0 e 0)
WR
00H
Command (CR)
Command (CR)
01H
Current Local DMA
Address 0 (CLDA0)
Page Start Register
(PSTART)
02H
Current Local DMA
Address 1 (CLDA1)
Page Stop Register
(PSTOP)
03H
Boundary Pointer
(BNRY)
Boundary Pointer
(BNRY)
04H
Transmit Status
Register (TSR)
Transmit Page Start
Address (TPSR)
05H
Number of Collisions
Register (NCR)
Transmit Byte Count
Register 0 (TBCR0)
06H
FIFO (FIFO)
Transmit Byte Count
Register 1 (TBCR1)
07H
Interrupt Status
Register (ISR)
Interrupt Status
Register (ISR)
08H
Current Remote DMA
Address 0 (CRDA0)
Remote Start Address
Register 0 (RSAR0)
09H
Current Remote DMA
Address 1 (CRDA1)
Remote Start Address
Register 1 (RSAR1)
0AH
Reserved
Remote Byte Count
Register 0 (RBCR0)
0BH
Reserved
Remote Byte Count
Register 1 (RBCR1)
0CH
Receive Status
Register (RSR)
Receive Configuration
Register (RCR)
0DH
Tally Counter 0
(Frame Alignment
Errors) (CNTR0)
Transmit Configuration
Register (TCR)
0EH
Tally Counter 1
(CRC Errors)
(CNTR1)
Data Configuration
Register (DCR)
0FH
Tally Counter 2
(Missed Packet
Errors) (CNTR2)
Interrupt Mask
Register (IMR)
27
5.0 Register Descriptions (Continued)
Page 1 Address Assignments
RA0–RA3
RD
(PS1 e 0, PS0 e 1)
WR
00H
Command (CR)
Command (CR)
01H
Physical Address
Register 0 (PAR0)
Physical Address
Register 0 (PA R0)
02H
Physical Address
Register 1 (PAR1)
Physical Address
Register 1 (PA R1)
03H
Physical Address
Register 2 (PAR2)
Physical Address
Register 2 (PA R2)
04H
Physical Address
Register 3 (PAR3)
Physical Address
Register 3 (PA R3)
05H
Physical Address
Register 4 (PAR4)
Physical Address
Register 4 (PA R4)
06H
Physical Address
Register 5 (PAR5)
Physical Address
Register 5 (PA R5)
07H
Current Page
Register (CURR)
Current Page
Register (C URR)
08H
Multicast Address
Register 0 (MAR0)
Multicast Address
Register 0 (MAR0)
09H
Multicast Address
Register 1 (MAR1)
Multicast Address
Register 1 (MAR1)
0AH
Multicast Address
Register 2 (MAR2)
Multicast Address
Register 2 (MAR2)
0BH
Multicast Address
Register 3 (MAR3)
Multicast Address
Register 3 (MAR3)
0CH
Multicast Address
Register 4 (MAR4)
Multicast Address
Register 4 (MAR4)
0DH
Multicast Address
Register 5 (MAR5)
Multicast Address
Register 5 (MAR5)
0EH
Multicast Address
Register 6 (MAR6)
Multicast Address
Register 6 (MAR6)
0FH
Multicast Address
Register 7 (MAR7)
Multicast Address
Register 7 (MAR7)
28
5.0 Register Descriptions (Continued)
Page 2 Address Assignments
RA0–RA3
(PS1 e 1, PS0 e 0)
RD
WR
00H
Command (CR)
Command (CR)
01H
Page Start Register
(PSTART)
Current Local DMA
Address 0 (CLDA0)
02H
Page Stop Register
(PSTOP)
Current Local DMA
Address 1 (CLDA1)
03H
Remote Next Packet
Pointer
Remote Next Packet
Pointer
04H
Transmit Page Start
Address (TPSR)
Reserved
05H
Local Next Packet
Pointer
Local Next Packet
Pointer
06H
Address Counter
(Upper)
Address Counter
(Upper)
07H
Address Counter
(Lower)
Address Counter
(Lower)
08H
Reserved
Reserved
09H
Reserved
Reserved
0AH
Reserved
Reserved
0BH
Reserved
Reserved
0CH
Receive Configuration
Register (RCR)
Reserved
0DH
Transmit
Configuration
Register (TCR)
Reserved
0EH
Data Configuration
Register (DCR)
Reserved
0FH
Interrupt Mask
Register (IMR)
Reserved
Note: Page 2 registers should only be accessed for diagnostic purposes.
They should not be modified during normal operation.
Page 3 should never be modified.
29
5.0 Register Descriptions (Continued)
COMMAND REGISTER (CR)
00H (READ/WRITE)
The Command Register is used to initiate transmissions, enable or disable Remote DMA operations and to select register
pages. To issue a command the microprocessor sets the corresponding bit(s) (RD2, RD1, RD0, TXP). Further commands may
be overlapped, but with the following rules: (1) If a transmit command overlaps with a remote DMA operation, bits RD0, RD1,
and RD2 must be maintained for the remote DMA command when setting the TXP bit. Note, if a remote DMA command is re-issued when giving the transmit command, the DMA will complete immediately if the remote byte count register has not been reinitialized. (2) If a remote DMA operation overlaps a transmission, RD0, RD1, and RD2 may be written with the desired values
and a ‘‘0’’ written to the TXP bit. Writing a ‘‘0’’ to this bit has no effect. (3) A remote write DMA may not overlap remote read
operation or vice versa. Either of these operations must either complete or be aborted before the other operation may start. Bits
PS1, PS0, RD2, and STP may be set any time.
7
6
5
4
3
2
1
0
PS1
PS0
RD2
RD1
RD0
TXP
STA
STP
Bit
Symbol
Description
D0
STP
STOP: Software reset command, takes the controller off-line, no packets will be received or transmitted.
Any reception or transmission in progress will continue to completion before entering the reset state. To
exit this state, the STP bit must be reset and the STA bit must be set high. To perform a software reset,
this bit should be set high. The software reset has executed only when indicated by the RST bit in the
ISR being set to 1. STP powers up high.
D1
STA
START: This bit is used to activate the NIC Core after either power up, or when the NIC Core has been
placed in a reset mode by software command or error. STA powers up low.
D2
TXP
TRANSMIT PACKET: This bit must be set to initiate transmission of a packet. TXP is internally reset
either after the transmission is completed or aborted. This bit should be set only after the Transmit Byte
Count and Transmit Page Start registers have been programmed.
D3 – D5
RD0 – RD2
REMOTE DMA COMMAND: These three encoded bits control operation of the Remote DMA channel.
RD2 can be set to abort any Remote DMA command in progress. The Remote Byte Count Registers
should be cleared when a Remote DMA has been aborted. The Remote Start Addresses are not
restored to the starting address if the Remote DMA is aborted.
Note: If the DP83907 has previously been in start mode and the STP is set, both the STP and STA bits will remain set.
RD2
0
0
0
0
1
RD1
0
0
1
1
X
RD0
0
1
0
1
X
Not Allowed
Remote Read
Remote Write (Note 2)
Send Packet
Abort/Complete Remote DMA (Note 1)
Note 1: If a remote DMA operation is aborted and the remote byte count has not decremented to zero, the data transfer port should
be read, for a remote read or send packet, or written to, for a remote write. This is required to ensure future correct operation.
D6, D7
PS0, PS1
PAGE SELECT: These two encoded bits select which register page is to be accessed with addresses
RA0 – 3.
PS1
PS0
0
0
Register Page 0
0
1
Register Page 1
1
0
Register Page 2
1
1
Reserved
30
5.0 Register Descriptions (Continued)
INTERRUPT STATUS REGISTER (ISR)
07H (READ/WRITE)
This register is accessed by the host processor to determine the cause of an interrupt. Any interrupt can be masked in the
Interrupt Mask Register (IMR). Individual interrupt bits are cleared by writing a ‘‘1’’ into the corresponding bit of the ISR. The
valid interrupt output is active as long as any unmasked signal is set, and will not go low until all unmasked bits in this register
have been cleared. The ISR must be cleared after power up by writing it with all 1’s.
7
6
5
4
3
2
1
0
RST
RDC
CNT
OVW
TXE
RXE
PTX
PRX
Bit
Symbol
D0
PRX
PACKET RECEIVED: Indicates packet received with no errors.
Description
D1
PTX
PACKET TRANSMITTED: Indicates packet transmitted with no errors.
D2
RXE
RECEIVE ERROR: Indicates that a packet was received with one or more of the following errors:
ÐCRC Error
ÐFrame Alignment Error
ÐFIFO Overrun
ÐMissed Packet
D3
TXE
TRANSMIT ERROR: Set when packet transmitted with one or more of the following errors:
ÐExcessive Collisions
ÐFIFO Underrun
D4
OVW
OVERWRITE WARNING: Set when receive buffer ring storage resources have been exhausted. (Local
DMA has reached Boundary Pointer.)
D5
CNT
COUNTER OVERFLOW: Set when MSB of one or more of the Network Tally Counters has been set.
D6
RDC
REMOTE DMA COMPLETE: Set when Remote DMA operation has been completed.
D7
RST
RESET STATUS: Set when DP83907 enters reset state and cleared when a Start Command is issued to
the CR. This bit is also set when a Receive Buffer Ring overflow occurs and is cleared when one or more
packets have been removed from the ring. Writing to this bit has no effect.
Note: This bit does not generate an interrupt, it is merely a status indicator.
31
5.0 Register Descriptions (Continued)
INTERRUPT MASK REGISTER (IMR)
0FH (WRITE)
The Interrupt Mask Register is used to mask interrupts. Each interrupt mask bit corresponds to a bit in the Interrupt Status
Register (ISR). If an interrupt mask bit is set, an interrupt will be issued whenever the corresponding bit in the ISR is set. If any bit
in the IMR is set low, an interrupt will not occur when the bit in the ISR is set. The IMR powers up all zeros.
Bit
7
6
5
4
3
2
1
0
Ð
RDCE
CNTE
OVWE
TXEE
RXEE
PTXE
PRXE
Symbol
Description
D0
PRXE
PACKET RECEIVED INTERRUPT ENABLE
0: Interrupt Disabled
1: Enables Interrupt when packet received
D1
PTXE
PACKET TRANSMITTED INTERRUPT ENABLE
0: Interrupt Disabled
1: Enables Interrupt when packet is transmitted
D2
RXEE
RECEIVE ERROR INTERRUPT ENABLE
0: Interrupt Disabled
1: Enables Interrupt when packet received with error
D3
TXEE
TRANSMIT ERROR INTERRUPT ENABLE
0: Interrupt Disabled
1: Enables Interrupt when packet transmission results in error
D4
OVWE
OVERWRITE WARNING INTERRUPT ENABLE
0: Interrupt Disabled
1: Enables Interrupt when Buffer Management Logic lacks sufficient buffers to store incoming packet
D5
CNTE
COUNTER OVERFLOW INTERRUPT ENABLE
0: Interrupt Disabled
1: Enables Interrupt when MSB of one or more of the Network Statistics counters has been set
D6
RDCE
DMA COMPLETE INTERRUPT ENABLE
0: Interrupt Disabled
1: Enables Interrupt when Remote DMA transfer has been completed
D7
Reserved
Reserved
32
5.0 Register Descriptions (Continued)
DATA CONFIGURATION REGISTER (DCR)
0EH (WRITE)
This Register is used to program the DP83907 for 8- or 16-bit memory interface, select byte ordering in 16-bit applications and
establish FIFO thresholds. The DCR must be initialized prior to loading the Remote Byte Count Registers. LAS is set on
power up.
Bit
D0
7
6
5
4
3
2
1
0
Ð
FT1
FT0
ARM
LS
LAS
BOS
WTS
Symbol
WTS
Description
WORD TRANSFER SELECT
0: Selects byte-wide DMA transfers
1: Selects word-wide DMA transfers
; WTS establishes byte or word transfers for both Remote and Local DMA transfers
Note: When word-wide mode is selected, up to 32k words are addressable; A0 remains low.
D1
BOS
BYTE ORDER SELECT
0: MS byte placed on AD15–AD8 and LS byte on AD7–AD0. (32xxx, 80x86)
1: MS byte placed on AD7–AD0 and LS byte on AD15–AD8. (680x0)
: Ignored when WTS is low
D2
LAS
LONG ADDRESS SELECT
0: Dual 16-bit DMA mode
1: Single 32-bit DMA mode
When LAS is high, the contents of the Remote DMA registers RSAR0, 1 are issued as A16–
A31 Power up high
D3
LS
LOOPBACK SELECT
0: Loopback mode selected. Bits D1 and D2 of the TCR must also be programmed for
Loopback operation
1: Normal Operation
D4
ARM
AUTO-INITIALIZE REMOTE
0: Send Command not executed, all packets removed from Buffer Ring under program
control
1: Send Command executed, Remote DMA auto-initialized to remove packets from Buffer
Ring
Note: Send Command cannot be used with 680x0 byte processors.
D5 and D6
FT0 and FT1
FlFO THRESHOLD SELECT: Encoded FIFO threshold. Establishes point at which the
memory bus is requested when filling or emptying the FIFO. During reception, the FIFO
threshold indicates the number of bytes (or words) the FIFO has filled serially from the
network before the FIFO is emptied onto the memory bus.
Note: FIFO threshold setting determines the DMA burst length.
Receive Thresholds
FT1
FT0
Word Wide
Byte Wide
0
0
1 Word
2 Bytes
0
1
2 Words
4 Bytes
1
0
4 Words
8 Bytes
1
1
6 Words
12 Bytes
During transmission, the FIFO threshold indicates the number of bytes (or words) the FIFO
has filled from the Local DMA before being transferred to the memory. Thus, the transmission
threshold is 16 bytes less the received threshold.
33
5.0 Register Descriptions (Continued)
TRANSMIT CONFIGURATION REGISTER (TCR)
ODH (WRITE)
The transmit configuration establishes the actions of the transmitter section of the DP83907 during transmission of a packet on
the network. LB1 and LB0 which select loopback mode power up as 0.
Bit
D0
7
6
5
4
3
2
1
0
Ð
Ð
Ð
OFST
ATD
LB1
LB0
CRC
Symbol
Description
CRC
INHIBIT CRC
0: CRC appended by transmitter
1: CRC inhibited by transmitter
In loopback mode CRC can be enabled or disabled to test the CRC logic.
LB0 and
LB1
ENCODED LOOPBACK CONTROL: These encoded configuration bits set the type of loopback that is to be
performed. Note that loopback in mode 2 places the ENDEC Module in loopback mode and that D3 of the
DCR must be set to zero for loopback operation.
LB1
LB0
Mode 0
0
0
Normal Operation (LPBK e 0)
Mode 1
0
1
Internal NIC Module Loopback (LPBK e 0)
Mode 2
1
0
Internal ENDEC Module Loopback (LPBK e 1)
Mode 3
1
1
External Loopback (LPBK e 0)
D3
ATD
AUTO TRANSMIT DISABLE: This bit allows another station to disable the DP83907’S transmitter by
transmission of a particular multicast packet. The transmitter can be re-enabled by resetting this bit or by
reception of a second particular multicast packet.
0: Normal Operation
1: Reception of multicast address hashing to bit 62 disables transmitter, reception of multicast address
hashing to bit 63 enables transmitter.
D4
OFST
COLLISION OFFSET ENABLE: This bit modifies the backoff algorithm to allow prioritization of nodes.
0: Backoff Logic implements normal algorithm.
1: Forces Backoff algorithm modification to 0 to 2min(3 a n, 10) slot times for first three collisions, then
follows standard backoff. (For the first three collisions, the station has higher average backoff delay
making a low priority mode.)
D5
Reserved
Reserved
D6
Reserved
Reserved
D7
Reserved
Reserved
D1 and
D2
34
5.0 Register Descriptions (Continued)
TRANSMIT STATUS REGISTER (TSR)
04H (READ)
This register records events that occur on the media during transmission of a packet. It is cleared when the next transmission is
initiated by the host. All bits remain low unless the event that corresponds to a particular bit occurs during transmission. Each
transmission should be followed by a read of this register. The contents of this register are not specified until after the first
transmission.
Bit
7
6
5
4
3
2
1
0
OWC
CDH
FU
CRS
ABT
COL
Ð
PTX
Symbol
Description
D0
PTX
PACKET TRANSMITTED: Indicates transmission without error. (No excessive collisions or FIFO underrun)
(ABT e ‘‘0’’, FU e ‘‘0’’).
D1
Reserved
Reserved
D2
COL
TRANSMIT COLLIDED: Indicates that the transmission collided at least once with another station on the
network. The number of collisions is recorded in the Number of Collisions Registers (NCR).
D3
ABT
TRANSMIT ABORTED: Indicates the DP83907 aborted transmission because of excessive collisions. (Total
number of transmissions including original transmission attempt equals 16.)
D4
CRS
CARRIER SENSE LOST: This bit is set when carrier is lost during transmission of the packet. Transmission is not
aborted on loss of carrier.
D5
FU
FIFO UNDERRUN: If the DP83907 cannot gain access of the bus before the FIFO empties, this bit is set.
Transmission of the packet will be aborted.
D6
CDH
CD HEARTBEAT: Failure of the transceiver to transmit a collision signal after transmission of a packet will set
this bit. The Collision Detect (CD) heartbeat signal must commence during the first 6.4 ms of the Interframe Gap
following a transmission. In certain collisions, the CD Heartbeat bit will be set even though the transceiver is not
performing the CD heartbeat test.
D7
OWC
OUT OF WINDOW COLLISION: Indicates that a collision occurred after a slot time (51.2 ms). Transmissions
rescheduled as in normal collisions.
35
5.0 Register Descriptions (Continued)
RECEIVE CONFIGURATION REGISTER (RCR)
0CH (WRITE)
This register determines operation of the DP83907 during reception of a packet and is used to program what types of packets to
accept.
7
6
5
4
3
2
1
0
Ð
Ð
MON
PRO
AM
AB
AR
SEP
Bits
Symbols
D0
SEP
SAVE ERRORED PACKETS
0: Packets with receive errors are rejected.
1: Packets with receive errors are accepted. Receive errors are CRC and Frame Alignment errors.
Description
D1
AR
ACCEPT RUNT PACKETS: This bit allows the receiver to accept packets that are smaller than 64
bytes. The packet must be at least 8 bytes long to be accepted as a runt.
0: Packets with fewer than 64 bytes rejected.
1: Packets with fewer than 64 bytes accepted.
D2
AB
ACCEPT BROADCAST: Enables the receiver to accept a packet with an all 1’s destination address.
0: Packets with broadcast destination address rejected.
1: Packets with broadcast destination address accepted.
D3
AM
ACCEPT MULTICAST: Enables the receiver to accept a packet with a multicast address, all multicast
addresses must pass the hashing array.
0: Packets with multicast destination address not checked.
1: Packets with multicast destination address checked.
D4
PRO
PROMISCUOUS PHYSICAL: Enables the receiver to accept all packets with a physical address.
0: Physical address of node must match the station address programmed in PAR0–PAR5.
1: All packets with physical addresses accepted.
D5
Reserved
Reserved (program to 0)
D6
Reserved
Reserved
D7
Reserved
Reserved
Note: D2 and D3 are ‘‘OR’d’’ together, i.e., if D2 and D3 are set the DP83907 will accept broadcast and multicast addresses as well as its own physIcal address. To
establish full promiscuous mode, bits D2, D3, and D4 should be set. In addition the multicast hashing array must be set to all 1’s in order to accept all multicast
addresses.
36
5.0 Register Descriptions (Continued)
RECEIVE STATUS REGISTER (RSR)
0CH (READ)
This register records status of the received packet, including information on errors and the type of address match, either
physical or multicast. The contents of this register are written to buffer memory by the DMA after reception of a good packet. If
packets with errors are to be saved the receive status is written to memory at the head of the erroneous packet if an erroneous
packet is received. If packets with errors are to be rejected the RSR will not be written to memory. The contents will be cleared
when the next packet arrives. CRC errors, Frame Alignment errors and missed packets are counted internally by the DP83907
which relinquishes the Host from reading the RSR in real time to record errors for Network Management Functions. The
contents of this register are not specified until after the first reception.
7
6
5
4
3
2
1
0
DFR
DIS
PHY
MPA
FO
FAE
CRC
PRX
Bit
Symbol
D0
PRX
PACKET RECEIVED INTACT: Indicates packet received without error. (Bits CRC, FAE, FO, and MPA are
zero for the received packet.)
Description
D1
CRC
CRC ERROR: Indicates packet received with CRC error. Increments Tally Counter (CNTR1). This bit will
also be set for Frame Alignment errors.
D2
FAE
FRAME ALIGNMENT ERROR: Indicates that the incoming packet did not end on a byte boundary and the
CRC did not match at last byte boundary. Increments Tally Counter (CNTR0).
D3
FO
FIFO OVERRUN: This bit is set when the FIFO is not serviced causing overflow during reception.
Reception of the packet will be aborted.
D4
MPA
MISSED PACKET: Set when packet intended for node cannot be accepted by SNIC because of a lack of
receive buffers or if the controller is in monitor mode and did not buffer the packet to memory. Increments
Tally Counter (CNTR2).
D5
PHY
PHYSICAL/MULTICAST ADDRESS: Indicates whether received packet had a physical or multicast
address type.
0: Physical Address Match
1: Multicast/Broadcast Address Match
D6
DIS
RECEIVER DISABLED: Set when receiver disabled by entering Monitor mode. Reset when receiver is reenabled when exiting Monitor mode.
D7
DFR
DEFERRING: Set when internal Carrier Sense or Collision signals are generated in the ENDEC module. If
the transceiver has asserted the CD line as a result of the jabber, this bit will stay set indicating the jabber
condition.
Note: Following coding applies to CRC and FAE bits:
FAE
0
0
1
1
CRC
0
1
0
1
Type of Error
No Error (Good CRC and k 6 Dribble Bits)
CRC Error
Illegal, wil not occur
Frame Alignment Error and CRC Error
37
5.0 Register Descriptions (Continued)
TL/F/12082 – 19
FIGURE 24. DMA Registers
boundaries. The bit assignment is shown below. The values
placed in bits D7-D0 will be used to initialize the higher order
address (A8-A15) of the Local DMA for transmission. The
lower order bits (A7 – A0) are initialized to zero.
5.3 DP8390 CORE DMA REGISTERS
The DMA Registers are partitioned into groups; Transmit,
Receive and Remote DMA Registers. The Transmit registers are used to initialize the Local DMA Channel for transmission of packets while the Receive Registers are used to
initialize the Local DMA Channel for packet Reception. The
Page Stop, Page Start, Current and Boundary Registers are
used by the Buffer Management Logic to supervise the Receive Buffer Ring. The Remote DMA Registers are used to
initialize the Remote DMA
Bit Assignment
TPSR
7
6
5
4
3
2
1
0
A15
A14
A13
A12
A11
A10
A9
A8
(A7–A0 Initialized to 0)
TRANSMIT BYTE COUNT REGISTER 0,1 (TBCR0,
TBCR1)
These two registers indicate the length of the packet to be
transmitted in bytes. The count must include the number of
bytes in the source, destination, length and data fields. The
maximum number of transmit bytes allowed is 64K bytes.
The DP83907 will not truncate transmissions longer than
1500 bytes. The bit assignment is shown below:
Note: In the figure above, registers are shown as 8 or 16 bits wide. Although some registers are 16-bit internal registers, all registers are
accessed as 8-bit registers. Thus the 16-bit Transmit Byte Count
Register is broken into two 8-bit registers. TBCR0 TBCR1. Also
TPSR, PSTART, PST0P, CURR and BNRY only check or control the
upper 8 bits of address information on the bus. Thus they are shifted
to positions 15-8 in the diagram above.
Transmit DMA Registers
TRANSMIT PAGE START REGISTER (TPSR)
This register points to the assembled packet to be transmitted. Only the eight higher order addresses are specified
since all transmit packets are assembled on 256-byte page
38
7
6
5
4
3
2
1
0
TBCR1
L15
L14
L13
L12
L11
L10
L9
L8
7
6
5
4
3
2
1
0
TBCR0
L7
L6
L5
L4
L3
L2
L1
L0
5.0 Register Descriptions (Continued)
Local DMA Receive Registers
REMOTE BYTE COUNT REGISTERS (RCB0,1)
7
6
5
4
3
2
1
0
RBCR1
A15
A14
A13
A12
A11
A10
A9
A8
7
6
5
4
3
2
1
0
RBCR0
A7
A6
A5
A4
A3
A2
A1
A0
PAGE START STOP REGISTERS (PSTART, PSTOP)
The Page Start and Page Stop Registers program the starting and stopping address of the Receive Buffer Ring. Since
the DP83907 uses fixed 256-byte buffers aligned on page
boundaries only the upper eight bits of the start and stop
address are specified.
Note:
RSAR0 programs the start address bits A0–A7.
PSTART, PSTOP bit assignment
PSTART
PSTOP
RSAR1 programs the start address bits A8–A15.
7
6
5
4
3
2
1
0
A15
A14
A13
A12
A11
A10
A9
A8
Address incremented by two for word transfers, and by one for byte transfers. Byte count decremented by two for word transfers and by one for byte
transfers.
RBCR0 programs LSB byte count.
RBCR1 programs MSB byte count.
BOUNDARY (BNRY) REGISTER
This register is used to prevent overflow of the Receive
Buffer Ring. Buffer management compares the contents of
this register to the next buffer address when linking buffers
together. If the contents of this register match the next buffer address the Local DMA operation is aborted.
7
BNRY
A15
6
A14
5
A13
4
A12
3
A11
2
A10
1
A9
CURRENT REMOTE DMA ADDRESS (CRDA0, CRDA1)
The Current Remote DMA Registers contain the current address of the Remote DMA. The bit assignment is shown
below:
CLDA0
5
4
3
2
1
0
A14
A13
A12
A11
A10
A9
A8
7
6
5
4
3
2
1
0
CRDA0
A7
A6
A5
A4
A3
A2
A1
A0
7
6
5
4
3
2
1
0
A15
A14
A13
A12
A11
A10
A9
A8
Physical Address Registers (PAR0 – PAR5)
The physical address registers are used to compare the
destination address of incoming packets for rejecting or accepting packets. Comparisons are performed on a bytewide basis. The bit assignment shown below relates the sequence in PAR0 – PAR5 to the bit sequence of the received
packet.
CURRENT LOCAL DMA REGISTER 0,1 (CLDA0,1)
These two registers can be accessed to determine the current Local DMA Address.
CLDA1
6
A15
A8
CURRENT PAGE REGISTER (CURR)
This register is used internally by the Buffer Management
Logic as a backup register for reception. CURR contains the
address of the first buffer to be used for a packet reception
and is used to restore DMA pointers in the event of receive
errors. This register is initialized to the same value as
PSTART and should not be written to again unless the controller is Reset.
CURR
7
CRDA1
0
D7
D6
D5
D4
D3
D2
D1
D0
PAR0
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
PAR1
DA15
DA14
DA13
DA12
DA11
DA10
DA9
DA8
PAR2
DA23
DA22
DA21
DA20
DA19
DA18
DA17
DA16
7
6
5
4
3
2
1
0
PAR3
DA31
DA30
DA29
DA28
DA27
DA26
DA25
DA24
A15
A14
A13
A12
A11
A10
A9
A8
PAR4
DA39
DA38
DA37
DA36
DA35
DA34
DA33
DA32
7
6
5
4
3
2
1
0
PAR5
DA47
DA46
DA45
DA44
DA43
DA42
DA41
DA40
A7
A6
A5
A4
A3
A2
A1
A0
Destination Address
Remote DMA Registers
P/S
REMOTE START ADDRESS REGISTERS (RSAR0,1)
Remote DMA operations are programmed via the Remote
Start Address (RSAR0,1) and Remote Byte Count
(RBCR0,1) registers. The Remote Start Address is used to
point to the start of the block of data to be transferred and
the Remote Byte Count is used to indicate the length of the
block (in bytes).
7
6
5
4
3
2
1
0
RSAR1
A15
A14
A13
A12
A11
A10
A9
A8
7
6
5
4
3
2
1
0
RSAR0
A7
A6
A5
A4
A3
A2
A1
A0
DA0
DA1
DA2
DA3
Source
....
DA46
DA47
SA0
...
Note:
P/S e Preamble, Synch
DA0 e Physical/Muftcast Bit
Multicast Address Registers (MAR0 – MAR7)
The multicast address registers provide filtering of multicast
addresses hashed by the CRC logic. All destination addresses are fed through the CRC logic and as the last bit of
the destination address enters the CRC, the 6 most significant bits of the CRC generator are latched. These 6 bits are
then decoded by a 1 of 64 decode to index a unique filter bit
(FB0 – 63) in the multicast address registers. If the filter bit
selected is set, the multicast packet is accepted. The sys-
39
Preamble and Start of Frame Delimiter (SFD)
5.0 Register Descriptions (Continued)
The Manchester encoded alternating 1, 0 preamble field is
used by the ENDEC to acquire bit synchronization with an
incoming packet. When transmitted each packet contains
62 bits of alternating 1, 0 preamble. Some of this preamble
will be lost as the packet travels through the network. The
preamble field is stripped by the NIC module. Byte alignment is performed with the Start of Frame Delimiter (SFD)
pattern which consists of two consecutive 1’s. The
DP83907 does not treat the SFD pattern as a byte, it detects only the two bit pattern. This allows any preceding
preamble within the SFD to be used for phase locking.
tem designer would use a program to determine which filter
bits to set in the multicast registers. All multicast filter bits
that correspond to multicast address accepted by the node
are then set to one. To accept all multicast packets all of
the registers are set to all ones.
Note: Although the hashing algorithm does not guarantee perfect filtering of
multicast address, it will perfectly filter up to 64 multicast addresses if
these addresses are chosen to map into unique locations in the multicast filter.
Destination Address
The destination address indicates the destination of the
packet on the network and is used to filter unwanted packets from reaching a node. There are three types of address
formats supported by the DP83907: physical, multicast and
broadcast. The physical address is a unique address that
corresponds only to a single node. All physical addresses
have an MSB of ‘‘0’’. These addresses are compared to the
internally stored physical address registers. Each bit in the
destination address must match in order for the DP83907 to
accept the packet. Multicast addresses begin with an MSB
of ‘‘1’’. The DP83907 filters multicast addresses using a
standard hashing algorithm that maps all multicast addresses into a 6-bit value. This 6-bit value indexes a 64-bit array
that filters the value. If the address consists of all 1’s it is a
broadcast address, indicating that the packet is intended for
all nodes. A promiscuous mode allows reception of all packets: the destination address is not required to match any
filters. Physical, broadcast, multicast, and promiscuous address modes can be selected.
TL/F/12082–20
FIGURE 25. Multlcast Addressing
6.0 Operation of DP83907
This section details the operation of the DP83907. The operations discussed are packet reception and transmission,
bus operations, and loopback diagnostics.
Source Address
The source address is the physical address of the node that
sent the packet. Source addresses cannot be multicast or
broadcast addresses. This field is simply passed to buffer
memory.
6.1 TRANSMIT/RECEIVE PACKET ENCAPSULATION/
DECAPSULATION;
A standard lEEE 802.3 packet consists of the following
fields: preamble, Start of Frame Delimiter (SFD), destination
address, source address, length, data, and Frame Check
Sequence (FCS). The typical format is shown in the figure
following. The packets are Manchester encoded and decoded by the ENDEC module and transferred serially to the NIC
module using NRZ data with a clock. All fields are of fixed
length except for the data field. The DP83907 generates
and appends the preamble, SFD and FCS field during transmission. The Preamble and SFD fields are stripped during
reception. (The CRC is passed through to buffer memory
during reception.)
Length Field
The 2-byte length field indicates the number of bytes that
are contained in the data field of the packet. This field is not
interpreted by the DP83907.
Data Field
The data field consists of anywhere from 46 to 1500 bytes.
Messages longer than 1500 bytes need to be broken into
multiple packets. Messages shorter than 46 bytes will require appending a pad to bring the data field to the minimum
length of 46 bytes. If the data field is padded, the number of
valid data bytes is indicated in the length field. The
DP83907 does not strIp or append pad bytes for short
packets, or check for oversize packets.
FCS Field
The Frame Check Sequence (FCS) is a 32-bit CRC field
calculated and appended to a packet during transmission to
allow detection of errors when a packet is received. During
reception, error free packets result in a specific pattern in
the CRC generator. Packets with improper CRC will be rejected. The AUTODIN II (X32 a X26 a X23 a X22 a X16 a
X12 a X11 a X10 a X8 a X7 a X5 a X4 a X2 a X1 a 1)
polynomial is used for the CRC calculations.
TL/F/12082–21
FIGURE 26. Ethernet Packet
40
6.0 Operation of DP83907 (Continued)
TL/F/12082 – 22
FIGURE 27. DP83907 Bus Architecture
Remote DMA channel is not used when the DP83907 is
used in a shared Memory mode. In this second mode the
buffer memory is dual ported, and directly mapped into the
system memory. In this mode the system CPU directly accesses the RAM under software control to transfer packet
data.
The following sections describe the operation of the Local
DMA channel for packet reception which is used in both
modes. For Shared Memory mode the description of the
Remote DMA does not apply.
For reference an example configuration using the DP83907
is shown in Figure 27 .
6.2 BUFFER MEMORY ACCESS CONTROL (DMA)
The buffer memory control capabilities of the DP83907
greatly simplify the use of the DP83907 in typical configurations. The local DMA channel transfers data between the
FIFO and memory. On transmission, the packet is DMA’d
from memory to the FIFO in bursts. Should a collision occur
(up to 15 times), the packet is re-transmitted with no processor intervention. On reception, packets are moved via DMA
from the FIFO to the receive buffer ring (as explained below).
A Remote DMA channel is also provided on the DP83907 to
accomplish transfers between a buffer memory and an internal Data Port when using the DP83907 in I/O Mode. This
TL/F/12082 – 23
FIGURE 28. DP83907 Receive Buffer Ring
41
6.0 Operation of DP83907 (Continued)
6.3 PACKET RECEPTION
Initialization of the Buffer Ring
The Local DMA receive channel uses a Buffer Ring Structure comprised of a series of contiguous fixed length 256
byte (128 word) buffers for storage of received packets. The
location of the Receive Buffer Ring is programmed in two
registers, a Page Start and a Page Stop Register. Ethernet
packets consist of a distribution of shorter link control packets and longer data packets, the 256 byte buffer length provides a good compromise between short packets and longer packets to most efficiently use memory. In addition these
buffers provide memory resources for storage of back-toback packets in loaded networks. The assignment of buffers
for storing packets is controlled by Buffer Management Logic in the DP83907. The Buffer Management Logic provides
three basic functions: linking receive buffers for long packets, recovery of buffers when a packet is rejected, and recirculation of buffer pages that have been read by the host.
At initialization, a portion of the 64k byte (or 32k word) address space is reserved for the receive buffer ring. Two
eight bit registers, the Page Start Address Register
(PSTART) and the Page Stop Address Register (PSTOP)
define the physical boundaries of where the buffers reside.
The DP83907 treats the list of buffers as a logical ring;
whenever the DMA address reaches the Page Stop Address, the DMA is reset to the Page Start Address.
Two static registers and two working registers control the
operation of the Buffer Ring. These are the Page Start Register, Page Stop Register (both described previously), the
Current Page Register and the Boundary Pointer Register.
The Current Page Register points to the first buffer used to
store a packet and is used to restore the DMA for writing
status to the Buffer Ring or for restoring the DMA address in
the event of a Runt packet, a CRC, or Frame Alignment
error. The Boundary Register points to the first packet in the
Ring not yet read by the host. If the local DMA address ever
reaches the Boundary, reception is aborted. The Boundary
Pointer is also used to initialize the Remote DMA for removing a packet and is advanced when a packet is removed. A
simple analogy to remember the function of these registers
is that the Current Page Register acts as a Write Pointer and
the Boundary Pointer acts as a Read Pointer.
Note 1: At initialization, the Page Start Register value should be loaded into
both the Current Page Register and the Boundary Pointer Register, if using
the Send Packet Command. If using manual Remote Reads, the Current
Page Register must always remain 1 a Boundary Register.
Note 2: The Page Start Register must not be initialized to 00H.
Beginning of Reception
When the first packet begins arriving the DP83907 begins
storing the packet at the location pointed to by the Current
Page Register. An offset of 4 bytes is saved in this first
buffer to allow room for storing receive status corresponding to this packet.
TL/F/12082–24
FIGURE 29. Buffer Ring at Initialization
TL/F/12082-25
FIGURE 30. Received Packet Enters the Buffer Pages
42
6.0 Operation of DP83907 (Continued)
Linking Receive Buffer Pages
Buffer Ring Overflow
If the length of the packet exhausts the first 256 byte buffer,
the DMA performs a forward link to the next buffer to store
the remainder of the packet. For a maximal length packet
the buffer logic will link six buffers to store the entire packet.
Buffers cannot be skipped when linking, a packet will always
be stored in contiguous buffers. Before the next buffer can
be linked, the Buffer Management Logic performs two comparisons. The first comparison tests for equality between
the DMA address of the next buffer and the contents of the
Page Stop Register. If the buffer address equals the Page
Stop Register, the buffer management logic will restore the
DMA to the first buffer in the Receive Buffer Ring value
programmed in the Page Start Address Register. The second comparison tests for equality between the DMA address of the next buffer address and the contents of the
Boundary Pointer Register. If the two values are equal the
reception is aborted. The Boundary Pointer Register can be
used to protect against overwrfting any area in the receive
buffer ring that has not yet been read. When linking buffers,
buffer management will never cross this pointer, effectively
avoiding any overwrites. If the buffer address does not
match either the Boundary Pointer or Page Stop Address,
the link to the next buffer is performed.
If the Buffer Ring has been filled and the DMA reaches the
Boundary Pointer Address, reception of the incoming packet will be aborted by the DP83907. Thus, the packets previously received and still contained in the Ring will not be
destroyed.
In heavily loaded networks which cause overflows of the
Receive Buffer Ring, the DP83907 may disable the local
DMA and suspend further receptions even if the Boundary
register is advanced beyond the Current register. In the
event that the DP83907 should encounter a receive buffer
overflow, it is necessary to implement the following routine.
A receive buffer overflow is indicated by the DP83907’s assertion of the overflow bit (OVW) in the Interrupt Status
Register (ISR).
If this routine is not adhered to, the DP83907 may act in an
unpredictable manner. It should also be noted that it is not
permissible to service an overflow interrupt by continuing to
empty packets from the receive buffer without implementing
the prescribed overflow routine. A flow chart of the
DP83907’s overflow routine can be found in Figure 32 .
Note: It is necessary to define a variable in the driver, which will be called
‘‘Resend’’.
1) Read and store the value of the TXP bit in the
DP83907’s Command Register.
2) Issue the STOP command to the DP83907. This is accomplished by setting the STP bit in the DP83907’s
Command Register. Writing 21H to the Command Register will stop the DP83907.
3) Wait for at least 1.6 ms. Since the DP83907 will complete any transmission or reception that is in progress,
it is necessary to time out for the maximum possible
duration of an Ethernet transmission or reception. By
waiting 1.6 ms this is achieved with some guard band
added. Previously, it was recommended that the RST
bit of the nterrupt Status Register be polled to insure
that the pending transmission or reception is completed. This bit is not a reliable indicator and subsequently
should be ignored.
Linking Buffers
Before the DMA can enter the next contiguous 256 byte
buffer, the address is checked for equality to PSTOP and to
the Boundary Pointer. If neither are reached, the DMA is
allowed to use the next buffer.
TL/F/12082 – 26
FIGURE 31. Linking Receive Buffer Pages
43
6.0 Operation of DP83907 (Continued)
4) Clear the DP83907’s Remote Byte Count registers
(RBCR0 and RBCR1).
5) Read the stored value of the TXP bit from step 1,
above.
If this value is a 0, set the ‘‘Resend’’ variable to a 0 and
jump to step 6.
If this value is a 1, read the DP83907’s Interrupt Status
Register. If either the Packet Transmitted bit (PTX) or
Transmit Error bit (TXE) is set to a 1, set the ‘‘Resend’’
variable to a 0 and jump to step 6. If neither of these
bits is set, place a 1 in the ‘‘Resend’’ variable and jump
to step 6.
This step determines if there was a transmission in
progress when the stop command was issued in step 2.
If there was a transmission in progress, the DP83907’s
ISR is read to determine whether or not the packet was
recognized by the DP83907. If neither the PTX nor TXE
bit was set, then the packet will essentially be lost and
retransmitted only after a time-out takes place in the
upper level software. By determining that the packet
was lost at the driver level, a transmit command can be
reissued to the DP83907 once the overflow routine is
completed (as in step 11). Also, it is possible for the
DP83907 to defer indefinitely, when it is stopped on a
busy network. Step 5 also alleviates this problem. Step
5 is essential and should not be omitted from the overflow routine, in order for the DP83907 to operate correctly.
6) Place the DP83907 in either mode 1 or mode 2 loopback. This can be accomplished by setting bits D2 and
D1, of the Transmit Configuration Register, to ‘‘0,1’’ or
‘‘1,0’’, respectively.
7) Issue the START command to the DP83907. This can
be accomplished by writing 22H to the Command Register. This is necessary to activate the DP83907’s Remote DMA channel.
8) Remove one or more packets from the receive buffer
ring.
9) Reset the overwrite warning (OVW, overflow) bit in the
Interrupt Status Register.
10) Take the DP83907 out of loopback. This is done by
writing the Transmit Configuration Register with the value it contains during normal operation. (Bits D2 and D1
should both be programmed to 0.)
11) If the ‘‘Resend’’ variable is set to a 1, reset the ‘‘Resend’’ variable and reissue the transmit command. This
is done by writing a value of 26H to the Command Register. If the ‘‘Resend’’ variable is 0, nothing needs to be
done.
Note 1: If Remote DMA is not being used, the DP83907 does not need to
be started before packets can be removed from the receive buffer
ring. Hence, step 8 could be done before step 7, eliminating or
reducing the time spent polling in step 5.
Note 2: When the DP83907 is in ST0P mode, the Missed Packet Tally
counter is disabled.
TL/F/12082 – 27
FIGURE 32. Overflow Routine
44
6.0 Operation of DP83907 (Continued)
TL/F/12082 – 28
FIGURE 33. Received Packet Aborted
if it Hits Boundary
Enabling the DP83907 on an Active Network
After the DP83907 has been initialized the procedure for
disabling and then re-enabling the DP83907 on the network
is similar to handling Receive Buffer Ring overflow as described previously.
1) Program Command Register for page 0 (Command
Register e 21H)
2) lnitialize Data Configuration Register (DCR)
3) Clear Remote Byte Count Registers (RBCR0, RBCR1)
if using Remote DMA.
4) lnitialize Receive Configuration Register (RCR)
5) Place the DP83907 in LOOPBACK mode 1 or 2 (Transmit Configuration Register e 02H or 04H)
6) Initialize Receive Buffer Ring: Boundary Pointer
(BNDRY), Page Start (PSTART), and Page Stop
(PSTOP)
7) CIear Interrupt Status Register (ISR) by writing OFFH to
it.
8) lnitialize Interrupt Mask Register (IMR)
9) Program Command Register for page 1 (Command
Register e 61H)
i) Initialize Physical Address Registers (PAR0– PAR5)
ii) Initialize Multicast Address Registers (MAR0 –
MAR7)
iii) Initialize CURRENT pointer
10) Put DP83907 in START mode (Command Register e
22H). The local receive DMA is still not active since the
DP83907 is in LOOPBACK.
11) Initialize the Transmit Configuration for the intended
value. The DP83907 is now ready for transmission and
reception.
TL/F/12082 – 29
FIGURE 34. Termination of Received
Packet-Packet Accepted
Successful Reception
If the packet is successfully received, the DMA is restored
to the first buffer used to store the packet (pointed to by the
Current Page Register). The DMA then stores the Receive
Status, a Pointer to where the next packet will be stored
(Buffer 4) and the number of received bytes. Note that the
remaining bytes in the last buffer are discarded and reception of the next packet begins on the next empty 256-byte
buffer boundary. The Current Page Register is then initialized to the next available buffer in the Buffer Ring. (The
location of the next buffer had been previously calculated
and temporarily stored in an internal scratchpad register.)
Buffer Recovery for Rejected Packets
If the packet is a runt packet or contains CRC or Frame
Alignment errors, it is rejected. The buffer management logic resets the DMA back to the first buffer page used to store
the packet (pointed to by CURR), recovering all buffers that
had been used to store the rejected packet. This operation
will not be performed if the DP83907 is programmed to accept either runt packets or packets with CRC or Frame
Alignment errors. The received CRC is always stored in
buffer memory after the last byte of received data for the
packet.
End of Packet Operations
At the end of the packet the DP83907 determines whether
the received packet is to be accepted or rejected. It either
branches to a routine to store the Buffer Header or to another routine that recovers the buffers used to store the packet.
TL/F/12082 – 30
FIGURE 35. Termination of Receive
Packet-Packet Reject
45
6.0 Operation of DP83907 (Continued)
General Transmit Packet Format
Error Recovery
If the packet is rejected as shown, the DMA is restored by
the DP83907 by reprogramming the DMA starting address
pointed to by the Current Page Register.
Storage Format for Received Packets
The following diagrams describe the format for how received packets are placed into memory by the local DMA
channel. These modes are selected in the Data Configuration Register.
AD15
AD8
AD7
Next Packet Pointer
Receive Status
Receive Byte Count 0
Byte 2
Byte 1
BOS e 0, WTS e 1 in Data Configuration Register. This format is used with
Series 32xxx, or 808xx processors.
AD15
AD8
AD7
AD0
Next Packet Pointer
Receive Status
Receive Byte Count 0
Receive Byte Count 1
Byte 1
Byte 2
Destination Address
6 Bytes
Byte
Source Address
6 Bytes
Count
Type/Length
2 Bytes
TBCR0, 1
Data
Pad (if data k 46 Bytes)
t 46 Bytes
Transmit Packet Assembly
The DP83907 requires a contiguous assembled packet with
the format shown. The transmit byte count includes the
Destination Address, Source Address, Length Field and
Data. It does not include preamble and CRC. When transmitting data smaller than 46 bytes, the packet must be padded to a minimum size of 64 bytes. The programmer is responsible for adding and stripping pad bytes.
The packets are placed in the buffer RAM by the system. In
I/O Mode the system programs the NIC Core’s Remote
DMA to mode the data from the data port to the RAM handshaking with system transfers loading the I/O data port. In
Shared Memory Mode the packets are written directly to the
RAM by system using standard memory transfer instructions (MOV).
For I/O mode the data transfer must be 16 bits (1 word)
when in 16 bit mode, and 8 bits when the DP83907 is set in
8 bit mode. The data width is selected by setting the WTS
bit in the Data Configuration Register and setting the DWID
pin for the proper mode.
In Shared Memory mode data transfer can be accomplished
by using either 8- or 16-bit data transfer instructions, because this mode responds to 8/16 bit data signaling on the
ISA bus. In this mode Shared Memory Control Register 2 bit
6 sets the bus interface data width, and the NIC Core’s data
width is set by the WTS bit in the Data Configuration Register.
AD0
Receive Byte Count 1
Transmit
BOS e 1, WTS e 1 in Data Configuration Register. This format is used with
680 x 0 type processors. (Note: the Receive Count ordering remains the
same for BOS e 0 or 1.)
Receive Status
Next Packet Pointer
Receive Byte Count 0
Receive Byte Count 1
Byte 0
Byte 1
BOS e 0 WTS e 0 in Data Configuration Register. This format is used with
general 8-bit processors.
Transmission
Prior to transmission, the TPSR (Transmit Page Start Register) and TBCR0, TBCR1 (Transmit Byte Count Registers)
must be initialized. To initiate transmission of the packet the
TXP bit in the Command Register is set. The Transmit
Status Register (TSR) is cleared and the DP83907 begins to
prefetch transmit data from memory (unless the DP83907 is
currently receiving). If the interframe gap has timed out the
DP83907 will begin transmission.
6.4 PACKET TRANSMISSION
The Local DMA is also used during transmission of a packet. Three registers control the DMA transfer during transmission, a Transmit Page Start Address Register (TPSR)
and the Transmit Byte Count Registers (TBCR0, 1). When
the DP83907 receives a command to transmit the packet
pointed to by these registers, buffer memory data will be
moved into the FIFO as required during transmission. The
DP83907 will generate and append the preamble, synch
and CRC fields.
46
6.0 Operation of DP83907 (Continued)
This format is used with Series 32xxx, or 808xx processors.
Conditions Required to Begin Transmission
In order to transmit a packet, the following three conditions
must be met:
1. The Interframe Gap Timer has timed out the first 6.4 ms
of the Interframe Gap
2. At least one byte has entered the FlFO. (This indicates
that the burst transfer has been started)
3. If a collision had been detected then before transmission
the packet time must have timed out.
In typical systems the DP83907 prefetches the first burst of
bytes before the 6.4 ms timer expires. The time during which
DP83907 transmits preamble can also be used to load the
FIFO.
D15
Destination Address 3
Destination Address 2
Destination Address 5
Destination Address 4
Source Address 1
Source Address 0
Source Address 3
Source Address 2
Source Address 5
Source Address 4
Type/Length 1
Type Length 0
Data 1
Data 0
Destination Address 5
Source Address 0
Source Address 1
Source Address 2
Source Address 3
Source Address 4
Source Address 5
Type Length 0
Type/Length 1
Data 0
Data 1
D0
Destination Address 1
Destination Address 2
Destination Address 3
Destination Address 4
Destination Address 5
Source Address 0
Source Address 1
Source Address 2
Source Address 3
Source Address 4
Source Address 5
BOS e 0, WTS e 0 in Data Configuration Register.
This format is used with general 8 bit processors.
D0
Destination Address 0
Destination Address 3
Destination Address 4
Destination Address 0
Transmit Packet Assembly Format
The following diagrams describe the format for how packets
must be assembled prior to transmission for different byte
ordering schemes. The various formats are selected in the
Data Configuration Register.
D7
Destination Address 2
D7
Note: NCR reads as zeroes if excessive collisions are encountered.
D8
D0
Destination Address 1
This format is used with 680x0 type processors.
Collision Recovery
During transmission, the Buffer Management logic monitors
the transmit circuitry to determine if a collision has occurred.
If a collision is detected, the Buffer Management logic will
reset the FlFO and restore the Transmit DMA pointers for
retransmission of the packet. The COL bit will be set in the
TSR and the NCR (Number of Collisions Register) will be
incremented. If 15 retransmissions each result in a collision
the transmission will be aborted and the ABT bit in the TSR
will be set.
Destination Address 1
D7
BOS e 1, WTS e 1 in Data Configuration Register.
Note: If carrier sense is asserted before a byte has been loaded into the
FIFO, the DP83907 will become a receiver.
D15
D8
Destination Address 0
Note: All examples above will result in a transmission of a packet in order of
DA0. DA1, DA3... bits within each byte will be transmitted least significant bit first.
DA e Destination Address
BOS e 0, WTS e 1 in Data Configuration Register.
47
6.0 Operation of DP83907 (Continued)
To initiate a loopback the user first assembles the loopback
packet then selects the type of loopback using the Transmit
Configuration register bits LB0, LB1. The transmit configuration register must also be set to enable or disable CRC generation during transmission. The user then issues a normal
transmit command to send the packet. During loopback the
receiver checks for an address match and if CRC bit in the
TCR is set, the receiver will also check the CRC. The last 8
bytes of the loopback packet are buffered and can read out
of the FlFO using FlFO read port.
6.5 LOOPBACK DIAGNOSTICS
Three forms of local Ioopback are provided on the
DP83907. The user has the ability to loopback through the
deserializer on the controller, through the ENDEC module or
transceiver. Because of the half duplex architecture of
the DP83907, loopback testing Is a special mode of operation with the following restrictions:
Restrictions During Loopback
The FlFO is split into two halves, one half is used for transmission the other for reception. Only 8-bit fields can be
fetched from memory so two tests are required for 16-bit
systems to verify integrity of the entire data path. During
loopback the maximum latency to obtain access to the buffer memory is 2.0 ms. Systems that wish to use the loopback
test yet do not meet this latency can limit the loopback
packet to 7 bytes without experiencing underflow. Only the
last 8 bytes of the loopback packet are retained in the FlFO.
The last 8 bytes can be read through the FIFO register
which will advance through the FIFO to allow reading the
receive packet sequentially.
Destination Address
e 6 bytes Station Physical
Source Address
e 6 bytes Station Physical
Loopback Modes
MODE1: Loopback Through the DP83907 Controller Module (LB1 e 0, LB0 e 1): If this loopback is used, The
DP83907 Module’s serializer is connected to the deserializer.
MODE 2: Loopback Through the ENDEC Module (LB1 e 1,
LB0 e 0): If the loopback is to be performed through the
SNI, the DP83907 provides a control (LPBK) that forces the
ENDEC module to loopback all signals.
MODE 3: Loopback to the external coax interface or twisted
pair interface module (LB1 e 1, LB0 e 1).
Packets can be transmitted to the cable in loopback mode
to check all of the transmit and receive paths and the cable
itself. If, in twisted pair mode, there is a link fail the transmitter will be disabled which could give misleading results in
Mode 3. The link integrity should be checked, by reading
Configuration Register B, before this test.
Address
Address
Length
2 bytes
Data
e 46 to 1500 bytes
CRC
Appended by DP8307
Controller if CRC e 0 in TCR
Reading the Loopback Packet
The last eight bytes of a received packet can be examined
by 8 consecutive reads of the FlFO register. The FIFO pointer is increment after the rising edge of the CPU’s read
strobe by internally synchronizing and advancing the pointer. This may take up to four bus clock cycles, if the pointer
has not been incremented by the time the CPU reads the
FIFO register again, the DP83907 will insert wait states.
When in word-wide mode with Byte Order Select set, the
loopback packet must be assembled in the even byte locations as shown below. (The loopback only operated with
byte wide transfers.)
LS Byte (D8–D15)
MS Byte (D0–D7)
Note: The FIFO may only be read during Loopback. Reading the FIFO at
any other time will cause the DP83907 to malfunction.
Destination
Source
Alignment of the Received Packet In the FIFO
Reception of the packet in the FIFO begins at location zero,
after the FIFO pointer reaches the last location in the FlFO,
the pointer wraps to the top of the FlFO overwriting the
previously received data. This process continued until the
last byte is received. The DP83907 then appends the received byte count in the next two locations of the FIFO. The
contents of the Upper Byte Count are also copied to the
next FlFO location. The number of bytes used in the loopback packet determined the alignment of the packet in the
FlFO. The alignment for a 64-byte packet is shown below.
Length
Data
CRS
WTS e 1
BOS e 1
(DCR Bits)
When in word-wide mode with Byte Order Select low, the
following format must be used for the loopback packet.
MS Byte (D8–D15)
LS Byte (D0–D7)
Destination
Source
Length
Data
CRS
WTS e 1
BOS e 0
(DCR Bits)
Note: When using loopback in word mode 2n bytes must be programmed in
the TBCR0, 1. When n e actual number of bytes assembled in even
or odd location.
48
FIFO
Location
FIFO Contents
0
Lower Byte Count
1
Upper Byte Count
2
Upper Byte Count
#
3
Last Byte
#
4
CRC1
#
5
CRC2
#
6
CRC3
7
CRC4
x
x
First Byte Read
Second Byte Read
#
x
Last Byte Read
6.0 Operation of DP83907 (Continued)
For the following alignment in the FIFO the packet length
should be (N x 8) a 5 Bytes. Note that if the CRC bit in the
TCR is set, CRC will not be appended by the transmitter. If
the CRC is appended by the transmitter, the 1st four bytes,
bytes N-3 to N, correspond to the CRC.
FIFO
Location
RECEIVER ACTIONS
1) Wait for synch, all preamble stripped.
2) Store packet in FIFO, increment receive byte count for
each incoming byte.
3) If CRC e 0 in TRC, receiver checks incoming packet for
CRC errors. If CRC e 1 in TCR, receiver does not check
CRC errors, CRC error bit always set in RSR (for address
matching packets).
4) At end of receive, receive byte count written into FIFO,
receive status register is updated. The PRX bit is typically set in the RSR even if the address does not match. If
CRC errors are forced, the packet must match the address filters in order for the CRC error bit in the RS to be
set.
FIFO Contents
x
x
0
Byte N-4
1
Byte N-3 (CRC1)
First Byte Read
2
Byte N-2 (CRC2)
#
3
Byte N-1 (CRC3)
#
4
Byte N (CRC4)
#
5
Lower Byte Count
#
6
Upper Byte Count
7
Upper Byte Count
Second Byte Read
#
x
EXAMPLES
The following examples show what results can be expected
from a properly operating DP83907 during loopback. The
restrictions and results of each type of loopback are listed
for reference. The loopback tests are divided into two sets
of tests. One to verify the data path, CRC generation and
byte count through all three paths. The second set of tests
uses internal loopback to verify the receiver’s CRC checking
and address recognition. For all of the tests the DCR was
programmed to 40H.
Last Byte Read
Loopback Tests
Loopback capabilities are provided to allow certain tests to
be performed to validate operation of the DP83907 prior to
transmitting and receiving packets on a live network. Typically these tests may be performed during power up of a
node. The diagnostic provides support to verify the following:
1) Verify integrity of data path. Received data is checked
against transmitted data.
2) Verify CRC logic’s capability to generate good CRC on
transmit, verify CRC on receive (good or bad CRC).
3) Verify that the Address Recognition Logic can
a) Recognize address match packets
b) Reject packets that fail to match an address
Path
DP83907
Internal
TCR
RCR
TSR
RSR
ISR
00
53
(Note 1)
02
(Note 2)
02
(Note 3)
02
Note 1: Since carrier sense and collision detect are generated in the ENDEC
module. They are blocked during internal loopbaok, carrier and CD heartbeat
are not seen and the CRS and CDH bits are set.
Note 2: CRC errors are always indicated by receiver if CRC is appended by
the transmitter.
Loopback Operation In the DP83907 Controller
Loopback is a modified form of transmission using only half
of the FIFO. This places certain restrictions on the use of
Ioopback testing. When loopback mode is selected in the
TCR, the FIFO is spilt. A packet should be assembled in
memory with programming of TPSR and TBCR0, TBCR1
registers. When the transmit command is issued the following operations occur:
Note 3: Only the PTX bit in the ISR is set, the PRX bit is only set if status is
written to memory. In loopback this action does not occur and the PRX bit
remains 0 for all loopbaok modes.
Note 4: All values are hex.
Path
DP83907
Internal
TRANSMITTER ACTIONS
1) Data is transferred from memory by the DMA until the
FIFO is filled. For each transfer TBCR0 and TBCR1 are
decremented. (Subsequent burst transfers are initiated
when the number of bytes in the FIFO drops below the
programmed threshold.)
2) The DP83907 generates 56 bits of preamble followed by
an 8-bit synch pattern.
3) Data transferred from FIFO to serializer.
4) If CRC e 1 in TCR, no CRC calculated by DP83907, the
last byte transmitted is the last byte from the FIFO (Allows software CRC to be appended). If CRC e 0,
DP83907 calculates and appends four bytes of CRC.
5) At end of Transmission PTX bit set in ISR.
TCR
04
RCR
TSR
RSR
ISR
00
43
(Note 1)
02
02
Note 1: CDH is set, CRS is not set since it is generated by the external
encoder/decoder.
Path
DP83907
Internal
TCR
06
RCR
TSR
RSR
ISR
00
03
(Note 1)
02
02
(Note 2)
Note 1: CDH and CRS should not be set. The TSR however, could also
contaln 01H, 03H, 07H and a variety of other values depending on whether
collisions were encountered or the packet was deferred.
Note 2: Will contain O8H if packet is not transmittable.
Note 3: During external loopback the DP83907 Controller is now exposed to
network traffic, it is therefore possible for the contents of both the Receive
portion of the FIFO and the RSR to be corrupted by any other paoket on the
network. Thus in a live network the contents of the FIF0 and RSR should not
be depended on. The DP83907 will still abide by the standard CSMA/CD
protocol in external loopback mode. (i.e. The network will not be disturbed
by the loopback paoket).
Note 4: All values are hex.
49
6.0 Operation of DP83907 (Continued)
Typically, the following statistics might be gathered in software:
CRC and Address Recognition
The next three tests exercise the address recognition logic
and CRC. These tests should be performed using internal
Ioopback only so that the DP83907 is isolated from interference from the network. These tests also require the capability to generate CRC in software.
The address recognition logic cannot be directly tested. The
CRC and FAE bits in the RSR are only set if the address if
the packet matches the address filters. If errors are expected to be set and they are not set, the packet has been
rejected on the basis of an address mismatch. The following
sequence of packets will test the address recognition logic.
The DCR should be set to 40H, the TCR should be set to
03H with a software generated CRC.
Packet Contents
Traffic:
Errors:
Results
Test
Address
CRC
RSR
Test A
Test B
Test C
Matching
Matching
Non-Matching
Good
Bad
Bad
01 (Note 1)
02 (Note 2)
01
Frames Sent OK
Frames Received OK
Multicast Frames Received
Packets Lost Due to Lack of
Resources
Retries/Packet
CRC Errors
Alignment Errors
Excessive Collisions
Packet with Length Errors
Heartbeat Failure
6.6 MEMORY ARBITRATION AND BUS OPERATION
The DP83907 will always operate as a slave device on it’s
peripheral interface to the ISA bus. However on the memory
bus, the DP83907 Controller operates in three possible
modes:
1. Bus Master of Local Packet Buffer RAM
2. Bus Slave when accessed by the CPU via the Bus Interface
3. Idle, when no activity is occurring.
Note 1: Status will read 21H if multicast address used.
Note 2: Status will read 22H if multtcast address used.
Note 3: In test A, the RSR is set up. In test B the address is found to match
since the CRC is flagged as bad. Test C proves that the address recognition
logic can distinguish a bad address and does not notify the RSR of the bad
CRC. The receiving CRC is proven to work in test A and test B.
Note 4: All values are hex.
TL/F/12082–31
FIGURE 36. Tally Counters
Network Management Functions
Network management capabilities are required for maintenance and planning of a local area network. The DP83907
supports the minimum requirement for network management in hardware, the remaining requirements can be met
with software. Software alone can not track during reception
of packets: CRC errors, Frame Alignment errors, and
missed packets, Figure 36 .
Since errored packets can be rejected, the status associated with these packets is lost unless the CPU can access the
Receive Status Register before the next packer arrives. In
situations where another packet arrives very quickly, the
CPU may have no opportunity to do this. The DP83907 Controller counts the number of packets with CRC errors and
Frame Alignment errors. 8-bit counters have been selected
to reduce overhead. The counters will generate interrupts
whenever their MSBs are set so that a software routine can
accumulate the network statistics and reset the counter betore overflow occurs. The counters are sticky so that when
they reach a count of 192 (C0H) counting is halted. An additional counter is provided to count the number of packets
the DP83907 misses due to buffer overflow or being off-line.
The structure of the counters is shown in Figure 36 .
Additional information required for network management is
available in the Receive and Transmit Status Registers.
Transmit status is available after each transmission for information regarding events during transmission.
TL/F/12082 – 32
FIGURE 37. DP8390 Core Bus States
Upon power-up the DP83907 is in an indeterminate state.
After receiving a hardware reset the DP83907 is a bus slave
in the Reset State, the receiver and transmitter are both
disabled in this state. The reset state can be re-entered
under four conditions, soft reset (Stop Command), register
reset (reset port), hard reset (RESET input) or an error that
shuts down the receiver of transmitter (FIFO underflow or
overflow, receive buffer ring overflow).
After initialization of registers, the DP83907 Controller is issued a Start command and the DP83907 enters Idle state.
Until the DMA is required the DP83907 remains in idle state.
50
6.0 Operation of DP83907 (Continued)
The idle state is exited and the DP83907 will drive the local
memory bus when a request from the FIFO in the DP8390
(NIC) core causes the memory bus interface logic to issue a
read or write operation, such as when the DP83907 is transmitting or receiving data.
The NIC Core’s Remote DMA also requests access from
the memory bus. When software programs an I/O data
transfer between the CPU and the buffer RAM, the Remote
DMA controls this request.
All Local DMA transfers are burst transfers, the DMA will
transfer an exact burst of bytes programmed in the Data
Configuration Register (DCR) then relinquish the memory
bus. If there are remaining bytes in the FIFO the next burst
will not be initiated until the FIFO threshold is exceeded.
I/O Mode Operation
In I/O mode the DP83907 transfers data to and from the
packet buffer RAM by utilizing the Remote DMA logic which
is programmed by the main system CPU to transfer data
through the DP83907’s internal data
TL/F/12082 – 34
FIGURE 39. 1st Received Packet Removed
by Remote DMA
I/O MODE REMOVING PACKETS FROM RING
Network activity is isolated on a local bus, where the
DP83907’s local DMA channel performs burst transfers between the buffer memory and the DP83907’s FIFO. The Remote DMA transfers data between the buffer memory and
the host memory via the internal bi-directional I/O port. The
Remote DMA provides local addressing capability and is
used as a slave DMA by the host. The host system reads
the I/O port to transfer data between the system and I/O
port. The DP83907 allows Local and Remote DMA operations to be interIeaved.
Packets are removed from the ring using the Remote DMA.
When using the Remote DMA the Send Packet command
can be used. This programs the Remote DMA to automatically remove the received packet pointed to by the Boundary Pointer. At the end of the transfer, the DP83907 moves
the Boundary Pointer, freeing additional buffers for reception. The Boundary Pointer can also be moved manually by
programming the Boundary Register. Care should be taken
to keep the Boundary Pointer at least one buffer behind the
Current Page Pointer.
Data transfer by the Remote DMA to the integrated I/O data
port is dependent on whether the DP83907 is set into 8 bit
mode or 16 bit mode. In 8 bit mode all transfers are 8 bits (1
byte) wide. When in 16 bit mode all transfers are 16 bits (1
word) wide. The data width is selected by setting the WTS
bit in the data Configuration Register and setting the DWID
pin for the proper mode.
The following is a suggested method for maintaining the
Receive Buffer Ring pointers:
1. At initialization, set up a software variable (nextÐpkt) to
indicate where the next packet will be read. At the beginning of each Remote Read DMA operation, the value of
nextÐpkt will be loaded into RSAR0 and RSAR1.
2. When initializing the DP83907 Controller set:
BNDRY e PSTART
TL/F/12082 – 33
FIGURE 38. I/O Operation: All Data Transfers and
Arbitration is Controlled by the NIC Core
INTERLEAVED LOCAL/REMOTE OPERATION
When in I/O mode the remote DMA is used to transfer data
to/from the main system. If a remote DMA transfer is initiated or in progress when a packet is being received or transmitted, the Remote DMA transfers will be interrupted for
higher priority Local DMA transfers. When the Local DMA
transfer is completed the Remote DMA will rearbitrate for
the bus and continue its transfers.
If the FIFO requires service while a remote DMA is in progress the Local DMA burst is appended to the Remote Transfer. When switching from a local transfer to a remote transfer there is a break to allow the CPU to fairly contend for the
bus.
REMOTE DMA BI-DIRECTIONAL PORT
The Remote DMA transfers data between the local buffer
memory and the internal bi-directional port (memory to I/O
transfer).
This transfer is arbitrated on a transfer by transfer basis
versus the burst transfer mode used for Local DMA transfers. This bi-directional port is integrated onto the DP83907,
and is read/written by the host. All transfers through this
port are asynchronous. At any one time transfers are limited
to one direction, either form the port to local buffer memory
(Remote Write) or form local buffer memory to the port (Remote Read).
CURR e PSTART a 1
nextÐpkt e PSTART a 1
3. After a packet is DMAed from the Receive Buffer Ring,
the Next Page Pointer (second byte in the DP83907 Controller buffer header is used to update BNDRY and
nextÐpkt.
51
6.0 Operation of DP83907 (Continued)
TL/F/12082 – 35
FIGURE 40. Remote DMA Auto Initialization from Buffer Ring
There are three modes of Remote DMA operation: Remote
Write, Remote Read, or Send Packet.
Two register pairs are used to control the Remote DMA, a
Remote Start Address (RSAR0, RSAR1) and a Remote
Byte Count (RBCRO, RBCR1) register pair. The Start Address Register pair points to the beginning of the block to be
moved while the Byte Count Register pair is used to indicate
the number of bytes to be transferred. Full handshake logic
is provided to move data between local buffer memory and
a bi-directional I/O port.
Remote Write: A Remote Write transfer is used to move a
block of data from the host into local buffer memory. The
Remote DMA will read data from the I/O port and sequentially write it to local buffer memory beginning at the Remote
Start Address. The DMA Address will be incremented and
the Byte Counter will be decremented after each transfer.
The DMA is terminated when the Remote Byte Count Register reaches a count of zero.
Remote Read: A Remote Read transfer is used to move a
block of data from local buffer memory to the host. The
Remote DMA will sequentially read data from the local buffer memory, beginning at the Remote Start Address, and
write data to the I/O port.
nextÐpkt e Next Page Pointer
BNDRY e Next Page Pointer b 1
If BNDRY k PSTART then BNDRY e PSTOP b 1
Note the size of the Receive Buffer Ring is reduced by one
256-byte buffer, this will not, however impede the operation
of the DP83907. The advantage of this scheme is that it
easily differentiates between buffer full and buffer empty: it
is full if BNDRY e CURR; empty when BNDRY e CURR-1.
If, in I/O mode, send packet is used to empty the buffer ring
this scheme cannot be used. BNDRY must be initialized
equal to CURR, or the first executed send packet will not
return data from the received packet, which will be written at
CURR. The Overwrite Warning bit of the Interrupt Status
Register must be used in this mode to differentiate between
buffer full and buffer empty.
I/O REMOTE DMA COMMANDS
The Remote DMA channel is used in the I/O Mode to both
assemble packets for transmission, and to remove received
packets from the Receive Buffer Ring. It may also be used
for moving blocks of data or commands between host memory and local buffer memory. (In Shared Memory Mode, the
Remote DMA should be disabled, and not used. Packet
transfer to/from the system is accomplished by normal CPU
read/write operations.)
52
6.0 Operation of DP83907 (Continued)
The DMA Address will be incremented and the Byte Counter will be decremented after each transjer. The DMA is
terminated when the Remote Byte Count Register reaches
zero.
Send Packet Command: The Remote DMA channel can
be automatically initialized to transfer a single packet from
the Receive Buffer Ring. The CPU begins this transfer by
issuing a ‘‘Send Packet’’ Command. The DMA will be initialized to the value of the Boundary Pointer Register and the
Remote Byte Count Register pair (RBCR0, RBCR1) will be
initialized to the value of the Receive Byte Count fields
found in the Buffer Header of each packet. After the data is
transferred, the Boundary Pointer is advanced to allow the
buffers to be used for new receive packets. The Remote
Read will terminate when the Byte Count equals zero. The
Remote DMA is then prepared to read the next packet from
the Receive Buffer Ring. If the DMA pointer crosses the
Page Stop Register, it is reset to the Page Start Address.
This allows the Remote DMA to remove packets that have
wrapped around to the top of the Receive Buffer Ring.
I/O WRITE TIMING
A Remote Write operation transfers data from the I/O port
to the local buffer RAM. The system transfers a byte-word
to the latch via IOWR. This write strobe is detected by the
DP83907 and the byte/word is transferred to local buffer
memory. The Remote DMA holds off further transfers into
the latch until the current byte/word has been transferred
from the latch.
1) DP83907 awaits data to be written by the system. System writes byte/word into latch.
2) Remote DMA reads contents of port and writes byte/
word to local buffer memory, increments address and
decrements byte count (RBCR0,1).
3) Go back to step 1.
Steps 1 – 3 are repeated until the remote DMA is complete.
6.7 FUNCTIONAL BUS TIMING
This section describes the bus cycles that the DP83907 performs. These timings can be subdivided into 3 basic categories:
1. ISA I/O Access: There are register accesses in both
modes, and I/O data accesses in I/O mode.
2. Shared RAM ISA Accesses: These are the timing for the
ISA bus accesses through the DP83907 to the memory
bus and buffer RAM.
3. Boot PROM ISA Accesses: These are the timing for the
ISA bus accesses through the DP83907 to the memory
bus and boot PROM.
4. Local and I/O RAM Accesses: This is the timing of the
Local DMA, accesses from the NlC Core FlF0 to the
RAM, and the Remote DMA accesses to the RAM over
the memory bus.
Note 1: In order for the DP83907 Controller to correctly execute the Send
Packet Command, the upper Remote Byte Count Register (RBCR1)
must first be loaded with 0FH.
Note 2: The Send Packet command cannot be used with 680x0 type processors.
I/O READ TIMlNG
1) The DMA reads word from local buffer memory and
writes the word into the internal latch, increments the
DMA address and decrements the byte count
(RBCR0,1).
2) Internally a request line is asserted to enable the system
to read the port. If the system reads this port before the
data has been written, then the system is sent a wait
signal to wait until the data has been written to the port.
Once written the systems read is allowed to complete.
3) The system reads the port, the read strobe for the port is
used as an acknowledge to the Remote DMA and it goes
back to step 1.
Steps 1 – 3 are repeated until the remote DMA is complete.
(i.e.. the byte count has gone to zero.)
Note that in order for the Remote DMA to transfer a word
from memory to the latch, it must arbitrate access to the
local buffer RAM. After each word is transferred to the internal latch, access to the RAM is relinquished. If a Local DMA
is in progress, the Remote DMA is held off until the local
DMA is complete.
ISA Bus I/O Accesses
The DP83907 is designed to directly interface to the ISA bus
(PC AT backplane bus). The CPU can read or write any
internal registers. All register accesses are byte wide. The
functional timing for DP83907 accesses are shown in the
following pages.
53
6.0 Operation of DP83907 (Continued)
8-Bit I/O Slave Read
TL/F/12082 – 36
This is the type of cycle used to read from a register or, in 8-bit mode, from a data transfer port. These accesses are entirely
asynchronous, with the DP83907 responding when it decodes the correct address on SA0-9 and an IORD. If AEN is high the
cycle will be ignored. CHRDY is deasserted if the DP83907 is not ready to respond and asserted when ready. If it is ready
immediately CHRDY is not deasserted. The data will always appear on SD0-7.
8-Bit I/O Slave Write
TL/F/12082 – 37
This is the type of cycle used to write to a register or, in 8-bit mode, to a data transfer port. These accesses are entirely
asynchronous, with the DP83907 responding when it decodes the correct address on SA0-9 and an IOWR. If AEN is high the
cycle will be ignored. CHRDY is deasserted if the DP83907 is not ready to respond and asserted when ready. If it is ready
immediately CHRDY is not deasserted. The data will always be taken from SD0-7.
54
6.0 Operation of DP83907 (Continued)
16-Bit I/O Slave Read
TL/F/12082 – 38
This is the type of cycle used to read from a data transfer port in 16-bit mode. These accesses are entirely asynchronous, with
the DP83907 responding when it decodes the correct address on SA0 – 9 and an IORD. If AEN is high the cycle will be ignored.
CHRDY is deasserted if the DP83907 is not ready to respond and asserted when ready. If it is ready immediately CHRDY is not
deasserted. IO16 is generated, when an address within the DP83907’s data transfer port is decoded, to indicate to the system
that this is a 16-bit transfer. If the IO16CON bit in Configuration Register B is low then it will be a straight decode of the SA0 – 9
lines. If that bit is high the IO16 output will be generated after IORD goes active, to indicate that this is a 16-bit transfer, and the
address should be even, SA0 low. The data will appear on SD0 – 15.
16-Bit I/O Slave Write
TL/F/12082 – 39
This is the type of cycle used to write to a data transfer port in 16-bit mode. These accesses are entirely asynchronous, with the
DP83907 responding when it decodes the correct address on SA0 – 9 and an IOWR. If AEN is high the cycle will be ignored.
CHRDY is deasserted if the DP83907 is not ready to respond and asserted when ready. If it is ready immediately CHRDY is not
deasserted. IO16 is generated, when an address within the DP83907’s data transfer port is decoded, to indicate to the system
that this is a 16-bit transfer. If the IO16CON bit in Configuration Register B is low then it will be a straight decode of the SA0 – 9
lines. If that bit is high the IO16 output will be generated after IOWR goes active, to indicate that this is a 16-bit transfer, and the
address should be even, SA0 low. The data will be taken from SD0 – 15.
55
6.0 Operation of DP83907 (Continued)
16-Bit I/O Cycle with IO16 Fix
Some Chips & Technologies and VLSI Technologies PC-AT chip sets have timing requirements in 16-bit I/O cycles that cannot
be achieved by the default DP83907 cycle, described on the previous page. When that cycle is executed with these chip sets,
the system does not recognize the CHRDY signal and does not insert wait states. The system executes a standard cycle and
deasserts IORD or IOW even if CHRDY is still deasserted. The DP83907 recognizes if this situation has occurred, asserts
CHRDY and sets a bus error bit in Configuration Register B to flag this error. Thus the user can test any new system to see if this
error occurs and then take some remedial action. The DP83907 supports a fix which can be selected by software, by writing to
Configuration Register B.
This fix is enabled by setting the IO16 bit of Configuration Register B. In normal operation any time a valid address exists on
SA0-9 IO16 is generated. Delaying IO16 until after the IORD or IOW can cure the problem on non-compliant machines. The
theory is that the system is fooled into thinking an 8-bit peripheral is responding, since IO16 is not generated for the valid
address, and accepts 8-bit I/O cycle timings for CHRDY. It then rechecks IO16 after the IORD or IOW strobe and correctly
determines it is a 16-bit peripheral. If a system did not recheck IO16 it would generate 2, 8-bit cycles instead of 1, 16-bit cycle.
The DP83907 would interpret each 8-bit access as a 16-bit transfer and decrement it’s DMA byte count by 2. Eventually the
system would attempt to access the data transfer port when the DP83907 had finished transferring data and CHRDY would be
deasserted indefinitely. To prevent misoperation this fix should only be implemented on systems that require it.
ISA BUS BOOT PROM ACCESS TIMING
Boot PROM Read Bus Timing
TL/F/12082 – 40
This is the type of cycle used to read the boot PROM. These accesses are entirely asynchronous, with the DP83907 responding
when it decodes the correct address on SA0-19 and a SMRD. If AEN is high the cycle will be ignored. CHRDY is deasserted if
the DP83907 is not ready to respond and asserted when ready. If it is ready immediately CHRDY is not deasserted. The data will
be driven from MSD0-7 onto SD0-7.
56
6.0 Operation of DP83907 (Continued)
Boot PROM Write Bus Timing
TL/F/12082 – 41
This is the type of cycle used to write to the boot PROM. These accesses are entirely asynchronous, with the DP83907
responding when it decodes the correct address on SA0-19 and a SMWR. If AEN is high the cycle will be ignored. CHRDY is
deasserted if the DP83907 is not ready to respond and asserted when ready. If it is ready immediately CHRDY is not deasserted.
The data will normally be taken from SD0-7. However, if M16 is generated and the access is to an odd address the data will be
taken from SD8-15. The data will always be driven onto MSD0-7. The BPWR bit of Configuration Register B must be high to
allow write cycles to the boot PROM.
57
6.0 Operation of DP83907 (Continued)
RAM ACCESS TIMING
Memory Support Read
TL/F/12082 – 42
This is a memory read cycle executed by the DP83907’s internal DMA. This is used to either load the data transfer port, during a
Remote Read in I/O mode, or to load the FIFO, for a transmission on the network, in both modes. This transfer is synchronized
to X1.
Memory Support Write
TL/F/12082 – 43
This is a memory write cycle executed by the DP83907’s internal DMA. This is used to either write from the data transfer port,
during a Remote Write in I/O mode, or to empty the FIFO, during a reception from the network, in both modes. This transfer is
synchronized to X1.
58
7.0 In-Circuit Test (ICT) Description
The test register is made available only when the test bit (D7 of cnfg. A) is set at the following I/O address:
I/O mode: Base a 1FHex.
The test register contains the following bits. Note that when the test bit is low the test register is held set except for D4 and D0
which is reset.
TABLE I. Test Modes (test pin e 1)
Test Mode
D7
D6
D5
D4
D3
D2
D1
D0
SAk9l
1
VIH/VIL
1
1
1
1
1
1
1
0
X
2
VOH/VOL
1
1
1
0
1
0
1
0
1
VIL/VIH test mode when high will AND all inputs (except RESET pin) and present outcome on IRQ k3l. To enable this st-nic
mode must NOT be entered.
VOH/VOL test mode is active in st-nic mode if SA k9l e 1. Then all o/p’s switch with SA k4l as per Table 2.
VOH/VOL mode output states (SAk9l e 1)
TABLE II
Output
SAk4l e 0
SAk4l e 1
MSAk13:1l
1555 Hex
0AAA Hex
MSDk15:0l
AAAA Hex
5555 Hex
SDk15:0l
AAAA Hex
5555 Hex
IRQk15, 12, 11, 10, 9, 5, 4, 3l
A2 Hex
5D Hex
MSWR
0
1
MSRD
1
0
RCS
0
1
BPCS
0
1
EECS
1
0
IO16
0
0
CHRDY (AEN, AORD Must be Low)
0
0
0, 1, 0
1, 0, 1
1
0
GDLNK, ACT, COL
THIN
59
DP83907 Preliminary Specification Design Guide
This document provides information on National Semiconductor’s DP83907 target design parametric specifications. These
specifications are provided as design targets for the DP83907. These parameters should be used to undergo systems design
activities, and are not provided as guaranteed parametric specifications. At this time these specifications are not tested, and are
subject to change based upon National’s product characterization and yield analysis.
Absolute Maximum Ratings
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
b 0.5V to a 7.0V
Supply Voltage (VCC)
Storage Temperature (TSTG)
Package Power Dissipation (PD)
Lead Temperature (TL)
(Soldering, 10 seconds)
Supply Voltage (VCC)
Operating Temperature (TA)
ESD Tolerance:
CZAP e 100 pF, RZAP e 1.5 kX
b 65§ C to a 150§ C
Min
4.75
0
2.0
Max
5.25
a 70
Units
V
§C
kV
900 mW
260§ C
Preliminary DC Specifications
Symbol
Description
Conditions
Min
Max
Units
SUPPLY CURRENT
ICC
Average Active (Transmitting and Receiving)
Supply Current
X1 e 20 MHz Clock
VIN e Switching
150
mA
ICCIDLE
Average Idle Supply Current
X1 e 20 MHz Clock
VIN e VCC or GND
120
mA
TTL INPUTS
VIL
Maximum Low Level Input Voltage
VIH
Minimum High Level Input Voltage
IIN
Input Current
0.8
2.0
VI e VCC or GND
b 10
V
V
a 10
mA
3ST TRI-STATE HIGH DRIVE I/O
VOH
Minimum High Level Output Voltage
IOH e b3 mA
VOL
Maximum Low Level Output Voltage
IOL e 24 mA
2.4
V
VIL
Maximum Low Level Input Voltage
VIH
Minimum High Level Input Voltage
IIN
Input Current
VI e VCC or GND
b 10
a 10
mA
IOZ
Maximum TRI-STATE Output Leakage Current
VOUT e VCC or GND
b 10
a 10
mA
0.1
V
0.5
0.8
2.0
V
V
V
MOS INPUTS, OUTPUTS AND I/O
VOH
Minimum High Level Output Voltage
IOH e b20 mA
VCC b 0.1
VOL
Maximum Low Level Output Voltage
IOL e 20 mA
V
VIL
Maximum Low Level Input Voltage
VIH
Minimum High Level Input Voltage
IIN
Input Current
VI e VCC or GND
b 10
a 10
mA
IIN1
Input Current MSA9–13, MSD0–2
VI e VCC or GND
b 10
a 10
mA
IIN2
Input Current MSD3–15, MSA1–8
VI e VCC or GND
RESET e Active
b 10
a 10
mA
IOZ
Maximum TRI-STATE Output Leakage Current
VOUT e VCC or GND
b 10
a 10
mA
IOL e 24 mA
0.5
V
IOL e 16 mA
0.5
V
0.8
2.0
V
V
OCH OPEN COLLECTOR HIGH DRIVE OUTPUT
VOL
Maximum Low Level Output Voltage
LED DRIVER OUTPUT
VOL
Maximum Low Level Output Voltage
60
Preliminary DC Specifications (Continued)
Symbol
Description
Conditions
Min
Max
Units
OSCILLATOR PINS (X1 AND X2)
VIH
X1 Input High Voltage
X1 is Connected to an
Oscillator
2.0
V
VIL
X1 Input Low Voltage
X1 is Connected to an
Oscillator
0.8
V
IOSC
X1 Input Current
X1 is Connected to an
Oscillator
VIN e VCC or GND
1
mA
TXOd g , TXO g Low Level Output Resistance
IOL e 25 mA
15
X
RTOH
TXOd g , TXO g High Level Output Resistance
IOH e b 25 mA
15
X
VSRON1
Receive Threshold Turn-On Voltage
10BASE-T Mode
g 300
g 585
mV
VSRON2
Receive Threshold Turn-On Voltage
Reduced Threshold
g 175
g 300
mV
VSROFF
Receive Threshold Turn-Off Voltage
g 175
g 300
mV
VDIFF
Differential Mode Input Voltage Range
VCC e 5.0V (Note 1)
b 3.1
a 3.1
VOD
Differential Output Voltage
On-Chip Filters Selected
TPI
RTOL
(Note 1)
100X Load
Typical:
5.0
(Notes 1, 2)
V
V
pk-pk
AUI
VOD
Differential Output Voltage (TX g )
78X Termination (Note 1)
VOB
Differential Idle Output Voltage
Imbalance (TX g )
78X Termination (Note 1)
VU
Undershoot Voltage (TX g )
78X Termination (Note 1)
VDS
Differential Squelch Threshold (RX g , CD g )
VCM
Differential Input Common Mode Voltage
(RX g , CD g )
(Note 1)
g 550
g 1200
mV
Typical: 40 mV
Typical: 80 mV
b 175
b 300
mV
0
5.25
V
Note 1: Not Tested in Production Test.
Note 2: In on-chip filter mode, the value of TPI VOD when measured driving a 100X load may not meet the IEEE 802.3 specification over temperature and process
without the use of a resistor on RTX. This does not adversely effect system performance. For more details please refer to Applications Note AN-974.
61
Preliminary Switching Design Guidelines
Memory Support Bus Accesses (for I/O port or FIFO transfers)
TL/F/12082 – 44
MEMORY SUPPORY BUS ACCESSES (for I/O Port or FIFO Transfers)
Symbol
Description
8-Bit Transfers
16-Bit Transfers
Min
Min
Max
Units
Max
T1
MSA1–13 Valid before RCS
Asserted
T2
MSA1–13 Valid before
MSRD–WR Asserted
20
20
ns
T3
MSRD–WR Width
70
70
ns
T4
RCS Valid to MSWR or MSRD Deasserted
105
105
ns
T5
MSA1–13 Valid after
MSRD–WR Deasserted
10
10
ns
T6
RCS Held after MSRD–WR
Deasserted
10
10
ns
T7
RCS Active to MSD(0:15) Valid
T8
Read Data Hold from MSRD Deasserted
0
0
ns
T9
Write Data Set-Up to MSWR Deasserted
40
40
ns
T10
Write Data Hold from MSWR Deasserted
10
10
ns
30
30
100
62
100
ns
ns
Preliminary Switching Design Guidelines (Continued)
ISA SLAVE ACCESSES
TL/F/12082 – 45
63
Preliminary Switching Design Guidelines (Continued)
ISA SLAVE ACCESSES (Continued)
Symbol
8-Bit Transfers
Description
Min
Max
16-Bit Transfers
Min
Units
Max
T2
AEN Valid before Command Strobe Active
60
60
ns
T3a
SA0–9 Valid before IORD, IOWR Asserted
40
20
ns
T3b
SA0–19 Valid before SMRD, SMWR Asserted
32
T4
SMRD, IORD, Asserted to SD0–15 Driven (Notes 3, 14)
0
T5a
SA0–9 Valid before IO16 Valid (Notes 1, 9)
60
ns
T5c
SA0–9 Valid and IORD, IOWR
Active before IO16 Valid (Notes 1, 10)
50
ns
T6a
IORD, IOWR Asserted to CHRDY Negated (Notes 2, 5)
100
50
ns
T6b
SMRD, SMWR Asserted to CHRDY Negated (Note 2)
100
T7
SMRD, SMWR, IORD, IOWR,
Negated before SA0–9 Invalid
20
20
ns
T9
SMRD, IORD, Negated to SD0–15 Read Data Invalid
(notes 3, 14)
0
0
ns
T10
SMRD, IORD negated to SD0–15 Floating (Note 3)
T11
D0–15 Write Data Valid to IOWR, SMWR Negated (Note 3)
60
T12
SMWR, IOWR, Negated to SD0–15 Write Data Invalid (Note 3)
20
20
ns
T13
SMRD, SMWR, IORD, IOWR Active Width (Note 8)
300
140
ns
T14a
IORD, IOWR Inactive Width
85
85
ns
T14b
SMRD, SMWR, Inactive Width
150
150
ns
T17
CHRDY Asserted to SD0–15 Read
Data Valid (Notes 2, 3, 6)
T18
SMRD, SMWR, IORD, IOWR Negated before AEN Invalid
T20
SMRD, IORD Asserted to SD0–15 Read Data Valid (Notes 3 and 7)
150
T24
Read Data Valid on MSD0–7 to Valid on SD0–7
70
T25
MSRD Deasserted to MSD0–7 Read Data Invalid (Note 3)
T26
Write Data Valid on SD0–7 to Valid on MSD0–7
ns
0
ns
45
45
40
60
25
60
25
0
ns
ns
ns
ns
90
ns
ns
ns
90
64
ns
ns
Preliminary Switching Design Guidelines (Continued)
ISA SLAVE ACCESSES (Continued)
Symbol
Description
8-Bit Transfers
16-Bit Transfers
Min
Min
Max
Units
Max
T27
SA0–19 Valid to BPCS Asserted (Note 11)
55
55
ns
T28a
MRD Asserted to MSRD Asserted
60
60
ns
T28b
MWR Asserted to MSWR Asserted
120
120
ns
T30
SA0–19 Invalid to BPCS Negated (Note 11)
0
T31
SMRD, Deasserted to MSRD Deasserted
0
ns
T33
MSWR Deasserted to MSD0–7 Invalid (Note 3)
0
ns
T35
BPCS Asserted to CHRDY Asserted (Note 13)
175
ns
T36
MSRD Asserted to CHRDY Asserted (Note 13)
150
ns
T38
MSD0-7 Asserted to CHRDY Asserted (Note 13)
250
ns
ns
Note 1: M16, IO16 are only asserted for 16-bit transfers.
Note 2: CHRDY is only deasserted if the NIC core can not service the access immediately. It is held deasserted until the NIC core is ready, causing the system to
insert wait states.
Note 3: On 8-bit transfers only 8 bits of MSD0–15 and D0–7 are driven.
Note 5: This is the standard CHRDY timing where CHRDY is asserted after IORD or IOWR.
Note 6: Read data valid is referenced to CHRDY when wait states have been inserted.
Note 7: If no wait states are inserted read data valid can be measured from IORD.
Note 8: This is a minimum timing with no additional wait states.
Note 9: This is the standard IO16 timing where IO16 is asserted after a valid address decode.
Note 10: This is the late IO16 timing, required by some machines, where IO16 is asserted after a valid address decode and IORD or IOWR going active.
Note 11: This is a timing for a RAM access.
Note 13: This is a timing for a Boot PROM access.
Note 14: Guaranteed by design.
SERIAL EEPROM TIMING
TL/F/12082 – 46
Symbol
Description
Min
Max
Units
T1
EECS Setup to MSD2
150
ns
T2
EECS Hold after MSD2
250
ns
T3
MSD2 Low Time
450
ns
T4
MSD2 High Time
450
ns
T5
MSD2 Clock Period (Note 1)
1
ms
T6
MSD1 Setup to MSD2 High
100
ns
T7
MSD2 Hold from MSD2 High
100
T8
MSD0 Valid from MSD2 High
ns
500
Note 1: Derived from crystal oscillator tolerance e g 0.01%.
65
ns
Preliminary Switching Design Guidelines (Continued)
TPI RECEIVE TIMING (End of Packet)
TL/F/12082 – 47
Symbol
Description
Min
Max
Units
teop1
Receive End of Packet Hold Time after Logic ‘‘1‘‘ (Note 1)
225
ns
teop0
Receive End of Packet Hold Time after Logic ‘‘0‘‘ (Note 1)
225
ns
Note 1: This parameter guaranteed by design and is not tested.
LINK PULSE TIMING
TL/F/12082 – 48
Symbol
Description
Min
Max
Units
tIp
Time between Link Output Pulses
8
24
ns
tIpw
Link Integrity Output Pulse Width
80
130
ns
66
Preliminary Switching Design Guidelines (Continued)
TPI TRANSMIT TIMING (End of Packet)
TL/F/12082 – 49
Description
Min
Max
tdel
Symbol
Pre-Emphasis Output Delay (TXO g to TXOd g ) (Note 1)
46
54
tOff
Transmit Hold Time at End of Packet (TXO g ) (Note 1)
250
ns
tOffd
Transmit Hold Time at End of Packet (TXOd g ) (Note 1)
200
ns
Note 1: This parameter is guaranteed by design and is not tested.
67
Units
ns
Preliminary Switching Design Guidelines (Continued)
AUI TRANSMIT TIMING (End of Packet)
TL/F/12082 – 50
Description
Min
tTOh
Symbol
Transmit Output High before Idle (Note 1)
200
Max
Units
ns
tTOI
Transmit Output Idle Time (Note 1)
8000
ns
AUI RECEIVE TIMING (End of Packet)
TL/F/12082 – 51
Description
Min
teop1
Symbol
Receive End of Packet Hold Time after Logic ‘‘1’’ (Note 1)
225
ns
teop0
Receive End of Packet Hold Time after Logic ‘‘0’’ (Note 1)
225
ns
Note 1: This parameter is guaranteed by design and is not tested.
68
Max
Units
69
DP83907 AT/LANTIC II
Physical Dimensions inches (millimeters)
132-Lead Plastic Quad Flatpak PQFP (VF)
Order Number DP83907VF
NS Package Number VF132A
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