ETC RTL8029AS

RTL8029AS
Realtek PCI Full-Duplex Ethernet
Controller with built-in SRAM
ADVANCE INFORMATION
REALTEK SEMI-CONDUCTOR CO., LTD.
HEAD OFFICE
1F, NO. 11, INDUSTRY E. RD. IX, SCIENCE-BASED
INDUSTRIAL PARK, HSINCHU 30077, TAIWAN, R.O.C.
TEL:886-3-5780211 FAX:886-3-5776047
OFFICE
3F, NO. 56, WU-KUNG 6 RD.,
TAIPEI HSIEN, TAIWAN, R.O.C.
TEL: 886-2-2980098 FAX: 886-2-2980094, 2980097
RTL8029AS Preliminary
1. FEATURES............................................................................................................................................................4
2. GENERAL DESCRIPTION..................................................................................................................................5
3. PIN CONFIGURATION .......................................................................................................................................6
4. PIN DESCRIPTIONS ............................................................................................................................................7
4.1. SIGNAL TYPE DEFINITION.......................................................................................................................................7
4.2. POWER PINS...........................................................................................................................................................7
4.3. PCI BUS INTERFACE PINS .......................................................................................................................................7
4.4. MEMORY INTERFACE PINS (INCLUDING BROM, EEPROM).....................................................................................8
4.5. MEDIUM INTERFACE PINS .......................................................................................................................................9
4.6. LED OUTPUT PINS .................................................................................................................................................9
5. REGISTER DESCRIPTIONS ............................................................................................................................. 10
5.1. GROUP 1: NE2000 REGISTERS.............................................................................................................................. 10
5.1.1. Register Table ............................................................................................................................................. 10
5.1.2. Register Functions....................................................................................................................................... 12
5.1.2.1. NE2000 Compatible Registers ...............................................................................................................................12
CR: Command Register (00H; Type=R/W) ....................................................................................................................12
ISR: Interrupt Status Register (07H; Type=R/W in Page0) ............................................................................................13
IMR: Interrupt Mask Register (0FH; Type=W in Page0, Type=R in Page2) ....................................................................14
DCR: Data Configuration Register (0EH; Type=W in Page0, Type=R in Page2).............................................................14
TCR: Transmit Configuration Register (0DH; Type=W in Page0, Type=R in Page2) ......................................................14
TSR: Transmit Status Register (04H; Type=R in Page0) ................................................................................................15
RCR: Receive Configuration Register (0CH; Type=W in Page0, Type=R in Page2)........................................................15
RSR: Receive Status Register (0CH; Type=R in Page0) .................................................................................................15
CLDA0,1: Current Local DMA Registers (01H & 02H; Type=R in Page0).....................................................................16
PSTART: Page Start Register (01H; Type=W in Page0, Type=R in Page 2) ...................................................................16
PSTOP: Page Stop Register (02H; Type=W in Page0, Type=R in Page2) .......................................................................16
BNRY: Boundary Register (03H; Type=R/W in Page0)..................................................................................................16
TPSR: Transmit Page Start Register (04H; Type=W in Page0) .......................................................................................16
TBCR0,1: Transmit Byte Count Registers (05H & 06H; Type=W in Page0)...................................................................16
NCR: Number of Collisions Register (05H; Type=R in Page0).......................................................................................16
FIFO: First In First Out Register (06H; Type=R in Page0) .............................................................................................16
CRDA0,1: Current Remote DMA Address registers (08H & 09H; Type=R in Page0) .....................................................16
RSAR0,1: Remote Start Address Registers (08H & 09H; Type=W in Page0)..................................................................16
RBCR0,1: Remote Byte Count Registers (0AH & 0BH; Type=W in Page0) ...................................................................16
CNTR0: Frame Alignment Error Tally Counter Register (0DH; Type=R in Page0).........................................................16
CNTR1: CRC Error Tally Counter Register (0EH; Type=R in Page0) ............................................................................17
CNTR2: Missed Packet Tally Counter Register (0FH; Type=R in Page0) .......................................................................17
PAR0-5: Physical Address Registers (01H - 06H; Type=R/W in Page1) .........................................................................17
CURR: Current Page Register (07H; Type=R/W in Page1)............................................................................................17
MAR0-7: Multicast Address Register (08H - 0FH; Type=R/W in Page1) .......................................................................17
5.1.2.2. RTL8029AS Defined Registers ..............................................................................................................................17
9346CR: 9346 Command Register (01H; Type=R/W except Bit0=R) .............................................................................18
CONFIG0: RTL8029AS Configuration Register 0 (03H; Type=R)..................................................................................18
CONFIG1: Reserved......................................................................................................................................................18
CONFIG2: RTL8029AS Configuration Register 2 (05H; Type=R except Bit[7:5]=R/W).................................................18
CONFIG3: RTL8029AS Configuration Register 3 (06H; Type=R except Bit[6,2:1]=R/W)..............................................19
HLTCLK: Halt Clock Register (09H; Type=W) .............................................................................................................20
8029ASID0,1: RTL8029AS ID = 8029H (0E, 0FH; Type=R) .........................................................................................20
5.2. GROUP 2: PCI CONFIGURATION SPACE REGISTERS ................................................................................................ 20
5.2.1. PCI Configuration Space Table ................................................................................................................... 20
5.2.2. PCI Configuration Space functions.............................................................................................................. 21
VID: Vendor ID Register (01-00H; Type=R) .......................................................................................................................21
DID: Device ID Register (03-02H; Type=R)........................................................................................................................21
RID: Revision ID Register (08H; Type=R) ..........................................................................................................................22
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RTL8029AS Preliminary
Command: Command Register (05-04H; Type=R except Bit1, 0=R/W)...............................................................................22
Status: Status Register (07-06H; Type=R)...........................................................................................................................22
PIFR: Programming InterFace Register (09H; Type=R) .......................................................................................................23
SCR: Sub-Class Register (0AH; Type=R) ...........................................................................................................................23
BCR: Base-Class Register (0BH; Type=R)..........................................................................................................................23
HTR: Header Type Register (0EH; Type=R) .......................................................................................................................23
LTR: Latency Timer Register (0DH; Type=R).....................................................................................................................23
BAR: Base Address Register (13-10H; Type=R/W except Bit4-0=R) ..................................................................................23
SVID: Subsystem Vendor ID Register (2C-2DH; Type=R).................................................................................. 23
SID: Subsystem ID Register (2E-2FH; Type=R)................................................................................................. 24
BROMBAR: Boot ROM Base Address Register (33-30H; Type=R/W except Bit12-1=R)....................................................24
ILR: Interrupt Line Register (3CH; Type=R/W) ..................................................................................................................24
IPR: Interrupt Pin Register (3DH; Type=R).........................................................................................................................24
6. FUNCTION DESCRIPTION............................................................................................................................... 25
6.1. RTL8029AS CONFIGURATION PROCESS ............................................................................................................... 25
6.2. 9346 CONTENTS .................................................................................................................................................. 26
6.2.1 Detail values of 9346 CONFIG2-3 & 8029ASID0-1 bytes ..........................................................................................26
6.2.2 ID PROM Contents....................................................................................................................................................27
6.3. LOCAL MEMORY BUS CONTROL ........................................................................................................................... 28
6.4. FLOW CONTROL .................................................................................................................................... 28
6.4.1. Control Frame Transmission ........................................................................................................ 28
6.4.2. Control Frame Reception ............................................................................................................. 28
6.5. LED BEHAVIORS ................................................................................................................................................. 29
6.5.1 LED_TX: Tx LED .....................................................................................................................................................29
6.5.2 LED_RX: Rx LED.....................................................................................................................................................29
6.5.3 LED_CRS=LED_TX+LED_RX: Carrier Sense LED ..................................................................................................30
6.5.4 LED_COL: Collision LED .........................................................................................................................................30
6.5.5 LED Output States in Power Down Modes.................................................................................................................31
6.6. LOOPBACK DIAGNOSTIC OPERATION ..................................................................................................................... 31
6.6.1. Loopback operation..................................................................................................................................... 31
(1) CRC enabled (CRC bit in TCR=0) ................................................................................................................................32
(2) CRC disabled (CRC bit in TCR=1) ...............................................................................................................................32
6.6.2. To Implement Loopback Test ....................................................................................................................... 32
(1) To verify the integrity of data path.................................................................................................................................32
(2) To verify CRC logic ......................................................................................................................................................32
(3) To verify the address recognition function .....................................................................................................................33
(4) To Test Cable Connection .............................................................................................................................................33
7. ELECTRICAL SPECIFICATIONS AND TIMINGS......................................................................................... 35
7.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................ 35
7.2. D.C. CHARACTERISTICS (TC=0 ¢J TO 70 ¢J, VCC=5V+5%) .................................................................................. 35
7.3. A.C. TIMING CHARACTERISTICS ........................................................................................................................... 35
7.3.1. PCI Configuration Read/Write .................................................................................................................... 35
7.3.1.1. Configuration Read ................................................................................................................................................36
7.3.1.2. Configuration Write ...............................................................................................................................................36
7.3.2. PCI I/O Read/Write ..................................................................................................................................... 37
7.3.2.1. PCI I/O Read .........................................................................................................................................................37
7.3.2.2. PCI I/O Write.........................................................................................................................................................37
7.3.4. Output Timing for PCI Interface.................................................................................................................. 38
7.3.5. Input Timing for PCI Interface .................................................................................................................... 38
7.3.6. Serial EEPROM (9346) Auto-load................................................................................................. ............ 39
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RTL8029AS Preliminary
1. FEATURES
m
100-pin PQFP
¯
¯
¯
¯
m
Pin-to-pin compatible with RTL8029
16K byte SRAM built in
Compliance to PCI V2.1
Programmable PCI Vendor ID and Sub Vendor ID
PCI local bus single-chip Ethernet controller
m Compliant to Ethernet II and IEEE802.3 10Base5, 10Base2, 10BaseT
m Supports Full-Duplex Ethernet function to double channel bandwidth
¯ Support Flow Control(802.3x) to improve network performance in full-duplex
mode
m Supports three level power down modes:
- Sleep
- Power down with internal clock running
- Power down with internal clock halted
m Built-in data prefetch function to improve performance
m Built-in 10BaseT transceiver
m Provides auto-detect capability between integrated 10BaseT transceiver and Attachment Unit
Interface (AUI)
m Supports auto polarity correction for 10BaseT
m Supports Boot ROM function for PCI bus
m Supports 8K, 16K and 32K Boot ROM size
m Use 9346 (64*16-bit EEPROM) to store resource configurations and ID parameters
m Capable of programming blank 9346 on board for manufacturing convenience
m Supports 4 diagnostic LED pins with programmable outputs
P.S. “¯” denotes new feature of RTL8029AS
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RTL8029AS Preliminary
2. GENERAL DESCRIPTION
The RTL8029AS controller is an NE2000 compatible Ethernet Controller for PCI interface. Taking
the benefit of PCI's high throughput rate, the RTL8029AS controller offers a 32-bit data path to
highly improve the data transfer rate compared with traditional Ethernet card on ISA, EISA and
MCA bus. Due to the additional benefits of PCI, the RTL8029AS controller provides a low
maintaining cost network environment without usage barriers. The Auto-configuration function of
PCI can relieve the users from pains of taking care the system resource conflict. The RTL8029AS
controller also supports full-duplex and power down features. With three levels power down control
features, the RTL8029AS controller is made to be an ideal choice of the network device for a
GREEN PCI PC system. The full-duplex function enables simultaneously transmission and reception
on the twisted-pair link to a full-duplex Ethernet switching hub. This feature not only increases the
channel bandwidth from 10 to 20 Mbps but also avoids the performance degrading problem due to
the channel contention characteristics of the Ethernet CSMA/CD protocol.
The RTL8029AS controller requires no glue logic and integrates with Manchester Encoder/Decoder
and 10BaseT transceiver on chip. The built-in 10BaseT transceiver can automatically correct the
polarity error on its receiving pair. The RTL8029AS controller also has the capability of autosensing for 10Base2 or 10BaseT connection. Four diagnostic LEDs supported by RTL8029AS
controller simplify the troubleshooting procedure in a network. Furthermore, The RTL8029AS
controller supports 8K, 16K & 32K byte Boot ROM. It can be applied in a workstation without disk
to improve the network security and management convenience. Data prefetch function in
RTL8029AS controller can enhance the data transmission and highly uplift the network performance
without extra fee.
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RTL8029AS Preliminary
3. PIN CONFIGURATION
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
MA12
MA13
LED2[LED_TX]
LED1[LED_RX][LED_CRS]
LED0[LED_COL][LED_LINK]
LED_BNC
GND
TPOUT+
TPOUTVDD
TXTX+
X1
X2
GND
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CDCD+
RXRX+
VDD
TPINTPIN+
INTAB
RSTB
CLK
GND
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
VDD
CBE3B
IDSEL
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
GND
CBE2B
FRAMEB
IRDYB
TRDYB
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65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
RTL8029AS
MA11
MA10
MA9
MA8
MA7
MA6
MA5
MA4
MA3[EESK]
MA2[EEDI]
MA1[EEDO]
MA0
EECS
VDD
MA14
50 NC
49 BOEB
48 GND
47 MD0
46 MD1
45 MD2
44 MD3
43 MD4
42 MD5
41 MD6
40 MD7
39 VDD
38 AD0
37 AD1
36 AD2
35 AD3
34 GND
33 AD4
32 AD5
31 AD6
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
AD7
CBE0B
AD8
AD9
AD10
AD11
AD12
AD13
VDD
AD14
AD15
CBE1B
PAR
GND
DEVSELB
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RTL8029AS Preliminary
4. PIN DESCRIPTIONS
4.1. Signal Type Definition
P
I
O
T/S
S/T/S
O/D
Power pins include VDD and GND.
Input is a standard input-only signal.
It indicates output signal.
Tri-State is a bi-directional, tri-state input/output pin.
Sustained Tri-State is an active low tri-state signal owned and driven by one and
only one agent at a time. The agent that drives an S/T/S pin low must drive it high
for at least one clock before letting it float.
Open Drain allowed multiple device to share as a wire-OR.
4.2. Power Pins
No.
22, 39, 52,
75, 85, 100
11, 17, 34,
48, 72, 80,
91
Name
VDD
Type
P
GND
P
Description
+5V DC power
Ground
4.3. PCI Bus Interface Pins
No.
90
Name
CLK
Type
I
92-99, 310, 20, 21,
23-28, 3033, 35-38
AD31-0
T/S
1, 12, 19,
29
CBE3-0B
T/S
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Descriptions
Bus Clock provides timing for all transactions on PCI and
is an input pin to every PCI device. All bus signals are
sampled on the rising edge of CLK and all parameters are
defined with respect to this edge.
Address/Data are multiplexed on the same PCI pins. A bus
transaction consists of an address phase followed by one or
more data phases. The address phase is the clock cycle in
which FRAMEB is asserted. During data phase AD7-0
contain the least significant byte(lsb) and AD31-24 contain
the most significant byte(msb). Write data is stable and
valid when IRDYB is asserted and read data is stable and
valid when TRDYB is asserted.
Bus Command/Byte Enables are multiplexed on the same
PCI pins. During the address phase of a transaction, CBE30B define the Bus Command. During the data phase CBE30B are used as Byte Enables. The Byte Enables define
which physical byte lanes carry meaning data. CBE0B
applies to byte 0(lsb) and CBE3B applies to byte 3(msb).
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RTL8029AS Preliminary
18
PAR
T/S
13
FRAMEB
S/T/S
14
IRDYB
S/T/S
15
TRDYB
S/T/S
16
DEVSELB
S/T/S
2
IDSEL
I
89
RSTB
I
88
INTAB
O/D
Parity is even parity across AD31-0 and CBE3-0B. PAR is
stable and valid one clock after the address phase. For data
phases PAR is stable and valid one clock after either
IRDYB is asserted on a write transaction or TRDYB is
asserted on a read transaction.
Cycle Frame is driven by the current master to indicate the
beginning and duration of an access. FRAMEB is asserted
to indicate a bus transaction is beginning. While FRAMEB
is asserted, data transfers continue. When FRAMEB is
deasserted, the transaction is in the final data phase.
Initiator Ready indicates the initiating agent's ability to
complete the current data phase of the transaction. IRDYB
is used in conjunction with TRDYB. A data phase is
completed on any clock when both IRDYB and TRDYB are
asserted. During a write, IRDYB indicates that valid data is
present on AD31-0. During a read, it indicates the master is
prepare to accept data. Wait cycles are inserted until both
IRDYB and TRDYB are asserted simultaneously.
Target Ready indicates the target's agent's ability to
complete the current data phase of the transaction. TRDYB
is used in conjunction with IRDYB. A data phase is
completed on any clock when both TRDYB and IRDYB are
asserted. During a read, TRDYB indicates that valid data is
present on AD31-0. During a write, it indicates the target is
prepare to accept data. Wait cycles are inserted until both
IRDYB and TRDYB are asserted simultaneously.
Device Select, when actively driven, indicates the driving
device has decoded its address as the target of the current
access. As an input, DEVSELB indicates whether any
device on the bus has been selected.
Initialization Device Select is used as a chip select for
RTL8029AS controller during configuration read and write
transaction.
When RSTB is asserted low, the RTL8029AS performs an
internal system hardware reset. RSTB must be held for a
minimum of 120 ns periods. RSTB may be asynchronous to
CLK when asserted or deasserted. It is recommended that
the deassertion be synchronous to guarantee clean and
bounce free edge.
Interrupt A is an asynchronous attention signal which is
used to request an interrupt.
4.4. Memory Interface Pins (including BROM, EEPROM)
No.
49
Name
BOEB
Type
O
50
53
NC
EECS
O
51, 67-54
[57]
MA14-0
[EESK]
O
O
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Description
Boot ROM chip select. Active low signal, asserted when
Boot ROM is read.
Unused
9346 chip select. Active high signal, asserted when 9346 is
read/write.
Boot ROM address bus
9346 serial data clock
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RTL8029AS Preliminary
[56]
[55]
40-47
[EEDI]
[EEDO]
MD7-0
O
I
I/O
9346 serial data input
9346 serial data output
Boot ROM data bus
4.5. Medium Interface Pins
No.
82, 81
Name
CD+,CD-
Type
I
84, 83
RX+,RX-
I
77, 76
TX+,TX-
O
87, 86
TPIN+,TPIN-
I
73, 74
TPOUT+,TPOUT-
O
78
79
X1
X2
I
O
Description
This AUI collision input pair carries the differential
collision input signal from the MAU.
This AUI receive input pair carries the differential receive
input signal from the MAU.
This AUI transmit output pair contains differential line
drivers which send Manchester encoded data to the MAU.
These outputs are source followers and require 270 ohm
pull-down resistors to GND.
This TP input pair receives the 10 Mbits/s differential
Manchester encoded data from the twisted-pair wire.
This pair carries the differential TP transmit output. The
output Manchester encoded signals have been pre-distorted
to prevent overcharge on the twisted-pair media and thus
reduce jitters.
20Mhz crystal or external oscillator input.
Crystal feedback output. This output is used in crystal
connection only. It must be left open when X1 is driven with
an external oscillator.
4.6. LED Output Pins
No.
71
Name
LED_BNC
Type
O
70
LED0
O
69, 68
LED1,LED2
O
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Description
This pin goes high when RTL8029AS's medium type is set
to 10Base2 mode or auto-detect mode with link test failure.
Otherwise, this pin is low. This pin can be used to control
the power of the DC converter for CX MAU and connected
to an LED to indicate the used medium type.
When LEDS0 bit (in CONFIG3 register of RTL8029AS
Page3) is 0, this pin acts as LED_COL. When LEDS0=1, it
acts as LED_LINK.
When LEDS1 bit (in CONFIG3 register of RTL8029AS
Page3) is 0, these 2 pins act as LED_RX & LED_TX
respectively. When LEDS1=1, these pins act as LED_CRS
& MCSB. Please refer to section 6.5 for details of the
lightening behavior of all LEDs.
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RTL8029AS Preliminary
5. REGISTER DESCRIPTIONS
The registers in RTL8029AS controller can be roughly divided into two groups by their address and
functions -- one for NE2000, the other for PCI Configuration Space.
5.1. Group 1: NE2000 Registers
This group includes 4 pages of registers which are selected by bit PS0 & PS1 in the CR register.
Each page contains 16 registers. Besides those registers compatible with NE2000, the RTL8029AS
controller defines some registers for software configuration and feature enhancement.
5.1.1. Register Table
No (Hex)
Page0
[R]
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10-17
18-1F
[W]
CR
CR
CLDA0
PSTART
CLDA1
PSTOP
BNRY
BNRY
TSR
TPSR
NCR
TBCR0
FIFO
TBCR1
ISR
ISR
CRDA0
RSAR0
CRDA1
RSAR1
RBCR0
8029ID0
RBCR1
8029ID1
RSR
RCR
CNTR0
TCR
CNTR1
DCR
CNTR2
IMR
Remote DMA Port
Reset Port
Page1
[R/W]
CR
PAR0
PAR1
PAR2
PAR3
PAR4
PAR5
CURR
MAR0
MAR1
MAR2
MAR3
MAR4
MAR5
MAR6
MAR7
Page2
[R]
CR
PSTART
PSTOP
TPSR
RCR
TCR
DCR
IMR
Page3
[R]
CR
9346CR
CONFIG0
CONFIG2
CONFIG3
8029ASID0
8029ASID1
[W]
CR
9346CR
CONFIG2
CONFIG3
HLTCLK
-
Notes: "-" denotes reserved. Registers with names typed in bold italic format are RTL8029AS
defined registers and are not supported in a standard NE2000 adapter.
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RTL8029AS Preliminary
Page 0 (PS1=0, PS0=0)
No.
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
Name
CR
CLDA0
PSTART
CLDA1
PSTOP
BNRY
TSR
TPSR
NCR
TBCR0
FIFO
TBCR1
ISR
CRDA0
RSAR0
CRDA1
RSAR1
8029ID0
RBCR0
8029ID1
RBCR1
RSR
RCR
CNTR0
TCR
CNTR1
DCR
CNTR2
IMR
Type
R/W
R
W
R
W
R/W
R
W
R
W
R
W
R/W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
Bit 7
PS1
A7
A15
A15
A15
A15
OWC
A15
0
TBC7
D7
TBC15
RST
A7
A7
A15
A15
0
RBC7
0
RBC15
DFR
CNT7
CNT7
CNT7
-
Bit 6
PS0
A6
A14
A14
A14
A14
CDH
A14
0
TBC6
D6
TBC14
RDC
A6
A6
A14
A14
1
RBC6
1
RBC14
DIS
CNT6
CNT6
FT1
CNT6
RDCE
Bit 5
RD2
A5
A13
A13
A13
A13
0
A13
0
TBC5
D5
TBC13
CNT
A5
A5
A13
A13
0
RBC5
0
RBC13
PHY
MON
CNT5
CNT5
FT0
CNT5
CNTE
Bit 4
RD1
A4
A12
A12
A12
A12
CRS
A12
0
TBC4
D4
TBC12
OVW
A4
A4
A12
A12
1
RBC4
0
RBC12
MPA
PRO
CNT4
OFST
CNT4
ARM
CNT4
OVWE
Bit 3
RD0
A3
A11
A11
A11
A11
ABT
A11
NC3
TBC3
D3
TBC11
TXE
A3
A3
A11
A11
0
RBC3
0
RBC11
0
AM
CNT3
ATD
CNT3
LS
CNT3
TXEE
Bit 2
TXP
A2
A10
A10
A10
A10
COL
A10
NC2
TBC2
D2
TBC10
RXE
A2
A2
A10
A10
0
RBC2
0
RBC10
FAE
AB
CNT2
LB1
CNT2
LAS
CNT2
RXEE
Bit 1
STA
A1
A9
A9
A9
A9
A9
NC1
TBC1
D1
TBC9
PTX
A1
A1
A9
A9
0
RBC1
1
RBC9
CRC
AR
CNT1
LB0
CNT1
BOS
CNT1
PTXE
Bit 0
STP
A0
A8
A8
A8
A8
PTX
A8
NC0
TBC0
D0
TBC8
PRX
A0
A0
A8
A8
0
RBC0
1
RBC8
PRX
SEP
CNT0
CRC
CNT0
WTS
CNT0
PRXE
Bit 7
PS1
DA7
DA15
DA23
DA31
DA39
DA47
A15
FB7
FB15
FB23
FB31
FB39
FB47
FB55
FB63
Bit 6
PS0
DA6
DA14
DA22
DA30
DA38
DA46
A14
FB6
FB14
FB22
FB30
FB38
FB46
FB54
FB62
Bit 5
RD2
DA5
DA13
DA21
DA29
DA37
DA45
A13
FB5
FB13
FB21
FB29
FB37
FB45
FB53
FB61
Bit 4
RD1
DA4
DA12
DA20
DA28
DA36
DA44
A12
FB4
FB12
FB20
FB28
FB36
FB44
FB52
FB60
Bit 3
RD0
DA3
DA11
DA19
DA27
DA35
DA43
A11
FB3
FB11
FB19
FB27
FB35
FB43
FB51
FB59
Bit 2
TXP
DA2
DA10
DA18
DA26
DA34
DA42
A10
FB2
FB10
FB18
FB26
FB34
FB42
FB50
FB58
Bit 1
STA
DA1
DA9
DA17
DA25
DA33
DA41
A9
FB1
FB9
FB17
FB25
FB33
FB41
FB49
FB57
Bit 0
STP
DA0
DA8
DA16
DA24
DA32
DA40
A8
FB0
FB8
FB16
FB24
FB32
FB40
FB48
FB56
Page 1 (PS1=0, PS0=1)
No.
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
LS009.0
1997.01.16
Name
CR
PAR0
PAR1
PAR2
PAR3
PAR4
PAR5
CURR
MAR0
MAR1
MAR2
MAR3
MAR4
MAR5
MAR6
MAR7
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
11
RTL8029AS Preliminary
Page 2(PS1=1, PS0=0)
No.
00H
01H
02H
03H
04H
05H
|
0BH
0CH
0DH
0EH
0FH
Name
CR
PSTART
PSTOP
TPSR
-
RCR
TCR
DCR
IMR
Type
R/W
R
R
Bit 7
PS1
A15
A15
Bit 6
PS0
A14
A14
Bit 5
RD2
A13
A13
Bit 4
RD1
A12
A12
Bit 3
RD0
A11
A11
Bit 2
TXP
A10
A10
Bit 1
STA
A9
A9
Bit 0
STP
A8
A8
R
A15
A14
A13
A12
A11
A10
A9
A8
R
R
R
R
-
FT1
RDCE
MON
FT0
CNTE
PRO
OFST
ARM
OVWE
AM
ATD
LS
TXEE
AB
LB1
LAS
RXEE
AR
LB0
BOS
PTXE
SEP
CRC
WTS
PRXE
Page 3(PS1=1, PS0=1)
No.
00H
01H
Name
CR
9346CR
02H
03H
04H
05H
CONFIG0
CONFIG2
06H
CONFIG3
07H
08H
09H
0AH
0B-0DH
*0EH
*0FH
TEST1
HLTCLK
TEST2
8029ASID0
8029ASID1
Type
R/W
R
W
Bit 7
PS1
EEM1
EEM1
Bit 6
PS0
EEM0
EEM0
Bit 5
RD2
-
Bit 4
RD1
-
Bit 3
RD0
EECS
EECS
Bit 2
TXP
EESK
EESK
Bit 1
STA
EEDI
EEDI
Bit 0
STP
EEDO
-
R
-
-
-
-
-
BNC
0
0
R
W*
R
W*
W
R
R
PL1
PL1
-
PL0
*FCE
PL0
*FCE
FUDUP LEDS1
*FUDUP
-
HLT7
HLT6
HLT5
0
1
0
0
1
0
*PF
LEDS0
Reserved
Unused
HLT4
HLT3
Reserved
Unused
0
1
0
0
BS1
SLEEP PWRDN
SLEEP PWRDN
BS0
-
HLT2
HLT1
HLT0
0
0
0
0
1
0
Notes: The registers marked with type='W*' can be written only if bits EEM1=EEM0=1.
Notes: "*" denotes the bits or registers which are RTL8029AS defined bits or
registers and are not supported in RTL8029.
5.1.2. Register Functions
5.1.2.1. NE2000 Compatible Registers
CR: Command Register (00H; Type=R/W)
This register is used to select register pages, enable or disable remote DMA operation and issue
commands.
LS009.0
1997.01.16
12
RTL8029AS Preliminary
Bit
7, 6
Symbol
PS1, PS0
Description
PS1
0
0
1
1
5-3
PS0
0
1
0
1
Register Page
0
1
2
3
Remark
NE2000 compatible
NE2000 compatible
NE2000 compatible
RTL8029AS
Configuration
RD2-0
RD2
0
0
0
0
1
2
TXP
1
STA
0
STP
RD1
0
0
1
1
*
RD0
0
1
0
1
*
Function
Not allowed
Remote Read
Remote Write
Send Packet
Abort/Complete remote DMA
This bit must be set to transmit a packet. It is internally reset either after the
transmission is completed or aborted. Writing a 0 has no effect.
The STA bit controls nothing. It only reflects the value written to this bit.
POWER UP=0.
This bit is the STOP command. When it is set, no packets will be received or
transmitted. POWER UP=1.
STA
1
0
STP
0
1
Function
Start Command
Stop Command
ISR: Interrupt Status Register (07H; Type=R/W in Page0)
This register reflects the NIC status. The host reads it to determine the cause of an interrupt.
Individual bits are cleared by writing a "1" into the corresponding bit. It must be cleared after
power up.
Bit
7
Symbol
RST
6
5
4
3
RDC
CNT
OVW
TXE
2
RXE
1
0
PTX
PRX
LS009.0
1997.01.16
Description
This bit is set when NIC enters reset state and is cleared when a start command is
issued to the CR. It is also set when receive buffer overflows and is cleared when
one or more packets have been read from the buffer.
Set when remote DMA operation has been completed.
Set when MSB of one or more of the network tally counters has been set.
This bit is set when the receive buffer has been exhausted.
Transmit error bit is set when a packet transmission is aborted due to excessive
collisions.
This bit is set when a packet received with one or more of the following errors:
- CRC error
- Frame alignment error
- Missed packet
This bit indicates packet transmitted with no errors.
This bit indicates packet received with no errors.
13
RTL8029AS Preliminary
IMR: Interrupt Mask Register (0FH; Type=W in Page0, Type=R in Page2)
All bits correspond to the bits in the ISR register. POWER UP=all 0s. Setting individual bits
will enable the corresponding interrupts.
DCR: Data Configuration Register (0EH; Type=W in Page0, Type=R in Page2)
Bit
7
6, 5
4
Symbol
FT1, FT0
ARM
3
LS
2
LAS
1
BOS
0
WTS
Description
Always 1
FIFO threshold select bit 1 and 0.
Auto-initialize Remote
0: Send Packet Command not executed.
1: Send Packet Command executed.
Loopback Select
0: Loopback mode selected. Bits 1 and 2 of the TCR must also be programmed for
Loopback operation.
1: Normal Operation
This bit must be set to zero. NIC only supports dual 16-bit DMA mode.
POWER UP =1
Byte Order Select
0: MS byte placed on MD15-8 and LS byte on MD7-0. (32xxx,80x86)
1: MS byte placed on MD7-0 and LS byte on MD15-8. (680x0)
Word Transfer Select
0: byte-wide DMA transfer
1: word-wide DMA transfer
TCR: Transmit Configuration Register (0DH; Type=W in Page0, Type=R in Page2)
Bit
7-5
4
3
Symbol
OFST
ATD
2, 1
LB1, LB0
Description
Always 1.
Collision Offset Enable.
Auto Transmit Disable.
0: normal operation
1: reception of multicast address hashing to bit 62 disables transmitter,
reception of multicast address hashing to bit 63 enables transmitter.
LB1
0
0
1
1
0
CRC
LB0
0
1
0
1
Remark
Normal Operation
Internal Loopback
External Loopback
External Loopback
The NIC CRC logic comprises a CRC generator for transmitter and a CRC
checker for receiver. This bit controls the activity of the CRC logic. If this bit set,
CRC is inhibited by transmitter. Otherwise CRC is appended by transmitter.
Conditions
CRC Bit
Mode
0
normal
1
normal
0
loopback
1
loopback
LS009.0
1997.01.16
Mode
0
1
2
3
CRC Logic Activities
CRC Generator CRC Checker
enabled
enabled
disabled
enabled
enabled
disabled
disabled
enabled
14
RTL8029AS Preliminary
TSR: Transmit Status Register (04H; Type=R in Page0)
This register indicates the status of a packet transmission.
Bit
7
Symbol
OWC
6
CDH
5
4
3
2
1
0
CRS
ABT
COL
PTX
Description
Out of Window Collision. It is set when a collision is detected after a slot time
(51.2us). Transmissions are rescheduled as in normal collisions.
CD Heartbeat. The NIC watches for a collision signal (i.e., CD Heartbeat signal)
during the first 6.4us of the interframe gap following a transmission. This bit is
set if the transceiver fails to send this signal.
Always 0.
Carrier Sense lost bit is set when the carrier is lost during transmitting a packet.
It indicates the NIC aborted the transmission because of excessive collisions.
It indicates the transmission collided with some other station on the network.
Always 1.
This bit indicates the transmission completes with no errors.
RCR: Receive Configuration Register (0CH; Type=W in Page0, Type=R in Page2)
Bit
7, 6
5
Symbol
MON
4
PRO
3
AM
2
AB
1
AR
0
SEP
Description
Always 1.
When monitor mode bit is set, received packets are checked for address match,
good CRC and frame alignment but not buffered to memory. Otherwise, packets
will be buffered to memory.
If PRO=1, all packets with physical destination address accepted.
If PRO=0, physical destination address must match the node address programmed
in PAR0-5.
If AM=1, packets with multicast destination address are accepted.
If AM=0, packets with multicast destination address are rejected.
If AB=1, packets with broadcast destination address are accepted.
If AB=0, packets with broadcast destination address are rejected.
If AR=1, packets with length fewer than 64 bytes are accepted.
If AR=0, packets with length fewer than 64 bytes are rejected.
If SEP=1, packets with receive errors are accepted.
If SEP=0, packets with receive errors are rejected.
RSR: Receive Status Register (0CH; Type=R in Page0)
Bit
7
6
Symbol
DFR
DIS
5
PHY
4
MPA
3
2
FAE
LS009.0
1997.01.16
Description
Deferring. Set when a carrier or a collision is detected.
Receiver Disabled. When the NIC enters the monitor mode, this bit is set and
receiver is disabled. Reset when receiver is enabled after leaving the monitor
mode.
PHY bit is set when the received packet has a multicast or broadcast destination
address. It is reset when the received packet has a physical destination address.
Missed Packet bit is set when the incoming packet can not be accepted by NIC
because of a lack of receive buffer or if NIC is in monitor mode. Increment
CNTR2 tally counter.
Always 0.
Frame Alignment Error bit reflects the incoming packet didn't end on a byte
boundary and CRC did not match at last byte boundary. Increment CNTR0 tally
counter.
15
RTL8029AS Preliminary
1
CRC
0
PRX
CRC error bit reflects packet received with CRC error. This bit will also be set
for FAE errors. Increment CNTR1 tally counter.
This bit indicates packet received with no errors.
CLDA0,1: Current Local DMA Registers (01H & 02H; Type=R in Page0)
These two registers can be read to get the current local DMA address.
PSTART: Page Start Register (01H; Type=W in Page0, Type=R in Page 2)
The Page Start register sets the start page address of the receive buffer ring.
PSTOP: Page Stop Register (02H; Type=W in Page0, Type=R in Page2)
The Page Stop register sets the stop page address of the receive buffer ring.
BNRY: Boundary Register (03H; Type=R/W in Page0)
This register is used to prevent overwrite of the receive buffer ring. It is typically used as a
pointer indicating the last receive buffer page the host has read.
TPSR: Transmit Page Start Register (04H; Type=W in Page0)
This register sets the start page address of the packet to the transmitted.
TBCR0,1: Transmit Byte Count Registers (05H & 06H; Type=W in Page0)
These two registers set the byte counts of the packet to be transmitted.
NCR: Number of Collisions Register (05H; Type=R in Page0)
The register records the number of collisions a node experiences during a packet
transmission.
FIFO: First In First Out Register (06H; Type=R in Page0)
This register allows the host to examine the contents of the FIFO after loopback.
CRDA0,1: Current Remote DMA Address registers (08H & 09H; Type=R in Page0)
These two registers contain the current address of remote DMA.
RSAR0,1: Remote Start Address Registers (08H & 09H; Type=W in Page0)
These two registers set the start address of remote DMA.
RBCR0,1: Remote Byte Count Registers (0AH & 0BH; Type=W in Page0)
These two registers set the data byte counts of remote DMA.
CNTR0: Frame Alignment Error Tally Counter Register (0DH; Type=R in Page0)
LS009.0
1997.01.16
16
RTL8029AS Preliminary
CNTR1: CRC Error Tally Counter Register (0EH; Type=R in Page0)
CNTR2: Missed Packet Tally Counter Register (0FH; Type=R in Page0)
PAR0-5: Physical Address Registers (01H - 06H; Type=R/W in Page1)
These registers contain my Ethernet node address and are used to compare the
destination address of incoming packets for acceptation or rejection.
CURR: Current Page Register (07H; Type=R/W in Page1)
This register points to the page address of the first receive buffer page to be used for a
packet reception.
MAR0-7: Multicast Address Register (08H - 0FH; Type=R/W in Page1)
These registers provide filtering bits of multicast addresses hashed by the CRC logic.
5.1.2.2. RTL8029AS Defined Registers
Page 0 (PS1=0, PS0=0)
Two registers are defined to contain the RTL8029AS chip ID and Read Sequence Command is NO
LONGER supported in RTL8029AS.
No.
0AH
0BH
Name
8029ID0
8029ID1
Type
R
R
Bit7-0
50H (ASCII code of "P")
43H (ASCII code of "C")
Page 3(PS1=1, PS0=1)
Page3 Power Up Values before loading 9346 contents
No.
Name
Type
00H CR
R/W
01H 9346CR
R/W
02H
03H CONFIG0
R
04H
05H CONFIG2 R/W*
06H CONFIG3 R/W*
07H
08H
09H HLTCLK
W
0AH
0BH
0CH
0DH
0EH 8029ASID0
R
0FH 8029ASID1
R
LS009.0
1997.01.16
Bit 7
0
0
Bit 6
0
0
Bit 5
1
-
Bit 4
0
-
Bit 3
0
*
Bit 2
0
*
Bit 1
0
*
Bit 0
1
*
-
-
-
-
-
*
0
0
*
-
*
*
0
*
0
*
-
0
*
0
*
-
1
1
1
1
1
1
1
1
0
1
0
0
1
0
0
0
1
0
0
0
0
0
1
0
17
RTL8029AS Preliminary
Page3 Content Descriptions
9346CR: 9346 Command Register (01H; Type=R/W except Bit0=R)
Bit
7-6
5-4
3
2
1
0
Symbol
EEM1-0
EECS
EESK
EEDI
EEDO
Description
These 2 bits select the RTL8029AS operating mode.
EEM1
0
0
EEM0
0
1
1
0
1
1
Operating Mode
Normal (DP8390 compatible)
Auto-load:
Entering this mode will make the RTL8029AS
load the contents of 9346 like when the RSTB
signal is asserted.
This auto-load operation will take about 2ms.
After it is completed, the RTL8029AS goes back
to the normal mode automatically (EEM1=EEM0
=0) and the CR register is reset to 21H.
9346 programming:
In this mode, both the local & remote DMA
operations of 8390 are disabled. The 9346 can be
directly accessed via bit3-0 which now reflect the
states of EECS, EESK, EEDI, & EEDO pins
respectively.
Config register write enable:
Before writing to the Page3 CONFIG2,3
registers, the RTL8029AS must be placed in this
mode. This will prevent RTL8029AS's
configurations from accidental change.
Not used.
These bits reflect the state of EECS, EESK, EEDI & EEDO pins in auto-load or
9346 programming mode.
CONFIG0: RTL8029AS Configuration Register 0 (03H; Type=R)
Bit
7-3
2
Symbol
BNC
1-0
-
Description
Not used
When set, this bit indicates that the RTL8029AS is using the 10Base2 thin cable
as its networking medium. This bit will be set in the following 2 cases:
(1) PL1=PL0=0 (auto-detect) and link test fails
(2) PL1=PL0=1 (10 Base 2)
Always 0s.
CONFIG1: Reserved
CONFIG2: RTL8029AS Configuration Register 2 (05H; Type=R except Bit[7:5]=R/W)
Bit
7-6
LS009.0
1997.01.16
Symbol
PL1-0
Description
Select network medium types.
18
RTL8029AS Preliminary
PL1
0
0
1
1
5
FCE
4
PF
3-2
1-0
BS1-0
PL0
0
1
0
1
Medium Type
TP/CX auto-detect (10BaseT link test is enabled)
10BaseT with link test disabled
10Base5
10Base2
Flow Control Enable: The flow control is enabled in full-duplex mode
only.
Pause Flag: Set when RTL8029AS is in backoff state because a pause
packet is received.
Not used
Select Boot ROM size
BS1
BS0
BROM size
0
0
No Boot ROM
0
1
8K Boot ROM
1
0
16K Boot ROM
1
1
32K Boot ROM
CONFIG3: RTL8029AS Configuration Register 3 (06H; Type=R except Bit[6,2:1]=R/W)
Bit
7
6
Symbol
FUDUP
5-4
LEDS1-0
Description
Unused
When this bit is set, RTL8029AS is set to the full-duplex mode which enables
simultaneously transmission and reception on the twisted-pair link to a fullduplex Ethernet switching hub. This feature not only increases the channel
bandwidth from 10 to 20 Mbps but also avoids the performance degrading
problem due to the channel contention characteristics of the Ethernet CSMA/CD
protocol.
These two bits select the outputs to LED2-0 pins.
LEDS0
0
1
LEDS1
0
1
3
2
LS009.0
1997.01.16
SLEEP
LED0 Pin
LED_COL
LED_LINK
LED1 Pin
LED_RX
LED_CRS
LED2 Pin
LED_TX
MCSB
Please refer to section 6.4 for the behavior of LEDs.
The MCSB signal is defined to put the local buffer SRAM into standby mode
while DMA is not in progress and thus saves powers.
Reserved. Must not write a 1 to this bit.
This bit, when set, puts RTL8029AS into sleep mode.
In sleep mode, all LED signals (P.S. MCSB is not an LED signal) except
LED_BNC are forced high to turn off the LEDs. The RTL8029AS still handles
the network transmission and reception like in normal mode. The LED_BNC is
not affected by this bit.
This bit's power-up initial value is 0 and can be modified by software when
EEM1=EEM0=1.
19
RTL8029AS Preliminary
1
PWRDN
0
-
This bit, when set, puts RTL8029AS into power down mode.
RTL8029AS supports two kinds of power down modes, which is selected by the
contents of the HLTCLK register:
(1) mode 1: power down with clock running
(2) mode 2: power down with clock halted
In both power down modes, the RTL8029AS's serial network interface and
transceiver are turned off. All network activities are ignored.
All LED signals except LED_BNC are forced high. The LED_BNC is forced low
to disable the DC converter for coaxial transceiver.
In power down mode 2, the RTL8029AS stops its internal clock for minimal
power consumption. Registers except HLTCLK are typically not accessible in this
mode.
This bit's initial value comes from 9346 and can be modified if EEM1=EEM0=1
in 9346CR register.
Unused
HLTCLK: Halt Clock Register (09H; Type=W)
This is the only active one of Group1 registers when RTL8029AS is inactivated. Writing to this
register is invalid if RTL8029AS is not in power down mode. (i.e., If PWRDN bit in CONFIG3
register is zero.) The data written to this register determines the RTL8029AS's power down mode.
Data
52H (ASCII code of 'R')
48H (ASCII code of 'H')
Other values
Power Down Mode
Mode 1 - clock Running
Mode 2 - clock Halted
Ignored
8029ASID0,1: RTL8029AS ID = 8029H (0E,0FH; Type=R)
5.2. Group 2: PCI Configuration Space Registers
5.2.1. PCI Configuration Space Table
No.
00H
01H
02H
03H
04H
Name
VID
DID
Command
05H
06H
07H
08H
09H
0AH
0BH
0CH
LS009.0
1997.01.16
Status
RID
PIFR
SCR
BCR
-
Type
R
R
R
R
R
W
R
W
R
R
R
R
R
R
Bit 7
VID7
VID15
DID7
DID15
0
0
0
0
0
0
0
0
Bit 6
VID6
VID14
DID6
DID14
0
0
0
0
0
0
0
0
Bit 5
VID5
VID13
DID5
DID13
0
0
0
0
0
0
0
0
Bit 4
Bit 3
VID4
VID3
VID12 VID11
DID4
DID3
DID12 DID11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
Bit 2
VID2
VID10
DID2
DID10
0
0
0
DST1
0
0
0
0
Bit 1
VID1
VID9
DID1
DID9
MEMEN
MEMEN
0
0
DST0
0
0
0
1
Bit 0
VID0
VID8
DID0
DID8
IOEN
IOEN
0
0
0
0
0
0
0
20
RTL8029AS Preliminary
0DH
0EH
0FH
10H
11H
12H
13H
14H
|
2BH
2CH
2DH
2EH
2FH
30H
LTR
HTR
BAR
0
0
0
0
0
0
0
0
0
0
0
0
R
W
R/W
R/W
R/W
BAR7
BAR7
BAR15
BAR23
BAR31
BAR6
BAR6
BAR14
BAR22
BAR30
BAR5
BAR5
BAR13
BAR21
BAR29
0
BAR10
BAR18
BAR26
0
BAR9
BAR17
BAR25
IOIN
BAR8
BAR16
BAR24
SVID7 SVID6 SVID5 SVID4 SVID3 SVID2
SVID15 SVID14 SVID13 SVID12 SVID11 SVID10
SID7
SID6
SID5
SID4
SID3
SID2
SID15 SID14 SID13 SID12 SID11 SID10
0
0
0
0
0
0
SVID1
SVID9
SID1
SID9
0
SVID0
SVID8
SID0
SID8
BROMEN
W
R
W
R/W
R/W
BMR15
BMR15
BMR23
BMR31
BMR14
BMR14
BMR22
BMR30
BMR13
BMR13
BMR21
BMR29
0
BMR18
BMR26
0
BMR17
BMR25
BROMEN
0
BMR16
BMR24
R
W
R
0
0
0
ILR2
ILR2
0
ILR1
ILR1
0
ILR0
ILR0
1
-
SVID
SID
BROMBA
R
31H
32H
33H
34H
|
3BH
3CH
R
R
R
R
R
R
R
-
ILR
3DH IPR
3EH |
FFH
0
0
0
0
Reserved
0
0
BAR12 BAR11
BAR20 BAR19
BAR28 BAR27
Reserved
BMR12 BMR11
BMR12 BMR11
BMR20 BMR19
BMR28 BMR27
Reserved
0
ILR3
ILR3
0
Reserved
5.2.2. PCI Configuration Space functions
The PCI configuration space is intended for configuration, initialization, and catastrophic error
handling functions. The functions of RTL8029AS's configuration space are described below.
VID: Vendor ID Register (01-00H; Type=R)
The Vendor ID register is a 16-bit register that identifies the manufacturer of the RTL8029AS
controller. Realtek Vendor ID = 10ECH(default value)
DID: Device ID Register (03-02H; Type=R)
The Device ID register is a 16-bit register that shows the device ID of the RTL8029AS controller.
RTL8029AS Device ID = 8029H(default value)
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Command: Command Register (05-04H; Type=R except Bit1, 0=R/W)
The Command register is a 16-bit register used to provide coarse control over a device's ability to
generate and respond to PCI cycles.
Bit
15-10
9
Symbol
FBTBEN
8
7
SERREN
ADSTEP
6
PERREN
5
4
VGASNOOP
MWIEN
3
SCYCEN
2
1
BMEN
MEMEN
0
IOEN
Description
Reserved area. Read as 0, write operation has no effect.
Fast Back-To-Back ENable. Read as 0, write operation has no effect. The
RTL8029AS will not generate Fast Back-to-Back cycles.
SERR ENable. Read as 0, write operation has no effect.
Address/Data STEPping. Read as 0, write operation has no effect. The
RTL8029AS never do address/data stepping.
This bit controls the device's response to parity errors. When the value of this bit
is 0, the device must ignore any parity errors that it detects and continues normal
operation. Read as 0, write operation has no effect.
VGA palette SNOOP. Read as 0, write operation has no effect.
Memory Write and Invalidate cycle ENable. Read as 0, write operation has no
effect.
Special CYCle ENable. Read as 0, write operation has no effect. The
RTL8029AS ignores all special cycle operation.
Bus Master ENable. Read as 0, write operation has no effect.
Controls a device's response to memory space accesses.
0 : Disable the device response
1 : Enable the device response
Controls a device's response to I/O space accesses.
0 : Disable the device response
1 : Enable the device response
Status: Status Register (07-06H; Type=R)
The Status register is a 16-bit register used to record status information for PCI bus related events.
Reads to this register behave normally. Writes are slightly different in that bits can be reset, but not
set.
Bit
15
14
13
12
11
10-9
Symbol
DPE
SSE
RMA
RTA
STA
DST1-0
8
7
6-0
DPD
FBBC
-
Description
Detected Parity Error. Read as 0, write operation has no effect.
Signaled System Error. Read as 0, write operation has no effect.
Received Master Abort. Read as 0, write operation has no effect.
Received Target Abort. Read as 0, write operation has no effect.
Signaled Target Abort. Read as 0, write operation has no effect.
These bits encode the timing of DEVSELB. They are set to 01b (medium),
indicating the RTL8029AS controller will assert DEVSELB two clocks after
FRAMEB is asserted.
Data Parity Detected. Read as 0, write operation has no effect.
Fast Back-to-Back Capable. Read as 0, write operation has no effect.
Reserved area. Read as 0, write operation has no effect.
RID: Revision ID Register (08H; Type=R)
The Revision ID register is an 8-bit register that specifies the RTL8029AS controller revision
number. Revision ID = 00H
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PIFR: Programming InterFace Register (09H; Type=R)
The Programming interface register is an 8-bit register that identifies the programming interface of
RTL8029AS controller. PCI doesn't define any other specific register level programming interface
for network devices. So PIFR = 00H.
SCR: Sub-Class Register (0AH; Type=R)
The Sub-class register is an 8-bit register that identifies specially the function of the RTL8029AS
controller. SCR = 00H indicates that the RTL8029AS controller is an Ethernet controller.
BCR: Base-Class Register (0BH; Type=R)
The Base-class register is an 8-bit register that broadly classifies the function of the RTL8029AS
controller. BCR = 02H indicates that the RTL8029AS controller is a network controller.
HTR: Header Type Register (0EH; Type=R)
The header type register is an 8-bit register that describes the layout of bytes 10H through 3FH in
configuration space and also whether or not the device contains multiple functions. HTR = 00H
Bit
7
Symbol
FUNC
6-0
LAYOUT
Description
single/multi FUNCtion. Read as 0, write operation has no effect.
0 : single function device
1: multiple functions device
The RTL8029AS controller is a single function device
PCI configuration space layout. These bits specify the layout of bytes 10H
through 3FH. One encoding, 00H is defined and specifies the layout show in
section 5.2.1. Read as 0, write operation has no effect.
LTR: Latency Timer Register (0DH; Type=R)
This register is an 8-bit register. LTR = 00H indicates when the RTL8029AS controller is
preempted, it will release the bus immediately after finishing the current data transfer.
BAR: Base Address Register (13-10H; Type=R/W except Bit4-0=R)
The Base Address register is a 32-bit register that determines the I/O space mapping of the
RTL8029AS controller.
Bit
31-5
4-2
Symbol
BAR31-5
IOSIZE
1
0
IOIN
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Description
These bits are used to set I/O base address for I/O operation.
These bits indicate how many I/O spaces to be used. Read as 0, write operation
has no effect.
Reserved area. Read as 0, write operation has no effect.
I/O space INdicator. Read as 1, write operation has no effect. Indicating that the
base address is an I/O base address.
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RTL8029AS Preliminary
SVID: Subsystem Vendor ID Register (2C-2DH; Type=R)
The Subsystem Vendor ID register is a 16-bit register that uniquely identifies the add-in
board or subsystem where the PCI device resides. The default value is 10ECH.
SID: Subsystem ID Register (2E-2FH; Type=R)
The Subsystem ID register is a 16-bit register that are vendor specific. The default value
is 8029H.
BROMBAR: Boot ROM Base Address Register (33-30H; Type=R/W except
Bit12-1=R)
The Base Boot ROM Address register is a 32-bit register that determines the Boot ROM space
mapping of the RTL8029AS controller.
Bit
31-15
14-11
10-1
0
Symbol
BMR31-15
BROMSIZE
BROMEN
Description
These bits are used to set Boot ROM base address for Boot ROM access.
These bits indicate how many Boot ROM spaces to be supported.
BS1
BS0
0
0
0
1
1
0
1
1
Description
No BROM : BROMEN=0(R)
BMR11,12=0,0(R)
8K BROM : BROMEN=0(R/W)
BMR11,12=0,0(R)
BMR13=0(R/W)
BMR14=0(R/W)
16K BROM : BROMEN=0(R/W)
BMR11,12=0,0(R)
BMR13=0(R)
BMR14=0(R/W)
32K BROM : BROMEN=0(R/W)
BMR11,12=0,0(R)
BMR13=0(R)
BMR14=0(R)
Reserved area. Read as 0, write operation has no effect.
BROM ENable bit.
0 : disable
1 : enable
ILR: Interrupt Line Register (3CH; Type=R/W)
The Interrupt Line register is an 8-bit register used to communicate with the routing of the
interrupt. It is written by the POST software to set interrupt line for the RTL8029AS controller.
ILR = 00-0FH
IPR: Interrupt Pin Register (3DH; Type=R)
The Interrupt Pin register is an 8-bit register indicating the interrupt pin used by the RTL8029AS
controller. The RTL8029AS controller uses the INTA interrupt pin. IPR = 01H
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6. FUNCTION DESCRIPTION
6.1. RTL8029AS Configuration Process
The RTL8029AS controller supports PCI configuration operation. In PCI system, the initial
process is completed by the system BIOS software. The system BIOS has to find where the system
resources are available, such as I/O base address, BROM memory base address, and interrupt
request line, and assigns the resources to the required devices. At the same time the RTL8029AS
controller performs a series of EEPROM read operation after power-up to set Ethernet ID, media
type, operation mode¡K, etc. The RTL8029AS's resource configuration information is stored in the
PCI configuration space as well as CONFIG registers in Group1 Page3. The CONFIG registers
power-up default values always come from the contents of 9346 and the values can be modified by
software. The update configuration is only valid temporarily and will be lost after an auto-load
command, an active RSTB, or PC power off. Permanent changes of configuration must be done by
changing the contents of 9346. Note that the BROM size can not be modified temporarily.
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6.2. 9346 Contents
The 9346 is a 1K-bit EEPROM. Although it is actually addressed by words, we list its contents by
bytes below for convenience.
Bytes
00H - 01H
02H - 0FH
10H - 17H
18H-75H
76H-77H
78H-7FH
Contents
(2 bytes)
00H
01H
CONFIG2
CONFIG3
(14 bytes)
02H - 07H
08H - 0FH
(8 bytes)
10H - 11H
12H - 17H
Ethernet ID 0-5
Product ID 0-7
Comments
Power-up initial value of Page3
Board Configurations
NE2000 ID PROM
Ethernet node address
Assigned by card makers; negligible
Flow Control
Pause Type 0-1
Pause Multicast ID0-5
Unused
(2 bytes)
8029ASID
The value is 8029H which is programmed
by PG8029.
(8 bytes)
PCI ID
PCI VID, DID, SVID and SID
78H-79H VID0-1
7AH-7BH DID0-1
7CH-7DH SVID0-1
7EH-7FH SID0-1
6.2.1 Detail values of 9346 CONFIG2-3 & 8029ASID0-1 bytes
CONFIG2
CONFIG3
8029ASID0
8029ASID1
Bit 7
PL1
*
0
1
Bit 6
PL0
FUDUP
0
0
Bit 5
FCE
LEDS1
1
0
Bit 4
*
LEDS0
0
0
Bit 3
*
*
1
0
Bit 2
*
*
0
0
Bit 1
BS1
PWRDN
0
0
Bit 0
BS0
*
1
0
P.S. '*' denotes don't care.
Note: RTL8029AS checks the 8029ASID word in 9346 when power up. If the value
matches “8029h”, the RTL8029AS works in RTL8029AS mode. You can use
all new features defined by RTL8029AS, such as Flow Control,
Programmable Vendor ID … etc. If the value doesn‘t match, the RTL8029AS
works like RTL8029. All enhanced functions and registers are not available.
Also the PCI IDs in 9346 are ignored and the RTL8029’s ID(10ECh, 8029h)
will be used instead.
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6.2.2 ID PROM Contents
The RTL8029AS emulates the ID PROM of NE2000 internally. After 9346 is loaded, the contents
of ID PROM are as follows.
offset
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
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Ethernet ID0
Ethernet ID1
Ethernet ID2
Ethernet ID3
Ethernet ID4
Ethernet ID5
PID0
PID1
PID2
PID3
PID4
PID5
PID6
PID7
57 (ASCII Code of "W")
57 (ASCII Code of "W")
Ethernet ID0
Ethernet ID1
Ethernet ID2
Ethernet ID3
Ethernet ID4
Ethernet ID5
PID0
PID1
PID2
PID3
PID4
PID5
PID6
PID7
42 (ASCII Code of "B")
42 (ASCII Code of "B")
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RTL8029AS Preliminary
6.3. Local Memory Bus Control
The local memory bus of RTL8029AS is shared by the BROM & 9346 EEPROM.The following
diagram demonstrates their connection relationship.
RTL8029AS
9346
MD7-0
MA14-2
MA1 [EEDO]
MA3-1
EESK
EEDI
EEDO
EECS
EECS
EECS
MA0
BOEB
BROM
MD7-0
D7-0
BOEB
CE
A14-0
MA14-0
OE
Figure 1. Local Memory Bus Block Diagram
6.4. Flow Control
The RTL8029AS supports IEEE802.3X flow control to improve performance in full-duplex
mode. It detects PAUSE packet to achieve flow control task.
6.4.1. Control Frame Transmission
When RTL8029AS detects its free receive buffer less than 3K bytes, it sends a PAUSE
packet with pause_time(=FFFFh) to inform the source station to stop transmission for
the specified period of time. After the driver has processed the packets in the receive
buffer and updated the boundary pointer, the RTL8029AS sends the other PAUSE
packet with pause_time(=0000h) to wake up the source station to restart transmission.
6.4.2. Control Frame Reception
RTL8029AS enters backoff state for the specified period of time when it receives a valid
PAUSE packet with pause_time(=n). If the PAUSE packet is received while
RTL8029AS is transmitting, RTL8029AS starts to backoff after current transmission
completes. RTL8029AS frees to transmit next packets again when it receives a valid
PAUSE packet with pause_time(=0000h) or the backoff timer(=n*51.2us) elapses.
Note: The PAUSE operation cannot be used to inhibit transmission of MAC Control
frames (e.g. PAUSE packet).
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6.5. LED Behaviors
This section describes the lighting behaviors of the LED output signals which may be selected by
LEDS1 and LEDS0 bits in the Page3 CONFIG3 register.
P.S. It is assumed that the LED is on when the signal goes low.
6.5.1 LED_TX: Tx LED
Power On
LED=low
No
Transmitting Packet?
Yes
LED=high for (100 +10) ms
LED=low for (6 +2) ms
6.5.2 LED_RX: Rx LED
Power On
LED=low
No
Receiving Packet?
Yes
LED=high for (100 +10) ms
LED=low for (6 +2) ms
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6.5.3 LED_CRS=LED_TX+LED_RX: Carrier Sense LED
Power On
LED=low
No
Tx or Rx Packet?
Yes
LED=high for (100 + 10) ms
LED=low for (6 +2) ms
6.5.4 LED_COL: Collision LED
Power On
LED=high
No
Collision (except Heartbeat)?
Yes
LED=low for (10 +5) ms
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6.5.5 LED Output States in Power Down Modes
LED Output
LED_BNC
LED_LINK
LED_COL
LED_TX
LED_RX
LED_CRS
Normal Mode / Idle
High
Low
Low
Low
Sleep Mode
High
High
High
High
High
Power Down Mode
Low
High
High
High
High
High
6.6. Loopback Diagnostic Operation
6.6.1. Loopback operation
The RTL8029AS provides 3 loopback modes. By loopback test, we can verify the integrity of data
path, CRC logic, address recognition logic and cable connection status.
Mode 1: Loopback through the NIC (LB1=0, LB0=1 in TCR).
The NRZ data is not transmitted to the SNI but instead it's loopbacked to the NIC's Rx
deserializer. The traffic on the cable is ignored.
Ref:
NIC
8390
SNI
83910
Mode 2: Loopback through the SNI (LB1=1, LB0=0 in TCR)
The Manchester encoded data is not transmitted to the MAU. It's loopbacked through
the SNI to NIC. The traffic on the cable is ignored.
Ref:
NIC
8390
SNI
83910
MAU
8392/RTL8005
Mode 3: Loopback through the cable (LB1=1, LB0=1 in TCR)
The packets are transmitted via the MAU onto the network and RTL8029AS receives all
incoming packets (not only the MAU-loopbacked Tx data) in the meantime.
Ref:
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8390
SNI
83910
MAU
8392/RTL8005
CABLE
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RTL8029AS Preliminary
q Alignment of the Reception FIFO
The reception FIFO is an 8-byte ring structure. The first received byte is put at location zero.
When the location pointer goes to the end of the FIFO, it wraps to the beginning of the FIFO and
overwrites the previous data. At the end of the packet reception, the FIFO contents are in the
"order" (from the ring structure's view) as shown below.
(1) CRC enabled (CRC bit in TCR=0)
s
s
s
s
s
1-byte received packet data
4-byte CRC
1-byte lower byte count
1-byte upper byte count
1-byte upper byte count
(2) CRC disabled (CRC bit in TCR=1)
s
s
s
s
5-byte received packet data
1-byte lower byte count
1-byte upper byte count
1-byte upper byte count
6.6.2. To Implement Loopback Test
(1) To verify the integrity of data path
s set RCR=00H to accept physical packet
s set PAR0-5 to accept packet
s set DCR=43H
s set TCR=02H, 04H, 06H to do loopback test 1, 2, 3 respectively
s set CRC enabled (CRC=00H in TCR)
s clear ISR
s Tx a packet and check ISR
s check FIFO after loopback
Notes: Loopback mode 3 is sensitive to the network traffic, so the values of FIFO may be not
correct.
(2) To verify CRC logic
q Select a loopback mode (e.g. mode 2) to test
A. To test CRC generator
s set RCR=00H to accept physical packet
s set PAR0-5 to accept packet
s set TCR=04H (CRC enabled)
s set DCR=43H
s clear ISR
s Tx a packet
s check CRC bytes in FIFO after loopback
B. To test CRC checker
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s
s
s
s
s
s
s
set RCR=00H to accept physical packet
set PAR0-5 to accept packet
set TCR=05H (CRC disabled)
set DCR=43H
clear ISR
Tx a packet with good or bad CRC appended by program
check FIFO, ISR & RSR after loopback
For bad CRC, expected: ISR=06H, RSR=02H (Tx:OK, Rx:CRC error)
For good CRC, expected: ISR=02H, RSR=01H (Tx:OK, Rx:OK)
Notes: In loopback mode, the received packets are not stored to SRAM, so PRX bit in ISR
isn't set.
(3) To verify the address recognition function
q Select a loopback mode (e.g. mode 2) to test
A. Right physical destination address
s set RCR=00H to accept physical packet
s set PAR0-5 to accept packet
s set TCR=04H (CRC enabled)
s set DCR=43H
s clear ISR
s Tx a packet
s check ISR after loopback
Expected: ISR=06H (packets accepted, Rx CRC error)
B. Wrong physical destination address
s set RCR=00H to accept physical packet
s set PAR0-5 to reject packet
s set TCR=04H (CRC enabled)
s set DCR=43H
s clear ISR
s Tx a packet
s check ISR after loopback
Expected: ISR=02H (packets rejected, Rx no response)
(4) To Test Cable Connection
q There are four physical medium types in RTL8029AS.
We perform loopback mode 3 to test the cable connection status.
s
s
s
s
s
s
s
set RCR=00H to accept physical packet
set PAR0-5 to accept packet
set TCR=06H (CRC enabled)
set DCR=43H
clear ISR
Tx a packet
check TSR after loopback
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A. 10Base2
If cable OK, get TSR=01H (Tx OK).
If cable FAIL, get TSR=0CH (Collision and Tx aborted).
B. 10Base5
If cable OK, get TSR=01H (Tx OK).
If MAU connected but cable FAIL, get TSR=0CH (Tx collision and Tx aborted).
If MAU not connected, get TSR=51H (Carrier sense is lost during transmission and CD
heartbeat fails.).
C. 10BaseT with link test disabled
RTL8029AS disables link test in this case, so cable OK or FAIL doesn't affect TSR; get
TSR=01H.
D. Auto-detection (10BaseT with link test enabled)
RTL8029AS automatically switches from 10BaseT to 10Base2 if the twisted-pair wire is not
connected (10BaseT link test fails).
If twisted-pair wire OK, get TSR=01H (Tx OK) & BNC=0 in CONFIG2.
If twisted-pair wire FAIL but coaxial cable OK, get TSR=01H (Tx OK) & BNC=1 in CONFIG2.
Otherwise, get TSR=0CH (same as 10Base2 connection fail).
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7. ELECTRICAL SPECIFICATIONS AND TIMINGS
7.1. Absolute Maximum Ratings
Operating Temperature ............................................................................................ 0¢J to 70¢J
Storage Temperature ................................................................................................ -65 ¢J to
140¢J
All Outputs and Supply Voltages, with respect to Ground ............................................ -0.5V to
7V
Power Dissipation ....................................................................................................
Warning:
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device. These are stress ratings only.
Functionality at or above these limits is not recommended and extended exposure to "Absolute
Maximum Ratings" may affect device reliability.
7.2. D.C. Characteristics (Tc=0 ¢J to 70 ¢J, Vcc=5V+5%)
Symbol
Vil
Vih
Vol
Voh
II
Parameter
Input Low Voltage
Input High Voltage
Low-level output voltage
High-level output voltage
Input Leakage Current
Min.
Typ.
2.0
Max.
0.8
5.5
0.55
Unit
V
V
V
10
µA
2.4
Conditions
Io=3mA, 6mA
Ioh=-2mA
V=GND to VDD
7.3. A.C. Timing Characteristics
7.3.1. PCI Configuration Read/Write
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7.3.1.1. Configuration Read
CLK
FRAMEB
IDSEL
AD31-0
ADDR
CBE3-0B
CMD
DATA
ADDR
DATA
BE
CMD
BE
IRDYB
TRDYB
DEVSELB
PAR
7.3.1.2. Configuration Write
CLK
FRAMEB
IDSEL
AD31-0
ADDR
DATA
ADDR
DATA
CBE3-0B
CMD
BE
CMD
BE
IRDYB
TRDYB
DEVSELB
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7.3.2. PCI I/O Read/Write
7.3.2.1. PCI I/O Read
CLK
FRAMEB
AD31-0
CBE3-0B
ADDR
CMD
DATA
ADDR
DATA
CMD
BE
BE
IRDYB
TRDYB
DEVSELB
PAR
7.3.2.2. PCI I/O Write
CLK
FRAMEB
AD31-0
CBE3-0B
ADDR
DATA
ADDR
DATA
CMD
BE
CMD
BE
IRDYB
TRDYB
DEVSELB
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7.3.3. BROM Read
CLK
FRAMEB
AD31-0
CBE3-0B
ADDR
DATA
CMD
BE
BE
IRDYB
TRDYB
DEVSELB
PAR
7.3.4. Output Timing for PCI Interface
CLK
T_val
OUTPUT
DELAY
Tri-State
OUTPUT
T_on
T_off
7.3.5. Input Timing for PCI Interface
CLK
T_su
INPUT
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RTL8029AS Preliminary
Symbol
tval
ton
toff
tsu
th
Parameter
CLK to Signal Valid Delay-bussed signals
Float to Active Delay
Active to Float Delay
Input Set up Time to CLK-bussed signals
Input Hold Time from CLK
Min.
2
Typ.
Max.
11
11
11
Unit
ns
ns
ns
ns
ns
7
0
7.3.6. Serial EEPROM (9346) Auto-load
EESK
EECS
EEDI
1
0
1
0
0
0
A2
A1
A0
EEDO
D1
D15 D14
T1
D0
T2
EESK
T4
T3
EEDI
T6
T5
EECS
T7
T8
EEDO
Symbol
T1
T2
T3
T4
T5
T6
T7
T8
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1997.01.16
Parameter
EESK high width
EESK low width
EEDI setup to EESK rising edge
EEDI hold from EESK falling edge
EECS goes high to EESK rising edge
EECS goes low from EESK falling edge
EEDO setup to EESK falling edge
EEDO hold from EESK falling edge
Min.
3.0
3.0
3.0
20
10
Typ.
3.2
3.2
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
39
RTL8029AS Preliminary
REALTEK Semiconductor Co., Ltd. reserved all rights of this document. No part of this
document may be copied or reproduced in any form or by any means or transferred to any third
party without the prior written consent of REALTEK Semiconductor Co., Ltd. REALTEK
reserves the right to change products or specifications without notice. This document has been
carefully checked and is believed to be accurate. However REALTEK Semiconductor Co., Ltd.
assumes no responsibility for inaccuracies.
LS009.0
1997.01.16
40
RTL8029AS Preliminary
Note:
Symbol
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
y
£c
LS009.0
1997.01.16
Dimension
mil
Min Typ
106.3 118.1
4.3 20.1
102.4 112.2
7.1 11.8
1.6
5.9
541.3 551.2
777.6 787.4
19.7 25.6
726.4 740.2
962.6 976.4
39.4 47.2
88.6 94.5
¡Ð
¡Ð
¡Ð
0¢X
in
Max
129.9
35.8
122.0
16.5
10.2
561.0
797.2
31.5
753.9
990.2
55.1
104.3
3.9
12¢X
Dimension
mm
Min Typ
2.70 3.00
0.11 0.51
2.60 2.85
0.18 0.30
0.04 0.15
13.75 14.00
19.75 20.00
0.50 0.65
18.45 18.80
24.45 24.80
1.00 1.20
2.25 2.40
¡Ð ¡Ð
0¢X ¡Ð
in
Max
3.30
0.91
3.10
0.42
0.26
14.25
20.25
0.80
19.15
25.15
1.40
2.65
0.10
12¢X
1.Dimension D & E do not include interlead flash.
2.Dimension b does not include dambar protrusion/intrusion.
3.Controlling dimension: Millimeter
4.General appearance spec. should be based on final visual
inspection spec.
TITLE : 100L QFP ( 14x20 mm**2 ) FOOTPRINT 4.8 mm
PACKAGE OUTLINE DRAWING
LEADFRAME MATERIAL:
APPROVE
DWG NO.
REV NO.
SCALE
CHECK
Ricardo Chen DATE
SHT NO.
1 OF
REALTEK SEMI-CONDUCTOR CO., LTD
41