NSC CLC5902VLA

N
CLC5902
Dual Digital Tuner/AGC
0
0
General Overview
The CLC5902 Dual Digital Tuner/AGC IC is a two channel digital
downconverter (DDC) with integrated automatic gain control
(AGC). The CLC5902 is a key component in the Diversity
Receiver Chipset (DRCS) which includes one CLC5902 Dual
Digital Tuner/AGC, two CLC5956 12-bit analog-to-digital
converters (ADCs), and two CLC5526 digitally controlled variable
gain amplifiers (DVGAs). A block diagram for a Diversity
Receiver Chipset based narrowband communications system is
shown in Figure 1. This system allows direct IF sampling of signals
up to 300MHz for enhanced receiver performance and reduced
system costs.
The CLC5902 offers high dynamic range digital tuning and
filtering based on hard-wired digital signal processing (DSP)
technology. Each channel has independent tuning, phase offset, and
gain settings. Channel filtering is performed by a series of three
filters. The first is a 4-stage Cascaded Integrator Comb (CIC) filter
with a programmable decimation ratio from 8 to 2048. Next there
are two symmetric FIR filters, a 21-tap and a 63-tap, both with
programmable coefficients. The first FIR filter decimates the data
by 2, the second FIR decimates by either 2 or 4. Channel filter
bandwidth at 52MSPS ranges from ±650kHz down to ±1.3kHz.
The CLC5902’s AGC controller monitors the ADC output and
controls the ADC input signal level by adjusting the DVGA setting.
AGC threshold, deadband+hysteresis, and the loop time constant
are user defined. Total dynamic range of greater than 120dB fullscale signal to noise can be achieved with the Diversity Receiver
Chipset.
CLC5526
CLC5956
Features
n 52MSPS Operation
n Two Independent Channels with
n
n
n
n
n
n
n
n
n
n
n
n
14-bit inputs
Greater than 100 dB image rejection
Greater than 100 dB spurious free
dynamic range
0.02 Hz tuning resolution
User Programmable AGC
Channel Filters include a Fourth
Order CIC followed by 21-tap and
63-tap Symmetric FIRs
FIR filters process 21-bit Data
with 16-bit Programmable Coefficients
Flexible output formats include
12-bit Floating Point or 8, 16, 24,
and 32 bit Fixed Point
Serial and Parallel output ports
JTAG Boundary Scan
8-bit Microprocessor Interface
380mW/channel, 52 MHz, 3.3V
128 pin PQFP package
Applications
n Cellular Basestations
n Satellite Receivers
n Wireless Local Loop Receivers
n Digital Communications
CLC5902
LC
IF A
ADC
DVGA
12
4
IF B
DVGA
ADC
LC
CLC5902
Dual Digital Tuner/AGC
May 1999
12
Dual Digital
Tuner/AGC
SerialOutA/B
SerialOutB
SCK
SFS
RDY
ParallelOutput[15..0]
ParallelOutputEnable
ParallelSelect[2..0]
CLK
Figure 1
Diversity Receiver Chipset Block Diagram
©1999 National Semiconductor Corporation
Rev. 3.05 May 27, 1999
Channel A Controls
AGC_IC_A
GAIN_A
AGC_RB_A
FREQ_A
PHASE_A DITH_A
Microprocessor
Interface
RD
WR
CE
A[7:0]
D[7:0]
AGAIN[2..0]
ASTROBE
AIN
MUX
A
BIN
MUX
B
14
14
Channel A
Tuning,
Channel Filters, and
AGC (see Figure 14)
Channel B
Tuning,
Channel Filters, and
AGC (see Figure 14)
Output Formatter
Floating Point:
4-bit Exponent and
8-bit Mantissa
or
Two’s Complement:
32-bit Truncated or
24-bit Rounded or
16-bit Rounded or
8-bit Truncated
(see Figure 26)
RDY
POUT[15..0]
PSEL[2..0]
POUT_EN
BSTROBE
BGAIN[2..0]
TEST_REG
Channel B Controls
AGC_IC_B
GAIN_B
AGC_RB_B
FREQ_B
PHASE_B DITH_B
Input Source
A_SOURCE
B_SOURCE
CK
CLK
GEN
SI
MR
Sync
Logic
AGC_EN
Figure 2
AOUT/BOUT
BOUT
SCK
SFS
Common Channel Controls
DEC
AGC_FORCE
DEC_BY_4
AGC_RESET_EN
SCALE
AGC_HOLD_IC
EXP_INH
AGC_LOOP_GAIN
F1_COEFF
AGC_COUNT
F2_COEFF
AGC_TABLE
Output Controls
RATE
SOUT_EN
SCK_POL
SFS_POL
RDY_POL
MUX_MODE
PACKED
FORMAT
DEBUG_EN
DEBUG_TAP
CLC5902 Dual Digital Tuner/AGC Block Diagram with Control Register Associations
Functional Description.
The CLC5902 block diagram is shown in Figure 2. The
CLC5902 contains two identical digital down-conversion
(DDC) circuits. Each DDC accepts a 14-bit sample at up
to 52MSPS, down converts from a selected carrier frequency to baseband, decimates the signal rate by a programmable factor ranging from 32 to 16384, provides
channel filtering, and outputs quadrature symbols.
A crossbar switch enables either of the two inputs or a test
register to be routed to either DDC channel. Flexible channel filtering is provided by the two programmable decimating FIR filters. The final filter outputs can be
converted to a 12-bit floating point format or standard
two’s complement format. The output data is available at
both serial and parallel ports.
The CLC5902 maintains over 100 dB of spurious free
dynamic range and over 100 dB of out-of-band rejection.
This allows considerable latitude in channel filter partitioning between the analog and digital domains.
The frequencies, phase offsets, and phase dither of the two
sine/cosine numerically controlled oscillators (NCOs) can
be independently specified. Both channels share the same
Rev. 3.05 May 27, 1999
2
decimation ratio, bandwidth, filter coefficients, and input/
output formats.
Each channel has its own AGC circuit for use with narrowband radio channels where most of the channel filtering precedes the ADC. The AGC closes the loop around
the CLC5526 DVGA, compressing the dynamic range of
the signal into the ADC. The AGC can be configured to
operate continuously or in a gated mode. The two AGC
circuits operate independently but share the same programmed parameters and control signals.
The chip receives configuration and control information
over a microprocessor-compatible bus consisting of an 8bit data I/O port, an 8-bit address port, a chip enable
strobe, a read strobe, and a write strobe. The chip’s control
registers (8 bits each) are memory mapped into the 8-bit
address space of the control port.
JTAG boundary scan and on-chip diagnostic circuits are
provided to simplify system debug and test.
The CLC5902 supports 3.3V I/O. The CLC5956 ADC
outputs are compatible with the CLC5902 inputs. The
CLC5902 outputs swing to the 3.3V rail so they can be
directly connected to 5V TTL inputs if desired.
©1999 National Semiconductor Corporation
CLC5902 Electrical Characteristics
(VCC=+3.3V, 52MHz, CIC Decimation=48, F2 Decimation=2, Tmin=-40°C, Tmax=+85°C; unless specified)
DC Characteristics
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Notes
Voltage input low
VIL
-0.5
0.8
V
1
Voltage input high
VIH
2.0
VCC+0.5
V
1
Input current
IIN
10
uA
1
Voltage output low (IOL = 4mA/12mA, see pin description)
VOL
0.4
V
1
Voltage output high (IOH = -4mA/-12mA, see pin description)
VOH
V
1
Input capacitance
CIN
4.0
pF
3
2.4
AC Characteristics
PARAMETER (CL=50pF)
SYMBOL
MIN
TYP
MAX
UNITS
Clock (CK) Frequency (Figure 7)
FCK
Spurious Free Dynamic Range
SFDR
-100
dBFS
Signal to Noise Ratio
SNR
-127
dBFS
Tuning Resolution
0.02
Hz
Phase Resolution
0.005
°
52
MHz
Notes
1
MR Active Time (Figure 5)
tMRA
4
CK periods
1
MR Inactive to first Control Port Access (Figure 5)
tMRIC
10
CK periods
1
MR Setup Time to CK (Figure 5)
tMRSU
9
ns
1
MR Hold Time to CK (Figure 5)
tMRH
2
ns
1
MR Inactive to A|BSTROBE Release (Figure 5)
tMRSR
SI Setup Time to CK (Figure 6)
tSISU
9
ns
1
SI Hold Time from CK (Figure 6)
tSIH
2
ns
1
SI Pulse Width (Figure 6)
tSIW
4
CK periods
1
SI Inactive to A|BSTROBE Release (Figure 6)
tSISR
CK duty cycle (Figure 7)
tCKDC
17
ns
17
40
ns
60
%
1
CK rise and fall times (VIL to VIH) (Figure 7)
tRF
ns
1
Input setup before CK goes high (A|BIN) (Figure 7)
tSU
7
ns
1
Input hold time after CK goes high (Figure 7)
tHD
3
ns
1
A|BSTROBE Pulse Width (Figure 8)
tSTBPW
1
CK period
2
1
CK period
2
CK periods
1
3
A|BGAIN Valid Setup before A|BSTROBE (Figure 8)
tGSU
AGC_EN Active Width (Figure 8)
tENW
2
SCK to SFS Valid (Table Note A) (Figure 9)
tSFSV
0
7
ns
1
SCK to A|BOUT Valid (Table Note B) (Figure 9)
tOV
0
7
ns
1
RDY Pulse Width (Figure 9)
tRDYW
CK periods
1
POUT_EN Active to POUT[15..0] Valid (Figure 10)
tOENV
15
ns
1
POUT_EN Inactive to POUT[15..0] Tri-State (Figure 10)
tOENT
15
ns
1
PSEL[2..0] to POUT[15..0] Valid (Figure 11)
tSELV
20
ns
1
RDY to POUT[15..0] New Value Valid (Table Note C) (Figure 12)
tRDYV
10
ns
1
Propagation Delay TCK to TDO (Figure 13)
tPLH
30
ns
1
Propagation Delay TCK to Data Out (Figure 13)
tPHL
35
ns
1
Disable Time TCK to TDO (Figure 13)
tPLZ
35
ns
1
Disable Time TCK to Data Out (Figure 13)
tPHZ
Enable Time TCK to TDO (Figure 13)
tPZL
©1999 National Semiconductor Corporation
3
4
0
35
ns
1
35
ns
1
Rev. 3.05 May 27, 1999
PARAMETER (CL=50pF)
SYMBOL
MIN
Enable Time TCK to Data Out (Figure 13)
tPZH
0
Setup Time Data to TCK (Figure 13)
tS
Setup Time TDI to TCK (Figure 13)
TYP
MAX
35
UNITS
Notes
ns
1
10
ns
1
tS
10
ns
1
Setup Time TMS to TCK (Figure 13)
tS
15
ns
1
Hold Time Data to TCK (Figure 13)
tH
55
ns
1
Hold Time TCK to TDI (Figure 13)
tH
55
ns
1
Hold Time TCK to TMS (Figure 13)
tH
10
ns
1
TCK Pulse Width High (Figure 13)
tWH
55
ns
1
TCK Pulse Width Low (Figure 13)
tWL
40
ns
1
TCK Maximum Frequency (Figure 13)
JTAGFMAX
MHz
1
Control Setup before the controlling signal goes low (Figure 14)
tCSU
5
ns
1
Control hold after the controlling signal goes high (Figure 14)
tCHD
5
ns
1
Controlling strobe pulse width (Write) (Figure 14)
tCSPW
30
ns
1
Control output delay controlling signal low to D (Read) (Figure 14)
tCDLY
30
ns
1
Control tri-state delay after controlling signal goes high (Figure 14)
tCZ
20
ns
1
Dynamic Supply Current (FCK =52MHz, N=48)
ICC
230
280
mA
1
Dynamic Supply Current (FCK =52MHz, N=8)
ICC
260
320
mA
1
10
essarily implied. Exposure to maximum ratings for extended periods may
affect device reliability.
Notes A - C
A. tSFSV refers to the rising edge of SCK when SCK_POL=0 and the
falling edge when SCK_POL=1.
B. tOV refers to the rising edge of SCK when SCK_POL=0 and the falling edge when SCK_POL=1.
C. tRDYV refers to the rising edge of RDY when RDY_POL=0 and the
falling edge when RDY_POL=1.
Notes 1 - 3
Recommended Operating Conditions
Positive Supply Voltage (VCC)
3.3V ±10%
Operating Temperature Range
-40°C to +85°C
Package Thermal Resistance
1. These parameters are 100% tested at 25°C.
2. Typical specifications are the mean values of the distributions of deliverable CLC5902s tested to date.
3. Min/max ratings are based on product characterization and simulation.
Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
θja
Package
128 pin PQFP
39°C/W
θjc
TBD°C/W
Reliability Information
Absolute Maximum Ratings
Positive Supply Voltage (VCC)
Voltage on Any Input or Output Pin
Transistor Count
-0.3V to 4.2V
-0.3V to VCC+0.5V
Input Current at Any Pin
±25mA
Package Input Current
±50mA
Package Dissipation at TA=25°C
Ordering Information
Order Code
1W
ESD Susceptibility
Human Body Model
Machine Model
1500V
100V
Soldering Temperature, Infrared, 10 seconds
300°C
Storage Temperature
CLC5902VLA
4
Temperature
Range
-40°C to
+85°C
Description
128-pin PQFP (industrial
temperature range)
CLC-DRCS-PCASM
Fully loaded Diversity
Receiver Chipset evaluation
board and control panel software.
CLC-CAPT-PCASM
Data Capture board for the
DRCS with Matlab analysis
routines.
-65°C to 150°C
NOTE: Absolute maximum ratings are limiting values, to be applied
individually, and beyond which the serviceability of the circuit may be
impaired. Functional operability under any of these conditions is not nec-
Rev. 3.05 May 27, 1999
1.2 million
©1999 National Semiconductor Corporation
Package Dimensions
DETAIL A
Dimension are in millimeters
Figure 3
CLC5902 Package Dimensions
©1999 National Semiconductor Corporation
5
Rev. 3.05 May 27, 1999
CLC5902
Dual Digital Tuner/AGC
(Top View)
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
NC
NC
NC
NC
VSS
POUT[5]
POUT[6]
POUT[7]
POUT[8]
POUT[9]
VDD
POUT[10]
POUT[11]
VSS
POUT[12]
POUT[13]
POUT[14]
VDD
POUT[15]
VSS
AOUT
SFS
SCK
VDD
BOUT
RDY
VSS
D[0]
VDD
D[1]
D[2]
D[3]
D[4]
D[5]
VSS
NC
NC
NC
VDD
BGAIN[2]
BGAIN[1]
BGAIN[0]
BSTROBE
AGC_EN
MR
SI
VSS
A[7]
VDD
A[6]
VSS
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
WR
RD
CE
VSS
D[7]
D[6]
VDD
NC
NC
VSS
(MSB) AIN[13]
AIN[12]
AIN[11]
AIN[10]
AIN[9]
AIN[8]
AIN[7]
VDD
AIN[6]
AIN[5]
AIN[4]
AIN[3]
AIN[2]
AIN[1]
AIN[0]
VSS
CK
VDD
(MSB) BIN[13]
BIN[12]
BIN[11]
BIN[10]
BIN[9]
BIN[8]
BIN[7]
VSS
BIN[6]
BIN[5]
BIN[4]
BIN[3]
BIN[2]
BIN[1]
BIN[0]
VSS
NC
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
VDD
AGAIN[2]
AGAIN[1]
AGAIN[0]
ASTROBE
NC
SCAN_EN
TRST
VSS
TCK
TMS
TDI
TDO
VDD
POUT_SEL[0]
POUT_SEL[1]
POUT_SEL[2]
POUT_EN
VSS
POUT[0]
POUT[1]
VDD
POUT[2]
POUT[3]
POUT[4]
VSS
CLC5902 Pinout
Figure 4
CLC5902 Pinout
Rev. 3.05 May 27, 1999
6
©1999 National Semiconductor Corporation
Pin Descriptions
Signal
Pin
DESCRIPTION
MR
45
MASTER RESET, Active low
Resets all registers within the chip. ASTROBE and BSTROBE are asserted during MR.
AIN[13:0],
BIN[13:0]
4:10,12:18
22:28,30:36
INPUT DATA, Active high
2’s complement input data. AIN[13] and BIN[13] are the MSBs. The data is clocked into the chip on the
rising edge of the clock (CK). The CLC595X connects directly to these input pins with no additional logic.
SERIAL OUTPUT DATA, Active high
The 2’s complement serial output data is transmitted on these pins, MSB first. The output bits change on
the rising edge of SCK (falling edge if SCK_POL=1) and should be captured on the falling edge of SCK
(rising if SCK_POL=1). These pins are tri-stated at power up and are enabled by the SOUT_EN control
register bit. See Figure 9 and Figure 29 timing diagrams. In Debug Mode AOUT=DEBUG[1],
BOUT=DEBUG[0].
AOUT
BOUT
(12mA drive)
82
78
AGAIN[2:0],
BGAIN[2:0]
125:127
40:42
OUTPUT DATA TO DVGA, Active high
3 bit bus that sets the gain of the DVGA determined by the AGC circuit.
ASTROBE,
BSTROBE
124
43
DVGA STROBE, Active low
Strobes the data into the DVGA. See Figure 8 and Figure 33 timing diagrams.
SCK
(12mA drive)
80
SFS
(12mA drive)
81
SERIAL DATA CLOCK, Active high or low
The serial data is clocked out of the chip by this clock. The active edge of the clock is user programmable.
This pin is tri-stated at power up and is enabled by the SOUT_EN control register bit. See Figure 9 and Figure 29 timing diagrams. In Debug Mode outputs an appropriate clock for the debug data.
SERIAL FRAME STROBE, Active high or low
The serial word strobe. This strobe delineates the words within the serial output streams. This strobe is a
pulse at the beginning of each serial word (PACKED=0) or each serial word I/Q pair (PACKED=1). The
polarity of this signal is user programmable. This pin is tri-stated at power up and is enabled by the
SOUT_EN control register bit. See Figure 9 and Figure 29 timing diagrams. In Debug Mode
SFS=DEBUG[2].
POUT[15:0]
(12mA drive)
84,86:88,90,91,
93:97,104:106,
108,109
PARALLEL OUTPUT DATA, Active high
The output data is transmitted on these pins in parallel format. The POUT_SEL[2..0] pins select one of
eight 16-bit output words. The POUT_EN pin enables these outputs. POUT[15] is the MSB. In Debug
Mode POUT[15..0]=DEBUG[19..4].
POUT_SEL[2:0]
112:114
PARALLEL OUTPUT DATA SELECT, Active high
The 16-bit output word is selected with these 3 pins according to Table 3. Not used in Debug Mode.
POUT_EN
111
PARALLEL OUTPUT ENABLE. Active low
This pin enables the chip to output the selected output word on the POUT[15:0] pins. Not used in Debug
Mode.
READY FLAG, Active high or low
The chip asserts this signal to identify the beginning of an output sample period (OSP). The polarity of this
signal is user programmable. This signal is typically used as an interrupt to a DSP chip, but can also be used
as a start pulse to dedicated circuitry. This pin is active regardless of the state of SOUT_EN. In Debug
Mode RDY=DEBUG[3].
RDY
(12mA drive)
77
CK
20
INPUT CLOCK. Active high
The clock input to the chip. The AIN, BIN, and SI input signals are clocked into the chip on the rising edge
of this clock.
SI
46
SYNC IN. Active low
The sync input to the chip. The decimation counters, dither, and NCO phase can be synchronized by SI.
This sync is clocked into the chip on the rising edge of the input clock (CK). Tie this pin high if external
sync is not required. All sample data is flushed by SI. To properly initialize the DVGA ASTROBE and
BSTROBE are asserted during SI.
D[7:0]
(12mA drive)
62,63,69:73,75
Table 1
DATA BUS. Active high
This is the 8 bit control data I/O bus. Control register data is loaded into the chip or read from the chip
through these pins. The chip will only drive output data on these pins when CE is low, RD is low, and WR
is high.
CLC5902 Pin Descriptions
©1999 National Semiconductor Corporation
7
Rev. 3.05 May 27, 1999
Signal
Pin
DESCRIPTION
A[7:0]
48,50,52:57
ADDRESS BUS. Active high
These pins are used to address the control registers within the chip. Each of the control registers within the
chip are assigned a unique address in a flat address space. A control register can be written to or read from
by setting A[7:0] to the register’s address.
RD
59
READ ENABLE. Active low
This pin enables the chip to output the contents of the selected register on the D[7:0] pins when CE is also
low.
WR
58
WRITE ENABLE. Active low
This pin enables the chip to write the value on the D[7:0] pins into the selected register when CE is also
low. This pin can also function as RD/WR if RD is held low.
CE
60
CHIP ENABLE. Active low
This control strobe enables the read or write operation. The contents of the register selected by A[7:0] will
be output on D[7:0] when RD is low and CE is low. If WR is low and CE is low, then the selected register
will be loaded with the contents of D[7:0].
AGC_EN
44
AGC ENABLE. Active low
When enabled this pin starts the AGC counter. The AGC will operate until the counter decrements to zero
then the AGC holds the last setting.
TDO
116
TEST DATA OUT. Active high
TDI
117
TEST DATA IN. Active high with pull-up
TMS
118
TEST MODE SELECT. Active high with pull-up
TCK
119
TEST CLOCK. Active high
TRST
121
RESET. Active low with pull-up
Asynchronous reset for TAP controller. Tie low or to MR if JTAG is not used.
SCAN_EN
122
SCAN ENABLE. Active low with pull-up
Enables access to internal scan registers. Tie high. Used for manufacturing test only!
VSS
3,19,29,37,47,51,
61,68,76,83,89,
98,103,110,120
Ground. Quantity 15.
VDD
11,21,39,49,64,
74,79,85,92,107,
115,128
Power. Quantity 12.
Table 1
CLC5902 Pin Descriptions
Timing Diagrams
CK
tMRH
tMRSU
tMRA
MR
tMRIC
RD
or WR
tMRSR
A|BSTROBE
Figure 5
CLC5902 Master Reset Timing
Rev. 3.05 May 27, 1999
8
©1999 National Semiconductor Corporation
CK
tSIH
tSISU
tSIW
SI
tSISR
A|BSTROBE
Figure 6
CLC5902 Synchronization Input (SI) Timing
1/FCK
tCKDC
tCKDC
CK
VIH
VIL
tHD
tRF
tSU
A|BIN
Figure 7
CLC5902 ADC Input and Clock Timing
CK
tSTBPW
A|BSTROBE
tGSU
(n-1)
A|BGAIN[2..0]
valid (n)
tENW
AGC_EN
Figure 8
CLC5902 DVGA Interface Timing
©1999 National Semiconductor Corporation
9
Rev. 3.05 May 27, 1999
SCK
SCK_POL=0
SCK=CK/2
SCK
SCK_POL=1
tSFSV
tSFSV
SFS
SFS_POL=0
SFS
SFS_POL=1
tOV
tOV
lsb or undef
A|BOUT
msb
Previous Q Output Word
msb-1
msb-2
msb-3
I Output Word
RDY
RDY_POL=0
tRDYW
RDY
RDY_POL=1
Figure 9
CLC5902 Serial Port Timing
POUT_EN
tOENV
tOENT
POUT[15..0]
Figure 10
CLC5902 Parallel Output Enable Timing
POUT_SEL[2..0]
n
n+1
n+2
tSELV
POUT[15..0]
Figure 11
tSELV
output (n)
output (n+1)
output (n+2)
CLC5902 Parallel Output Select Timing
RDY
RDY_POL=0
RDY
RDY_POL=1
tRDYV
POUT[15..0]
Figure 12
old output
new output
CLC5902 Parallel Output Data Ready Timing
Rev. 3.05 May 27, 1999
10
©1999 National Semiconductor Corporation
TCK
tPLH,tPHL
TDO, D
TCK
tPZH
tPHZ
tPZL
tPLZ
D
TCK
TDO
tWH
tWL
1/JTAGfmax
TCK
tH
tS
TMS, TDI, D
Figure 13
CLC5902 JTAG Port Timing
CE
WR
tCHD
RD
tCSU
A[7:0]
tCDLY
tCZ
D[7:0]
READ CYCLE; NORMAL MODE
CE
tCSPW
WR
RD
tCSU
A[7:0]
tCHD
D[7:0]
WRITE CYCLE; NORMAL MODE
CE
tCHD
WR
tCSU
A[7:0]
tCDLY
tCZ
D[7:0]
READ CYCLE; RD HELD LOW
tCSPW
CE
WR
tCSU
A[7:0]
tCHD
D[7:0]
WRITE CYCLE; RD HELD LOW
Figure 14
CLC5902 Control I/O Timing
©1999 National Semiconductor Corporation
11
Rev. 3.05 May 27, 1999
tialized, the NCO dither generators will be reset, and the
CIC decimation ratio will be initialized. Only the configuration data loaded into the microprocessor interface
remains unaffected.
Detailed Description
Control Interface
The CLC5902 is configured by writing control information into 148 control registers within the chip. The contents of these control registers and how to use them are
described in Table 5. The registers are written to or read
from using the D[7:0], A[7:0], CE, RD and WR pins (see
Table 1 for pin descriptions). This interface is designed to
allow the CLC5902 to appear to an external processor as a
memory mapped peripheral. See Figure 14 for details.
SI may be held low as long as desired after a minimum of
4 CK periods.
Input Source
The input crossbar switch allows either AIN, BIN, or a
test register to be routed to the channel A or channel B
AGC/DDC. The AGC outputs, AGAIN and BGAIN, are
not switched. If AIN and BIN are exchanged the AGC
loop will be open and the AGCs will not function properly.
AIN and BIN should meet the timing requirements shown
in Figure 7.
The control interface is asynchronous with respect to the
system clock, CK. This allows the registers to be written
or read at any time. In some cases this might cause an
invalid operation since the interface is not internally synchronized. In order to assure correct operation, SI must be
asserted after the control registers are written.
Selecting the test register as the input source allows the
AGC or DDC operation to be verified with a known input.
See the test and diagnostics section for further discussion.
The D[7:0], A[7:0], WR, RD and CE pins should not be
driven above the positive supply voltage.
Down Converters
Master Reset
A detailed block diagram of each DDC channel is shown
in Figure 15. Each down converter uses a complex NCO
and mixer to quadrature downconvert a signal to baseband. The “FLOAT TO FIXED CONVERTER” treats the
15-bit mixer output as a mantissa and the AGC output,
EXP, as a 3-bit exponent. It performs a bit shift on the data
based on the value of EXP. This bit shifting is used to
expand the compressed dynamic range resulting from the
DVGA operation. The DVGA gain is adjusted in 6dB
steps which are equivalent to each digital bit shift.
A master reset pin, MR, is provided to initialize the
CLC5902 to a known condition and should be strobed
after power up. This signal will clear all sample data and
all user programmed data (filter coefficients and AGC settings). All outputs will be disabled (tri-stated). ASTROBE
and BSTROBE will be asserted to initialize the DVGA
values. Table 5 describes the control register default values.
Synchronizing Multiple CLC5902 Chips
The exponent (EXP) can be forced to its maximum value
by setting the EXP_INH bit. If x in ( n ) is the DDC input,
the signal after the “FLOAT TO FIXED CONVERTER” is
A system containing two or more CLC5902 chips will
need to be synchronized if coherent operation is desired.
To synchronize multiple CLC5902 chips, connect all of
the sync input pins together so they can be driven by a
common sync strobe. Synchronization occurs on the rising
edge of CK when SI goes back high. When SI is asserted
all sample data will be flushed immediately, the numerically controlled oscillator (NCO) phase offset will be ini-
17
SIN
COS
x3 ( n )
Data @ FCK/N
DEC_BY_4
F2_COEF
Data @ FCK/N*2
21
I
SAT
21
F2 FILTER
DECIMATE BY
2 OR 4
21
SAT & ROUND
21
F1 FILTER
DECIMATE BY 2
22
SHIFT UP
22
SAT & ROUND
15
17
F1_COEF
DEC
CIC FILTER
DECIMATE BY
8 TO 2K
Data @ FCK
= FS (FSAMPLE)
GAIN_A
SCALE
SHIFT UP
14
15
FLOAT
TO FIXED
CONVERTER
ROUND
EXPONENT
MUXA
EQ. 1
EXP
3
x in ( n )
EXP
for the I component. Changing the ‘cos’ to ‘sin’ in this
equation will provide the Q component.
EXP_INH
EXP
(from AGC)
FREQ_A
x 3 ( n ) = x in ( n ) • cos ( ωn ) • 2
TO
OUTPUT
CIRCUIT
Q
Data @ FCK/N*2*F2_DEC
= OFS (Output FSAMPLE)
NCO
PHASE_A
Figure 15
N = DEC + 1
CLC5902 Down Converter, Channel A (Channel B is identical)
Rev. 3.05 May 27, 1999
12
©1999 National Semiconductor Corporation
The “FLOAT TO FIXED CONVERTER” circuit expands
the dynamic range compression performed by the DVGA.
Signals from this point onward extend across the full
dynamic range of the signals applied to the DVGA input.
This allows the AGC to operate continuously through a
burst without producing artifacts in the signal due to the
settling response of the decimation filters after a 6dB
DVGA gain adjustment. For example, if the DVGA input
signal were to increase causing the ADC output level to
cross the AGC threshold level, the gain of the DVGA
would change by -6dB. The 6dB step is allowed to propagate through the ADC and mixers and is compensated out
just before the filtering. The accuracy of the compensation
is dependent on the accuracy of the DVGA gain step. This
operating mode requires 21 bits (14-bit ADC output + 7bit shift) to represent the full linear dynamic range of the
signal. The output word must be set to either 24-bit or 32bit to take advantage of the entire dynamic range available. The CLC5902 can also be configured to output a
floating point format with up to 138dB of numerical resolution using only 12 output bits.
The “SHIFT UP” circuit will be discussed in the Four
Stage CIC filter section on page 14.
A 4-stage cascaded-integrator-comb (CIC) filter and a
two-stage decimate by 4 or 8 finite impulse response (FIR)
filter are used to lowpass filter and isolate the desired signal. The CIC filter reduces the sample rate by a programmable factor ranging from 8 to 2048 (decimation ratio).
The CIC outputs are followed by a gain stage and then followed by a two-stage decimate by 4 or 8 filter. The gain
circuit allows the user to boost the gain of weak signals by
up to 42 dB in 6 dB steps. It also rounds the signal to 21
bits and saturates at plus or minus full scale.
The first stage of the two stage filter is a 21-tap, symmetric
decimate by 2 FIR filter (F1) with programmable 16 bit
tap weights. The coefficients of the first 11 taps are downloaded to the chip as 16 bit words. Since the filter is a symmetric configuration only the first 11 coefficients must be
loaded. The F1 section on page 15 provides a generic set
of coefficients that compensate for the rolloff of the CIC
filter and provide a passband flat to 0.01dB with 70 dB of
out of band rejection. A second coefficient set is provided
that has a narrower output passband and greater out-ofband rejection. The second set of coefficients is ideal for
systems such as GSM where far-image rejection is more
important than adjacent channel rejection.
The second stage is a 63 tap decimate by 2 or 4 programmable FIR filter (F2) also with 16 bit tap weights. Filter
coefficients for a flat response from -0.4FS to +0.4FS of
the output sample rate with 80dB of out of band rejection
are provided in the F2 section. A second set of F2 coefficients is also provided to enhance performance for GSM
systems. The user can also design and download their own
final filter to customize the channel’s spectral response.
Typical uses of programmable filter F2 include matched
(root-raised cosine) filtering, or filtering to generate oversampled outputs with greater out of band rejection. The 63
tap symmetrical filter is downloaded into the chip as 32
words, 16 bits each. Saturation to plus or minus full scale
is performed at the output of F1 and F2 to clip the signal
rather than allow it to roll over.
The Numerically Controlled Oscillator
The tuning frequency of each down converter is specified
as a 32 bit word (.02Hz resolution at CK=52MHz) and the
phase offset is specified as a 16 bit word (.005°). These
two parameters are applied to the Numerically Controlled
Complex NCO Output
0
0
-20
-20
-40
-40
Magnitude (dB)
Magnitude (dB)
Complex NCO Output
-60
-80
-60
-80
-100
-100
-120
-120
-140
-140
-160
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
-160
-0.5
0.5
Frequency Normalized to FS
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
Frequency Normalized to FS
(b) After Phase Dithering
(a) Before Phase Dithering
Figure 16
-0.4
Example of NCO spurs due to phase truncation
©1999 National Semiconductor Corporation
13
Rev. 3.05 May 27, 1999
Oscillator (NCO) circuit to generate sine and cosine signals used by the digital mixer. The NCOs can be synchronized with NCOs on other chips via the sync pin SI. This
allows multiple down converter outputs to be coherently
combined, each with a unique phase and amplitude.
Complex NCO Output
Phase Dither Disabled
0
NCO frequency swept through FS/8
from -FCK/2 to +FCK(1-2-31)/2.
In some cases the sampling process causes the order of the
I and Q components to be reversed. Should this occur simply invert the polarity of the tuning frequency F.
-20
-40
Magnitude (dB)
The tuning frequency is set by loading the FREQ register
according to the formula FREQ = 232F/FCK, where F is
the desired tuning frequency and FCK is the chip’s clock
rate. FREQ is a 2’s complement word. The range for F is
-60
-80
-100
-120
-140
The 2’s complement format represents full-scale negative
as 10000000 and full-scale positive as 01111111 for an 8bit example.
is the desired phase in radians ranging between 0 and 2π.
PHASE is an unsigned 16-bit number. P ranges from 0 to
2π(1-2-16).
Phase dithering can be enabled to reduce the spurious signals created by the NCO due to phase truncation. This
truncation is unavoidable since the frequency resolution is
much finer than the phase resolution. With dither enabled,
spurs due to phase truncation are below -100 dBc for all
frequencies and phase offsets. Each NCO has its own
dither source and the initial state of one is maximally offset with respect to the other so that they are effectively
uncorrelated. The phase dither sources are on by default.
They are independently controlled by the DITH_A and
DITH_B bits. The amplitude resolution of the ROM creates a worst-case spur amplitude of -101dBc rendering
amplitude dither unnecessary.
The spectrum plots in Figure 16 show the effectiveness of
phase dither in reducing NCO spurs due to phase truncation for a worst-case example (just below F S /8). With
dither off, the spur is at -86.4dBFS. With dither on, the
spur is below -125dBFS, disappearing into the noise floor.
This spur is spread into the noise floor which results in an
SNR of -83.6dBFS.
Figure 17 shows the spur levels as the tuning frequency is
scanned over a narrow portion of the frequency range. The
spurs are again a result of phase quantization but their
locations move about as the frequency scan progresses. As
before, the peak spur level drops when dithering is
enabled. When dither is enabled and the fundamental frequency is exactly at F S /8, the worst-case spur due to
amplitude quantization can be observed at -101dBc in Figure 18.
Rev. 3.05 May 27, 1999
14
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
Frequency Normalized to FS
Figure 17
NCO Spurs due to Phase Quantization
Complex NCO Output
Phase Dither Enabled
0
-20
-40
Magnitude (dB)
The 16 bit phase offset is set by loading the PHASE register according to the formula PHASE = 216P/2π, where P
-160
-0.5
-60
-80
-100
-120
-140
-160
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
Frequency Normalized to FS
Figure 18
Worst Case Amplitude Spur, NCO at FS/8
Four Stage CIC Filter
The mixer outputs are decimated by a factor of N in a four
stage CIC filter. N is programmable to any integer
between 8 and 2048. Decimation is programmed in the
DEC register where DEC = N - 1. The programmable decimation allows the chip’s usable output bandwidth to range
from about 2.6kHz to 1.3MHz when the input data rate
(which is equal to the chip’s clock rate, FCK) is 52 MHz. A
block diagram of the CIC filter is shown in Figure 19.
©1999 National Semiconductor Corporation
Data @ FCK
= FS (FSAMPLE)
Figure 19
DECIMATE
BY FACTOR
OF N
22
66
22-bit input to SHIFT_UP is aligned
at the bottom of the 66-bit path when SCALE=0.
DATA
OUT
Data @ FCK/N
N = DEC + 1
Four-stage decimate by N CIC filter
The CIC filter has a gain equal to N4 (filter decimation^4)
which must be compensated for in the “SHIFT UP” circuit
shown in Figure 19 as well as Figure 15. This circuit has a
gain equal to 2(SCALE-44), where SCALE ranges from 0 to
40. This circuit divides the input signal by 244 providing
maximum headroom through the CIC filter. For optimal
noise performance the SCALE value is set to increase this
level until the CIC filter is just below the point of distortion. A value is normally calculated and loaded for
SCALE such that GAIN SHIFTUP ⋅ GAIN CIC ≤ 1 . The
actual gain of the CIC filter will only be unity for powerof-two decimation values. In other cases the gain will be
somewhat less than unity.
Channel Gain
symmetric with the following 11 unique taps (1|21, 2|20,
..., 10|12, 11):
29, -85, -308, -56, 1068, 1405, -2056, -6009,
1303, 21121, 32703
Frequency Response of F1 Using STD Set
0
−10
−20
−30
Magnitude (dB)
DATA
IN
SHIFT UP
SCALE
−40
−50
−60
−70
−80
The gain of each channel can be boosted up to 42 dB by
shifting the output of the CIC filter up by 0 to 7 bits prior
to rounding it to 21 bits. For channel A, the gain of this
−90
−100
0
0.1
0.2
0.3
0.4
Frequency Normalized To Filter Input Sample Rate
GAIN_A
stage is: GAIN = 2
, where GAIN_A ranges from 0
to 7. Overflow due to the GAIN circuit is saturated
(clipped) at plus or minus full scale. Each channel can be
given its own GAIN setting.
First Programmable FIR Filter (F1)
The CIC/GAIN outputs are followed by two stages of filtering. The first stage is a 21 tap decimate-by-2 symmetric
FIR filter with programmable coefficients. Typically, this
filter compensates for a slight droop induced by the CIC
filter. In addition, it often provides stopband assistance to
F2 when deep stop bands are required. The filter coefficients are 16-bit 2’s complement numbers. Unity gain will
be achieved through the filter if the sum of the 21 coefficients is equal to 216. If the sum is not 216, then F1 will
introduce a gain equal to (sum of coefficients)/216. The 21
coe ffi ci ent s a re ide nti fi ed as c oeffic ie nts
h 1 ( n ), n = 0, …, 20 where h 1 ( 10 ) is the center tap.
The coefficients are symmetric, so only the first 11 are
loaded into the chip.
Figure 20
0.5
F1 STD frequency response
The second set of coefficients (GSM set) are intended for
applications that need deeper stop bands or need oversampled outputs. These requirements are common in cellular
systems where out of band rejection requirements can
exceed 100dB (see Figure 21). They are useful for wideband radio architectures where the channelization is done
after the ADC. These filter coefficients introduce a gain of
0.984 and are:
-49, -340, -1008, -1617, -1269, 425, 3027, 6030,
9115, 11620, 12606
Second Programmable FIR Filter (F2)
The second stage decimate by two or four filter also uses
externally downloaded filter coefficients. The filter coefficients are 16-bit 2’s complement numbers. Unity gain will
be achieved through the filter if the sum of the 63 coefficients is equal to 216. If the sum is not 216, then the F2 will
introduce a gain equal to (sum of coefficients)/216.
Two example sets of coefficients are provided here. The
first set of coefficients, referred to as the standard set
(STD), compensates for the droop of the CIC filter providing a passband which is flat (0.01 dB ripple) over 95% of
the final output bandwidth with 70dB of out-of-band rejection (see Figure 20). The filter has a gain of 0.999 and is
The 63 coefficients are identified as h 2 ( n ) , n = 0 ,… ,62
15
Rev. 3.05 May 27, 1999
©1999 National Semiconductor Corporation
where h 2 ( 31 ) is the center tap. The coefficients are symmetric, so only the first 32 are loaded into the chip.
Frequency Response of F1 Using GSM Set
Frequency Response of F2 Using GSM Set
5
0
0
−5
−20
Magnitude (dB)
Magnitude (dB)
−10
−40
−60
−15
−20
−25
−30
−80
−35
−40
−100
−45
−120
0
0.1
0.2
0.3
0.4
Frequency Normalized To Filter Input Sample Rate
Figure 21
−50
0.5
F1 GSM frequency response
0
Figure 23
An example filter (STD F2 coefficients, see Figure 22)
with 80dB out-of-band rejection, gain of 1.00, and 0.03 dB
peak to peak passband ripple is created by this set of 32
unique coefficients:
-14, -20, 19, 73, 43, -70, -82, 84, 171, -49, -269, 34, 374, 192, -449,
0.1
0.2
0.3
0.4
Frequency Normalized To Filter Input Sample Rate
0.5
F2 GSM frequency response
The filter coefficients of both filters can be used to tailor
the spectral response to the user’s needs. For example, the
first can be loaded with the standard set to provide a flat
response through to the second filter. The latter can then
be programmed as a Nyquist (typically a root-raisedcosine) filter for matched filtering of digital data.
Combined Frequency Response of CIC/F1/F2 Using STD Set
-430, 460,751, -357, -1144, 81, 1581, 443, -2026,
-1337, 2437, 2886,
0
FCK = 52MHz
Decimation = 192
OFS = 270.83kHz
-2770, -6127, 2987, 20544, 29647
Magnitude (dB)
Frequency Response of F2 Using STD Set
0
−10
−20
Magnitude (dB)
−30
−50
−100
−40
−50
−60
−150
−70
0
−80
500
1000
1500
2000
Frequency (KHz)
2500
3000
−90
−100
0
0.1
0.2
0.3
0.4
Frequency Normalized To Filter Input Sample Rate
Figure 22
Figure 24
0.5
The complete channel filter response for standard coefficients is shown in Figure 24. Passband flatness is shown in
Figure 25.
F2 STD frequency response
A second set of F2 coefficients (GSM set, see Figure 23)
suitable for meeting the stringent wideband GSM requirements with a gain of 0.999 are:
The complete filter response for GSM coefficients is
shown in Figure 26.
GSM Passband flatness is shown in Figure 27.
The mask shown in Figure 26 is derived from the ETSI
GSM 5.05 specifications for a normal Basestation Transceiver (BTS). For interferers, 9dB was added to the carrier
to interference (C/I) ratios. For blockers, 9dB was added to
the difference between the blocker level and 3dB above
the reference sensitivity level.
-536, -986, 42, 962, 869, 225, 141, 93, -280, -708,
-774, -579, -384,
-79, 536, 1056, 1152, 1067, 789, 32, -935, -1668,
-2104, -2137, -1444,
71, 2130, 4450, 6884, 9053, 10413, 10832
Rev. 3.05 May 27, 1999
CIC, F1, & F2 STD frequency response
16
©1999 National Semiconductor Corporation
Overall Channel Gain
Combined Frequency Response of CIC/F1/F2 Using STD Set
0.1
The overall gain of the chip is a function of the amount of
decimation (N), the settings of the “SHIFT UP” circuit
(SCALE), the GAIN setting, the sum of the F1 coefficients, and the sum of the F2 coefficients. The overall gain
is shown below in Equation 2.
0.08
0.06
Magnitude (dB)
0.04
0.02
0
1
4
G DDC = --- ( DEC + 1 )
2
−0.02
−0.04
−0.06
−0.08
−0.1
0
Figure 25
50
100
150
Frequency (KHz)
200
⋅2
[ SCALE – 44 – AGAIN ⋅ ( 1 – EXP_INH ) ]
⋅2
GAIN
⋅ G F1 ⋅ G F2
250
Where:
CIC, F1, & F2 STD Passband Flatness
21
Combined Frequency Response of CIC/F1/F2 Using GSM Set
∑ h1( i )
0
=1
G F1 = i--------------------16
2
FCK = 52MHz
Decimation = 192
OFS = 270.83kHz
−20
Magnitude (dB)
EQ. 2
EQ. 3
and:
−40
63
∑ h2( i )
−60
=1
G F2 = i--------------------16
2
−80
It is assumed that the DDC output words are treated as
fractional 2’s complement words. The numerators of G F1
−100
0
Figure 26
500
1000
1500
2000
Frequency (KHz)
2500
EQ. 4
3000
and G F2 equal the sums of the impulse response coefficients of F1 and F2, respectively. For the STD and GSM
sets, G F1 and G F2 are nearly equal to unity. Observe that
CIC, F1, & F2 GSM frequency response
the AGAIN term in EQ. 2 is cancelled by the DVGA operation so that the entire gain of the DRCS is independent of
Combined Frequency Response of CIC/F1/F2 Using GSM Set
1
1
the DVGA setting when EXP_INH=0. The --- appearing in
2
0.5
EQ. 2 is the result of the 6dB conversion loss in the mixer.
Magnitude (dB)
0
1
For full-scale square wave inputs the --- should be set to 1
2
−0.5
to prevent signal distortion.
Data Latency and Group Delay
−1
The latency from a sync event to data output is approximately 8N CK periods for F2 decimation by 2 and 24N
CK periods for F2 decimation by 4. Actual non-zero data
output can be further delayed depending on the F1 and F2
filter coefficients.
−1.5
−2
0
Figure 27
20
40
60
Frequency (KHz)
80
100
CIC, F1, & F2 GSM Passband Flatness
©1999 National Semiconductor Corporation
Group Delay is approximately 90N CK periods for F2
decimation by 2 or 4.
17
Rev. 3.05 May 27, 1999
Serial Outputs
Output Modes
After processing by the DDC, the data is then formatted
for output.
Note
All output data is two’s complement.
RDY_POL, SCK_POL, SFS_POL
MUX_MODE
SERIAL OUTPUTS
RDY
MUX_MODE
AOUT
SCK
SFS
AOUT
BOUT
MUX
POUT[15..0]
16
POUT_SEL[2..0]
3
POUT_EN
Figure 28
CLC5902 output circuit
The channel outputs are accessible through serial output
pins and a 16-bit parallel output port. The RDY pin is provided to notify the user that a new output sample period
(OSP) has begun. OSP refers to the interval between output samples at the decimated output rate. For example, if
the input rate (and clock rate) is 52 MHz and the overall
decimation factor is 192 (N=48, F2 decimation=2) the
OSP will be 3.69 microseconds which corresponds to an
output sample rate of 270.83kHz. An OSP starts when a
sample is ready and stops when the next one is ready.
BOUT
0
OUTA
OUTB
1
OUTA, OUTB
LOW
Table 2
PACKED
NUMBER FORMAT
CONTROL
SERIALIZER AND
TDM FORMATTER
DIVIDE
BY
RATE
FORMAT
CH A
CH B
CK
POLARITY INVERT
Output formats include truncation to 8 or 32 bits, rounding
to 16 or 24 bits, and a 12-bit floating point format (4-bit
exponent, 8-bit mantissa, 138dB numeric range). This
function is performed in the OUTPUT CIRCUIT shown in
Figure 28.
The CLC5902 provides a serial clock (SCK), a frame
strobe (SFS) and two data lines (AOUT and BOUT) to
output serial data. The MUX_MODE control register
specifies whether the two channel outputs are transmitted
on two separate serial pins, or multiplexed onto one pin in
a time division multiplexed (TDM) format. Separate output pins are not provided for the I and Q halves of complex data. The I and Q outputs are always multiplexed
onto the same serial pin. The I-component is output first,
followed by the Q-component. By setting the PACKED
mode bit to ‘1’ a complex pair may be treated as a single
double-wide word. The RDY signal is used to identify the
first word of a complex pair of the TDM formatted output.
The TDM modes are summarized in Table 2.
TDM Modes
The serial outputs use the format shown in Figure 29. Figure 29(a) shows the standard output mode (the PACKED
mode bit is low). The chip clocks the frame and data out of
the chip on the rising edge of SCK (or falling edge if the
SCK_POL bit in the input control register is set high).
Data should be captured on the falling edge of SCK (rising if SCK_POL=1). The chip sends the I data first by setting SFS high (or low if SFS_POL in the input control
register is set high) for one clock cycle, and then transmitting the data, MSB first, on as many SCK cycles as are
necessary. Without a pause, the Q data is transferred next
as shown in Figure 29(a). If the PACKED control bit is
high, then the I and Q components are sent as a double
length word with only one SFS strobe as shown in Figure
29(b). If both channels are multiplexed out the same serial
pin, then the subsequent I/Q channel words will be transmitted immediately following the first I/Q pair as shown
in Figure 29(c). Figure 29(c) also shows how the RDY
signal can be used to identify the I and Q channels in the
TDM serial transmission.The serial output rate is programmable using the RATE register as a integer division
of the input clock, the division ratio ranging from 1 to 256.
The serial interface will not work properly if the programmed rate of SCK is insufficient to clock out all the
bits in one OSP.
Serial Port Output Number Formats
Several numeric formats are selectable using the FORMAT control register. The I/Q samples can be rounded to
16 or 24 bits, or truncated to 8 bits. The packed mode
works as described above for these fixed point formats. A
floating point format with 138dB of dynamic range in 12
bits is also provided. The mantissa (m) is 8 bits and the
exponent (e) is 4 bits. The MSB of each segment is trans-
Note
The serial outputs power up in a tri-state
condition and must be enabled when the chip
is configured. Parallel outputs are enabled by
the POUT_EN pin.
Rev. 3.05 May 27, 1999
18
©1999 National Semiconductor Corporation
clock stops and data is zero after transfers are complete
SCK
SFS
AOUT
I15
I1
I14
I0
Q15
Q14
Q1
Q0
(a) UNPACKED MODE, FRAME SYNC AT THE START OF EACH WORD
clock stops and data is zero after transfers are complete
SCK
SFS
I15
AOUT
I14
I1
I0
Q15
Q14
Q1
Q0
(b) PACKED MODE, ONE FRAME SYNC AT THE START OF EACH DOUBLE-WORD TRANSFER
RDY
leading edge of RDY aligns with leading edge of SFS
RDY is 4 CK periods wide
Output Sample Period (OSP)
SFS
AOUT
IA
QA
SFS
AOUT
IA
QA
IB
QB
MUX_MODE=0
IA
QA
MUX_MODE=1
IA
QA
IB
QB
(c) ONE OR TWO CHANNEL MUX MODES (PACKED MODE IS ON)
clock stops and data is zero after transfers are complete
SCK
SFS
AOUT
mI7
mI6
mI0
eI3
eI2
eI0
eQ3
eQ0
mQ7
mQ0
(d) FLOATING POINT FORMAT
Figure 29
Serial output formats. Refer to Figure 9 for detailed timing information
mitted first. When this mode is selected, the I/Q samples
are packed regardless of the state of MUX_MODE, and
the data is sent as mI/eI/eQ/mQ which allows the two
exponents to form an 8-bit word. This is shown in Figure
29(d). For all formats, once the defined length of the word
is complete, SCK stops toggling.
can be formatted as floating point numbers with an 8-bit
mantissa and a 4 bit exponent. For the fixed-point formats,
the valid bits are justified into the MSBs of the registers of
Table 3 and all other bits are set to zero. For the floating
POUT_SEL
Parallel Outputs
Output data from the channels can also be taken from a
16-b it par allel po rt. A 3-bit word applied to the
POUT_SEL[2:0] pins determines which 16-bit segment is
multiplexed to the parallel port. Table 3 defines this mapping. To allow for bussing of multiple chips, the parallel
port is tri-stated unless POUT_EN is low. The RDY signal indicates the start of an OSP and that new data is ready
at the parallel output. The user has one OSP to cycle
through whichever registers are needed. The RATE register must be set so that each OSP is at least 5 SCK periods.
The I/Q samples can be rounded to 16 or 24 bits or the full
32 bit word can be read. By setting the word size to 32 bits
it is possible to read out the top 16 bits and only observe
the top 8 bits if desired. Additionally, the output samples
©1999 National Semiconductor Corporation
19
Floating Point
Register Contents
0
IA upper 16 bits
0000/eIA/mIA
1
IA lower 16 bits
0x0000
2
QA upper 16 bits
0000/eQA/mQA
3
QA lower 16 bits
0x0000
4
IB upper 16 bits
0000/eIB/mIB
5
IB lower 16 bits
0x0000
6
QB upper 16 bits
0000/eQB/mQB
7
QB lower 16 bits
0x0000
Table 3
Parallel Port Output Numeric Formats
Normal Register
Contents
Register Selection for Parallel Output
point format, the valid bits are placed in the upper 16 bits
of the appropriate channel register using the format 0000/
eI/mI for the I samples.
Rev. 3.05 May 27, 1999
AGC
The CLC5902 AGC processor monitors the output level of
the ADC and servos it to the desired setpoint. The ADC
input is controlled by the DVGA to maintain the proper
setpoint level. DVGA operation results in a compression
of the signal through the ADC. The DVGA signal compression is reversed in the CLC5902 to provide > 120dB
of linear dynamic range. This is illustrated in Figure 30.
Diversity Receiver
Chipset Full Scale
Output Power
A
O GC
ve O
rT p
hi era
s R te
an s
ge
D
D
C
pu
ut
O
6dB steps the deadband should always be greater than 6dB
to prevent oscillation. An increased deadband value will
reduce the amount of AGC operation. A decreased deadband value will increase the amount of AGC operation but
will hold the ADC output closer to the setpoint. The
threshold should be set so that transients do not cause sustained overrange at the ADC inputs. The threshold setting
can also be used to set the ADC input near its optimal performance level.
The AGC may be configured to free run, operate for a programmable period of time (burst mode), or stop running. If
a burst start pulse is applied to the AGC_EN pin in burst
mode, the AGC will free run for AGC_HOLD_COUNT
CK periods then freeze. At the beginning of the next burst
either the freeze value is maintained or an initial condition
is set from AGC_IC_A|B based on AGC_RESET_EN.
Allowing the AGC to free run should be appropriate for
most applications. Table 4 shows the AGC mode control
bits.
t
ADC Full Scale
AGC Threshold
AGC Mode
ADC Output
Deadband+Hysteresis
Figure 30
Input Power
6dB
AgcRstEn
AgcForce
Free Run
0
0
1
Burst, hold previous value
0
0
0
Burst, use initial conditions
0
1
0
Manual
1
0
0
Table 4
Output Gain Scaling vs. Input Signal
In order to use the AGC the DRCS Control Panel software
should be used to calculate the programmable parameters.
To generate these parameters only the desired setpoint,
deadband+hysteresis, and loop time constant need to be
supplied. All subsequent calculations are performed by the
software. Complete details of the AGC operation are provided in an appendix but are not required reading.
DVGA Output Power
AgcHldIC
AGC Operating Modes
Power Management
The CLC5902 can be placed in a low power (static) state
by stopping the input clock. To prevent this from placing
the CLC5902 into unexpected states, the SI pin of the
CLC5902 should be asserted prior to disabling the input
clock and held asserted until the input clock has returned
to a stable condition.
Deadband
Reference
Setpoint
6dB
Hysteresis=Deadband-6dB
DVGA Input Power
Figure 31
AGC Setup.
AGC setpoint and deadband+hysteresis are illustrated in
Figure 31. The loop time constant is a measure of how fast
the loop will track a changing signal. Values down to
approximately 1.0 microsecond will be stable with the second order LC noise filter. Since the DVGA operates with
Rev. 3.05 May 27, 1999
20
©1999 National Semiconductor Corporation
Real-time access to the following signals is provided by
configuring the control interface debug register:
Test and Diagnostics
The CLC5902 supports IEEE 1149.1 compliant JTAG
Boundary Scan for the I/O’s. The following pins are used:
TRST
TMS
TDI
TDO
TCK
(test reset)
(test mode select)
(test data in)
(test data out)
(test clock)
•
•
•
•
NCO sine and cosine outputs
data after round following mixers
data before F1 and F2
data after the CIC filter within the AGC
The access points are multiplexed to a 20-bit parallel output port which is created from signal pins POUT[15:0],
AOUT, BOUT, SFS, and RDY according to the table
below:
The following JTAG instructions are supported:
Normal Mode Pin
Debug Mode Pin
Instruction
Description
POUT[15:0]
DEBUG[19..4]
BYPASS
Connects TDI directly to TDO
RDY
DEBUG[3]
EXTEST
Drives the ‘extest’ TAP controller output
SFS
DEBUG[2]
IDCODE
Connects the 32-bit ID register to TDO
AOUT
DEBUG[1]
SAMPLE/PRELOAD
Drives the ‘samp_load’ TAP controller output
BOUT
DEBUG[0]
HIGHZ
Tri-states the outputs
The JTAG Boundary Scan can be used to verify printed
circuit board continuity at the system level.
The user is able to program a value into TEST_REG and
substitute this for the normal channel inputs from the AIN/
BIN pins by selecting it with the crossbar. With the NCO
frequency set to zero this allows the DDCs and the output
interface of the chip to be verified. Also, the AGC loop
can be opened by setting AGC_HOLD_IC high and setting the gain of the DVGA by programming the appropriate value into the AGC_IC_A/B register.
SCK will be set to the proper strobe rate for each debug
tap point. POUT_EN and PSEL[2..0] have no effect in
Debug Mode. The outputs are turned on when the Debug
Mode bit is set. Normal serial outputs are also disabled.
Control Registers
The chip is configured and controlled through the use of 8bit control registers. These registers are accessed for reading or writing using the control bus pins (CE, RD, WR,
A[7:0], and D[7:0]) described in the Control Interface section. The register names and descriptions are listed in
Table 5.
Control Registers
Register Name
Width
Type
Defaulta
Addr
Bit
Description
DEC
11b
R/W
7
0(LSBs)
1(MSBs)
7:0
2:0
CIC decimation control. N=DEC+1. Valid range is from 7 to 2047. Format is an unsigned
integer. This affects both channels.
DEC_BY_4
1b
R/W
0
1
4
Controls the decimation factor in F2. 0=Decimate by 2. 1=Decimate by 4. This affects both
channels.
SCALE
6b
R/W
0
2
5:0
CIC SCALE parameter. Format is an unsigned integer representing the number of left bit
shifts to perform on the data prior to the CIC filter. Valid range is from 0 to 40. This affects
both channels.
GAIN_A
3b
R/W
0
3
2:0
Value of left bit shift prior to F1 for channel A.
GAIN_B
3b
R/W
0
4
2:0
Value of left bit shift prior to F1 for channel B.
RATE
1B
R/W
1
5
7:0
Determines rate of serial output clock. The output rate is FCK/(RATE+1). Unsigned integer.
SOUT_EN
1b
R/W
0
6
0
Enables the serial output pins AOUT, BOUT, SCK, and SFS. 0=Tristate. 1=Enabled.
SCK_POL
1b
R/W
0
6
1
Determines polarity of the SCK output. 0=AOUT, BOUT, and SFS change on the rising edge
of SCK (capture on falling edge). 1=They change on the falling edge of SCK.
SFS_POL
1b
R/W
0
6
2
Determines polarity of the SFS output. 0=Active High. 1=Active Low.
RDY_POL
1b
R/W
0
6
3
Determines polarity of the RDY output. 0=Active High. 1=Active Low.
MUX_MODE
1b
R/W
0
6
4
Determines the mode of the serial outputs. 0=Each channel is output on its respective pin,
1=Both channels are multiplexed and output on AOUT. See also Table 2.
PACKED
1b
R/W
0
6
5
Controls when SFS goes active. 0=SFS pulses prior to the start of the I and the Q words.
1=SFS pulses only once prior to the start of each I/Q sample pair (i.e. the pair is treated as a
double-sized word) The I word precedes the Q word. See Figure 29.
FORMAT
2b
R/W
0
6
6:7
Determines output number format. 0=Truncate serial output to 8 bits. Parallel output is truncated to 32 bits. 1=Round both serial and parallel to 16 bits. All other bits are set to 0.
2=Round both serial and parallel to 24 bits. All other bits are set to 0. 3=Output floating point.
8-bit mantissa, 4-bit exponent. All other bits are set to 0.
Table 5
CLC5902 Control Registers
©1999 National Semiconductor Corporation
21
Rev. 3.05 May 27, 1999
Register Name
Width
Type
Defaulta
Addr
Bit
Description
FREQ_A
4B
R/W
0
7-10
7:0
Frequency word for channel A. Format is a 32-bit, 2’s complement number spread across 4
registers. The LSBs are in the lower registers. The NCO frequency F is F/FCK=FREQ_A/232.
PHASE_A
2B
R/W
0
11-12
7:0
Phase word for channel A. Format is a 16-bit, unsigned magnitude number spread across 2
registers. The LSBs are in the lower registers. The NCO phase PHI is PHI=2*pi*PHASE_A/
2^16.
FREQ_B
4B
R/W
0
13-16
7:0
Frequency word for channel B. Format is a 32-bit, 2’s complement number spread across 4
registers. The LSBs are in the lower registers. The NCO frequency F is F/FCK=FREQ_B/232.
PHASE_B
2B
R/W
0
17-18
7:0
Phase word for channel B. Format is a 16-bit, unsigned magnitude number spread across 2
registers. The LSBs are in the lower registers. The NCO phase PHI is PHI=2*pi*PHASE_B/
2^16.
A_SOURCE
2
R/W
0
19
1:0
0=Select AIN as channel input source. 1=Select BIN. 2=3=Select TEST_REG as channel
input source.
B_SOURCE
2
R/W
1
19
2:3
0=Select AIN as channel input source. 1=Select BIN. 2=3=Select TEST_REG as channel
input source.
EXP_INH
1b
R/W
0
20
0
0=Allow exponent to pass into FLOAT TO FIXED converter. 1=Force exponent in DDC channel to a 7 (maximum digital gain). This affects both channels.
AGC_FORCE
1b
R/W
1
20
1
0=Enable AGC counter operation. 1=AGC loop operates continuously regardless of
AGC_EN pin. This affects both channels.
AGC_RESET_EN
1b
R/W
0
20
2
0=Initial condition is never used. 1=Integrator is reset each time the AGC transitions from
idle to active. This affects both channels.
AGC_HOLD_IC
1b
R/W
0
20
3
0=Normal closed-loop operation. 1=Hold integrator at initial condition. This affects both
channels.
AGC_LOOP_GAIN
2b
R/W
0
20
4:5
Bit shift value for AGC loop. Valid range is from 0 to 3. This affects both channels.
AGC_COUNT
2B
R/W
0
21-22
7:0
Counter value for AGC enable counter. Format is a 16-bit, unsigned magnitude number
spread across 2 registers. The LSBs are in the lower register. The value represents the number of CK cycles over which the loop is active.
AGC_IC_A
1B
R/W
0
23
7:0
AGC integrator initial condition for channel A. Format is an 8-bit, unsigned magnitude number. This number is written into the magnitude MSBs of the channel A AGC integrator whenever it is reset to the initial condition.
AGC_IC_B
1B
R/W
0
24
7:0
AGC integrator initial condition for channel B. Format is an 8-bit, unsigned magnitude number. This number is written into the magnitude MSBs of the channel B AGC integrator whenever it is reset to the initial condition.
AGC_RB_A
1B
R
0
25
7:0
AGC integrator readback value for channel A. Format is an 8-bit, unsigned magnitude number. The user can read the magnitude MSBs of the channel A integrator from this register.
AGC_RB_B
1B
R
0
26
7:0
AGC integrator readback value for channel B. Format is an 8-bit, unsigned magnitude number. The user can read the magnitude MSBs of the channel B integrator from this register.
TEST_REG
14b
R/W
0
27(LSBs)
28(MSBs)
7:0
5:0
Test input source. Instead of processing values from the AIN/BIN pins, the value from this
location is used instead. Format is 14-bit 2s complement number spread across 2 registers.
Reserved
1B
-
-
29
7:0
For future use.
Reserved
1B
-
-
30
7:0
For future use.
DEBUG_EN
1b
R/W
0
31
0
0=Normal. 1=Enables access to the internal probe points.
DEBUG_TAP
5b
R/W
0
31
1:5
Selects internal node tap for debug.
0 selects F1 output for BI, 20 bits
1 selects F1 output for BQ, 20 bits
2 selects F1 output for AQ, 20 bits
3 selects F1 output for AI, 20 bits
4 selects F1 input for BI, 20 bits
5 selects F1 input for BQ, 20 bits
6 selects F1 input for AI, 20 bits
7 selects F1 input for AQ, 20 bits
8 selects NCO A, cosine output. 17 bits, 3 LSBs are 0.
9 selects NCO A, sine output, 17 bits, 3 LSBs are 0.
10 selects NCO B, cosine output, 17 bits, 3 LSBs are 0.
11 selects NCO B, sine output, 17 bits, 3 LSBs are 0.
12 selects NCO AI, rounded output, 15 bits, 5 LSBs are 0.
13 selects NCO AQ, rounded output, 15 bits, 5 LSBs are 0.
14 selects NCO BI, rounded output, 15 bits, 5 LSBs are 0.
15 selects NCO BQ, rounded output, 15 bits, 5 LSBs are 0.
16-31 selects AGC CIC filter output. 9 MSBs from ch A, next 9 bits from ch B, 2 LSBs are 0.
DITH_A
1b
R/W
1
31
6
0=Disable NCO dither source for channel A. 1=Enable.
DITH_B
1b
R/W
1
31
7
0=Disable NCO dither source for channel B. 1=Enable.
AGC_TABLE
32B
R/W
0
128-159
7:0
RAM space that defines key AGC loop parameters. Format is 32 separate 8-bit, 2’s complement numbers. This is common to both channels.
F1_COEFF
22B
R/W
0
160-181
7:0
Coefficients for F1. Format is 11 separate 16-bit, 2’s complement numbers, each one spread
across 2 registers. The LSBs are in the lower registers. For example, coefficient h0[7:0] is in
address 160, h0[15:8] is in address 161, h1[7:0] is in address 162, h1[15:8] is in address
163.
F2_COEFF
64B
R/W
0
182-245
7:0
Coefficients for F2. Format is 32 separate 16-bit, 2’s complement numbers, each one spread
across 2 registers. The LSBs are in the lower registers. For example, coefficient h0[7:0] is in
address 182, h0[15:8] is in address 183, h1[7:0] is in address 184, h1[15:8] is in address
185.
Table 5
CLC5902 Control Registers
a. These are the default values set by a master reset (MR). Sync in (SI) will not affect any of these values.
Rev. 3.05 May 27, 1999
22
©1999 National Semiconductor Corporation
Condensed Hexadecimal Address Map
Reg Nam e
DEC
D EC _BY_4
SCALE
G A IN 1 _ A
G A IN 1 _ B
RATE
S E R IA L _ C T R L
FR EQ _A
PH ASE_A
FR EQ _B
PH ASE_B
SOURCE
AG C _C TR L
AG C _C O U N T
A G C _ IC _ A
A G C _ IC _ B
AG C _R B_A
AG C _R B_A
TEST_R EG
DEBUG
AG C _TABLE
F1_C O EFF
F2_C O EFF
Addr
[
[
[
[
[
[
[
[
[
[
[$
[%
[&
['
[(
[)
[
[
[
[
[
[
[
[
[
[
[$
[%
[&
[)
[
[)
[$
[%
[%
[)
B it7
D ec7
B it6
D ec6
R a te 7
FM T1
FA7
FA15
FA23
FA31
PA7
PA15
FB7
FB15
FB23
FB31
PB7
PB15
R a te 6
FM T0
FA6
FA14
FA22
FA30
PA6
PA14
FB6
FB14
FB22
FB30
PB6
PB14
A g c C n t7
A g c C n t1 5
A g c Ic A 7
A g c Ic B 7
AgcR bA 7
AgcR bB 7
T e s t7
A g c C n t6
A g c C n t1 4
A g c Ic A 6
A g c Ic B 6
A gcR bA 6
A gcR bB 6
T e s t6
D IT H _ B
D IT H _ A
©1999 National Semiconductor Corporation
B it5
D ec5
S c a le 5
B it 4
D ec4
D e cB y4
S c a le 4
R a te 5
Packed
FA5
FA13
FA21
FA29
PA5
PA13
FB5
FB13
FB21
FB29
PB5
PB13
R a te 4
M uxM ode
FA4
FA12
FA20
FA28
PA4
PA12
FB4
FB12
FB20
FB28
PB4
PB12
AgcLG 1
A g c C n t5
A g c C n t1 3
A g c Ic A 5
A g c Ic B 5
AgcR bA5
AgcR bB5
T e s t5
T e s t1 3
T a p S e l4
AgcLG 0
A g c C n t4
A g c C n t1 2
A g c Ic A 4
A g c Ic B 4
AgcR bA4
AgcR bB4
T e s t4
T e s t1 2
T a p S e l3
B it 3
D ec3
B it 2
D ec2
D ec10
S c a le 3
S c a le 2
G 1A2
G 1B2
R a te 3
R a te 2
R D Y_PO L SFS_PO L
FA3
FA2
FA11
FA10
FA19
FA18
FA27
FA26
PA3
PA2
PA11
PA10
FB3
FB2
FB11
FB10
FB19
FB18
FB27
FB26
PB3
PB2
PB11
PB10
B S rc 1
B S rc 0
A g c H ld IC A g c R s t E n
A g c C n t3
A g c C n t2
A g c C n t1 1 A g c C n t 1 0
A g c Ic A 3
A g c Ic A 2
A g c Ic B 3
A g c Ic B 2
AgcR bA3 AgcR bA2
AgcR bB3 AgcR bB2
T e s t3
T e s t2
T e s t1 1
T e s t1 0
T a p S e l2
T a p S e l1
B it 1
D ec1
D ec9
S c a le 1
G 1A1
G 1B1
R a te 1
SCK_PO L
FA1
FA9
FA17
FA25
PA1
PA9
FB1
FB9
FB17
FB25
PB1
PB9
A S rc 1
A g c F o rce
A g c C n t1
A g c C n t9
A g c Ic A 1
A g c Ic B 1
AgcR bA1
AgcR bB1
T e s t1
T e s t9
T a p S e l0
B it 0
D ec0
D ec8
S c a le 0
G 1A0
G 1B0
R a te 0
SO U T_EN
FA0
FA8
FA16
FA24
PA0
PA8
FB0
FB8
FB16
FB24
PB0
PB8
A S rc 0
E x p In h
A g c C n t0
A g c C n t8
A g c Ic A 0
A g c Ic B 0
AgcR bA0
AgcR bB0
T e s t0
T e s t8
D ebugEn
T h e A g c T a b le lo a d s f r o m t h e lo w a d d r e s s to t h e h ig h a d d r e s s in t h is o r d e r :
1 s t lo c a t io n , 2 n d lo c a t io n …
T h e F I R C o e f f ic ie n t s lo a d f r o m t h e lo w a d d r e s s t o t h e h ig h a d d r e s s in t h is o r d e r
1 s t lo c a t io n lo w b y t e , 1 s t lo c a t io n h ig h b y t e , 2 n d lo c a t io n …
23
Rev. 3.05 May 27, 1999
The power detector bandwidth is set by the CIC filter to
FCK/8. The absolute value circuit doubles the effective
input frequency. This has the effect of reducing the power
detector bandwidth from FCK/8 to FCK/16.
AGC Theory of Operation
A block diagram of the AGC is shown in Figure 32. The
DVGA interface comprises four pins for each of the channels. The first three pins of this interface are a 3-bit binary
word that controls the DVGA gain in 6dB steps (AGAIN).
The final pin is ASTROBE which allows the AGAIN bits
to be latched into the DVGA’s register. A key feature of
the ASTROBE, illustrated Figure 33, is that it toggles
only if the data on AGAIN has changed from the previous
cycle. Not shown is that ASTROBE and BSTROBE are
independent. For example, ASTROBE should only toggle
when AGAIN has changed. BSTROBE should not toggle
because AGAIN has changed. This is done to minimize
unnecessary digital noise on the sensitive analog path
through the DVGA. ASTROBE and BSTROBE are
asserted during MR and SI to properly initialize the
DVGAs.
For a full-scale sinusoidal input, the absolute value circuit
output is a dc value of 511 ⋅ ( 2 ⁄ π ) . Because the absolute
value circuit also generates undesired even harmonic
terms, the CIC filter (response shown in Figure 34), is
required to remove these harmonics. The first response
null occurs at FCK/8, where FCK is the clock frequency,
and the response magnitude is at least 25dB below the dc
value from FCK/10 to 9FCK/10. Because the 2nd harmonic
from the absolute value circuit is about 10dB below the dc
this means that the ripple in the detected level is about
0.7dB or less for input frequencies between F CK /20 to
19FCK/20.
The “FIXED TO FLOAT CONVERTER” takes the fixed
point 9-bit output from the CIC filter and converts it to a
“floating point” number. This conversion is done so that
the 32 values in the RAM can be uniformly assigned (dB
The absolute value circuit and the 2-stage, decimate-by-8
CIC filter comprise the power detection part of the AGC.
AGC_TABLE
AGC_LOOP_GAIN
8
12
AGAIN
3
12
MUX
5
SHIFT DOWN
9
32X8
RAM
POUT
FIXED
TO FLOAT
CONVERTER
16
2 STAGE
DECIMATE BY 8
CIC FILTER
10
SHIFT DOWN
AIN[13:4]
ABSOLUTE
VALUE
EXP
AGC_IC_A
AGC_HOLD_IC
AGC_RESET_EN
AGC_FORCE
LOAD
ONE SHOT
AGC_EN
PERIOD
COUNTER
AGC_COUNT
16
FUNCTION PROGRAMMED
INTO RAM
LOG
EN
-REF
Figure 32
CLC5902 AGC circuit, Channel A
ASTROBE does not pulse because AGAIN[2:0] does not change
1 SCK delay
CK
CK/8
ASTROBE
AGAIN[2:0]
Figure 33
Timing diagram for AGC/DVGA interface, Channel A. Refer to Figure 8 for detailed timing information.
Rev. 3.05 May 27, 1999
24
©1999 National Semiconductor Corporation
As shown in Figure 32, the 32X8 RAM look-up table
implements the functions of log converter, reference subtraction, error amplifier, and deadband. The user must
build each of these functions by constructing a set of 8-bit,
2’s complement numbers to be loaded into the RAM. Each
of these functions and how to construct them are discussed
in the following paragraphs.
0
Magnitude (dB)
-10
-20
-30
A log conversion is done in order to keep the loop gain
independent of operating point. To see why this is beneficial, the control gain of the DVGA computed without log
conversion is,
-40
-50
′
-60
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
K DVGA =
1
Frequency Normalized to Sample Rate
Figure 34
= – v i ⋅ ln ( 2 ) ⋅ 2
Power detector filter response
scale) to detected power levels (54 db range). This provides a resolution of 1.7dB between detected power levels.
The truth table for this converter is given in Table 6. The
upper three bits of the output represent the exponent (e)
OUTPUT
(eeemm)
INPUT
0-3
000XX
4-7
001XX
8-15
010XX
16-31
011XX
32-63
100XX
64-127
101XX
128-255
110XX
256-511
111XX
Table 6
2
,
where G is the decimal equivalent of GAIN and G o
accounts for the DVGA gain in excess of unity. This equation assumes that the DVGA gain control polarity is positive as is the case for the CLC5526. The gain around the
entire loop must be negative. Observe in Equation 6 that
the control gain is dependent on operating point G. If we
instead compute the control gain with log conversion,
EQ. 7
which is no longer operating-point dependent. The log
function is constructed by computing the CIC filter output
associated with each address (Equation 5) and converting
these to dB. Full scale (dc signal) is 20 log ( 511 ) = 54dB .
EQ. 5
, E ≥ 1.
The max() and min() operators account for row 1 of Table
6 which is a special case because M=POUT. Equation 5
associates each address of the RAM with a CIC filter output.
©1999 National Semiconductor Corporation
EQ. 6
= – 6.02,
and the lower 2 are the mantissa (m). The exponent is
determined by the position of the leading ‘1’ out of the
CIC filter. An output of ‘001XX’ corresponds to a leading
‘1’ in bit 2 (LSB is bit 0). The exponent increases by one
each time the leading ‘1’ advances in bit position. The
mantissa bits are the two bits that follow the leading ‘1’. If
we define E as the decimal value of the exponent bits and
M as the decimal value of the mantissa bits, the output of
the CIC filter, POUT, corresponding to a given “FIXED TO
FLOAT CONVERTER” output is,
( max ( E, 1 ) – 1 )
( G – Go)
( G – Go)
K DVGA = ∂ [ 20 ⋅ log ( v i ⋅ 2
) ],
∂G
Fixed to Float Converter Truth Table
P OUT = [ 4 ⋅ min ( E, 1 ) + M ] ⋅
( G – Go)
∂
(v ⋅ 2
),
∂G i
25
The reference subtraction is constructed by subtracting the
desired loop servo point (in dB) from the table values
computed in the previous paragraph. For example, if it is
desired that the DVGA servo the ADC input level (sinusoidal signal) to -6dBFS, the number to subtract from the
data is
511 2
20 log  --------- ⋅ --- = 44dB .
 2 π
EQ. 8
The table data will then cross through zero at the address
corresponding to this reference level. A deadband wider
than 6dB should then be constructed symmetrically about
this point. This prevents the loop from hunting due to the
6dB gain steps of the DVGA. Any deadband in excess of
6dB appears as hysteresis in the servo point of the loop as
illustrated in Figure 31. The deadband is constructed by
loading zeros into those addresses on either side of the one
which corresponds to the reference level.
The last function of the RAM table is that of error amplification. All the operations preceding this one gave a table
slope S RAM = 1 . This must now be adjusted in order to
control the time constant of the loop given by,
Rev. 3.05 May 27, 1999
20
AGC RAM CONTENTS
AGC RAM CONTENTS
20
0
-20
-40
-60
-80
0
5
10
-40
-60
-80
15
20
25
-120
30
0
10
20
30
40
ADDRESS
POUT (dB)
(a)
(b)
50
60
Example of programmed RAM contents
8
1- + 1--- .
τ = ----------  -----F CK  G L 2
EQ. 9
The term GL in this equation is the loop gain,
G L = – 6.02 ⋅ S RAM ⋅ 2
( AGC_LOOP_GAIN – 4 )
.
EQ. 10
The design equations are obtained by solving Equation 9
for GL and Equation 10 for S RAM . AGC_LOOP_GAIN is
a control register value that determines the number of bits
to shift the output of the RAM down by. This allows some
of the loop gain to be moved out of the RAM so that the
full output range of the table is utilized but not exceeded.
The valid range for AGC_LOOP_GAIN is from 0 to 3
which corresponds to a 1 to 4 bit shift left.
An example set of numbers to implement a loop having a
reference of 6dB below full scale, a deadband of 8dB, and
a loop gain of 0.108 is:
AGC_RB_A (or AGC_RB_B) register. The top 3 bits
below the sign become AGAIN and are output along with
ASTROBE signal on the DVGA interface pins. The valid
range of AGAIN is from 0 to 7 which corresponds to a
valid range of 0 to 210-1 for the 11-bit, 2’s complement
integrator output from which AGAIN is derived. This is
illustrated in Figure 36. The integrator saturates at these
7
For this range to be
the same size as all
others, the max
integrator output must
be limited to 8x27-1
=210-1
6
5
AGAIN
Figure 35
-20
-100
-100
-120
0
4
3
2
-102 -102 -88 -80 -75 -70 -66
The min integrator
output must be
limited to 0 so that
the sign of AGAIN
is positive
1
-63 -61 -56 -53 -50
-47 -42 -39 -36 -33 -29 -25
0
0
-22 -19 -15 -11
0
0
0
0
0 13 17
2x27
3x27
4x27
5x27
6x27
7x27
8x27
Integrator Output
20
These values are shown plotted in Figure 35 with respect
to the table addresses in (a), and the CIC filter output
POUT in (b). For a 52MHz clock rate and
AGC_LOOP_GAIN=2, these values result in a loop time
constant of 1.5µs .
The error signal from the loop gain “SHIFT DOWN” circuit is gated into the loop integrator. The gate is controlled
by a timing and control circuit discussed in the next paragraph. A MUX within the integrator feedback allows the
integrator to be initialized to the value loaded into
AGC_IC_A (channel B can be set independently). The
conditions under which it is initialized are configured in
the registers associated with the timing and control circuit.
The top eight bits of the integrator output can also be read
back over the microprocessor interface from the
Rev. 3.05 May 27, 1999
1x27
0
26
Figure 36
AGC integrator output limits
limits to prevent overshoots as the integrator attempts to
enter the valid range. The AGAIN value is inverted (EXP)
and used to adjust the gain of the incoming signal to provide a linear output dynamic range. The relationship
between the DVGA analog gain (AGAIN) and the
“FIXED TO FLOAT CONVERTER” digital gain (EXP) is
shown in Table 7. The DVGA’s compression of the incoming signal in the analog domain vs. the subsequent expansion in the digital domain is shown in Figure 30.
Several control bits allow the user to configure a variety of
AGC algorithms. The AGC may free run by setting
AGC_FORCE high and AGC_HOLD_IC low. If a burst
start pulse is available and sent to the AGC_EN pin, the
©1999 National Semiconductor Corporation
AGAINa
EXPb
000 = -12dB
111 = +0dB
001 = -6dB
110 = -6dB
010 = +0dB
101 = -12dB -12dB
14 14 14 13 12 11
011 = +6dB
100 = -18dB -12dB
14 14 14 14 13 12 11
100 = +12dB
011 = -24dB -12dB
14 14 14 14 14 13 12 11
...
5
4
3
2
1
0
L
L
L
101 = +18dB
010 = -30dB -12dB
14 14 14 14 14 14 13 12 ...
6
5
4
3
2
1
0
L
L
110 = +24dB
001 = -36dB -12dB
14 14 14 14 14 14 14 13 ...
7
6
5
4
3
2
1
0
L
111 = +30dB
000 = -42dB -12dB
14 14 14 14 14 14 14 14 ...
8
7
6
5
4
3
2
1
0
Table 7
Inputc
21 20 19 18 17 16 15 14 ...
8
7
6
5
4
3
2
1
0
-12dB
14 13 12 11
-12dB
14 14 13 12 11
10 9
8
7
...
1
0
L
L
L
L
L
L
L
10 9
8
...
2
1
0
L
L
L
L
L
L
10 9
...
3
2
1
0
L
L
L
L
L
10 ...
4
3
2
1
0
L
L
L
L
15-bit Mixer Output Alignment into the 22-bit SHIFT-UP Based On EXP.
d
a. AGAIN sets the DVGA or analog gain value.
b. EXP sets the “FIXED TO FLOAT CONVERTER” or digital gain value.
c. 22-bit input to SHIFT-UP block in Figure 15 horizontally, linearized SHIFT-UP value vertically.
d. The numbers in the center of the table represent the mixer output bits. ‘L’ represents a logic low.
AGC may be configured to adapt the gain during the
power ramp sequence then hold it steady afterwards by
setting AGC_FORCE low, AGC_HOLD_IC low and programming AGC_HOLD_COUNT for the period of the
power ramp. In addition, one can provide an initial condition and set AGC_RESET_EN high to have the gain start
at a prescribed value at the beginning of each burst. The
AGC becomes active when the AGC_EN pin goes low
and remains active for AGC_HOLD_COUNT samples
after AGC_EN goes high. The AGC_HOLD_COUNT
can be programmed to one value during the random access
burst and a smaller value during a normal burst. Finally,
one might program a more narrow AGC loop bandwidth
during normal transmission. Just prior to the next burst
transmission from a mobile, set the initial condition to the
value read back from the AGC accumulator at the end of
the previous burst from that specific mobile. Allowing the
AGC to free run should be appropriate for most applications. If the INH_EXP bit is not set, the DVGA gain word
(EXP) is routed to the “FLOAT TO FIXED CONVERTER” in the DDCs prior to the programmable decimation filter. The EXP signals are delayed to account for
the propagation delay of the DVGA interface and the
CLC5956 ADC. The basic AGC modes are summarized in
Table 4.
©1999 National Semiconductor Corporation
27
Evaluation Hardware
Evaluation boards are available to facilitate designs based
on the CLC5902:
CLC-DRCS-PCASM
The Diversity Receiver Chipset evaluation board providing a complete narrowband receiver from IF to digital
symbols.
CLC-CAPT-PCASM
A simple method for capturing output data from CLC
ADCs and the CLC5902.
SOFTWARE
Control panel software for the CLC5902 supports complete device configuration on both evaluation boards.
Capture software manages the capture of data and its storage in a file on a PC.
Matlab script files support data analysis: FFT, DNL, and
INL plotting.
This software and additional application information is
available on the CLC Evaluation Kit CDROM.
Rev. 3.05 May 27, 1999
CLC5902
Dual Digital Tuner/AGC
Customer Design Applications Support
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Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018.
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Rev. 3.05 May 27, 1999