HI-1573, HI-1574 MIL-STD-1553 3.3V Monolithic Dual Transceivers June 2013 DESCRIPTION PIN CONFIGURATIONS The receiver section of the each bus converts the 1553 bus bi-phase differential data to complementary CMOS / TTL data suitable for input to a Manchester decoder. Each receiver has a separate enable input, which forces the receiver outputs to logic "0" (HI-1573) or logic “1” (HI1574). To minimize the package size for this function, the transmitter outputs are internally connected to the receiver inputs, so that only two pins are required for connection to each coupling transformer. For designs requiring independent access to transmitter and receiver 1553 signals, please contact your Holt Sales representative. FEATURES ! Compliant to MIL-STD-1553A and B, ARINC 708A ! 3.3V single supply operation ! Smallest footprint available in 7 mm x 7 mm N/C 1 RXENA 2 GNDA 3 GNDA 4 GNDA 5 VDDB 6 VDDB 7 BUSB 8 BUSB 9 BUSB 10 BUSB 11 33 N/C 32 N/C 31 TXINHA 30 RXA 29 RXA 28 N/C 27 N/C 26 TXB 25 TXB 24 TXINHB 23 N/C 1573PCI 1573PCT 1573PCM 1574PCI 1574PCT 1574PCM N/C 12 N/C 13 N/C 14 N/C 15 RXENB 16 GNDB 17 GNDB 18 GNDB 19 RXB 20 RXB 21 N/C 22 The transmitter section of each bus takes complementary CMOS / TTL Manchester II bi-phase data and converts it to differential voltages suitable for driving the bus isolation transformer. Separate transmitter inhibit control signals are provided for each transmitter. 44 N/C 43 BUSA 42 BUSA 41 BUSA 40 BUSA 39 VDDA 38 VDDA 37 TXA 36 TXA 35 N/C 34 N/C The HI-1573 and HI-1574 are low power CMOS dual transceivers designed to meet the requirements of the MIL-STD-1553 specification. 44 Pin Plastic 7mm x 7mm Chip-scale package (QFN) VDDA 1 BUSA 2 BUSA 3 RXENA 4 GNDA 5 VDDB 6 BUSB 7 BUSB 8 RXENB 9 GNDB 10 1573PSI 1573PST 1573PSM 1574PSI 1574PST 1574PSM 20 19 18 17 16 15 14 13 12 11 TXA TXA TXINHA RXA RXA TXB TXB TXINHB RXB RXB 20 Pin Plastic ESOIC - WB package VDDA 1 20 TXA 44- pin plastic chip-scale package (QFN) BUSA 2 19 TXA ! Less than 0.5W maximum power dissipation ! Available in DIP and small outline (ESOIC) BUSA 3 package options ! Industrial and extended temperature ranges ! Industry standard pin configurations RXENA 4 1573CDI 1573CDT 1573CDM BUSB 7 BUSB 8 17 RXA 16 RXA GNDA 5 VDDB 6 18 TXINHA 1574CDI 1574CDT 1574CDM 15 TXB 14 TXB 13 TXINHB RXENB 9 12 RXB GNDB 10 11 RXB 20 Pin Ceramic DIP package (DS1573 Rev. Q) HOLT INTEGRATED CIRCUITS www.holtic.com 06/13 HI-1573, HI-1574 PIN DESCRIPTIONS PIN (DIP & SOIC) 1 SYMBOL FUNCTION DESCRIPTION VDDA power supply +3.3 volt power for transceiver A 2 BUSA analog output MIL-STD-1533 bus driver A, positive signal 3 BUSA analog output MIL-STD-1553 bus driver A, negative signal 4 RXENA digital input 5 GNDA power supply Ground for transceiver A 6 VDDB power supply +3.3 volt power for transceiver B 7 BUSB analog output MIL-STD-1533 bus driver B, positive signal 8 BUSB analog output MIL-STD-1553 bus driver B, negative signal 9 RXENB digital input 10 GNDB power supply Receiver A enable. If low, forces RXA and RXA low (HI-1573) or High (HI-1574) Receiver B enable. If low, forces RXB and RXB low (HI-1573) or High (HI-1574) Ground for transceiver B 11 RXB digital output Receiver B output, inverted 12 RXB digital output Receiver B output, non-inverted 13 TXINHB digital input Transmit inhibit, bus B. If high BUSB, BUSB disabled 14 TXB digital input Transmitter B digital data input, non-inverted 15 TXB digital input Transmitter B digital data input, inverted 16 RXA digital output Receiver A output, inverted 17 RXA digital output Receiver A output, non-inverted 18 TXINHA digital input Transmit inhibit, bus A. If high BUSA, BUSA disabled 19 TXA digital input Transmitter A digital data input, non-inverted 20 TXA digital input Transmitter A digital data input, inverted FUNCTIONAL DESCRIPTION The HI-1573 family of data bus transceivers contains differential voltage source drivers and differential receivers. They are intended for applications using a MIL-STD-1553 A/B data bus. The device produces a trapezoidal output waveform during transmission. The receiver’s differential input stage drives a filter and threshold comparator that produces CMOS data at the RXA/B and RXA/B output pins. When the MIL-STD-1553 bus is idle and RXENA or RXENB are high, RXA/B will be logic “0” on HI-1573 and logic “1” on HI-1574. TRANSMITTER The receiver outputs are forced to the bus idle state (logic "0” on HI-1573 or logic “1” on HI-1574) when RXENA or RXENB is low. Data input to the device’s transmitter section is from the complementary CMOS inputs TXA/B and TXA/B. The transmitter accepts Manchester II bi-phase data and converts it to differential voltages on BUSA/B and BUSA/B. The transceiver outputs are either direct- or transformer-coupled to the MILSTD-1553 data bus. Both coupling methods produce a nominal voltage on the bus of 7.5 volts peak to peak. The transmitter is automatically inhibited and placed in the high impedance state when both TXA/B and TXA/B are driven with the same logic state. A logic “1” applied to the TXINHA/B input will force the transmitter to the high impedance state, regardless of the state of TXA/B and TXA/B. RECEIVER The receiver accepts bi-phase differential data from the MILSTD-1553 bus through the same direct- or transformercoupled interface as the transmitter. MIL-STD-1553 BUS INTERFACE A direct-coupled interface (see Figure 2) uses a 1:2.5 ratio isolation transformer and two 55 ohm isolation resistors between the transformer and the bus. The primary centertap of the isolation transformer must be connected to GND. In a transformer-coupled interface (see Figure 2), the transceiver is connected to a 1:1.79 isolation transformer which in turn is connected to a 1:1.4 coupling transformer. The transformer-coupled method also requires two coupling resistors equal to 75% of the bus characteristic impedence (Zo) between the coupling transformer and the bus. Figure 3 and Figure 4 show test circuits for measuring electrical characteristics of both direct- and transformercoupled interfaces respectively. (See electrical characteristics on the following pages). HOLT INTEGRATED CIRCUITS 2 HI-1573, HI-1574 Data Bus Each Bus TRANSMITTER Isolation Transformer Coupler Network BUSA/B TXA/B Transmit Logic Direct or Transformer Slope Control TXA/B BUSA/B TXINHA/B RECEIVER RXA/B Input Filter Receive Logic RXA/B Comparator RXENA/B Figure 1. Block Diagram TRANSMIT WAVEFORM - EXAMPLE PATTERN TXA/B TXA/B BUSA/B - BUSA/B Vin (Line to Line) tDR tDR tDR RXA/B (HI-1573) tRG tRG tRG tRG RXA/B (HI-1573) RXA/B (HI-1574) RXA/B (HI-1574) HOLT INTEGRATED CIRCUITS 3 tDR HI-1573, HI-1574 RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS Supply voltage (VDD) Supply Voltage -0.3 V to +5 V Logic input voltage range VDD....................................... 3.3V... ±5% -0.3 V dc to +3.6 V Receiver differential voltage 50 Vp-p Temperature Range Driver peak output current +1.0 A Power dissipation at 25°C ceramic DIL, derate 1.0 W 7mW/°C Industrial .......................-40°C to +85°C Extended.......................-55°C to +125°C Solder Reflow Temperature 260°C Junction Temperature 175°C Storage Temperature -65°C to +150°C NOTE: Stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device. These are stress ratings only. Operation at the limits is not recommended. DC ELECTRICAL CHARACTERISTICS VDD = 3.3 V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS 3.15 3.30 3.45 V Operating Voltage VDD Total Supply Current ICC1 Not Transmitting 4 10 mA ICC2 Transmit one bus @ 50% duty cycle 225 250 mA ICC3 Transmit one bus @ 100% duty cycle 425 500 mA 0.06 W 0.5 W Power Dissipation PD1 Not Transmitting PD2 Transmit one bus @ 100% duty cycle 0.3 Min. Input Voltage (HI) VIH Digital inputs Max. Input Voltage (LO) VIL Digital inputs Min. Input Current (HI) IIH Digital inputs Max. Input Current (LO) IIL Digital inputs -20 µA Min. Output Voltage (HI) VOH IOUT = -1.0mA, Digital outputs 90% VDD (LO) VIH IOUT = 1.0mA, Digital outputs Max. Output Voltage RECEIVER 70% VDD 30% VDD 20 µA 10% VDD (Measured at Point “AD“ in Figure 3 unless otherwise specified) Input resistance RIN Differential Input capacitance CIN Differential Common mode rejection ratio CMRR Input Level VIN Input common mode voltage Differential -5.0 Detect VTHD 1 Mhz Sine Wave Measured at Point “AD“ in Figure 3 RXA/B, RXA/B pulse width >70 ns No Detect VTHND No pulse at RXA/B, RXA/B Theshold Voltage - Transformer-coupled Kohm 5 40 VICM Threshold Voltage - Direct-coupled 20 Detect VTHD 1 MHz Sine Wave Measured at Point “AT“ in Figure 4 RXA/B, RXA/B pulse width >70 ns No Detect VTHND No pulse at RXA/B, RXA/B HOLT INTEGRATED CIRCUITS 4 pF dB 9 Vp-p 5.0 V-pk 1.15 Vp-p 0.28 0.86 Vp-p Vp-p 0.20 Vp-p HI-1573, HI-1574 DC ELECTRICAL CHARACTERISTICS (cont.) VDD = 3.3 V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETER TRANSMITTER SYMBOL CONDITION MIN TYP MAX UNITS 6.0 9.0 Vp-p 18.0 27.0 Vp-p 10.0 mVp-p -90 90 mV -250 250 mV (Measured at Point “AD” in Figure 3 unless otherwise specified) Output Voltage Direct coupled VOUT Transformer coupled VOUT Output Noise 35 ohm load (Measured at Point “AD“ in Figure 3) 70 ohm load (Measured at Point “AT“ in Figure 4) VON Output Dynamic Offset Voltage Direct coupled VDYN Transformer coupled VDYN Differential, inhibited 35 ohm load (Measured at Point “AD“ in Figure 3) 70 ohm load (Measured at Point “AT“ in Figure 4) Output resistance ROUT Differential, not transmitting Output Capacitance COUT 1 MHz sine wave 10 Kohm 15 pF AC ELECTRICAL CHARACTERISTICS VDD = 3.3 V, GND = 0V, TA =Operating Temperature Range (unless otherwise specified). PARAMETER RECEIVER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 500 ns (Measured at Point “AT” in Figure 4) Receiver Delay tDR From input zero crossing to RXA/B or RXA/B Note 3 Receiver gap time tRG Receiver Enable Delay tREN Spacing between RXA/B and RXA/B pulses 60 430 Note 1 Note 2 From RXENA/B rising or falling edge to ns 40 ns 150 ns ns RXA/B or RXA/B TRANSMITTER (Measured at Point “AD” in Figure 3) Driver Delay tDT TXA/B, TXA/B to BUSA/B, BUSA/B Rise time tr 35 ohm load 100 300 Fall Time tf 35 ohm load 100 300 ns tDI-H Inhibited output 100 ns tDI-L Active output 150 ns Inhibit Delay Note 1. Measured using a 1 MHz sinusoid, 20 V peak to peak, line to line at point “AT” (Guaranteed but not tested). Note 2. Measured using a 1 MHz sinusoid, 860 mV peak to peak, line to line at point “AT” (100% tested). Note 3. Measured using a 1 MHz sinusoid, 860 mV peak to peak, line to line at point “AT”. Measured from input zero crossing point. Isolation Transformer BUS A 55W BUS A 55W MIL-STD-1553 BUS A (Direct Coupled) Transceiver A 1:2.5 MIL-STD-1553 Stub Coupler Isolation Transformer BUS B 52.5W BUS B 52.5W Transceiver B 1:1.79 1:1.4 HI-1573 / HI-1574 Figure 2. Bus Connection Example using HI-1573 or HI-1574 HOLT INTEGRATED CIRCUITS 5 MIL-STD-1553 BUS B (Transformer Coupled) HI-1573, HI-1574 VDD Each Bus Isolation Transformer TXA/B TXA/B RXA/B MIL-STD-1553 Transceiver BUS A/B 55W BUS A/B 55W 35W RXA/B 1:2.5 Point “AD” HI-1573 / HI-1574 GND Figure 3. Direct Coupled Test Circuit VDD Each Bus Isolation Transformer TXA/B TXA/B RXA/B MIL-STD-1553 Transceiver RXA/B BUS A/B 70W BUS A/B 1:1.79 Point “AT” HI-1573 / HI-1574 GND Figure 4. Transformer Coupled Test Circuit HEAT SINK - ESOIC & CHIP-SCALE PACKAGE The heat sink is electrically isolated and may be soldered to any convenient power or ground plane. Both the HI-1573PSI/T/M and HI-1574PSI/T/M use a 20-pin thermally enhanced SOIC package. The HI-1573PCI/T/M and HI-1574PCI/T/M use a plastic chip-scale package (QFN). These packages include a metal heat sink located on the bottom surface of the device. This heat sink should be soldered down to the printed circuit board for optimum thermal dissipation. APPLICATIONS NOTE Holt Applications Note AN-500 provides circuit design notes regarding the use of Holt's family of MIL-STD-1553 transceivers. Layout considerations, as well as recommended interface and protection components are included. THERMAL CHARACTERISTICS PART NUMBER PACKAGE STYLE ØJA Heat sink unsoldered 54°C/W 52°C 112°C 152°C Heat sink soldered 47°C/W 49°C 109°C 149°C 20-pin Ceramic side-brazed DIP Socketed 62°C/W 56°C 116°C 156°C 44-pin Plastic chipscale package (QFN) Heat sink unsoldered 49°C/W 50°C 110°C 150°C HI-1573PSI / T / M 20-pin Thermally enhanced plastic SOIC (ESOIC) HI-1574PSI / T / M HI-1573CDI / T / M HI-1574CDI / T / M HI-1573PCI / T / M HI-1574PCI / T / M JUNCTION TEMPERATURE CONDITION TA=25°C TA=85°C TA=125°C Data taken at VDD=3.3V, continuous transmission at 1Mbit/s, single transmitter enabled. HOLT INTEGRATED CIRCUITS 6 HI-1573, HI-1574 ORDERING INFORMATION HI - 157x xx x x (Plastic) PART NUMBER Blank F PART NUMBER PACKAGE DESCRIPTION Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free RoHS compliant) TEMPERATURE RANGE FLOW BURN IN I -40°C TO +85°C I No T -55°C TO +125°C T No M -55°C TO +125°C M Yes PART NUMBER PACKAGE DESCRIPTION PC 44 PIN PLASTIC CHIP-SCALE PACKAGE QFN (44PCS) PS 20 PIN PLASTIC ESOIC, Thermally Enhanced Wide SOIC w/Heat Sink (20HWE) PART NUMBER RXENA = 0 RXA RXA RXENB = 0 RXB RXB 1573 0 0 0 0 1574 1 1 1 1 HI - 157xCD x (Ceramic) PART NUMBER TEMPERATURE RANGE FLOW BURN IN I -40°C TO +85°C I No Gold (Pb-free, RoHS compliant) T -55°C TO +125°C T No Gold (Pb-free, RoHS compliant) M -55°C TO +125°C M Yes Tin / Lead (Sn / Pb) Solder PART NUMBER RXENA = 0 RXA RXA RXENB = 0 RXB RXB LEAD FINISH PACKAGE DESCRIPTION 1573 0 0 0 0 20 PIN CERAMIC SIDE BRAZED DIP (20C) 1574 1 1 1 1 20 PIN CERAMIC SIDE BRAZED DIP (20C) HOLT INTEGRATED CIRCUITS 7 HI-1573, HI-1574 RECOMMENDED TRANSFORMERS The HI-1573 and HI-1574 transceivers have been characterized for compliance with the electrical requirements of MIL-STD-1553 when used with the following transformers. Holt recommends the Premier Magnetics parts as offering the best combination of electrical performance, low cost and small footprint. MANUFACTURER PART NUMBER APPLICATION TURNS RATIO(S) DIMENSIONS Premier Magnetics PM-DB2725EX Isolation Dual tapped 1:1.79, 1:2.5 0.4 x 0.4 x 0.242 inches Premier Magnetics PM-DB2702 Stub coupling 1:1.4 .625 x .625 x .250 inches Premier Magnetics PM-DB-2791S Isolation 1:2.5 0.4 x 0.4 x 0.185 inches Premier Magnetics PM-DB-2795S Isolation 1:1.79 0.4 x 0.4 x 0.185 inches Premier Magnetics PM-DB-2798S Isolation Dual tapped 1:1.79, 1:2.5 0.4 x 0.4 x 0.185 inches Premier Magnetics PM-DB-2762 Isolation Dual ratio 1:2.5 0.4 x 0.4 x 0.320 inches Premier Magnetics PM-DB-2766 Isolation Dual ratio 1:1.79 0.4 x 0.4 x 0.320 inches HOLT INTEGRATED CIRCUITS 8 HI-1573, HI-1574 REVISION HISTORY Document Rev. Date Description of Change DS1573 Clarification of transmitter and receiver functions in Description, clarification of available temperature ranges, and corrected a dimension in Recommended Transformers table. Add ‘M’ Flow option to chip-scale package (QFN). Clarify nomenclature of chip-scale package as QFN. Correct typographical errors in package dimensions. Clarified status of RXA/B and RXA/B pins in bus idle state when RXENA or RXENB are high (logic “1”). Fix typos in tRG and tDT descriptions in AC characteristics table. Added latest Premier Magnetics transformer recommendations. Remove Technotrol transformer recommendations. Updated functional description text for clarity. Revised figures 2,3, and 4. Updated package drawings. L 09/26/08 M 04/13/09 N O 07/24/09 10/13/09 P 01/26/12 Q 06/20/13 HOLT INTEGRATED CIRCUITS 9 PACKAGE DIMENSIONS 20-PIN PLASTIC SMALL OUTLINE (ESOIC) - WB (Wide Body, Thermally Enhanced) inches (millimeters) Package Type: 20HWE .008 ± .005 (.215 ± .115) .295 ± .015 (7.495 ± .385) .504 BSC (12.80) .407 BSC (10.33) Bottom View .210 ± .015 (5.335 ± .385) .295 BSC (7.50) Top View See Detail A .016 ± .004 (.419 ± .109) Electrically isolated heat sink pad on bottom of package .086 ± .005 (2.181 ± .131) .050 BSC (1.27) 0° to 8° .008 ± .004 (.200 ± .100) .033 ± .017 (.835 ± .435) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) Connect to any ground or power plane for optimum thermal dissipation Detail A 20-PIN CERAMIC SIDE-BRAZED DIP inches (millimeters) Package Type: 20C 1.000 ±.010 (25.400 ±.254) .310 ±.010 (7.874 ±.254) .050 TYP. (1.270 TYP.) .125 min (3.175) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) .300 ± .010 (7.620 ± .254) .085 ±.009 (2.159 ± .229) .200 max (5.080) .100 BSC (2.54) .017 ±.002 (.432 ±.051) HOLT INTEGRATED CIRCUITS 10 .010 + 0. 02/-.001 (.254 ±.051/-.025) PACKAGE DIMENSIONS 44-PIN PLASTIC CHIP-SCALE PACKAGE (QFN) inches (millimeters) Package Type: 44PCS .276 BSC (7.00) .216 ± .002 (5.50 ± .05) .020 BSC (0.50) .276 BSC (7.00) .216 ± .002 (5.50 ± .05) Top View Bottom View .010 (0.25) typ .039 max (1.00) .008 typ (0.2) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) Electrically isolated heat sink pad on bottom of package Connect to any ground or power plane for optimum thermal dissipation HOLT INTEGRATED CIRCUITS 11 .016 ± .002 (0.40 ± .05)