HOLTIC HI

HI-6110
MIL-STD-1553 / MIL-STD-1760
BC / RT / MT Message Processor
May 2010
FEATURES
The HI-6110 may be configured as a Bus Controller (BC), a
Remote Terminal (RT), a Monitor Terminal (MT), or a Monitor
Terminal with assigned RT address. 16-bit registers store
incoming and outgoing Command, Status and Data words.
Using two 32-word data FIFOs, the HI-6110 can store the
maximum number of 1553 words occurring in any message.
For messages with transmitted data words, data may be
written in advance or on-the-fly. Received data can be
retrieved on-the-fly or all at once after the Valid Message flag
is asserted.
BC message sequences are initiated by a rising edge on the
BCSTART input, or a 0 to 1 transition at the BCSTART bit in
the Control Register. All RT command responses are
automatically initiated after a valid Command Word is
received.
A single encoder services both buses, each of which have a
dedicated analog transformer driver. Each driver dissipates
less than 200 mW of on-chip power at 100% duty cycle.
Each bus receiver has a dedicated Manchester decoder. In
BC mode, a RCV signal indicates when valid 1553 words are
received. In RT/MT modes, RCV indicates a valid command
received, while the 1553 command decoder updates a
Message register so the external controller can identify
command type and respond appropriately. Guaranteed by
design, the HI-6110 cannot generate messages exceeding
660uS, the duration of a Command or Status Word plus 32
contiguous data words.
The external host controller reads and writes a simplified
register structure in the HI-6110 over a 16-bit parallel bus.
The system designer has flexibility over many aspects of
configuration. Control and status monitoring can be done in
hardware (by reading/writing control pins) or in software (by
reading/writing register bits).
((DS6110 Rev. R)
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Monolithic CMOS Technology
3.3V operation
Exceptionally low power
On-chip message buffering
Selectable master clock frequency
Dual differential 1553 bus transceivers
Bus Controller / Remote Terminal /
Monitor Terminal operating modes
• Compliant to MIL-STD-1553B Notice 2
and MIL-STD-1760 Stores Management
APPLICATIONS
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MIL-STD-1553 Terminals
Flight Control and Monitoring
ECCM Interfaces
Stores Management
Test Equipment
Sensor Interfaces
Instrumentation
PIN CONFIGURATION (Top View)
52 - STR
51 - VDDLOG
50 - RTAP
49 - RTA4
48 - RTA3
47 - RTA2
46 - RTA1
45 - RTA0
44 - RTMODE
43 - BCMODE
42 - RCVA
41 - TXINHA
40 - BUSA
The HI-6110 is a CMOS integrated circuit implementing the
MIL-STD-1553 (1553) data communications protocol
between a host processor and a dual redundant 1553 data
bus. The single chip architecture has a digital section
containing all necessary logic and memory to process and
store the command and data words for one complete 1553
message. The analog section includes dual transceivers
coupled to the 1553 buses through external current mode
transformers. The device is available in an industry standard
64-pin 9 mm square QFN package, making it the smallest
dual redundant 1553 interface product on the market.
R/W - 1
CS - 2
D0 - 3
D1 - 4
D2 - 5
D3 - 6
D4 - 7
D5 - 8
D6 - 9
D7 - 10
D8 - 11
D9 - 12
D10 - 13
HI-6110PQI
&
HI-6110PQT
39 - VDDA
38 - BUSA
37 - BUSB
36 - VDDB
35 - BUSB
34 - TXINHB
33 - RCVB
32 - FFEMPTY
31 - RF0 / RCMDA
30 - RF1 / RCMDB
29 - RFLAG
28 - VALMESS
27 - ERROR
D11 - 14
D12 - 15
D13 - 16
D14 - 17
D15 - 18
RA2 - 19
RA1 - 20
RA0 - 21
BCSTART - 22
RA3 - 23
CLK - 24
GND - 25
MR - 26
GENERAL DESCRIPTION
52 Pin Plastic Quad Flat Pack (PQFP)
See page 35 for 64-Pin QFN Pin Configuration
HOLT INTEGRATED CIRCUITS
www.holtic.com
05/10
HI-6110
PIN DESCRIPTIONS
SIGNAL
FUNCTION
STR
R/W
CS
D0 - D15
RA0 - RA3
INPUT
INPUT
INPUT
I/O
INPUTS
BCSTART
INPUT
CLK
GND
MR
INPUT
POWER
INPUT
ERROR
OUTPUT
VALMESS
OUTPUT
FFEMPTY
OUTPUT
RFLAG
OUTPUT
RF0 /
RCMDA
OUTPUT
RF1 /
RCMDB
OUTPUT
RCVA
RCVB
OUTPUTS
TXINHA
TXINHB
BUSA, BUSA
BUSB, BUSB
BCMODE
INPUT
INPUT
XFMR
RTMODE
INPUT
INPUT
RTA0-RTA4
INPUTS
RTAP
INPUT
VDDLOG
POWER
VDDA, VDDB POWER
DESCRIPTION
During I/O operations, data is latched on rising edge. (Internal 12KW pull-up)
Device register access, READ = 1, WRITE = 0. (Internal 12KW pull-up)
Chip Select for register reads and writes, active low. (Internal 12KW pull-down)
Data bus signals. (Internal 12KW pull-down per signal)
Register access address, inputs are ORed with corresponding Control register bits.
(Internal 12KW pull-down per signal)
Message starts on rising edge when in BC mode. Input is ORed with a corresponding
Control register bit, where a 0 to 1 transition will also trigger message start. (This input
has an Internal 12KW pull-down.)
System Clock. (Internal 12KW pull-down)
Power supply Ground, 0V.
Master Reset, active high. Clears all data FIFOs and all registers except the Control,
Transmit Status Word and Transmit Mode Data Word registers. This input is ORed
with a corresponding Control register bit. (Internal 12KW pull-down)
ERROR goes high when a message error is detected.
In BC mode, ERROR resets when BCSTART is asserted to begin the next message.
For RT and MT modes, ERROR resets automatically after 3 to 4uS.
This output signal mirrors a corresponding Status register bit.
Goes high at the end of a valid message sequence. This output signal mirrors a
corresponding Status register bit.
When low, data is available in the receive data FIFO for the active bus. This output
signal mirrors a corresponding Status register bit.
This pin goes low each time the decoder detects a valid 1553 word on the active data
bus, set by Control Register bits 5:4. Falling edges occur for command words, status
words and mode command data words, but not for data words associated with
subaddress commands. Signal is not asserted for words on the inactive bus, or for
words transmitted by the device itself, e.g., no assertion for command words when in
BC mode. Use falling edge-triggered logic only; Falling edge typically occurs 3us after
the detected word's mid-parity. This output mirrors a corresponding Status register bit.
RF0 function: If “1” when reading Bus A Word register, the stored word had data sync.
RCMDA function: In RT or MT mode, pin goes high when a valid receive command
was decoded on Bus A. This output mirrors a corresponding Status register bit.
RF1 function: If “1” when reading Bus B Word register, the stored word had data sync.
RCMDA function: In RT or MT mode, pin goes high when a valid receive command
was decoded on Bus B. This output mirrors a corresponding Status register bit.
Receive A and Receive B flags: In BC mode, these signals go high when any valid
word is received on Bus A or Bus B.
In RT or MT mode, these signals go high when a valid command is received on Bus A
or Bus B. For valid RT-to-RT only, RCV goes high after command word pair. These
output signals mirror two corresponding Status register bits.
Logic one disables the Bus A transmitter. (Internal 12KW pull-up)
Logic one disables the Bus B transmitter. (Internal 12KW pull-up)
Positive and negative polarity of 1553 signals for Buses A and B. These signal pairs
connect the analog transceivers to the external transformer.
Selects operating mode. This input signal is ORed with a corresponding
Control register bit. (Internal 12KW pull-up)
Selects operating mode. This input signal is ORed with a corresponding
Control register bit. (Internal 12KW pull-down)
Remote Terminal address inputs, for RT mode. (Internal 12KW pull-up per signal)
This input sets Remote Terminal address parity, odd. (Internal 12KW pull-down)
+3.3VDC ±5% power supply input for internal logic
+3.3VDC ±5% power supply inputs for Bus A and Bus B transceivers
HOLT INTEGRATED CIRCUITS
2
HI-6110
FUNCTIONAL DESCRIPTION
HOST INTERFACE
The Holt HI-6110 provides a simple interface between a host
subsystem and a MIL-STD-1553 dual redundant data bus.
Messages are processed one at a time. The HI-6110 automatically
handles message formatting, error checking, message data
buffering, protocol checking and default responses. The host may
override default message responses by updating registers on-thefly.
The host communicates with the HI-6110 using a 16-bit
bidirectional data bus. On-chip bus transceivers allow the device to
be connected to the MIL-STD-1553 data buses using external
coupling transformers.
The HI-6110 can be configured as 1553 Bus Controller (BC),
Remote Terminal (RT) or Bus Monitor (MT). The BCMODE and
RTMODE inputs define the mode of operation as follows:
BCMODE RTMODE 1553 OPERATING MODE
1
0
Bus Controller (BC)
0
1
Remote Terminal (RT)
1
1
Bus Monitor (no assigned RT address)
0
0
Bus Monitor with assigned RT address
The HI-6110 is further configured by setting various configuration
bits in the on-chip Control Register. Different sets of 16-bit registers
and message data FIFOs are available depending upon the mode
of operation (BC, RT or MT). The STR pin is used as the timing
signal for data read and write cycles. Data is output on the 16-bit
bidirectional data bus, D15-D0, when R/W is high and STR is low.
D15-D0 are inputs when R/W is low, and data is written into internal
registers on the rising edge of the STR signal. The Chip Select input
CS must be low for all register read / write operations:
CS R/W STR
1
X
X
0
X
1
0
1
0
0
0
0
D15-D0
High impedance
High impedance
Output
Input
OPERATION
No operation
No operation
Read
Write (on STR rising edge)
Four Register address inputs (RA3, RA2, RA1, RA0) are used to
select internal registers during host read or write operations. Note
that internal registers may be write-only, read-only or read/write.
The register address map is different for BC, RT and MT modes as
not all registers are used in each mode. Table 1 defines the HI-6110
address map in detail.
Table 1. HI-6110 Internal Register Address Map
ADDRESS
RA3:0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 1 0 0
ADDRESS
RA3:0
X 0 0 0
X 0 0 1
X 0 1 0
X 0 1 1
X 1 X X
REGISTER READ (R/W=1)
MODE
BC
RT or MT with assigned RT address
STATUS WORD 1 ( if RT-RT, Receive RT ) COMMAND WORD 1
STATUS WORD 2 only RT-RT Transmit RT COMMAND WORD 2 (from last RT-RT)
RECEIVED MODE DATA WORD
RECEIVED STATUS WORD (from last RT-RT)
RECEIVED DATA FIFO
RECEIVED DATA FIFO
STATUS REGISTER
STATUS REGISTER
MESSAGE REGISTER
ERROR REGISTER
ERROR REGISTER
BUS A WORD
BUS A WORD
BUS B WORD
BUS B WORD
CONTROL REGISTER
CONTROL REGISTER
BC
COMMAND WORD 1
COMMAND WORD 2 ( used for RT-RT only)
TRANSMIT DATA FIFO
CONTROL REGISTER
REGISTER WRITE (R/W=0)
MODE
RT or MT with assigned RT address
TRANSMIT STATUS WORD
TRANSMIT MODE DATA WORD
RESET TRANSMIT DATA FIFO
TRANSMIT DATA FIFO
CONTROL REGISTER
MT without assigned RT address
COMMAND WORD 1
COMMAND WORD 2 from last RT-RT
BC-transmitted MODE DATA WORD
Transmit RT STATUS WORD from last RT-RT
DATA FIFO, incl. RT-transmitted mode data
STATUS REGISTER
MESSAGE REGISTER
ERROR REGISTER
STATUS WORD (from receiving RT, if RT-RT)
BUS A WORD
BUS B WORD
CONTROL REGISTER
MT without assigned RT address
CONTROL REGISTER
Table 2. MIL-STD-1553 Word Type Decoding
SIGNAL
RF1 RF0
0 0
0 1
1 0
SIGNALS RF1 AND RF0 IDENTIFY LAST RECEIVED 1553 WORD TYPE
MODE
BC
RT or MT with assigned RT address
MT without assigned RT address
pulses low if STATUS WORD 2
Valid Receive Command Bus A
Valid Receive Command Bus A
Valid Receive Command Bus B
Valid Receive Command Bus B
While reading the BUS A WORD or BUS B WORD registers, sync type for the stored word can be determined from the RF0 and RF1 outputs.
While the /STR input is held low, output RF1 = 1 if the stored Bus Word had Command Sync, or output RF0 = 1 if the stored Bus Word had Data Sync.
HOLT INTEGRATED CIRCUITS
3
HI-6110 (BUS CONTROLLER MODE)
INITIALIZATION
BUS CONTROLLER
In Bus Controller mode, the user must first perform a Master Reset
to initialize the BC protocol engine and clear all message registers
and data FIFOs. This may be achieved by pulsing the MR input
high, or writing a "1" to Control Register bit 0. The user must select a
master clock (CLK) frequency by programming Control Register
bits 11 and 12, and the Response Time Out must be programmed
per Control Register bit 14. Refer to the BC Register Formats
section for a full description of available registers and their
functions in Bus Controller Mode.
The HI-6110 is configured for Bus Controller operation by setting
the BCMODE input high and the RTMODE input low. Alternatively,
Control Register bits 3:2 (RTMODE:BCMODE) may be
programmed to 0:1. Control Register bits 3:2 are logically ORed
with the input pins with the same signal name.
Figure 1. shows a block diagram of the HI-6110 in Bus Controller
mode
Command Word 1
Command Word 2
Parallel
to
Serial
TX
DATA
FIFO
Manchester
Encoder
TXINHA
BUSA
Serial
to
Parallel
Bus A
Manchester
Decoder
BUSA
Transceiver
Bus A Word
D15-D0
CS
R/W
STR
RA2-RA0
FFEMPTY
Host
Data
Interface
Status Word 1
Status Word 2
Mux
RX
DATA
FIFO
TXINHB
Bus B Word
Serial
to
Parallel
BUSB
Bus B
Manchester
Decoder
BUSB
Transceiver
VALMESS
ERROR
RFLAG
RCVA
RCVB
RF0
RF1
CLK
MR
BCSTART
BCMODE
RTMODE
Status Register
Message
Status
Control Register
BC Error Register
Protocol
Control
BC Protocol Engine
Figure 1. Block Diagram - Bus Controller Mode
HOLT INTEGRATED CIRCUITS
4
HI-6110 (BUS CONTROLLER MODE)
REGISTER FORMATS (BC Mode)
NAME
REPTO
13
12
CLKSEL
11
10 - 7
Reserved
RA3:0
6
5-4
TRB, TRA
3-2
RTMODE,
BCMODE
1
BCSTART
0
MR
A
RT
M
BC O D
M E
BC O D
S E
M TA
R RT
5
4
X
MSB 15 14 13 12 11 10 9
BIT
15
14
TR
0
X
X
TR
N
B
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LK d
R SE
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R rve
A3 d
R
A2
R
A1
R
A0
CONTROL REGISTER (R/W) Write Address: X1XX, Read Address: 1100
8
7
6
0
1
3
2
1
0
LSB
FUNCTION
Not used in BC mode
Controls the time-out which causes the No Response Error.
0
17 usec Gap (equivalent to 57 usec for 5.2.1.7 of the RT Validation Test Plan)
1
131 usec Gap
Not used in BC mode
Selects the frequency of the HI-6110 external CLK input, as follows:
CLKSEL
Value
0
24 MHz
1
12 MHz
This bit must be written to “0”.
Register Address for HI-6110 register and data read and write operations. The register address is defined by
the logical OR of these bits and their corresponding input pins. Writting Control Register bits 10:7 to 0000 is
necessary if the RA0 - RA3 input pins are used for HI-6110 register addressing.
Not used in BC mode
Setting either TRA or TRB to "1" enables transmit on MIL-STD-1553 BUS A or BUS B. Setting both TRA and
TRB selects neither bus. The BC protocol engine connects to the selected, active bus. The 1553 receiver,
Manchester decoder and RCV output signal are still operational on the inactive bus. Valid words received on the
inactive bus can be read without changing active bus by reading the Bus A Word or Bus B Word register.
NOTE: The TXINHA and TXINHB input pins can override bus enablement.
HI-6110 mode select bits. These Control Register bits are logically OR'ed with their corresponding input pins,
allowing the user to select 1553 operating mode under either hardware or software control:
RTMODE BCMODE
1553 OPERATING MODE
0
0
Bus Monitor (MT), with assigned RT address
0
1
Bus Controller (BC)
1
0
Remote Terminal (RT)
1
1
Bus Monitor (MT), without assigned RT address
If initially reset, writing a "1" to this bit initiates a BC message sequence. This bit should be reset before next
message.
Master Reset. Writing "1" and then “0” to this bit performs the same function as pulsing the MR pin. All register
and data FIFOs are cleared when master reset is asserted. The Control Register is the exception; it is not
affected by Master Reset.
TRANSMIT DATA FIFO (Write only) Write Address: X010
MIL-STD-1553 Message Data Word 15:0
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
MSB
LSB
RECEIVE DATA FIFO (Read only) Read Address: 0100
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
The Transmit Data FIFO is 32-words deep and holds MILSTD-1553 message data. The FIFO is cleared on Master
Reset.
Message data to be transmitted by the BC may be loaded into
the TRANSMIT DATA FIFO by the host prior to BCSTART.
Any data word must be loaded before mid-parity bit for the
1553 word it follows. Words are transmitted in the order they
are loaded.
The Receive Data FIFO is 32-words deep and holds MILSTD-1553 message data. The FIFO is cleared by Master
Reset or when BCSTART occurs.
MIL-STD-1553 Message Data Word 15:0
MSB
The Control Register settings determine HI-6110 operating
mode, clock frequency and the bus enabled for transmit. It can
also be used to address registers for read/write operations, to
assert master reset, and to initiate MIL-STD-1553 message
sequences.
0
LSB
All MIL-STD-1553 data words received by the BC are stored in
the Receive DATA FIFO. A low FFEMPTY flag (output pin or
Status register bit) means message data is available to be
read by the host. Successive data reads cause FFEMPTY to
go high when the last word is read.
HOLT INTEGRATED CIRCUITS
5
HI-6110 (BUS CONTROLLER MODE)
BC OPERATION
RT Address
T/
R
COMMAND WORD 1 REGISTER (Write only) Write Address: X000
MSB 15 14 13 12 11 10 9
Subaddress /
Mode
8
7
Data Word Count /
Mode Code
6
5
4
3
2
1
0
LSB
The Command Word 1 register is loaded by the host with the
MIL-STD-1553 Command Word to be issued by the Bus
Controller. Bit 10 should be set for Transmit, reset for Receive.
For RT to RT commands, Command Word 1 register holds the
receive command word and Command Word 2 register holds
the transmit command word.
RT Address
T/
R
COMMAND WORD 2 REGISTER (Write only) Write Address: X001
Subaddress /
Mode
Used only for RT-to-RT commands, the Command Word 2
register is loaded by the host with the MIL-STD-1553 transmit
Command Word addressed to the transmitting Remote
Terminal. The Command Word 1 register is loaded with the
receive Command Word addressed to the receiving Remote
Terminal.
Data Word Count /
Mode Code
1
MSB 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
LSB
If the next Message is not an RT-to-RT transfer, it is necessary
to write the Transmit/Receive bit 10 to “0”.
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STATUS WORD 1 REGISTER (Read only) Read Address: 0000
The Status Word 1 register holds the returned MIL-STD-1553
Status Word received from an RT responding to a BC issued
command.
M
RT Address
MSB 15 14 13 12 11 10 9
8
R
R
R
7
6
5
4
3
2
1
0
LSB
For RT to RT commands, the Status Word 1 register captures
the status word returned by the receiving remote terminal,
while the Status Word 2 register captures the status word
returned by the transmitting remote terminal
Used only for RT to RT commands, the Status Word 2 register
captures the MIL-STD-1553 status word returned by the
transmitting remote terminal.
M
RT Address
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STATUS WORD 2 REGISTER (Read only) Read Address: 0001
MSB 15 14 13 12 11 10 9
8
R
R
R
7
6
5
4
3
2
1
0
LSB
BUS A WORD REGISTER (Read only) Read Address: 1001
BUS B WORD REGISTER (Read only) Read Address: 1010
In BC mode, the Bus A Word register holds the last valid MILSTD-1553 word received on Bus A. The Bus B Word register
holds the last valid MIL-STD-1553 word received on Bus B.
Bus A/B Word 15:0
MSB 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
LSB
While /STROBE is low to read a Bus Word register, the sync
type associated with the stored word can be determined from
the RF0 and RF1 pins. The RF1 signal is high for Command
Sync, the RF0 signal is high for Data Sync.
HOLT INTEGRATED CIRCUITS
6
HI-6110 (BUS CONTROLLER MODE)
BC OPERATION
ER
R
VA OR
LM
N E
ot S
U S
N se
ot d
U
R se
FL d
FF AG
E N
R MP
C T
V Y
R B
C
V
ID A
LE
STATUS REGISTER (Read only) Read Address: 0101
Not Used
0
0
MSB 15 14 13 12 11 10
0
0
0
0
0
9
BIT
15- 9
8
NAME
ERROR
7
VALMESS
5-6
4
3
RFLAGN
FFEMPTY
2
1
0
RCVB
RCVA
IDLE
8
7
0
0
6
5
4
3
2
1
0
LSB
The Status Register may be interrogated by the host at any
time. It provides information that allows the user to determine
whether the HI-6110 is busy executing a MIL-STD-1553
message and its progress. After a message sequence has
completed, the Status register indicates whether an error was
detected or if the message sequence was successful.
FUNCTION
Not used. These bits are set to "0".
This bit is "0" after Master Reset or if the last MIL-STD-1553 message sequence was valid. ERROR is set
to a "1" if the last sequence had an error. The nature of the message error can be determined by examining
the Error Register. The ERROR output pin reflects the state of this bit.
This bit is a "0" after reset or the last MIL-STD-1553 message containing an error. VALMESS goes high on
the completion of an error-free MIL-STD-1553 message sequence. VALMESS is reset to a zero at the start
of each new BC message. The VALMESS output pin reflects the state of this bit.
Not used.
This bit goes low any time a Status Word is received
If "0" then the receive Data FIFO contains at least one word of data. This bit is set to a "1" on reset, or when a
new BC command sequence is initiated, or when the user has read all available received data words from
the receiver Data FIFO. The FFEMPTY output pin reflects the state of this bit.
Set to a "1" if the Bus B Word register holds a valid MIL-STD-1553 word.
Set to a "1" if the Bus A Word register holds a valid MIL-STD-1553 word.
If "1" then the Bus Controller is idle. This bit is a zero throughout the time a MIL-STD-1553 message is in
progress. The bit returns to a "1" when the message is completed.
O
SW ER
1 R
SW ER
2 R
FF ER
E R
N RR
ot
U
C se
O d
N
N ER
ot R
U
C se
SY d
D CE
SY R
R
M CE
AN R
R
N ER
O R
R
C
V
ERROR REGISTER (Read only) Read Address: 0111
PR
Not Used
0
0
0
0
0
MSB 15 14 13 12 11 10 9
BIT
15 - 11
10
9
NAME
PROERR
SW1ERR
8
7
6
5
4
3
2
1
0
SW2ERR
FFERR
CONERR
CSYCERR
DSYCERR
MANERR
NORCV
0
0
8
7
6
5
4
3
2
1
0
LSB
The BC Error Register is cleared at reset and at the beginning
of each MIL-STD-1553 message sequence. If an error is
encountered during message execution, the ERROR pin goes
high, the ERROR bit is set in the Status Register, and one or
more bits are set in the Error Register. After the error condition
is flagged, the Error Register should be interrogated before
the receipt of the next Manchester Word.
FUNCTION
Not used. These bits are set to "0".
Protocol Error: Extraneous word detected on the bus during a message sequence.
Status Word 1 Error: In an RT-RT sequence. the receiving RT Status Word has the wrong RT address.
For RT to RT transfers, SW1ERR reports an error in the Status Word received from the receiving RT.
Status Word 2 Error: In an RT-RT sequence. the transmitting RT Status Word has the wrong RT address.
Data FIFO Error: Data was not available in the transmit Data FIFO in time to allow transmission.
Not used. This bit is set to "0".
Contiguous Message Error: Transmission was not contiguous.
Not used. This bit is set to "0".
Command Sync Error: Expected Command Sync, but got Data Sync.
Data Sync Error: Expected Data Sync, but got Command Sync.
Manchester Encoding Error: The decoder detected an error in Manchester encoding, bit count or parity.
This bit is set when a data word is expected while processing a receive command, but a gap is detected.
It is also set when an RT-to-RT "No Response Timeout" occurs, as defined per MIL-HDBK-1553, Figure 8
"RT-RT Timeout Measurement". The HI-6110 asserts this error when the bus dead-time between the RTRT command pair and the transmit RT Status Word exceeds 15 uS when Control Register bit 14 = "0" or
129uS when Control Register bit 14 = "1".
HOLT INTEGRATED CIRCUITS
7
HI-6110 (BUS CONTROLLER MODE)
ISSUING BC COMMANDS
Register operations in the HI-6110 can be addressed using
either the RA0-RA3 inputs or the RA3:RA0 bits in the Control
Register. Each RA input is logically ORed with its
corresponding Control Register bit. When using input pins
for register addressing, the Control Register bits 10:7 must
be reset. Register addressing via Control Register bits 10:7
is a 2-step process. First, the target register address is
written to the Control Register (and the RA0-RA3 inputs
must be held low). Next, the desired register operation is
performed: the Control Register provides the register
address while the R/W and STB inputs specify data direction
and clock the data transfer.
A MIL-STD-1553 Bus Controller message can be preloaded into the HI-6110 by writing the required Command
Word to the Command Word 1 Register. The Command
Word 2 register is used to hold the second (Transmit)
Command Word for RT to RT commands. Message data for
MIL-STD-1553 Receive commands are loaded by the host
into the Transmit Data FIFO. For Mode Code commands
with data word, a data word to be transmitted must be written
to the Transmit Data FIFO.
A BC message sequence commences when a positive edge
occurs at the BCSTART input pin, or when Control Register
bit 1 (BCSTART) transitions from 0 to 1 as a result of a
register write operation by the Host. Control Register bit 1 is
NOT automatically reset upon BC message sequence
execution. Therefore, when using the Control Register to
start message sequences, it is first necessary to reset bit 1
before it is set to initiate the next message sequence. The
MIL-STD-1553 message is properly formatted by the HI6110 and output on the selected MIL-STD-1553 data bus.
The HI-6110 waits for a response from the MIL-STD-1553
bus if the command type expects a response. The
responding RT's Status Word is captured in the HI-6110
Status Word 1 Register. The Status Word 2 register is used
to capture the Status Word from the transmitting RT during
RT-to-RT transfer commands. Message data words
received from the transmitting RT are stored in the Receive
Data FIFO. A mode data word received from the transmitting
RT is also stored in the Receive Data FIFO.
If the reply from the MIL-STD-1553 responding terminal was
a valid response and met all response time, Sync and Data
encoding, parity checks, word count, RT address, and
contiguous message requirements, then the VALMESS
output pin goes high and bit 7 in the Status Register is set.
The host may then retrieve the contents of the Status Word
register(s) and Receive Data FIFO as required by the
application software. The FFEMPTY output pin will be low if
the FIFO contains at least one data word, and the
corresponding bit 3 in the Status Register will be reset.
When all data words have been read by the host controller,
the FFEMPTY output pin goes high, and bit 3 in the Status
Register is set.
The final result of any BC message sequence is assertion of
either a VALMESS flag or an ERROR flag. If an error is
detected during a MIL-STD-1553 message sequence, the
ERROR output pin is asserted, corresponding bit 8 in the
Status Register is set, and the appropriate error bit(s) are set
in the Error Register. The host may interrogate the Error
Register to determine what action is necessary to correct the
error. The VALMESS output remains low for any message
for which an error is detected.
There are limited circumstances when VALMESS may be
followed by ERROR. For example, if the BC requests an RT
response with 4 data words but instead receives 5, the extra
data word will cause the VALMESS flag to be reset and
ERROR to be set. The host controller has the option of
reading RT responses on-the-fly by monitoring the RFLAG
and FFEMPTY flags, or may simply wait for end of sequence
flags, VALMESS or ERROR.
While the Transmit Data FIFO may be pre-loaded before
starting a message sequence, any data word may be loaded
on the fly, as long as it is written before mid-sync during that
word’s transmit window. In order to have the full 32 word
capacity available, the Transmit Data FIFO should be
cleared before writing data. The FIFO is cleared at Master
Reset, or when VALMESS or ERROR is asserted at the end
of a message.
The Receive Data FIFO is cleared at Master Reset, or by
performing a series of FIFO read operations until FFEMPTY
goes high. The Receive Data FIFO will not accept new
receive data when full. The FIFO must have at least one
empty register by mid-sync within the time window for any
incoming data word.
HOLT INTEGRATED CIRCUITS
8
HI-6110 (BUS CONTROLLER MODE)
EXAMPLE BC MIL-STD-1553 MESSAGE SEQUENCES
The HI-6110 Bus Controller issues a Receive Command with 3
data words to a Remote Terminal on the bus. The correct Status
Word is received.
Example 1. BC TO RT Transfer (BCRT message)
Host Write Data FIFO (Data Word 3)
Host Write Data FIFO (Data Word 2)
Host Write Data FIFO (Data Word 1)
Host Read SW1 (Status Word)
Host Write CW1 (Command Word)
STR
BCSTART
Receive
Command
MIL-STD-1553 Bus
Data
Word 1
Data
Word 3
Data
Word 2
Status
Word
From HI-6110 Bus Controller
From RT
VALMESS
Example 2. RT TO BC Transfer (RTBC message)
The HI-6110 Bus Controller issues a Transmit Command
requiring a 2 data word response to a Remote Terminal on the
bus. The correct Status Word and 2 Data Words are received and
read by the host.
Host Read Data FIFO (Data Word 2)
Host Read Data FIFO (Data Word 1)
Host Read SW1 (Status Word)
Host Write CW1 (Command Word)
STR
BCSTART
Transmit
Command
MIL-STD-1553 Bus
Data
Word 1
Status
Word
From HI-6110 BC
Data
Word 2
From RT
VALMESS
FFEMPTY
Example 3. RT to RT Transfer (RTRT message)
The HI-6110 Bus Controller issues an RT to RT transfer with 2
data words to two Remote Terminal on the bus. The RTs execute
the command and the Bus Controller validates the RT responses.
Note that the data transferred is captured by the HI-6110 Bus
Controller and may be read by the host.
Host Read Data FIFO (Data Word 2)
Host Read Data FIFO (Data Word 1)
Host Read SW2 (Status Word Tx)
Host Write CW2 (Transmit Command)
Host Write CW1 (Receive Command)
Host Read SW1 (Status Word Rx)
STR
BCSTART
MIL-STD-1553 Bus
Receive
Command
Transmit
Command
From HI-6110 Bus Controller
Status
Word (Tx)
Data
Word 1
Data
Word 2
From Transmitting RT
VALMESS
FFEMPTY
HOLT INTEGRATED CIRCUITS
9
Status
Word (Rx)
From Receiving RT
HI-6110 (BUS CONTROLLER MODE)
EXAMPLE BC MIL-STD-1553 MESSAGE SEQUENCES
Example 4. Mode Code Command without Data Word
Host Write CW1 (Command Word)
The HI-6110 Bus Controller issues a Mode Code Command to a
Remote Terminal on the bus. The correct Status Word is received.
Host Read SW1 (Status Word)
STR
BCSTART
Mode Code
Command
Status
Word
From HI-6110 Bus Controller
From RT
MIL-STD-1553 Bus
VALMESS
The HI-6110 Bus Controller issues a Mode Command with Data
Word (Transmit) to a Remote Terminal. The Status Word and
mode data word are received; the data word is stored in the
Receive FIFO. Status Word and mode data are read by the host.
Example 5. Mode Code with Data Word (Transmit)
Host Read Data FIFO (Mode Data)
Host Write CW1 (Command Word)
Host Read SW1 (Status Word)
STR
BCSTART
MIL-STD-1553 Bus
Mode Code
Command
Status
Word
Mode
Data
From RT
From HI-6110 BC
VALMESS
FFEMPTY
The HI-6110 Bus Controller issues a Mode Command with Data
word (Receive) to a Remote Terminal on the bus. The correct
Status Word is returned and read by the host.
Example 6. Mode Code with Data Word (Receive)
Host Write Data FIFO (Mode Data)
Host Write CW1 (Command Word)
Host Read SW1 (Status Word)
STR
BCSTART
MIL-STD-1553 Bus
Mode Code
Command
Mode
Data
From HI-6110 BC
Status
Word
From RT
VALMESS
HOLT INTEGRATED CIRCUITS
10
HI-6110 (BUS CONTROLLER MODE)
EXAMPLE BC MIL-STD-1553 MESSAGE SEQUENCES
The HI-6110 Bus Controller issues a Broadcast Receive
Command with 3 data words to all Remote Terminals.
Example 7. Broadcast BC to RT(s) Transfer
Host Write Data FIFO (Data Word 1)
Host Write CW1 (Command Word)
Host Write Data FIFO (Data Word 2)
Host Write Data FIFO (Data Word 3)
STR
BCSTART
Receive
Command
MIL-STD-1553 Bus
Data
Word 1
Data
Word 3
Data
Word 2
From HI-6110 Bus Controller
VALMESS
The HI-6110 Bus Controller issues a Broadcast RT to RT transfer
Command with 2 data words to a Remote Terminal on the bus.
The RT broadcasts the message and the Bus Controller validates
the RT response. The transmitted data words are captured by the
HI-6110 Bus Controller and may be read by the host controller.
Example 8. Broadcast RT to RT(s) Transfer
Host Read Data FIFO (Data Word 2)
Host Write CW2 (Transmit Command)
Host Read Data FIFO (Data Word 1)
Host Write CW1 (Receive Command)
Host Read SW2 (Status Word Tx)
STR
BCSTART
Receive
Command
MIL-STD-1553 Bus
Transmit
Command
Status
Word (Tx)
From HI-6110 Bus Controller
Data
Word 1
Data
Word 2
From Transmitting RT
VALMESS
Example 9. Broadcast Mode Code without Data Word
Host Write CW1 (Command Word)
The HI-6110 Bus Controller issues a Broadcast Mode Command
without data word to all Remote Terminals on the bus.
STR
BCSTART
MIL-STD-1553 Bus
Mode Code
Command
From HI-6110 BC
VALMESS
Example 10. Broadcast Mode Code with Data Word
Host Write CW1 (Command Word)
The HI-6110 Bus Controller issues a Broadcast Mode Command
with data word to all Remote Terminals on the bus.
Host Write Data FIFO (Mode Data)
STR
BCSTART
MIL-STD-1553 Bus
Mode Code
Command
Mode
Data
From HI-6110 BC
VALMESS
HOLT INTEGRATED CIRCUITS
11
HI-6110 (REMOTE TERMINAL MODE)
REMOTE TERMINAL
INITIALIZATION
The HI-6110 is configured for Remote Terminal operation by setting
the BCMODE input low and the RTMODE input high. An alternative
is programming Control Register bit 2 (BCMODE) to a "0" and
programming Control Register bit 3 (RTMODE) to a "1". These
Control Register bits are logically ORed with their corresponding
input pins.
Figure 2. shows a block diagram of the HI-6110 in Remote Terminal
mode.
Status Word
TX
DATA
FIFO
In Remote Terminal mode, the host controller first performs a
Master Reset to initialize the RT protocol engine and clear all
message registers and data FIFOs. This may be achieved by
pulsing the MR input high, or writing a "1" and then a “0” to Control
Register bit 0. The user must select a master clock (CLK) frequency
by programming Control Register bits 11 and 12. Refer to the RT
Register Formats section for a full description of available registers
and their functions in Remote Terminal Mode.
Parallel
to
Serial
Manchester
Encoder
TXINHA
BUSA
Mode Data (W)
Serial
to
Parallel
Bus A
Manchester
Decoder
BUSA
Transceiver
Bus A Word
Command Word 1
D15-D0
CS
R/W
STR
RA3-RA0
FFEMPTY
Host
Data
Interface
Command Word 2
RX
DATA
FIFO
Mode Data (R)
TXINHB
Status Word Rec'd
Bus B Word
Serial
to
Parallel
BUSB
Bus B
Manchester
Decoder
BUSB
Transceiver
VALMESS
ERROR
RFLAG
RCVA
RCVB
RCVCMDA
RCVCMDB
Status Register
Message
Status
Control Register
RT Error Register
Message Register
CLK
MR
BCSTART
BCMODE
RTMODE
Protocol
Control
RTA4-RTA0
RTAP
Terminal
Address
RT Protocol Engine
Figure 2. Block Diagram - Remote Terminal Mode
HOLT INTEGRATED CIRCUITS
12
HI-6110 (REMOTE TERMINAL MODE)
REGISTER FORMATS (RT Mode)
R
N
ot
U
s
EP ed
T
ID O
W
C T
LK
R SE
es L
e
R rve
A3 d
R
A2
R
A1
R
A0
R
ER
TR R
B
TR
A
RT
M
BC OD
M E
N OD
ot
u E
M se
R d
CONTROL REGISTER (R/W) Write Address: X1XX, Read Address: 1100
X
0
MSB 15 14 13 12 11 10 9
BIT
15
14
NAME
REPTO
13
IDWT
12
CLKSEL
11
10 - 7
Reserved
RA3:0
6
RERR
5-4
TRB, TRA
3-2
RTMODE,
BCMODE
1
0
MR
8
7
6
5
4
1
0
X
3
2
1
0
LSB
The Control Register value specifies HI-6110 operating mode,
clock frequency and the bus enabled for transmit. It can also
be used to address registers for read/write operations, assert
master reset, as well as data word suppression when illegal
command detection is implemented .
FUNCTION
Not used.
Controls the time-out which causes the No Response Error.
0
17 usec Gap (equivalent to the 57 usec measurement of 5.2.1.7 of the RT Validation Test Plan)
1
131 usec Gap
Inhibit Data Word Transmission. When “illegal command detection” is required, this feature alows
“command illegalization”. When the IDWT bit is set, normal transmission of ordinary and mode data words is
suppressed for all transmit commands. NOTE: There will be no VALMESS or ERROR assertion for the affected
message. For normal response to the next command, this bit must be reset before that command’s Status
Word bit 0 is transmitted.
Selects the frequency of the HI-6110 external clock input. CLKSEL equals “0” selects a 24 MHz clock while
CLKSEL equals “1” selects a 12 MHz clock.
This bit must be reset to “0”
Register Address for HI-6110 register and data read / write operations. The register address is defined by
the logical OR of these bits and their corresponding input pins. Setting Control Register bits 10:7 to 0000
ensures that only the input pins are used for addressing registers.
Reset ERROR. If RERR is low, the ERROR output pin can only be reset by asserting MR, master reset. Writing
RERR high causes the ERROR output to be reset (rising edge). If the RERR is left high, the ERROR output
will automatically reset after 3 to 4 microseconds. For normal operation, this bit is set to “1”.
Setting either TRA or TRB to "1" enables transmission on MIL-STD-1553 BUS A or BUS B. Setting both TRA and
TRB selects neither bus. The RT protocol engine connects to the selected, active bus. The 1553 receiver,
Manchester decoder and RCV output signal are still operational on the inactive bus. This is useful when the
remote terminal receives a command on the inactive bus, indicated by RCV signal output. The RT must switch
active buses to service the command. Valid words received on the inactive bus can be read without changing
active bus by reading the Bus A Word or Bus B Word register, but the terminal cannot respond as transmit is
disabled. NOTE: the TXINHA and TXINHB input pins can override bus enablement.
HI-6110 mode select. These Control Register bits are logically OR'ed with their corresponding input pins,
allowing the user to select 1553 operating mode under either hardware or software control:
RTMODE
BCMODE
1553 OPERATING MODE
0
0
Bus Monitor (MT), with assigned RT address
0
1
Bus Controller (BC)
1
0
Remote Terminal (RT)
1
1
Bus Monitor (MT), without assigned RT address
Not used in RT mode.
Master Reset. Writing "1" and then “0” to this bit performs the same function as pulsing the MR pin. All registers
and data FIFOs are cleared when master reset is asserted. The Control Register is the exception; it is not
affected by master reset.
TRANSMIT DATA FIFO (Write only) Write Address: X011
RESET TRANSMIT DATA FIFO Write Address: X010
MIL-STD-1553 Message Data Word 15:0
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
MSB
LSB
The 32-word Transmit Data FIFO holds MIL-STD-1553
message data. Each data word for transmit must be written
into the FIFO before mid-parity bit transmission for the
preceding MIL-STD-1553 word occurs. Words are transmitted
in the order loaded. The FIFO is cleared by Master Reset, at
assertion of VALMESS or ERROR outputs, or by any write to
register address X010. See section, “AC Electrical
Characteristics” for special timing requirements when writing
to register address X010 to reset the FIFO.
BUS A WORD REGISTER (Read only) Read Address: 1001
BUS B WORD REGISTER (Read only) Read Address: 1010
Bus A/B Word 15:0
MSB 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
LSB
In RT mode, the Bus A Word register holds the last valid
MIL-STD-1553 word received on Bus A. The Bus B Word
register holds the last valid MIL-STD-1553 word received on
Bus B.
HOLT INTEGRATED CIRCUITS
13
HI-6110 (REMOTE TERMINAL MODE)
RT OPERATION
RECEIVE DATA FIFO (Read only) Read Address: 0100
The Receive Data FIFO is 32-words deep and holds MILSTD-1553 data words received by the RT. The FIFO is cleared
on Master Reset or after all words have been read by the host.
MIL-STD-1553 Message Data Word 15:0
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
MSB
LSB
A low FFEMPTY flag (pin or Status register) means FIFO data
is available to be read by the host. Successive data reads
cause FFEMPTY to go high when the last data word is read.
COMMAND WORD 1 REGISTER (Read only) Read Address: 0000
RT Address
T/
R
For all commands except RT to RT, the Command Word 1
register contains the last valid Command Word received.
MSB 15 14 13 12 11 10 9
Subaddress /
Mode
8
7
6
Data Word Count /
Mode Code
5
4
3
2
1
0
LSB
If the last valid command received was RT to RT, the
Command Word 1 register holds the first (receive) command
word and the Command Word 2 Register holds the second
(transmit) command word. Then if Message Register bits 3
and 9 are both 0, the Command Word 1 register contains the
valid command.
Subaddress /
Mode
If the last valid command received was RT to RT, the
Command Word 2 register contains the second (transmit)
command word. (See note above for Command Word 1.)
Whenever Message Register bit 3 or bit 9 is set, the valid
command is contained in the Command Word 2 register.
Data Word Count /
Mode Code
T/
RT Address
R
COMMAND WORD 2 REGISTER (Read only) Read Address: 0001
1
MSB 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
LSB
Whenever RCV is asserted, the active Command Word
register can always be determined by checking Message
Register bits 3 and 9.
M
RT Address
es
In sag
st e
r
E
Se um rro
rv ent r
ic at
e
R ion
eq
R
es ue
er st
ve
d,
M
Br
us
oa
tb
d
Bu ca
e
”0
sy st
00
C
Su
om
”
bs
m
D ys
a
nd
yn te
a m
R
Te mi F
ec
l
rm c B ag
ei
ve
in us
al
d
Fl Co
ag nt
ro
lA
cc
ep
ta
nc
e
TRANSMIT STATUS WORD REGISTER (Write only) Write Address: X000
MSB 15 14 13 12 11 10 9
8
R
R
R
7
6
5
4
3
2
1
0
LSB
The Transmit Status Word register holds bits 10:0 for the
status word transmitted by the remote terminal in response to
a (non-broadcast) command. Status word bits 15:11 are
automatically set to match the RT Address present at the
RTA4:0 input pins. The HI-6110 automatically transmits a
status word in response to valid non-broadcast commands.
The register may be changed anytime prior to status word
mid-sync bit. The Transmit Status Word register is not
affected by MR, master reset, and bits 10:0 must be set to”0” at
terminal initialization.
M
RT Address
es
In sag
st e
r
E
Se um rro
rv ent r
ic at
e
R ion
eq
R
es ue
er st
ve
d
Br
oa
Bu dca
sy st
C
Su
om
bs
m
y
D s
an
yn te
d
am m
R
Te i F
ec
rm c B lag
ei
ve
in us
al
d
Fl Co
ag nt
ro
lA
cc
ep
ta
nc
e
RECEIVED STATUS WORD REGISTER (Read only) Read Address: 0011
MSB 15 14 13 12 11 10 9
8
R
R
R
7
6
5
4
3
2
1
0
LSB
Updated only during RT to RT transmit messages, the
Received Status Word register captures the MIL-STD-1553
status word transmitted by the receiving remote terminal.
HOLT INTEGRATED CIRCUITS
14
HI-6110 (REMOTE TERMINAL MODE)
RT OPERATION
ER
R
VA OR
LM
R E
F1 S
S
R
F0
R
FL
FF AG
E N
R MP
C T
V Y
R B
C
V
ID A
LE
STATUS REGISTER (Read only) Read Address: 0101
Not used
0
0
0
0
0
0
0
MSB 15 14 13 12 11 10
9
BIT
15- 9
8
NAME
ERROR
7
VALMESS
6
5
4
RF1
RF0
RFLAGN
3
FFEMPTY
2
RCVB
1
RCVA
0
IDLE
8
7
6
5
4
3
2
1
0
LSB
The Status Register may be interrogated by the host at any
time. It provides information that allows the user to determine
whether the HI-6110 is busy executing a MIL-STD-1553
message and its progress. After a message sequence has
completed, the Status register indicates whether an error was
detected or if the message sequence was successful.
FUNCTION
Not used. These bits are set to "0".
This bit is reset to "0" after MR, and will automatically reset 2 to 3 uS after assertion if Control register RERR
bit is set. ERROR is set to a "1" if the last sequence had an error. The nature of the message error can be
determined by examining the Error Register. The ERROR output pin reflects the state of this bit.
This bit is a "0" after reset or after a MIL-STD-1553 message containing an error. VALMESS goes high
upon completion of an error-free MIL-STD-1553 message sequence. VALMESS is reset to a zero each
time a valid command is received on the active bus. The VALMESS output pin mirrors the state of
this bit.
This bit goes high when a valid Receive Command arrives on Bus B. It is reset by the RCV B flag.
This bit goes high when a valid Receive Command arrives on Bus A. It is reset by the RCV A flag.
During a message sequence this bit goes low at the arrival of a Command Word, Status Word, or Mode
Data Word. For consecutive words, this bit will momentarily go high between words. The RFLAG output
reflects the state of this bit.
If "0", the receive Data FIFO contains at least one unread data word. This bit is set to "1" upon master reset,
or when the user has read all available received data words from the receiver Data FIFO. The FFEMPTY
output pin reflects the state of this bit.
Set to "1" upon receipt of a valid Command Word on Bus B except for RT-to-RT receive commands when it
is set after the second Command Word is received. The RCVB output pin mirrors the state of this bit.
Set to "1" upon receipt of a valid Command Word on Bus A except for RT-toRT receive commands when it
is set after the second Command Word is received. The RCVA output pin mirrors the state of this bit.
If "1", the RT is idle. This bit is “0” throughout the time the RT is processing a valid MIL-STD-1553
Command message. The bit returns to a "1" when the message is completed.
RT
P
N AR
ot ER
U
FF se R
ER d
N R
ot
U
C se
O d
N
G ER
AP R
SE ER
Q R
SY ER
N R
M CE
AN R
R
N ER
O R
R
C
V
ERROR REGISTER (Read only) Read Address: 0111
Not used
0
0
0
0
0
0
BIT
15 - 10
9
NAME
RTPARERR
8
7
6
5
4
3
FFERR
CONERR
GAPERR
SEQERR
2
1
0
SYNCERR
MANERR
NORCV
0
0
MSB 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
LSB
The RT Error Register is cleared at Master Reset and error
flags are automatically reset if Control Register bit 6 = “1”. If
an error is encountered during message execution, the
ERROR pin goes high, the ERROR bit is set in the Status
Register, and one or more bits are set in the Error Register to
specify the type of error detected.
FUNCTION
Not used. These bits are set to "0".
RT Parity Error in the pin-programmed RT address. RT address parity is checked only at Master Reset, and
once this bit is set, the host controller must perform a subsequent Master Reset to update parity status.
Not used. This bit is set to "0".
Data was not available in the Transmit Data FIFO.
Not used. This bit is set to "0".
Contiguous Message Error: Transmission was not contiguous.
Bus activity was detected in the 4.0 uS gap after a valid message was completed.
The next event after a Command Word was erroneous. For example, a gap following a valid receive
Command Word, or a contiguous Data Word following a transmit Command Word.
Sync Error: Expected Command Sync and got Data Sync, or vice versa.
Manchester Encoding Error: The decoder detected an error in Manchester encoding, bit count or parity.
This bit is set when a data word is expected while processing a receive command, but a gap is detected.
It is also set when an RT-to-RT "No Response Timeout" occurs, as defined per MIL-HDBK-1553, Figure 8
"RT-RT Timeout Measurement". The HI-6110 asserts this error when the bus dead-time between the RTRT command pair and the transmit RT Status Word exceeds 15 uS.
HOLT INTEGRATED CIRCUITS
15
HI-6110 (REMOTE TERMINAL MODE)
RT OPERATION
TRANSMIT MODE DATA WORD REGISTER (Write only) Write Address: X001
Mode Data Word 15:0
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
MSB
LSB
The write-only Transmit Mode Data Word register is loaded by
the host with the Mode Data word to be transmitted by the
remote terminal in response to a mode code with mode data
word (transmit) command. The Transmit Mode Data Word
register is not affected by MR, master reset.
RECEIVE MODE DATA WORD REGISTER (Read only) Read Address: 0010
Mode Data Word 15:0
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
MSB
LSB
MESSAGE REGISTER (Read only) Read Address: 0110
Not Used
0 13 12 11 10 9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
0
Hex
The Message Register identifies command type when a new
valid command is received from the MIL-STD-1553 bus
controller. When a valid command is received, message type
is decoded and appropriate Message Register bit(s) are set.
Two bit pairs are mirrored: Bit pair 3 and 12, Bit pair 5 and 13.
Message Type Flags
MSB 15 14 13 12 11 10 9
Last Valid Command Decoded
The read-only Receive Mode Data Word register holds the
value of the last mode data word received during a mode code
with data word (receive) command addressed to this RT. This
register is reset only by MR master reset.
LSB
In the table below, “RTA” indicates assigned Remote Terminal
address. Broadcast command occurs when address = 11111.
Bit 10 is set for mode code or non-RT-RT transmit commands
where bits 15:11 equal RTA or 11111. Bit 10 enables detection
and “illegalization” for three undefined mode code command
types listed in the table below.
Command Word 1 Bit Fields
NON-MODE COMMANDS
Receive command from BC, not broadcast
Receive command from BC, broadcast
Receive command, RT-RT, not broadcast
Receive command, RT-RT, broadcast
Transmit command, RT to BC
Transmit command, RT-RT, not broadcast
Transmit command, RT-RT, broadcast
MODE CODE COMMANDS
0410 MC0 - MC15 T/R=1 no mode data, not broadcast
0400 * MC0 - MC15 T/R=1 no mode data, broadcast
0410 MC0 - MC15 T/R=0 not broadcast, UNDEFINED
0400 MC0 - MC15 T/R=0 broadcast, UNDEFINED
2420 MC16 - MC31 T/R=1 mode data, not broadcast
0400 * MC16 - MC31 T/R=1 broadcast, UNDEFINED
0040 MC16 - MC31 T/R=0 mode data, not broadcast
0800 MC16 - MC31 T/R=0 mode data, broadcast
* Two cases where 0400 is reset 550nS after RCV
0001
0080
0004
0100
0402
1008
0200
15:11
RTA
11111
RTA
11111
RTA
not 11111
11111
10
0
0
0
0
1
0
0
9:5
00001 -11110
00001 -11110
00001 -11110
00001 -11110
00001 -11110
00001 -11110
00001 -11110
4:0
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
RTA
11111
RTA
11111
RTA
11111
RTA
11111
1
1
0
0
1
1
0
0
0000 or 11111
0000 or 11111
0000 or 11111
0000 or 11111
0000 or 11111
0000 or 11111
0000 or 11111
0000 or 11111
0XXXX
0XXXX
0XXXX
0XXXX
1XXXX
1XXXX
1XXXX
1XXXX
Command Word 2 Bit Fields
15:11
10
9:5
4:0
XXXXX 1
not RTA 1
00001-11110 XXXXX
00001-11110 XXXXX
RTA
RTA
00001-11110 XXXXX
00001-11110 XXXXX
1
1
Command Word 2
only applies for
RT-RT commands
RESET TRANSMIT DATA FIFO (Write Only) Write Address: X010
Performing a host write cycle to register address X010 causes
the Transmit Data FIFO to be cleared. New data may be
loaded into the FIFO by writing to register address X011 as
described above.
Don't Care
X
MSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
LSB
Note that no data is stored when performing a write cycle to
register address X010 and the actual data presented on the
databus is not used (don't care).
HOLT INTEGRATED CIRCUITS
16
HI-6110 (REMOTE TERMINAL MODE)
REMOTE TERMINAL OPERATION
The HI-6110 remote terminal (RT) address is set by wiring the
RTA4:RTA0 input pins to the desired address. RTA0 is the least
significant address input. The RTAP input must be set/reset to
reflect odd parity for the RA4:0 address inputs. Upon Master Reset,
the HI-6110 reads the RT address inputs and checks for correct
parity. If a parity error is detected, the PARERR bit is set in the Error
Register and the HI-6110 RT will not respond to MIL-STD-1553
Command Words. The host controller must correct the RT addressparity mismatch, then reassert Master Reset to enable bus
operations.
When configured as a Remote Terminal, the HI-6110 continuously
monitors both MIL-STD-1553 buses. Each received Command
Word is checked for validity. The RCVA and RCVB outputs are
asserted only when a received command is valid. Valid is defined
as having an RT address matching the pin-programmed RT
address or the command is a broadcast command. If a valid
command is received on Bus A, the RCVA signal goes high to notify
the host. Similarly, when a valid command arrives on Bus B, the
RCVB signal goes high.
The received command may be read from the appropriate
Command Word register, or the Message register may be read to
quickly determine the type of response needed. The RT protocol
sequencer will initiate a response in accordance with the
requirements of MIL-STD-1553. If the message type requires a
Status Word response and the bus TR bit is set in the Control
Register, the HI-6110 RT will automatically transmit its Status Word
approximately 7 to 9 uS after RCVA or RCVB goes high. The
Status Word register can be modified up to 1.3 uS past mid-sync,
occurring when the Status Word is transmitted.
If transmit data words are part of the command response, the
automatic response delay provides time for the host to load the
Transmit Data FIFO. The first data word must be written to the
FIFO not later than 20 uS after Status Word mid-sync. All data
words must be written before mid-sync occurring within its
transmission window. All data words may be written in rapid
succession once RCVA or RCVB goes high.
Upon error-free completion of the message, VALMESS goes high.
(One exception: broadcast mode code commands without mode
data word do not generate VALMESS.) If an error is detected,
VALMESS remains low and the ERROR signal goes high. The
ERROR register can be read to determine error type.
In applications requiring illegal command detection, the HI-6110
readily handles command “illegalization”. Upon detecting an illegal
command, the host microcontroller takes steps to (a) send the
Remote Terminal Status Word with the Message Error (ME) bit set
(non-broadcast commands only), and (b) suppress transmission of
any data words associated with the normal response to the
command. For part (a), the Status Word register is modified by
setting the ME bit. This is done first to make sure the change is
effective before Status Word transmission begins. For part (b), bit
13 in the Control Register is set to suppress data word
transmission.
NOTE: Once bit 13 is set in the Control register, the affected
message will NOT conclude with VALMESS or ERROR assertion.
Control Register bit 13 should be written to a zero before the next
message is processed. The host might perform the Control
Register write as part of the RCV flag service routine in order to
restore normal operation for legal commands.
The Receive Data FIFO is cleared at Master Reset, or by
performing a series of FIFO read operations until FFEMPTY goes
high. The Receive Data FIFO will not accept new receive data
when full.
When the Control Register is written to change the active bus, the
HI-6110 automatically resets any message in process on the
former bus and begins a new message sequence on the new bus.
To comply with RT response time limits, it is typically necessary to
write the Control Register within 2 uS of the rising edge of the RCV
flag on the alternate bus. Note that when the active bus is
switched, the RT message sequencer retrieves and responds to
the last valid command word received on the previously inactive
bus. This applies regardless of when the command word was
received. For this reason, bus switching should only occur in
response to a current RCV or RCMD signal or otherwise be
followed by a master reset.
The HI-6110 readily handles superseding commands. For
superseding commands on the same bus as described in 5.2.1.4 of
the RT Validation test, the 6110 will generate a new RCV flag upon
receiving a valid command after a 4 uS gap. The message
sequencer is automatically reset and the new sequence initiated.
RT validation section 5.2.1.8 “Bus Switching” tests a condition
otherwise prohibited by the 1553 standard: overlapping valid
commands on the two buses. To meet the requirements of this test,
certain steps are required: (a) When switching buses for the
superseding command, reset Control Register TRA and TRB bits
for 200 nS minimum before setting the TRx bit for the newly active
bus. This resets transmission for an in-process command
response. To simplify the software, the example software does this
for all bus switching. (b) The RT should always respond to the
command occurring last. A potential problem occurs when an RTRT receive command is interrupted by a valid command on the
other bus. Although CW1 is valid for the remote terminal, RCV for
all RT-RT commands occurs after CW1 and CW2 are both
received. When a valid command that overlaps CW1 occurs on the
other bus, its RCV will go high before the RT-RT RCV. The
overlapping command occurs later, although its RCV precedes the
RT-RT RCV. The RT-RT RCV must be ignored. To correctly
respond to the overlapping command, the software must utilize the
RCMDA and RCMDB signals as described below. Please refer to
the software example in the reference design for a working
implementation.
The RCMDA output goes high when a valid non-mode receive
command is decoded on Bus A. The RCMDB signal performs the
same function for Bus B. Successful compliance with RT validation
5.2.1.8 “Bus Switching” requires host interaction when RCMD is
asserted for the inactive bus. When this occurs, the host should
immediately make that bus active. If an ordinary receive command
is coming from the Bus Controller, RCV for the newly-active bus will
go high about 4 uS after RCMD. If an RT-RT receive command,
RCV follows RCMD by 20 uS. In either case once RCV is asserted,
the RT can begin polling FFEMPTY to acquire received data words
as they arrive.
HOLT INTEGRATED CIRCUITS
17
HI-6110 (REMOTE TERMINAL MODE)
EXAMPLE RT MIL-STD-1553 MESSAGE SEQUENCES
Example 1. BC TO RT Transfer
The HI-6110 RT receives a Receive Command with 3 data words
from the MIL-STD-1553 bus. The HI-6110 captures the message
data words and outputs a status word.
Host Read Data FIFO (Data Word 3)
Host Read Data FIFO (Data Word 2)
Host Read Data FIFO (Data Word 1)
Host Read and Decode Message
Host Change Bus if required
Host Write SW (Status Word), Optional
STR
MIL-STD-1553 Bus
Receive
Command
Data
Word 1
Data
Word 2
Data
Word 3
From MIL-STD-1553 bus
Status
Word
From HI-6110 RT
VALMESS
RCMDA/B
RCVA/B
FFEMPTY
Example 2. RT TO BC Transfer
Host Write Data FIFO (Data Word 2)
Host Write Data FIFO (Data Word 1)
Host Write SW (Status Word), Optional
The HI-6110 RT receives a Transmit Command with 2 data words
from the MIL-STD-1553 bus. The host controller HI-6110 RT
reads the Command Word to determine number of data words,
and updates the Status Word register and the requested number
of data words.
Host Read CW1 (Command Word)
Host Read and Decode Message Register
STR
MIL-STD-1553 Bus
Transmit
Command
Data
Word 1
Status
Word
From MIL-STD-1553 bus
Data
Word 2
From HI-6110 RT
VALMESS
RCVA/B
FFEMPTY
Example 3. RT to RT Transfer,
HI-6110 is the transmitting RT
Host Write Data FIFO (Data Word 1)
The HI-6110 RT receives an RT to RT transfer with 2 data words
command from the MIL-STD-1553 bus. In this case, the HI-6110
is the transmitting RT. The HI-6110 issues the necessary Status
Word and Data Words, and monitors the acknowledging Status
Word from the receiving RT.
Host Write SW (Status Word), Optional
Host Read CW2 (Transmit Command)
Host Read SWR (Status Word Received)
Host Read and Decode Message Register
Host Write Data FIFO (Data Word 2)
STR
MIL-STD-1553 Bus
Receive
Command
Transmit
Command
From MIL-STD-1553 bus
Status
Word 1
Data
Word 1
From HI-6110 RT
VALMESS
RCVA/B
FFEMPTY
HOLT INTEGRATED CIRCUITS
18
Data
Word 2
Status
Word 2
From Receiving RT
HI-6110 (REMOTE TERMINAL MODE)
EXAMPLE RT MIL-STD-1553 MESSAGE SEQUENCES
The HI-6110 RT receives an RT to RT transfer with 2 data words
command from the MIL-STD-1553 bus. In this case, the HI-6110
is the receiving RT. The HI-6110 captures the message data and
issues the necessary Status Word. In this particular example, the
host did not update the Status Word Register and the HI-6110 reissues the last value of SW.
Example 4. RT to RT Transfer,
HI-6110 is the receiving RT
Host Read and Decode Message
Host Read Data FIFO (Data Word 1)
Host Change Bus if required
Host Read Data FIFO (Data Word 2)
STR
MIL-STD-1553 Bus
Receive
Command
Transmit
Command
Data
Word 1
Status
Word 1
From MIL-STD-1553 bus
Data
Word 2
From Transmitting RT
Status
Word 2
From HI-6110 RT
VALMESS
RCMDA/B
RCVA/B
FFEMPTY
Example 5. Mode Code Command without Data Word
Host Write SW (Status Word)
Host Read CW1 (Command Word)
Host Read and Decode Message Register
The HI-6110 RT receives a Mode Code Command without Data
Word from the MIL-STD-1553 bus. The correct Status Word is
output. In this example, the host updates the Status Word register
prior to RT response. The Status Word update must be
completed within 5uS after the RCVA/B rising edge. If no host
write is performed, the HI-6110 will output the current value of the
SW register.
STR
Mode Code
Command
Status
Word
From MIL-STD-1553 bus
From HI-6110 RT
MIL-STD-1553 Bus
VALMESS
RCVA/B
FFEMPTY
Example 6. Mode Code with Data Word (Transmit)
Host Write MODE (Mode Data)
Host Write SW (Status Word)
Host Read CW1 (Control Word)
Host Read and Decode Message Register
The HI-6110 RT receives a Mode Command with Data Word
(Transmit) from the MIL-STD-1553 bus. The required Status
Word and Mode Data Word are transmitted by the HI-6110 RT. In
this particular example, the host updates both the Status Word
and Mode Data registers prior to RT response. A Status Word
update must be completed within 5uS after the RCVA/B rising
edge. If no host writes are performed, the HI-6110 will output the
current values of the SW register and Mode Data register.
STR
MIL-STD-1553 Bus
Mode Code
Command
Status
Word
From MIL-STD-1553 bus
Mode
Data
From HI-6110 RT
VALMESS
RCVA/B
FFEMPTY
HOLT INTEGRATED CIRCUITS
19
HI-6110 (REMOTE TERMINAL MODE)
EXAMPLE RT MIL-STD-1553 MESSAGE SEQUENCES
The HI-6110 RT receives a Mode Command with Data word
(Receive) from the MIL-STD-1553 bus. The correct Status Word
is returned and the host reads the Mode Data value. In this
particular example, the host reads the Message Register to
determine what type of MIL-STD-1553 command was received. A
default value is used for the Status Word response.
Example 7. Mode Code with Data Word (Receive)
Host Read and Decode Message Register
Host Read MODE (Receive Mode Data)
STR
Mode Code
Command
MIL-STD-1553 Bus
Mode
Data
From MIL-STD-1553 bus
Status
Word
From HI-6110 RT
VALMESS
RCVA/B
FFEMPTY
Example 8. Broadcast BC to RT Transfer
The HI-6110 RT receives a Broadcast Receive Command with 3
data words from the MIL-STD-1553 bus. No Status Word is
returned.
Host Read and Decode Message
Host Read Data FIFO (Data Word 3)
Host Read Data FIFO (Data Word 2)
Host Read Data FIFO (Data Word 1)
Host Change Bus if required
STR
Receive
Command
MIL-STD-1553 Bus
Data
Word 1
Data
Word 3
Data
Word 2
VALMESS
RCMDA/B
RCVA/B
FFEMPTY
The HI-6110 RT receives a Broadcast RT to RT transfer
Command with 2 data words from the MIL-STD-1553 bus. The
HI-6110 RT is the transmitter. Note that RCVA/B doesn’t go high
until the Transmit Command matching the HI-6110 RT address is
received. The HI-6110 broadcasts the message and does not wait
for a Status Word to be returned.
Example 9. Broadcast RT to RT Transfer
HI-6110 is the transmitting RT
Host Write Data FIFO (Data Word 1)
Host Write SW (Status Word)
Host Read CW2 (Transmit Command)
Host Read and Decode Message Register
Host Write Data FIFO (Data Word 2)
STR
MIL-STD-1553 Bus
Receive
Command
Transmit
Command
From MIL-STD-1553 bus
Status
Word 1
Data
Word 1
From HI-6110 RT
VALMESS
RCVA/B
FFEMPTY
HOLT INTEGRATED CIRCUITS
20
Data
Word 2
HI-6110 (REMOTE TERMINAL MODE)
EXAMPLE RT MIL-STD-1553 MESSAGE SEQUENCES
The HI-6110 RT receives a Broadcast RT to RT transfer
Command with 2 data words from the MIL-STD-1553 bus. The
HI-6110 RT is the receiver. The HI-6110 captures the message
which is read by the host. A Status Word is not transmitted.
Example 10. Broadcast RT to RT Transfer,
HI-6110 is the receiving RT
Host Read and Decode Message
Host Read Data FIFO (Data Word 2)
Host Change Bus if required
Host Read Data FIFO (Data Word 1)
STR
MIL-STD-1553 Bus
Receive
Command
Transmit
Command
Status
Word 1
From MIL-STD-1553 bus
Data
Word 1
Data
Word 2
From transmitting RT
VALMESS
RCMDA/B
RCVA/B
FFEMPTY
Example 11. Broadcast Mode Code without Data Word
Host Read CW1 (Command Word)
The HI-6110 RT receives a Broadcast Mode Command without
Data word from the MIL-STD-1553 bus. The Mode Command
Word is read by the host. Note:The RCV signal pulse is less than
1 uS wide, and Message Register flag is cleared at the same time.
STR
MIL-STD-1553 Bus
Mode Code
Command
From MIL-STD-1553 bus
VALMESS
RCVA/B
FFEMPTY
Example 12. Broadcast Mode Code with Data Word
The HI-6110 RT receives a Broadcast Mode Command with Data
word from the MIL-STD-1553 bus. The host reads the Mode Data
word received.
Host Read MODE (Mode Data)
Host Read CW1 (Command Word)
STR
MIL-STD-1553 Bus
Mode Code
Command
Mode
Data
From HI-6110 BC
VALMESS
RCVA/B
FFEMPTY
HOLT INTEGRATED CIRCUITS
21
HI-6110 (BUS MONITOR MODE)
BUS MONITOR
The HI-6110 may be configured as Bus Monitor with or without an
assigned RT address. Resetting both BCMODE and RTMODE to
“0” configures the HI-6110 as a Bus Monitor with assigned RT
address (MT/RT mode). Setting both BCMODE and RTMODE to
“1” configures the HI-6110 as a Bus Monitor without an RT address
(MT mode). In either Mode, the HI-6110 captures all information
that occurs on the selected MIL-STD-1553 bus. All bus
transactions are checked for errors. If a message sequence is
good, the VALMESS signal is asserted at the end of the message. If
an error occurs, ERROR is asserted. The host may interrogate the
ERROR Register to determine the nature of the error. Command
Words, Status Words, Message Data and Mode Words are
captured for all bus transactions and may be read by the host.
In MT/RT mode, the HI-6110 will respond to all MIL-STD-1553
messages with assigned RT address matching the pinprogrammed RT address. All conditions pertinent to RT responses
are described in the previous Remote Terminal Mode section of this
document.
In MT mode (no assigned RT address), the HI-6110 does not
transmit information to the MIL-STD-1553 bus and acts as a
passive monitor as described by the MIL-STD-1553 specification.
Figure 3 represents the HI-6110 in MT mode.
INITIALIZATION
In Bus Monitor mode, the user must first perform Master Reset to
initialize the MT protocol engine and clear all message registers
and data FIFOs. This may be achieved by pulsing the MR input
high, or writing a "1" to Control Register bit 0. The user must select a
master clock (CLK) frequency by programming Control Register
bits 11 and 12. Refer to the MT Register Formats section for a full
description of available registers and their functions in Bus Monitor
Mode.
In MT mode (without assigned RT address) the five RT Address
input pins RTA0 to RTA4 must be pulled high or left unconnected. In
the second case, internal pull-up resistors act to hold the five RTA
inputs high. In MT mode, the RTAP pin is “don’t care”.
Receiver
Serial
to
Parallel
BUSA
Manchester
Decoder
Bus A
BUSA
Bus A Word
Command Word 1
D15-D0
CS
R/W
STR
RA3-RA0
FFEMPTY
Host
Data
Interface
Command Word 2
RX
DATA
FIFO
Mode Data (R)
Status Word Rec'd
Receiving Status
Word (RT-RT)
Bus B Word
Receiver
Serial
to
Parallel
BUSB
Bus B
Manchester
Decoder
BUSB
VALMESS
ERROR
RFLAG
RCVA
RCVB
RCVCMDA
RCVCMDB
CLK
MR
BCSTART
BCMODE
RTMODE
Status Register
Message
Status
Control Register
MT Error Register
MT Protocol Engine
Message Register
Protocol
Control
Figure 3. Block Diagram - Bus Monitor (without assigned RT address) Mode
HOLT INTEGRATED CIRCUITS
22
HI-6110 (BUS MONITOR MODE)
REGISTER FORMATS (MT Mode)
U
N
N
ot
N
ot
U
se
d
s
ot ed
U
C se
LK d
R SE
es L
e
R rve
A3 d
R
A2
R
A1
R
A0
R
ER
M R
R
B
M
R
A
RT
M
BC OD
M E
N OD
ot
U E
M se
R d
CONTROL REGISTER (R/W) Write Address: X1XX, Read Address: 1100
X
X
X
0
X
MSB 15 14 13 12 11 10 9
BIT
15-13
12
11
10 - 7
6
5-4
3-2
1
0
8
7
6
5
4
3
2
1
0
LSB
The Control Register value specifies HI-6110 operating mode,
clock frequency and specifies which bus is enabled for
monitoring. Control Register bits can also be used for
addressing registers in read/write operations, or to assert
master reset.
NAME
CLKSEL
FUNCTION
Not used in MT mode.
Selects the frequency of the HI-6110 external CLK input, as follows:
CLKSEL
Value
0
24 MHz
1
12 MHz
Reserved Must be reset to “0”
RA3:0
Register Address for HI-6110 register and data read / write operations. The register address is defined by the
logical OR of these bits and their corresponding input pins. Setting Control Register bits 10:7 to 0000 ensures
that just the address input pins control register addressing.
RERR
Reset ERROR. If RERR is low the ERROR output signal is only reset on reception of a new valid command.
Setting RERR high (rising edge) resets a high ERROR output . If the RERR bit is left high, ERROR outputs will
automatically reset after 3 to 4 microseconds. For normal operation, this bit is set to “1”.
MRB, MRA Setting either MRA or MRB to "1"connects the protocol engine to Monitor BUS A or Monitor BUS B. Setting
both MRA and MRB selects neither bus. The 1553 receiver, Manchester decoder and RCV output signal
remain operational on the inactive bus. When the monitor terminal receives a command on the inactive bus, its
RCV signal output goes high. The MT must switch active buses so received data words, message results, etc.
will be stored in the proper registers. Valid words received on the inactive bus can be read without changing
active bus by reading the Bus A Word or Bus B Word Register, but any received message words, errors, message
results etc. are not updated if the bus is not enabled by setting the appropriate MRA or MRB bit.
RTMODE, HI-6110 mode select. These Control Register bits are logically OR'ed with their corresponding input pins. The
BCMODE user can select 1553 operating mode under either hardware or software control:
RTMODE
BCMODE 1553 OPERATING MODE
0
1
Bus Controller (BC)
1
0
Remote Terminal (RT)
1
1
Bus Monitor without assigned RT address (MT)
0
0
Bus Monitor with assigned RT address (RT-MT) in which Control Register bits
5:4 enable transmit for valid commands for which command terminal address matches
the assigned Remote Terminal address. See the RT mode section.
Not used in MT mode.
MR
Master Reset. Writing "1" and then “0” to this bit performs the same function as pulsing the MR pin. All register
and data FIFOs are cleared when master reset is asserted. The Control Register is the exception; it is not
affected by Master Reset.
RECEIVE DATA FIFO (Read only) Read Address: 0100
The Receive Data FIFO is 32-words deep and holds all MILSTD-1553 received data words. The FIFO is cleared at Master
Reset.
MIL-STD-1553 Message Data Word 15:0
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
MSB
LSB
A low FFEMPTY flag (output pin or Status register bit) means
FIFO data is available to be read by the host. Successive data
word fetches will cause FFEMPTY to go high when the last
data word is read.
BUS A WORD REGISTER (Read only) Read Address: 1001
BUS B WORD REGISTER (Read only) Read Address: 1010
Bus A/B Word 15:0
MSB 15 14 13 12 11 10 9
8
7
6
In MT mode, the Bus A Word register holds the last valid MILSTD-1553 word received on Bus A. The Bus B Word register
holds the last valid MIL-STD-1553 word received on Bus B.
5
4
3
2
1
0
LSB
HOLT INTEGRATED CIRCUITS
23
HI-6110 (BUS MONITOR MODE)
MT OPERATION
es
In sag
st e
r
E
Se um rro
rv e n t r
ic a t
e
R io n
eq
R
es ue
er st
ve
d
Br
oa
Bu dca
sy st
C
Su
om
bs
m
y
D s
an
yn te
d
am m
R
Te i F
ec
rm c B la g
ei
ve
in u s
al
d
Fl Co
a g nt
ro
lA
cc
ep
ta
nc
e
STATUS WORD 1 REGISTER (Read only) Read Address: 1000
For non-broadcast single-RT commands, the Status Word 1
register holds the MIL-STD-1553 Status Word transmitted by
the RT.
M
RT Address
MSB 15 14 13 12 11 10 9
8
R
R
R
7
6
5
4
3
2
1
0
LSB
For RT to RT messages, the Status Word 1 register holds the
MIL-STD-1553 Status Word sent by the transmitting Remote
Terminal.
es
In sag
st e
r
E
Se um rro
rv ent r
ic at
e
R ion
eq
R
es ue
er st
ve
d
Br
oa
Bu dca
sy st
C
Su
om
bs
m
y
D s
an
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d
am m
R
Te i F
ec
rm c B lag
ei
ve
in us
al
d
Fl Co
ag nt
ro
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cc
ep
ta
nc
e
STATUS WORD 2 REGISTER (Read only) Read Address: 0011
M
RT Address
MSB 15 14 13 12 11 10 9
8
R
R
R
7
6
5
4
3
2
1
0
LSB
Used only for RT to RT messages, the Status Word 2 register
holds the MIL-STD-1553 Status Word sent by the receiving
Remote Terminal.
R
VA OR
LM
R E
F1 S
S
R
F0
R
FL
FF AG
E N
R MP
C T
V Y
R B
C
V
ID A
LE
STATUS REGISTER (Read only) Read Address: 0101
ER
Not used
0
0
0
0
0
0
0
MSB 15 14 13 12 11 10 9
BIT
15- 9
8
NAME
ERROR
7
VALMESS
6
5
4
RF1
RF0
RFLAGN
3
FFEMPTY
2
1
0
RCVB
RCVA
IDLE
8
7
6
5
4
3
2
1
0
LSB
The Status Register may be interrogated by the host at any
time. It provides information that allows the user to determine
whether the HI-6110 MT is busy monitoring an active MILSTD-1553 message and its progress. After a message
sequence has completed, the Status register indicates
whether an error was detected or if the message sequence
was successful.
FUNCTION
Not used. These bits are set to "0".
This bit is set to "0" after reset or when the last MIL-STD-1553 message sequence was valid. ERROR is set
to a "1" if the last sequence had an error. The nature of the message error can be determined by examining
the Error Register. The ERROR output pin reflects the state of this bit.
This bit is a "0" after reset or the last MIL-STD-1553 message contained an error. VALMESS goes high on
the completion of an error-free MIL-STD-1553 message sequence. VALMESS is reset to a zero each time
new valid Command Word is received by the RT. The VALMESS output pin reflects the state of this bit.
Register address bit 1 for the last written word register.
Register address bit 0 for the last written word register.
Goes low when a new MIL-STD-1553 Command Word is received by the RT, or a Status Word is received
from the receiving RT during an RT - to - RT transfer. RFLAGN returns high momentarily upon the receipt of
any new 1553 word. The RFLAG output reflects the state of this bit.
If "0" then the receive Data FIFO contains at least one word of data. This bit is set to a "1" on reset, or when
the user has read all available received data words from the receiver Data FIFO. The FFEMPTY output pin
reflects the state of this bit.
Set to a "1" upon receipt of a valid Command Word. The RCVB output pin mirrors the state of this bit.
Set to a "1" upon receipt of a valid Command Word. The RCVA output pin mirrors the state of this bit.
If "1" then the RT is idle. This bit is a zero throughout the time the RT is processing a valid MIL-STD-1553
Command message. The bit returns to a "1" when the message is completed.
HOLT INTEGRATED CIRCUITS
24
HI-6110 (BUS MONITOR MODE)
MT OPERATION
RT
P
N AR
ot ER
U
FF se R
ER d
N R
ot
U
O se
C d
N
G ER
AP R
C ER
W R
E
SY RR
N
M CE
AN R
R
N ER
O R
R
C
V
ERROR REGISTER (Read only) Read Address: 0111
Not used
0
0
0
0
0
0
0
MSB 15 14 13 12 11 10 9
BIT
15- 10
9
8
7
6
5
4
3
2
1
0
NAME
RTPARERR
FFERR
CONERR
GAPERR
WCERR
SYNCERR
MANERR
NORCV
0
8
7
6
5
4
3
2
1
0
LSB
FUNCTION
Not used. These bits are set to "0".
RT Parity Error: There is a parity error in the pin-programmed RT address of this RT.
Not used. This bit is set to "0".
Data was not available in the Transmit Data FIFO.
Not used. This bit is set to "0".
Contiguous Message Error: Transmission was not contiguous.
Bus activity was detected in the 4.0 uS gap after a valid message was completed.
Word Count Error.
Sync Error: Expected Command Sync and got Data Sync, or vice versa.
Manchester Encoding Error: The decoder detected an error in Manchester encoding, bit count or parity.
This bit is set when a data word is expected while processing a receive command, but a gap is detected.
It is also set when an RT-to-RT "No Response Timeout" occurs, as defined per MIL-HDBK-1553, Figure 8
"RT-RT Timeout Measurement". The HI-6110 asserts this error when the bus dead-time between the RTRT command pair and the transmit RT Status Word exceeds 15 uS.
MESSAGE REGISTER (Read only) Read Address: 0110
Not Used
8
7
6
5
4
3
2
1
0
MSB 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Hex
The Message Register identifies command type when a new
valid command is received from the MIL-STD-1553 bus
controller. When a valid command is received, message type
is decoded and appropriate Message Register bit(s) are set.
Register bits 5 and 13 are mirrored.
Message Type Flags
0 13 12 11 10 9
0
The RT Error Register is cleared at reset and on receipt of a
valid MIL-STD-1553 Command Word. If an error is
encountered during message execution, the ERROR pin goes
high, the ERROR bit is set in the Status Register, and one or
more bits are set in the Error Register. The host may
interrogate the Error register at any time to determine the type
of error encountered.
Last Valid Command Decoded
LSB
Broadcast commands occur when Command Word bits 15:11
= 11111. Values other than 11111 indicate the Remote Terminal
address for a non-broadcast command. Message Register bit
10 is set for any mode code or transmit command. This
enables detection of the three undefined mode code
command types listed under Bit 10 below.
Command Word 1 Bit Fields
NON-MODE COMMANDS
Receive command from BC, not broadcast
Receive command from BC, broadcast
RT-RT command, not broadcast
RT-RT command, broadcast
Transmit command, RT to BC
MODE CODE COMMANDS
0410 MC0 - MC15 T/R=1 no mode data, not broadcast
0400 * MC0 - MC15 T/R=1 no mode data, broadcast
0410 MC0 - MC15 T/R=0 not broadcast, UNDEFINED
0400 MC0 - MC15 T/R=0 broadcast , UNDEFINED
2420 MC16 - MC31 T/R=1 mode data, not broadcast
0400 * MC16 - MC31 T/R=1 broadcast , UNDEFINED
0040 MC16 - MC31 T/R=0 mode Data, not broadcast
0800 MC16 - MC31 T/R=0 mode data, broadcast
0001
0080
0004
0100
0402
Command Word 2 Bit Fields
15:11
RTA
11111
RTA
11111
RTA
10
0
0
0
0
1
9:5
00001 -11110
00001 -11110
00001 -11110
00001 -11110
00001 -11110
4:0
15:11 10
9:5
4:0
XXXXX
XXXXX
XXXXX XXXXX 1 00001-11110 XXXXX
XXXXX not RTA 1 00001-11110 XXXXX
XXXXX
RTA
11111
RTA
11111
RTA
11111
RTA
11111
1
1
0
0
1
1
0
0
0000 or 11111
0000 or 11111
0000 or 11111
0000 or 11111
0000 or 11111
0000 or 11111
0000 or 11111
0000 or 11111
0XXXX
0XXXX
0XXXX
0XXXX
1XXXX
1XXXX
1XXXX
1XXXX
* Two cases where 0400 is reset 550nS after RCV
HOLT INTEGRATED CIRCUITS
25
Command Word 2
only applies for
RT-RT commands
HI-6110 (BUS MONITOR MODE)
MT OPERATION
RT Address
T/
R
COMMAND WORD 1 REGISTER (Read only) Read Address: 0000
MSB 15 14 13 12 11 10 9
Subaddress /
Mode
8
7
6
5
Data Word Count /
Mode Code
For all commands except RT to RT, the Command Word 1
register contains the last valid Command Word received.
4
When RCV is asserted, if Message Register bit 2 or bit 8 is set,
the new message is RT to RT. The Command Word 1 register
holds the first (receive) command and the Command Word 2
Register holds the second (transmit) command.
3
2
1
0 LSB
RT Address
T/
R
COMMAND WORD 2 REGISTER (Read only) Read Address: 0001
MSB 15 14 13 12 11 10 9
Subaddress /
Mode
8
7
6
Data Word Count /
Mode Code
5
4
3
2
1
0
The Command Word 2 register contains the second (transmit)
command word from the last RT-RT message. (See note
above for Command Word 1.)
LSB
Whenever RCV is asserted, RT-RT messages can be
detected by checking Message Register bits 2 and 8.
RECEIVE MODE DATA REGISTER (Read only) Read Address: 0010
Mode Data Word 15:0
15 14 13 12 11 10 9
8
7
6
5
MSB
4
3
2
1
0
LSB
BUS MONITOR OPERATION (MT mode)
When configured as a Bus Monitor with no assigned RT address,
the HI-6110 continuously monitors the selected MIL-STD-1553 bus
and passively captures all bus traffic. The HI-6110 never transmits
information onto the bus. When a Command Word is received, a
validation check is performed. If the Command Word contains no
errors, the RFLAG pin goes low and the HI-6110 MT captures the
complete message in its internal registers and Receiver Data FIFO
as appropriate.
If the valid Command Word was received on Bus A, the RCVA
signal goes high to notify the host that a new message has
commenced. The RCVB pin is asserted when the valid Command
Word arrived on Bus B.
The read-only Receive Mode Data Register holds the Mode
Code Data Word received during a Mode Code with Data
Word (Receive) Command.
The HI-6110 bus monitor treats the unexpected word as a
superseding command for the RxRT. Monitor processing stops for
the RT-RT message stops. The new command word is stored in the
Command Word 1 register and the HI-6110 stores message results
for the new superseding message in the appropriate registers. To
assure this treatment for the RxRT superseding command, the host
should apply Master Reset after completion of any fulfilled RT-RT
command, following all necessary register operations by the host.
This reset should be performed before reception of the next RT-RT
command that might be followed by a superseding command to the
RxRT occuring before the TxRT response.
The above paragraph describes an unlikely occurrence because
the BC's transmission of a superseding command is likely to collide
on the bus with the TxRT response to the original RT-RT command.
The Command Word may be read from the Command Word 1
register, or the Message register can be read to directly learn the
type of command received.
If the monitored MIL-STD-1553 system utilizes RT-RT commands,
special precautions arise if superseding commands may occur on
the same bus. Consider this unusual sequence of events:
a) an RT-RT command pair is received. Command Word 1
addresses the receiving RT (called "RxRT" in this example)
and Command Word 2 addresses the transmitting RT (called
"TxRT").
b) following the RT-RT command pair, the Bus Monitor
normally expects to see the TxRT Status Word followed by the
commanded number of data words. Instead, the word
following the RT-RT command pair has command sync and is
addressed to the RxRT (not the TxRT).
HOLT INTEGRATED CIRCUITS
26
HI-6110 (BUS MONITOR MODE)
BUS MONITOR OPERATION (MT/RT mode)
When configured as a Monitor with assigned RT address, the HI6110 responds to all commands that match its hard-wired RT
address as described in the RT section of this data sheet. All other
bus traffic is monitored as described in this MT section.
To operate as Monitor with assigned RT address, Control Register
bits 3:2 are reset to 00. In this operating mode, the monitor asserts
RCV for RCVA or RCVB upon detection of any properly encoded
command occurring on Bus A or Bus B. Assertion of RCV indicates
either a monitored command, or a valid command which requires a
Monitor Terminal response. If received command word bits 15:11
match the assigned terminal address present on input pins RTA4:0
and parity bit RTAP, the device will respond to the command as the
addressed terminal. When RCV is asserted, there is no way to
distinguish valid commands from monitored commands, using only
the HI-6110 output signals available to the host.
3. Detect (or rule out) a valid broadcast
message in the CW1 register
Broadcast commands in Command Word 1 register are considered
valid to the Monitor's assigned terminal address. Unless the
Monitor's assigned terminal address must recognize and act upon
broadcast messages, there is no need to test for CW1 broadcast
11111 terminal address match since no response is transmitted for
broadcast commands. If step 2 test fails but broadcast commands
are allowed, test CW1 address match to 11111 to detect (or rule out)
valid broadcast messages.
4. Process the monitored message
Ruling out a valid command in steps 1-3 means the new command
in CW1 is monitored. If the Message Register value is either
0x0004 or 0x0100, the message is a monitored RT-RT sequence
and CW2 is also involved in the message.
Monitor Terminal With or Without Assigned RT Address
Valid commands (that is, commands with address match) can
occur in Command Word 1 or Command Word 2. Detection of valid
commands has higher priority than detection of monitored
commands because many valid commands require timely host
servicing of HI-6110 registers for fulfillment. Here is a logic
sequence to distinguish valid commands from monitored
commands:
Control Register bits 4-5 designate the active and inactive buses.
When the HI-6110 is idle, one of these bits is usually set, reflecting
the bus where the last command was serviced. The bus
corresponding to the set Control Register bit is designated ’‘active”
while the bus corresponding to the reset bit is designated “inactive”.
1. Detect (or rule out) a valid RT-RT
transmit command in the CW2 register
When RCVA or RCVB is asserted, the host reads the Message
Register. Register values 0x1008 and 0x0200 only occur for RT-RT
transmit commands in Remote Terminal mode. These values never
occur for monitored commands. If the Message Register contains
either value, the decoded command is a valid RT-RT transmit
command, and the Command Word 2 register contains the transmit
command to which the Monitor Terminal must respond. Detection
of valid command requires immediate host action to fulfill message
requirements; the host must load the HI-6110 Transmit FIFO in time
for data transmission. Steps 2-4 are skipped.
When a new command is decoded, a RCVA or RCVB output is
asserted. When RCV occurs on the inactive bus, the host should
toggle HI-6110 Control Register bits 4-5 to switch active / inactive
buses and service the new command. Under unusual conditions, a
new command can occur on the inactive bus while the device is still
processing an earlier command on the active bus. Monitoring of the
first message (or response, if the command matched the Monitor
Terminal assigned RT address) is unaffected by RCV assertion for
the overlapping command on the inactive bus. However
processing will stop for an unfinished message on the active bus
whenever the host toggles HI-6110 Control Register bits 4-5 to
switch active / inactive buses to service the new command. This is
consistent with MIL-STD-1553, which says a new command has
priority over an earlier command.
2. Detect (or rule out) another
valid command in the CW1 register
When Command Word 2 does not contain 0x1008 or 0x0200,
newly decoded Command Word 1 must be tested for address
match to the Monitor's assigned terminal address to detect
command validity. The host must read the Command Word 1
register, looking for a value match between the word's upper 5 bits
and the 5-bit value present at HI-6110 RTA4:0 input pins. A signal
path must be provided so the host can directly read the 5-bit
RTA4:0 value, as the terminals' active address value cannot be
determined by reading HI-6110 registers. When Command Word 1
address match occurs, the host must take all necessary steps to
fulfill the valid command. For example, when transmit commands
occur, the host must load the HI-6110 Transmit FIFO in time for data
transmission, following the same rules presented for dedicated
Remote Terminal operating mode.
Monitor Terminal With Assigned RT Address Only
Building on the above scenario, the host switches active bus
whenever RCV assertion indicates a new command was detected
on the inactive bus. When the Monitor is operating with assigned
RT address, each RCV assertion can indicate a monitored
command, or a valid command matching the Monitor Terminal
assigned RT address. When command address match occurs for a
new “inactive bus” command, switching active bus by writing
Control Register bits 5-4 disrupts the terminal's ability to transmit a
command response. The HI-6110 does not respond to the
command that caused bus switching to occur. Once bus switching
occurs, all following commands on the same bus (monitored or with
matching address) are fully processed by the terminal.
Monitored commands without RT address match (or all commands
when operating in Monitor mode without assigned RT address) are
correctly handled by the HI-6110, even when they occur on the
inactive bus and the host switches buses to service/monitor the
message.
HOLT INTEGRATED CIRCUITS
27
HI-6110 (BUS MONITOR MODE)
EXAMPLE MT MIL-STD-1553 MESSAGE SEQUENCES
Example 1. BC TO RT Transfer
The HI-6110 MT monitors a Receive Command with 3 data words
fon the MIL-STD-1553 bus. The HI-6110 captures the message
data words and does not respond to the bus.
Host Read Status Word Received
Host Read Data FIFO (Data Word 3)
Host Read Data FIFO (Data Word 2)
Host Read CW1 (Command Word)
Host Read Data FIFO (Data Word 1)
STR
MIL-STD-1553 Bus
Receive
Command
Data
Word 1
Data
Word 3
Data
Word 2
From Bus Controller
Status
Word
From responding RT
VALMESS
RCMDA/B
RCVA/B
FFEMPTY
Example 2. RT TO BC Transfer
The HI-6110 MT monitors a Transmit Command with 2 data words
on the MIL-STD-1553 bus. The HI-6110 MT captures the
Command Word from the BC and the Status Word and Message
Data from the responding RT.
Host Read Data FIFO (Data Word 2)
Host Read Data FIFO (Data Word 1)
Host Read Status Word Received
Host Read CW1 (Command Word)
STR
MIL-STD-1553 Bus
Transmit
Command
Data
Word 1
Status
Word
From Bus Controller
Data
Word 2
From responding RT
VALMESS
RCVA/B
FFEMPTY
Example 3. RT TO RT Transfer
The HI-6110 MT monitors an RT to RT transfer with 2 data words
command on the MIL-STD-1553 bus. The HI-6110 captures the
message data and the Status Words from both the transmitting
and Receiving RTs.
Host Read Receiving Status Word (SW2)
Host Read SWR (Status Word 1)
Host Read CW2 (Transmit Command)
Host Read Data FIFO (Data Word 2)
Host Read CW1 (Receive Command)
Host Read Data FIFO (Data Word 2)
STR
MIL-STD-1553 Bus
Receive
Command
Transmit
Command
From Bus Controller
Status
Word 1
Data
Word 1
Data
Word 2
From Transmitting RT
VALMESS
RCMDA/B
RCVA/B
FFEMPTY
HOLT INTEGRATED CIRCUITS
28
Status
Word 2
From Receiving RT
HI-6110 (BUS MONITOR MODE)
EXAMPLE MT MIL-STD-1553 MESSAGE SEQUENCES
The HI-6110 MT monitors a Mode Code Command on the MILSTD-1553 bus. The responding RT's correct Status Word is
captured.
Example 4. Mode Code Command without Data Word
Host Read CW1 (Command Word)
Host Read Status Word Recived
STR
MIL-STD-1553 Bus
Mode Code
Command
Status
Word
From Bus Controller
From responding RT
VALMESS
RCVA/B
FFEMPTY
Example 5. Mode Code with Data Word (Transmit)
The HI-6110 MT monitors a Mode Command with Data word
(Transmit) on the MIL-STD-1553 bus. The Status Word and
Mode Data Word from the responding RT are captured and read
by the host.
Host Read MODE (Mode Data)
Host Read Status Word Received
Host Read CW1 (Control Word)
STR
Mode Code
Command
MIL-STD-1553 Bus
Status
Word
From Bus Controller
Mode
Data
From responding RT
VALMESS
RCVA/B
FFEMPTY
The HI-6110 MT monitors a Mode Command with Data word
(Receive) on the MIL-STD-1553 bus. The Mode Data Word from
the BC and the Status Word from the responding RT are captured
by the HI-6110 MT and read by the host.
Example 6. Mode Code with Data Word (Receive)
Host Read MODE (Mode Data)
Host Read Status Word Received
Host Read Message Register
STR
MIL-STD-1553 Bus
Mode Code
Command
Mode
Data
From Bus Controller
Status
Word
From responding RT
VALMESS
RCVA/B
FFEMPTY
HOLT INTEGRATED CIRCUITS
29
HI-6110 (BUS MONITOR MODE)
EXAMPLE MT MIL-STD-1553 MESSAGE SEQUENCES
Example 7. Broadcast BC to RT Transfer
Host Read Data FIFO (Data Word 3)
The HI-6110 MT monitors a Broadcast Receive Command with 3
data words on the MIL-STD-1553 bus. The message data is
captured and read by the host
Host Read Data FIFO (Data Word 2)
Host Read Data FIFO (Data Word 1)
Host Read CW1 (Command Word)
STR
Receive
Command
MIL-STD-1553 Bus
Data
Word 1
Data
Word 2
Data
Word 3
From Bus Controller
VALMESS
RCMDA/B
RCVA/B
FFEMPTY
The HI-6110 MT monitors a Broadcast RT to RT transfer
Command with 2 data words on the MIL-STD-1553 bus. The HI6110 MT captures the message data and the Status Word from
the transmitting RT. Note the behavior of the FFEMPTY signal
when the first data word is read, temporarily emptying the FIFO,
before message completion.
Example 8. Broadcast RT to RT Transfer
Host Read CW2 (Transmit Command)
Host Read CW1 (Receive Command)
Host Read Data FIFO (Data Word 1)
Host Read Status Word Received
Host Read Data FIFO (Data Word 2)
STR
MIL-STD-1553 Bus
Receive
Command
Transmit
Command
Status
Word 1
From Bus Controller
Data
Word 1
Data
Word 2
From transmitting RT
VALMESS
RCMDA/B
RCVA/B
FFEMPTY
Example 9. Broadcast Mode Code without Data Word
Host Reade CW1 (Command Word)
The HI-6110 MT monitors a Broadcast Mode Command without
Data word on the MIL-STD-1553 bus. The Mode Command Word
is read by the host
STR
MIL-STD-1553 Bus
Mode Code
Command
From Bus Controller
VALMESS
RCVA/B
FFEMPTY
HOLT INTEGRATED CIRCUITS
30
HI-6110 (BUS MONITOR MODE)
EXAMPLE MT MIL-STD-1553 MESSAGE SEQUENCES
Example 11. Broadcast Mode Code with Data Word
The HI-6110 RT receives a Broadcast Mode Command with Data
word from the MIL-STD-1553 bus. The host reads the Mode Data
word received.
Host Read MODE (Mode Data)
Host Read CW1 (Command Word)
STR
Mode Code
Command
MIL-STD-1553 Bus
Mode
Data
From HI-6110 BC
VALMESS
RCVA/B
FFEMPTY
DATA BUS TIMING DIAGRAMS
DATA BUS TIMING - WRITE
REG
ADDR
DATA BUS TIMING - READ
REG
ADDR
VALID
tAWH
tAWS
VALID
tARH
tARS
tSTR
tSTR
STR
STR
tDWS
tDRS
tDWH
DATA
BUS
VALID
tDRH
VALID
DATA
BUS
tCSRS
tCSWS
tCSRH
tCSWH
CS
CS
tRWRS
tRWWS
tRWRH
tRWWH
R/W
R/W
Figure 4.
Figure 5.
Refer to AC Electrical Characteristics Table
Refer to AC Electrical Characteristics Table
HOLT INTEGRATED CIRCUITS
31
HI-6110
RECOMMENDED OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS
Supply voltage (VDD)
Supply Voltage
-0.3 V to +5 V
Logic input voltage range
VDD .................................... 3.3V... ±5%
-0.3 V DC to +3.6 V
Receiver differential voltage
10 Vp-p
Temperature Range
Driver peak output current
+1.0 A
Power dissipation at 25°C
1.0 W
Solder Temperature
Industrial ........................ -40°C to +85°C
Extended ..................... -55°C to +125°C
275°C for 10 sec.
Junction Temperature
175°C
Storage Temperature
-65°C to +150°C
NOTE:
Stresses above absolute maximum
ratings or outside recommended operating
conditions may cause permanent damage to the
device. These are stress ratings only. Operation
at the limits is not recommended.
DC ELECTRICAL CHARACTERISTICS
VDD = 3.3 V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
3.15
3.30
3.45
V
Operating Voltage
VDD
Power Supply Current
ICC1
Not Transmitting
4
10
mA
ICC2
Continuous supply current while
one bus transmits @ 100%
duty cycle, 70 ohm resistive load
750
800
mA
PD1
Not Transmitting
60
mW
PD2
Transmit one bus @ 100% duty
cycle, 70 ohm resistive load
750
mW
See Note 1 below
Device Power Dissipation
See Note 2 below
650
Min. Input Voltage
(HI)
VIH
Digital inputs
Max. Input Voltage
(LO)
VIL
Digital inputs
30%
VDD
Min. Input Current
(HI)
IIH
Digital inputs
20
µA
Max. Input Current
(LO)
IIL
Digital inputs
Pull-Up / Pull-Down Current
IPUD
Digital inputs and data bus
Min. Output Voltage
(HI)
VOH
IOUT = -1.0mA, Digital outputs
(LO)
VIH
IOUT = 1.0mA, Digital outputs
Max. Output Voltage
RECEIVER
VDD
-20
µA
275
µA
90%
VDD
10%
VDD
(Measured at Point “AD“ in Figure 6 unless otherwise specified)
Input resistance
RIN
Differential
Input capacitance
CIN
Differential
Common mode rejection ratio
CMRR
Input Level
VIN
Input common mode voltage
Detect
VTHD
No Detect
VTHND
Theshold Voltage - Transformer-coupled
Detect
VTHD
No Detect
VTHND
20
Kohm
5
40
Differential
pF
dB
9
Vp-p
-5.0
5.0
V-pk
1 Mhz Sine Wave
(Measured at Point “AD“ in Figure 6)
1.15
20.0
Vp-p
0.28
Vp-p
1 MHz Sine Wave
(Measured at Point “AT“ in Figure 7)
0.86
14.0
Vp-p
0.20
Vp-p
VICM
Threshold Voltage - Direct-coupled
=
70%
Note 1: In actual use, the highest practical transmit duty cycle is 96%, occurring when a Remote Terminal responds to a series of 32 data word
transmit commands (RT to BC) repeating with minimum intermessage gap of 4us (2us dead time) and typical HI-6110 RT response delay of 5us.
Note 2: While one bus continuously transmits, the power delivered by the 3.3VDC power supply is 3.3V x 750mA typical = 2.48W. Most of the
transmit power (2.48W - 0.65W = 1.83W) is dissipated in the bus load, not in the device.
HOLT INTEGRATED CIRCUITS
32
HI-6110
DC ELECTRICAL CHARACTERISTICS (cont.)
VDD = 3.3 V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified)
PARAMETER
TRANSMITTER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
(Measured at Point “AD” in Figure 6 unless otherwise specified)
Output Voltage
VOUT
35 ohm load
6.0
9.0
Vp-p
VOUT
70 ohm load
(Measured at Point “AT“ in Figure 7)
18.0
27.0
Vp-p
VON
Differential, inhibited
10.0
mVp-p
VDYN
35 ohm load
-90
90
mV
VDYN
70 ohm load
(Measured at Point “AT“ in Figure 7)
-250
250
mV
Output Resistance
ROUT
Differential, not transmitting
10
Output Capacitance
COUT
1 MHz sine wave
Direct coupled
Transformer coupled
Output Noise
Output Dynamic Offset Voltage
Direct coupled
Transformer coupled
Kohm
15
pF
AC ELECTRICAL CHARACTERISTICS
VDD = 3.3 V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified)
PARAMETER
TRANSMITTER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
(Measured at Point “AD” in Figure 6)
Rise time
tr
35 ohm load
100
--
300
ns
Fall Time
tf
35 ohm load
100
--
300
ns
tDI-H
Inhibited output
--
100
ns
tDI-L
Active output
--
150
ns
Inhibit Delay
PARAMETER
DATA BUS TIMING - WRITE
Address Write Setup Time
Address Write Hold Time, only writes to reg. address X010, Reset Transmit FIFO
Address Write Hold Time, all other register write operations
Data Write Setup Time
Data Write Hold Time
CS Write Setup Time
CS Write Hold Time
R/W Write Setup Time
R/W Write Hold Time
DATA BUS TIMING - READ
Address Read Setup Time
Address Read Hold Time
Data Read Setup Time
Data Read Hold Time
CS Read Setup Time
CS Read Hold Time
R/W Read Setup Time
R/W Read Hold Time
MIN
TYP
MAX
UNITS
tSTR
tAWS
tAWH
tAWH
tDWS
tDWH
tCSWS
tCSWH
tRWWS
tRWWH
50
--
--
ns
0
--
--
ns
100
--
--
ns
30
--
--
ns
30
--
--
ns
30
--
--
ns
50
--
--
ns
30
--
--
ns
0
--
--
ns
30
--
--
ns
90
--
--
ns
(See Figure 4)
Strobe STR Pulse Width
Strobe STR Pulse Width
SYMBOL
(See Figure 5)
tSTR
tARS
tARH
tDRS
tDRH
tCSRS
tCSRH
tRWRS
tRWRH
HOLT INTEGRATED CIRCUITS
33
0
--
--
ns
30
--
--
ns
--
--
150
ns
--
60
--
ns
0
--
--
ns
30
--
--
ns
20
--
--
ns
30
--
--
ns
HI-6110
TRANSMITTER
1:2.5
55 W
BUSA/B
Tx Data from
Manchester
Encoder
35 W
BUSA/B
Isolation
Transformer
TXINHA/B
Point “AD“
55 W
RECEIVER
2.5:1
55 W
Point “AD“
Rx Data to
Manchester
Decoder
35 W
55 W
Isolation
Transformer
Figure 6. Direct Coupled Test Circuits
TRANSMITTER
Point
“AT”
1:2.5
1:1.4
BUSA/B
Tx Data from
Manchester
Encoder
52.5 W
(.75 Zo)
35 W (.5 Zo)
BUSA/B
TXINHA/B
52.5 W
(.75 Zo)
Isolation
Transformer
1.4:1
Point
“AT”
Coupling
Transformer
2.5:1
52.5 W
(.75 Zo)
RECEIVER
Rx Data to
Manchester
Decoder
35 W (.5 Zo)
52.5 W
(.75 Zo)
Coupling
Transformer
Isolation
Transformer
Figure 7. Transformer Coupled Test Circuits
HEAT SINKING THE LEADLESS PLASTIC
CHIP CARRIER PACKAGE
The HI-6110PCI/T/M is packaged in a 64-pin plastic chipscale package (QFN). This package has a metal heat sink
pad on its bottom surface which is electrically isolated
from the die. The heat sink may be connected to VDD,
GND or left floating.
For optimum thermal dissipation the heat sink should be
soldered to a metalized pad on the printed circuit board.
Redundant "vias" between the exposed board surface
and an internal VDD or GND power plane will enhance
thermal conductivity.
APPLICATIONS NOTE
Holt Applications Note AN-500 provides circuit design
notes regarding the use of Holt MIL-STD-1553 data
communications devices. Layout considerations, as well
as recommended interface and protection components
are included.
HOLT INTEGRATED CIRCUITS
34
HI-6110
THERMAL CHARACTERISTICS
Data taken at VDD = 3.3V, continuous data transmission at 1 Mbit/s, single transmitter enabled.
qJA
52 pin PQFP
Mounted on
circuit board
60.9
°C / W
56°C
116°C
156°C
Heat sink pad
unsoldered
31.1
°C / W
41°C
101°C
141°C
Heat sink pad
soldered
22.8
°C / W
37°C
97°C
137°C
TA= 25°C TA= 85°C TA= 125°C
64 pin QFN
VDDLOGRTAP
RTA4
RTA3
RTA2
RTA1
RTA0
RTMODE
BCMODE
RCVA
TXINHA
-
PIN CONFIGURATION (Top View)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
HI-6110PCI / T
CONDITION
STR
R/W
CS
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
HC-6110PCI
HC-6110PCT
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
HI-6110PQI / T
JUNCTION TEMPERATURE
PACKAGE STYLE
D10
D11
D12
D13
D14
D15
RA2
RA1
RA0
BCSTART
RA3
CLK
GND
-
PART NUMBER
64 Pin Leadless Plastic Chip Carrier (QFN)
See page 1 for 52-pin PQFP Pin Configuration
HOLT INTEGRATED CIRCUITS
35
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
BUSA
VDDA
BUSA
BUSB
VDDB
BUSB
TXINHB
RCVB
FFEMPTY
RF0 / RCVCMDA
RF1 / RCVCMDB
RFLAG
VALMESS
ERROR
MR
HI-6110
ORDERING INFORMATION
HI-6110 xx x x
PART
NUMBER
Blank
F
PART
NUMBER
PACKAGE
DESCRIPTION
Tin / Lead (Sn / Pb) Solder
100% Matte Tin (Pb-free RoHS compliant)
TEMPERATURE
RANGE
FLOW
BURN
IN
I
-40°C TO +85°C
I
No
T
-55°C TO +125°C
T
No
M
-55°C TO +125°C
M
Yes
PART
NUMBER
PACKAGE
DESCRIPTION
PC
64 PIN PLASTIC 9 x 9mm CHIP SCALE QFN (64PCS) not available with “M” flow
PQ
52 PIN PLASTIC QUAD FLAT PACK PQFP (52PTQS)
HOLT INTEGRATED CIRCUITS
36
HI-6110
REVISION HISTORY
Dwg. No. Rev.
Date
Description of Change
DS6110
L
05/01/08
In BC Mode, Error Register bit 4 changed to “not used”.
In RT Mode, revised text for “Transmit Data FIFO,” “Reset Transmit Data FIFO”.
In MT Mode, revised text for “Status Word 1 Register,” “Status Word 2 Register”
In MT Mode, expanded text describing “Bus Monitor Operation (MT Mode)”
Table “DATA BUS TIMING - WRITE” added new line for Address Write Hold Time
M
08/12/08
Expanded section entitled “Bus Monitor Operation (MT/RT Mode).” This includes all text
in the section’s second, added page. Renumbered all following pages.
N
12/15/08
Revised AC Electrical Characteristics
Modified QFN and PQFP package dimensions to be consistent with current package
vendor.
O
02/06/09
P
03/19/09
Q
03/10/10
R
05/03/10
Clarified description of internal pull-up & pull-down resistors. Clarified temperature
ranges.
Clarified initialization state of the Transmit Status Word Register for Remote Terminal
Mode.
Clarified RFLAG in Pin Description Table. Power Supply Currents and Power
Dissipation revised for worst case load.
Corrected the electrical characteristic description of the heat sink pad on the bottom of
the QFN package.
HOLT INTEGRATED CIRCUITS
37
HI-6110 PACKAGE DIMENSIONS
64-PIN PLASTIC CHIP-SCALE PACKAGE (QFN)
inches (millimeters)
Package Type: 64PCS
Heat sink pad on bottom of package.
Heat sink may be left floating or
connected to VDD or GND.
.354
BSC
(9.00)
.281 ± .003
(7.125 ± .075)
.0197
BSC
(0.50)
.354
BSC
(9.00)
.281 ± .003
(7.125 ± .075)
Top View
Bottom
View
.010
typ
(0.25)
.016 ± .004
(0.40 ± .10)
.008
typ
(0.20)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
.039
max
(1.00)
52-PIN PLASTIC QUAD FLAT PACK (PQFP)
inches (millimeters)
Package Type: 52PTQS
.0256
BSC
(.65)
.394
BSC SQ
(10.0)
.520
BSC SQ
(13.2)
.0145 ± .0035
(.375 ± .075)
.035 ± .006
(.88 ± .15)
.063
typ
(1.6)
.008
min
(.20)
See Detail A
.063 max.
(1.6)
.005
R min
(.13)
.055 ± .002
(1.40 ± .05)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
HOLT INTEGRATED CIRCUITS
38
.005
R min
(.13)
DETAIL A
0° £ Q £ 7°