IDT IDT74SSTUA32866BFG

IDT74SSTUA32866
1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
1.8V CONFIGURABLE
BUFFER WITH ADDRESSPARITY TEST
FEATURES:
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IDT74SSTUA32866
When used in pairs, the C0 input of the first register is tied low and the
C0 input of the second register is tied high. The C1 input of both registers
are tied high. The QERR output of the first SSTUA32866 is left floating and
the valid error information is latched on the QERR output of the second
SSTUA32866.
If an error occurs and the QERR output is driven low, it stays latched low
for two clock cycles or until RESET is driven low. The DIMM-dependent
signals (DODT, DCKE, DCS, and CSR) are not included in the parity check.
The CO input controls the pinout configuration of the 1:2 pinout from
register A configuration (when low) to register B configuration (when high).
The C1 input controls the pinout configurationfrom 25-bit 1:1 (when low) to
14-bit 1:2 (when high). C0 and C1 should not be switched during normal
operation. They should be hard-wired to a valid low or high level to
configure the register in the desired mode. In the 25-bit 1:1 pinout
configuration, the A6, D6, and H6 terminals are driven low and should not
be used.
The device supports low-power standby operation. When RESET is low,
the differential input recievers are disabled, and undriven (floating) data,
clock, and reference voltage (VREF) inputs are allowed. In addition, when
RESET is low, all registers are reset and all outputs except QERR are forced
low. The LVCMOS RESET and Cn inputs always must be held at a valid
logic high or low level.
There are two VREF pins (A3 and T3). However, it is necessary to only
connect one of the two VREF pins to the external VREF power supply. An
unused VREF pin should be terminated with a VREF coupling capacitor.
The device also supports low-power active operation by monitoring both
system chip select (DCS and CSR) inputs and will gate the Qn and PPO
outputs from changing states when both DCS and CSR inputs are high. If
either DCS or CSR input is low, the Qn and PPO outputs will function
normally. Also, if the internal low power signal (LPS1) is high, the device
will gate the QERR output from changing states. If LPS1 is low, the QERR
output will function normally. The RESET input has priority over the DCS
and CSR control and when driven low will force the Qn and PPO outputs
low, and the QERR output high. If the DCS control functionality is not desired,
then the CSR input can be hard-wired to ground, in which case the setuptime requirement for DCS would be the same as for the other D data inputs.
To control the low-power mode with DCS only, then the CSR input should
be pulled up to VDD through a pullup resistor.
To ensure defined outputs from the register before a stable clock has been
supplied, RESET must be held in the low state during power up.
1.8V Operation
SSTL_18 style clock and data inputs
Differential CLK input
Configurable as 25-bit 1:1 or 14-bit 1:2 registered buffer
Control inputs compatible with LVCMOS levels
Flow-through architecture for optimum PCB design
Latch-up performance exceeds 100mA
ESD >2000V per MIL-STD-883, Method 3015; >200V using
machine model (C = 200pF, R = 0)
Checks parity on data inputs
Maximum operating frequency: 410MHz
Optimized for DDR2 - 400 / 533 / 667 (PC2 - 3200 / 4300 / 5300)
JEDEC R/C E, F, G, H, and J
Available in 96-pin LFBGA package
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COMMERCIAL TEMPERATURE RANGE
APPLICATIONS:
• Along with CSPUA877 DDR2 PLL, provides complete solution for
DDR2 DIMMs
DESCRIPTION:
This 25-bit 1:1 / 14-bit 1:2 configurable registered buffer is designed for
1.7V to 1.9V VDD operation. In the 1:1 pinout configuration, only one device
per DIMM is requred to drive nine SDRAM loads. In the 1:2 pinout
configuration, two devices per DIMM are required to drive eighteen
SDRAM loads. All inputs are SSTL_18, except reset (RESET) and control
(Cn) inputs, which are LVCMOS. All outputs are edge-controlled circuits
optimized for unterminated DIMM loads, and meet SSTL_18 specifications,
except the open-drain error (QERR) output.
The SSTUA32866 operates from a differential clock (CLK and CLK).
Data are registered at the crossing of CLK going high and CLK going low.
Parity is checked on the parity bit (PAR_IN) input which arrives one cycle
after the input data to which it applies. The QERR output is open drain.
When used as a single device, the C0 and C1 inputs are tied low. In this
configuration, the partial-parity-out (PPO) and QERR signals are produced
two clock cycles after the corresponding data output.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
JUNE 2005
1
c
2005 Integrated Device Technology, Inc.
DSC 6382/9
IDT74SSTUA32866
1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM (1:2) - A CONFIGURATION (POSITIVE LOGIC)
RESET
CLK
CLK
VREF
DCKE
QCKEA
1D
C1
R
DODT
QCKEB
QODTA
1D
C1
R
DCS
QODTB
QCSA
1D
C1
R
QCSB
CSR
D2
0
1
1D
Q2A
C1
R
One of 11 Channels
TO 10 OTHER CHANNELS (D3, D5, D6, D8-D14)
2
Q2B
IDT74SSTUA32866
1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM (1:2) - B CONFIGURATION (POSITIVE LOGIC)
RESET
CLK
CLK
VREF
DCKE
QCKEA
1D
C1
R
DODT
QCKEB
QODTA
1D
C1
R
DCS
QODTB
QCSA
1D
C1
R
QCSB
CSR
D1
0
1
1D
Q1A
C1
R
One of 11 Channels
TO 10 OTHER CHANNELS (D2-D6, D8-D10, D12-D13)
3
Q1B
IDT74SSTUA32866
1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION (TYPE A)
6
QCKEB
Q2B
Q3B
QODTB
Q5B
Q6B
C0
QCSB
NC
Q8B
Q9B
Q10B
Q11B
Q12B
Q13B
Q14B
5
QCKEA
Q2A
Q3A
QODTA
Q5A
Q6A
C1
QCSA
NC
Q8A
Q9A
Q10A
Q11A
Q12A
Q13A
Q14A
4
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VDD
3
VREF
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VREF
2
PPO
DNU
DNU
QERR
DNU
DNU
RESET
DCS
CSR
DNU
DNU
DNU
DNU
DNU
DNU
DNU
1
DCKE
D2
D3
DODT
D5
D6
PAR_IN
CLK
CLK
D8
D9
D10
D11
D12
D13
D14
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
96-PIN LFBGA
1:2 REGISTER (TYPE A, FRONTSIDE)
TOP VIEW
PIN CONFIGURATION (TYPE B)
6
Q1B
Q2B
Q3B
Q4B
Q5B
Q6B
C0
QCSB
NC
Q8B
Q9B
Q10B
QODTB
Q12B
Q13B
QCKEB
NC
Q8A
Q9A
Q10A
QODTA
Q12A
Q13A
QCKEA
5
Q1A
Q2A
Q3A
Q4A
Q5A
Q6A
C1
QCSA
4
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VDD
3
VREF
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VREF
2
PPO
DNU
DNU
QERR
DNU
DNU
RESET
DCS
CSR
DNU
DNU
DNU
DNU
DNU
DNU
DNU
1
D1
D2
D3
D4
D5
D6
PAR_IN
CLK
CLK
D8
D9
D10
DODT
D12
D13
DCKE
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
96-PIN LFBGA
1:2 REGISTER (TYPE B, BACKSIDE)
TOP VIEW
4
IDT74SSTUA32866
1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM (1:1)
RESET
CLK1
CLK1
VREF
DCKE
1D
C1
QCKE
C1
QOTD
C1
QCS
R
DODT
1D
R
DCS
1D
R
CSR
D2
0
1
1D
C1
R
One of 22 Channels
TO 21 OTHER CHANNELS (D3, D5, D6, D8-D25)
5
Q2
IDT74SSTUA32866
1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
6
DNU
Q15
Q16
DNU
Q17
Q18
C0
DNU
NC
Q19
Q20
Q21
Q22
Q23
Q24
Q25
5
QCKE
Q2
Q3
QODT
Q5
Q6
C1
QCS
NC
Q8
Q9
Q10
Q11
Q12
Q13
Q14
4
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VDD
3
VREF
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VREF
2
PPO
D15
D16
QERR
D17
D18
RESET
DCS
CSR
D19
D20
D21
D22
D23
D24
D25
1
DCKE
D2
D3
DODT
D5
D6
PAR_IN
CLK
CLK
D8
D9
D10
D11
D12
D13
D14
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
*Rows 3 and 4 are reserved for VDD and GND.
96-PIN LFBGA
1:1 REGISTER
TOP VIEW
96 BALL LFBGA PACKAGE ATTRIBUTES
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Top
Marking
TOP VIEW
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
1
2
3
4
5
6
BOTTOM VIEW
6
SIDE VIEW
IDT74SSTUA32866
1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
COMMERCIAL TEMPERATURE RANGE
FUNCTION TABLE (EACH FLIP-FLOP) (1)
Inputs
Qx
QCSx
QODTx, QCKEx
RESET
DCS
CSR
CLK
CLK
Dx, DODT, DCKE
Outputs
Output
Outputs
H
L
L
↑
↓
L
L
L
L
H
L
L
↑
↓
H
H
L
H
(2)
Q0(2)
H
L
L
L or H
L or H
X
Q0
H
L
H
↑
↓
L
L
L
L
H
L
H
↑
↓
H
H
L
H
X
Q0
(2)
Q0
(2)
Q0
(2)
Q0(2)
H
L
H
L or H
L or H
H
H
L
↑
↓
L
L
H
L
H
H
L
↑
↓
H
H
H
H
H
H
L
L or H
L or H
X
Q0(2)
Q0(2)
Q0(2)
H
H
H
↑
↓
L
Q0(2)
H
L
(2)
H
H
H
↑
↓
H
Q0
H
H
H
H
H
L or H
L or H
X
Q0(2)
Q0(2)
Q0(2)
L
X or Floating
X or Floating
X or Floating
X or Floating
X or Floating
L
L
L
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑ = LOW to HIGH
↓ = HIGH to LOW
2. Output level before the indicated steady-state conditions were established.
PARITY AND STANDBY FUNCTION TABLE(1)
Inputs
Outputs
RESET
DCS
CSR
CLK
CLK
Σ of Inputs = H (D1 - D25)
PAR_IN(2)
PPO(3)
QERR(4)
H
L
X
↑
↓
Even
L
L
H
H
L
X
↑
↓
Odd
L
H
L
H
L
X
↑
↓
Even
H
H
L
H
L
X
↑
↓
Odd
H
L
H
H
H
L
↑
↓
Even
L
L
H
H
H
L
↑
↓
Odd
L
H
L
H
H
L
↑
↓
Even
H
H
L
H
H
L
↑
↓
Odd
H
L
H
H
H
H
↑
↓
X
X
PPO 0
QERR0
H
X
X
L or H
L or H
X
X
PPO 0
QERR0
L
X or Floating
X or Floating
X or Floating
X or Floating
X or Floating
X or Floating
L
H
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑ = LOW to HIGH
↓ = HIGH to LOW
2. Data Inputs = D2, D3, D5, D6, D8 - D25 when C0 = 0 and C1 = 0.
Data Inputs = D2, D3, D5, D6, D8 - D14 when C0 = 0 and C1 = 1.
Data Inputs = D1 - D6, D8 - D10, D12, D13 when C0 = 1 and C1 = 1.
3. PAR_IN arrives one clock cycle (C0 = 0), or two clock cycles (C0 = 1), after the data to which it applies.
4. This transition assumes QERR is HIGH at the crossing of CLK going HIGH and CLK going LOW. If QERR is LOW, it stays latched LOW for two clock cycles or until RESET
is driven LOW.
7
IDT74SSTUA32866
1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
COMMERCIAL TEMPERATURE RANGE
LOGIC DIAGRAM (1:1)
G2
RESET
CLK
CLK
D2 - D3,
D5 - D6,
D8 - D25
VREF
H1
J1
LPS0
(Internal Node)
22
CE
CE
D
A3, T3
22
CLK
D2 - D3,
D5 - D6,
D8 - D25
Q2 - Q3,
Q5 - Q6,
Q8 - Q25
22
R
22
D2 - D3,
D5 - D6,
D8 - D25
Parity
Check
C1
G5
D
0
1
1
0
D
CLK
CLK
R
R
PAR_IN
C0
D
A2
CLK
R
CE
G1
D2
G6
CLK
2-Bit
Counter
LPS1
(Internal Node)
R
0
D
1
CLK
R
Parity Logic Diagram for 1:1 Register - A Configuration (Positive Logic); C0 = 0, C1 = 0
8
PPO
QERR
IDT74SSTUA32866
1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
COMMERCIAL TEMPERATURE RANGE
LOGIC DIAGRAM (1:2)
G2
RESET
CLK
CLK
D2 - D3,
D5 - D6,
D8 - D14
VREF
H1
J1
LPS0
(Internal Node)
11
CE
CE
D
A3, T3
11
CLK
D2 - D3,
D5 - D6,
D8 - D14
Q2A - Q3A,
Q5A - Q6A,
Q8A - Q14A
11
11
Q2B - Q3B,
Q5B - Q6B,
Q8B - Q14B
R
11
D2 - D3,
D5 - D6,
D8 - D14
Parity
Check
C1
G5
1
0
D
1
D
R
R
PAR_IN
C0
CLK
R
CE
G1
D2
G6
CLK
2-Bit
Counter
LPS1
(Internal Node)
R
0
D
1
CLK
R
Parity Logic Diagram for 1:2 Register - A Configuration (Positive Logic); C0 = 0, C1 = 1
9
PPO
0
D
CLK
CLK
A2
QERR
IDT74SSTUA32866
1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
MODE SELECT
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
VDD
(2,3)
Max.
Unit
C0
C1
–0.5 to 2.5
V
0
0
1:1 25-bit to 25-bit
Description
Supply Voltage Range
COMMERCIAL TEMPERATURE RANGE
Device Mode
Input Voltage Range
–0.5 to 2.5
V
0
1
1:2 14-bit to 28-bit, Front (Type A)
VO(2,3)
Output Voltage Range
–0.5 to VDD +0.5
V
1
0
Reserved
IIK
Input Clamp Current
±50
mA
1
1
1:2 14-bit to 28-bit, Back (Type B)
±50
mA
±50
mA
±100
mA
–65 to +150
°C
VI
VI < 0
VI > VDD
IOK
Output Clamp Current VO < 0
VO > VDD
IO
Continuous Output Current,
VO = 0 to VDD
VDD
Continuous Current through each
VDD or GND
TSTG
Storage Temperature Range
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative voltage ratings may be exceeded if the ratings of the
I/P and O/P clamp current are observed.
3. This value is limited to 2.5V maximum.
TERMINAL FUNCTIONS (ALL PINS)
Terminal
Name
Electrical
Characteristics
GND
Ground Input
Ground
Description
VDD
1.8V nominal
Power Supply Voltage
VREF
0.9V nominal
Input Reference Voltage
CLK
Differential Input
Positive Master Clock Input
CLK
Differential Input
Negative Master Clock Input
Cx
LVCMOS Input
Configuration Control Inputs
RESET
LVCMOS Input
Asynchronous Reset Input. Resets registers and disables VREF data and clock differential-input receivers.
CSR, DCS
SSTL_18 Input
Chip Select Inputs. Disables outputs Dx switching when both inputs are HIGH.
Dx
SSTL_18 Input
Data Input. Clocked in on the crossing of the rising edge of CLK and the falling edge of CLK.
DODT
SSTL_18 Input
The outputs of this register bit will not be suspended by the DCS and CSR controls
DCKE
SSTL_18 Input
The outputs of this register bit will not be suspended by the DCS and CSR controls
Qx
1.8V CMOS
Data Outputs that are suspended by the DCS and CSR controls
QCSx
1.8V CMOS
Data Output that will not be suspended by the DCS and CSR controls
QODTx
1.8V CMOS
Data Output that will not be suspended by the DCS and CSR controls
QCKEx
1.8V CMOS
Data Output that will not be suspended by the DCS and CSR controls
PAR_IN
SSTL_18 Input
Parity Input. Clocked on the rising edge of CLK one cycle after corresponding data input.
QERR
Open Drain Output
Output Error bit, generated one cycle after the corresponding data output
PPO
1.8V CMOS
Partial Parity Output. Indicates ODD parity of Data Inputs and Parity In.
10
IDT74SSTUA32866
1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
COMMERCIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, TA = 25ºC (1,2)
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
Supply Voltage
1.7
—
1.9
V
VREF
Reference Voltage
0.49 * VDD
0.5 * VDD
0.51 * VDD
V
V TT
Termination Voltage
VREF– 40mV
VREF
VREF+ 40mV
V
0
—
VDD
V
VREF+ 250mV
—
—
—
—
VREF– 250mV
VI
Input Voltage
VIH
AC High-Level Input Voltage
VIL
AC Low-Level Input Voltage
Data Inputs, CSR, DCS,
VIH
DC High-Level Input Voltage
PAR_IN
VIL
DC Low-Level Input Voltage
VIH
High-Level Input Voltage
VIL
Low-Level Input Voltage
VICR
Common Mode Input Voltage
VID
Differential Input Voltage
IOH
High-Level Output Current
Data Outputs, PPO
IOL
Low-Level Output Current
Data Outputs, PPO, QERR
TA
Operating Free-Air Temperature
0
V
VREF+ 125mV
—
—
—
—
VREF– 125mV
RESET, Cx
0.65 * VDD
—
—
V
RESET, Cx
—
—
0.35 * VDD
V
CLK, CLK
0.675
—
1.125
V
CLK, CLK
600
—
—
mV
—
—
–8
mA
—
—
8
—
70
°C
NOTES:
1. The RESET and Cx inputs of the device must be held at valid levels (not floating) to ensure proper device operation.
2. The differential inputs must not be floating unless RESET is LOW.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0°C to +70°C, VDD = 1.8V ± 0.1V
Symbol
Parameter
Test Conditions
Min.
Typ.
VOH
Output HIGH Voltage
IOH = –6 mA
1.2
VOL
Output LOW Voltage
IOL = 6 mA
—
II
IDD
IDDD
Max.
Unit
—
—
V
—
0.5
V
VI = VDD or GND; VDD = 1.9V
—
—
±5
μA
IO = 0, VDD = 1.9V, RESET = GND
—
—
100
μA
Static Operating
IO = 0, VDD = 1.9V, RESET = VDD, VI = VIH (AC) or VIL (AC)
—
—
40
mA
Dynamic Operating
IO = 0, VDD = 1.8V, RESET = VDD, VI = VIH (AC) or VIL (AC),
—
—
—
μA/Clock
(Clock Only)
CLK and CLK Switching 50% Duty Cycle.
1:1 Mode
—
—
—
1:2 Mode
—
—
—
2.5
—
3.5
All Inputs
(1)
Static Standby
IO = 0, VDD = 1.8V, RESET = VDD,
Dynamic Operating
VI = VIH (AC) or VIL (AC), CLK and CLK Switching at
(Per Each Data Input)
50% Duty Cycle. One Data Input Switching at
MHz
μA/Clock
Half Clock Frequency, 50% Duty Cycle.
Data Inputs, CSR, PAR_IN
CI
Input
CLK and CLK
VICR = 0.9V, VID = 600mV
2
—
3
RESET
VI = VDD or GND
—
—
—
NOTE:
1. Each VREF pin (A3, T3) should be tested independently, with the other pin open circuit.
11
MHz/Data
pF
IDT74SSTUA32866
1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
COMMERCIAL TEMPERATURE RANGE
TIMING REQUIREMENTS OVER RECOMMENDED OPERATING FREE-AIR
TEMPERATURE RANGE
VDD = 1.8V ± 0.1V
Symbol
Min.
Max.
Unit
Clock Frequency
—
410
MHz
Pulse Duration, CLK, CLK HIGH or LOW
1
—
ns
tACT(1,2)
Differential Inputs Active Time
—
10
ns
tINACT(1,3)
Differential Inputs Inactive Time
—
15
ns
fCLOCK
tw
tSU
Parameter
Setup Time
tH
Hold Time
DCS before CLK↑, CLK↓, CSR HIGH; CSR before CLK↑, CLK↓, DCS HIGH
0.7
—
DCS before CLK↑, CLK↓, CSR LOW
0.5
—
DODT, DCKE, and data before CLK↑, CLK↓
0.5
—
PAR_IN before CLK↑, CLK↓
0.5
—
DCS , DODT, DCKE, and data after CLK↑, CLK↓
0.5
—
PAR_IN after CLK↑, CLK↓
0.5
—
ns
ns
NOTES:
1. This parameter is not production tested.
2. Data and VREF inputs must be low a minimum time of tACT max, after RESET is taken HIGH.
3. Data, VREF, and clock inputs must be held at valid levels (not floating) a minimum time of tINACT max, after RESET is taken LOW.
SWITCHING CHARACTERISTICS OVER RECOMMENDED FREE-AIR OPERATING
RANGE (UNLESS OTHERWISE NOTED) (1)
VDD = 1.8V ± 0.1V
Symbol
Parameter
Min
Max.
Unit
410
—
MHz
CLK and CLK to Q
1.2
1.9
ns
CLK and CLK to Q (simultaneous switching)
—
2
ns
fMAX
tPDM(2)
tPDMSS(2,3)
RESET to Q
—
3
ns
dV/dt_r
tRPHL
Output slew rate from 20% to 80%
1
4
V/ns
dV/dt_f
Output slew rate from 20% to 80%
1
4
V/ns
dV/dt_Δ(4)
Output slew rate from 20% to 80%
—
1
V/ns
CLK and CLK to PPO
0.5(5)
1.8(5)
ns
tPLH
CLK and CLK to QERR
1.2(5)
3(5)
ns
tPHL
CLK and CLK to QERR
1(5)
2.4(5)
ns
tRPHL
RESET to PPO
—
3
ns
tRPLH
RESET to QERR
—
3
ns
tPD
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS.
2. Includes 350ps of test load transmission line delay.
3. This parameter is not production tested.
4. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate).
5. For reference only. Final values to be determined.
12
IDT74SSTUA32866
1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
COMMERCIAL TEMPERATURE RANGE
REGISTER TIMING
RESET
DCS
CSR
n
n+1
n+2
n+3
CLK
CLK
tSU
tH
D1 - D25
tPD
CLK to Q
Q1 - Q25
tH
tSU
PAR_IN
tPD
CLK to Q
PPO
tPD
CLK to QERR
QERR
Timing Diagram for SSTUA32866 Used as a Single Device; C0 = 0, C1 = 0
13
tPD
CLK to QERR
n+4
IDT74SSTUA32866
1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
COMMERCIAL TEMPERATURE RANGE
REGISTER TIMING
RESET
DCS
CSR
n
n+1
n+2
n+3
n+4
CLK
CLK
tSU
tH
D1 - D14
tPD
CLK to Q
Q1 - Q14
tH
tSU
PAR_IN
tPD
CLK to PPO
PPO
tPD
CLK to QERR
tPD
CLK to QERR
QERR
(not used)
Timing Diagram for the First SSTUA32866 (1:2 Register-A Configuration) Device Used in a Pair; C0 = 0, C1 = 1
14
IDT74SSTUA32866
1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
COMMERCIAL TEMPERATURE RANGE
REGISTER TIMING
RESET
DCS
CSR
n
n+1
n+2
n+3
n+4
CLK
CLK
tSU
tH
D1 - D14
tPD
CLK to Q
Q1 - Q14
tSU
PAR_IN
tH
(1)
tPD
CLK to PPO
PPO
(not used)
tPD
CLK to QERR
tPD
CLK to QERR
QERR
Timing Diagram for the First SSTUA32866 (1:2 Register-B Configuration) Device Used in a Pair; C0 = 1, C1 = 1
15
IDT74SSTUA32866
1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS (VDD = 1.8V ± 0.1V)
VDD
DUT
RL = 1KΩ
TL = 50Ω
CLK
CLK
CLK Inputs
TL = 350ps, 50Ω
Test Point
Out
CL = 30 pF
RL = 1KΩ
Test Point
RL = 100Ω
Load Circuit
Test Point
VDD
LVCMOS
RESET
Input
VDD/2
VDD/2
0V
CLK
tACT
tINACT
90%
IDD
VICR
VICR
CLK
tPLH
VID
tPHL
VOH
10%
Output
VTT
VTT
VOL
Voltage and Current Waveforms
Inputs Active and Inactive Times
Voltage Waveforms - Propagation Delay Times
tW
Input
VICR
VICR
VID
LVCMOS
RESET
Input
Voltage Waveforms - Pulse Duration
VIH
VDD/2
VIL
tRPHL
VOH
Output
VTT
VOL
CLK
VICR
VID
CLK
Voltage Waveforms - Propagation Delay Times
tSU
tH
VIH
Input
VREF
VREF
VIL
Voltage Waveforms - Setup and Hold Times
NOTES:
1. CL includes probe and jig capacitance.
2. IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA
3. All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz, ZO = 50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. VTT = VREF = VDD/2
6. VIH = VREF + 250mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input.
7. VIL = VREF - 250mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input.
8. VID = 600mV.
9. tPLH and tPHL are the same as tPDM.
16
IDT74SSTUA32866
1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS (VDD = 1.8V ± 0.1V)
VDD
DUT
RL = 50Ω
Out
Test Point
CL = 10 pF
Load Circuit: High-to-Low Slew-Rate Adjustment
Output
VOH
80%
20%
dv_f
VOL
dt_f
Voltage Waveforms: High-to-Low Slew-Rate Adjustment
DUT
Out
Test Point
CL = 10 pF
RL = 50Ω
Load Circuit: Low-to-High Slew-Rate Adjustment
dt_r
VOH
dv_r
80%
20%
VOL
Output
Voltage Waveforms: Low-to-High Slew-Rate Adjustment
NOTES:
1. CL includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz, ZO = 50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
17
IDT74SSTUA32866
1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS (VDD = 1.8V ± 0.1V)
VDD
Timing
Inputs
DUT
VI(PP)
VICR
VICR
RL = 1KΩ
tPLH
Out
Test Point
Output
Waveform 2
CL = 10 pF
VOH
0.15V
0V
Voltage Waveforms - Open-Drain Output LOW-to-HIGH Transition
Time with Respect to Clock Inputs
Load Circuit: QERR Output
CK
DUT
Out
Test Point
CL = 5 pF
tPLH
VI(PP)
VICR
VICR
CK
tPLH
VOH
RL = 1KΩ
VTT
Output
Load Circuit: Partial-Parity-Out Load Circuit
VOL
Voltage Waveforms - Propagation Delay Times with with Respect
to Clock Inputs
LVCMOS RESET
LVCMOS
RESET
Input
VIH
VCC
Input
VCC/2
VDD/2
VIL
0V
tPLH
tPLH
Output
Waveform 2
VOH
VOH
0.15V
Output
0V
Voltage Waveforms - Open-Drain Output LOW-to-HIGH Transition
Time with Respect to Reset Input
Timing
Inputs
VICR
VICR
VTT
VOL
Voltage Waveforms - Propagation Delay Times with with Respect
to Reset Input
VI(PP)
tPLH
Output
Waveform 1
VCC
VCC/2
VOL
Voltage Waveforms - Open-Drain Output HIGH-to-LOW Transition
Time with Respect to Clock Inputs
NOTES:
1. CL includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz, ZO = 50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
18
IDT74SSTUA32866
1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
XX
XXX
XX
SSTUA32
Temp. Range
Device Type Package
BFG
Low Profile, Fine Pitch, Ball Grid Array - Green
866
1.8V Configurable Registered Buffer with
Address-Parity Test
74
0°C to +70°C
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19
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