HI-8483 ARINC 429 Dual Line Receiver February 2012 GENERAL DESCRIPTION The HI-8483 bus interface unit is a dual differential line receiver in accordance with the requirements of the ARINC 429 bus specification. The device translates incoming ARINC 429 signals to normal CMOS/TTL levels on each of its two independent receive channels. The HI-8483 is a functional alternative to the Fairchild/Raytheon RM3283 and DEI3283. Two TTL compatible self-test inputs for testing the ARINC channels are available. They can be used to override the ARINC input data and set the channel outputs to a known state. The self-test mode checks the entire circuit including the analog line receivers and digital logic. PIN CONFIGURATIONS (Top Views) -VS - 1 TESTA - 2 CAP2B - 3 IN2B - 4 OUT2B - 5 IN2A - 6 CAP2A - 7 OUT2A - 8 +VL - 9 N/C - 10 HI-8483PSI HI-8483PST HI-8483PSM 20 - TESTB 19 - CAP1A 18 - IN1A 17 - CAP1B 16 - IN1B 15 - OUT1A 14 - GND 13 - N/C 12 - OUT1B 11 - +VS 20 - Pin Plastic Small Outline package (SOIC) (See ordering information for additional pin configurations) All the ARINC inputs have built-in hysteresis to reject noise that may be present on the ARINC bus. Additional input noise filtering can also be accomplished with external capacitors. The HI-8483 is available in a variety of ceramic & plastic packages including Small Outline (SOIC), DIP & Leadless Chip Carrier (LCC). -VS - 1 20 - TESTB TESTA - 2 19 - CAP1A CAP2B - 3 18 - IN1A OUT2B - 5 IN2A - 6 FEATURES • • • • • • 17 - CAP1B IN2B - 4 HI-8483CRI HI-8483CRT HI-8483CRM Converts ARINC 429 levels to digital data Input hysteresis for superior noise rejection 14 - GND OUT2A - 8 13 - N/C 20-Pin SOIC, DIP & LCC packages are available (DS8483 Rev. A) 12 - OUT1B 11 - +VS N/C - 10 20 - Pin Ceramic Dual In Line package (CERDIP) (See ordering information for additional pin configurations) TTL and CMOS outputs and test inputs Military screening available 15 - OUT1A CAP2A - 7 +VL - 9 Replacement for RM3283 and DEI3283 16 - IN1B TRUTH TABLE ARINC INPUTS TEST INPUTS OUTPUTS V (A) - V (B) TEST A TEST B OUT A OUT B Null 0 0 0 0 Zero 0 0 0 1 One 0 0 1 0 Don't Care 0 1 0 1 Don't Care 1 0 1 0 Don't Care 1 1 0 0 HOLT INTEGRATED CIRCUITS www.holtic.com 02/12 HI-8483 PIN DESCRIPTIONS SIGNAL FUNCTION CAP1A CAP1B CAP2A CAP2B GND IN1A IN1B IN2A IN2B OUT1A OUT1B OUT2A OUT2B TESTA TESTB +VL +VS -VS INPUT INPUT INPUT INPUT POWER ARINC INPUT ARINC INPUT ARINC INPUT ARINC INPUT OUTPUT OUTPUT OUTPUT OUTPUT INPUT INPUT POWER POWER POWER DESCRIPTION Filter capacitor input for terminal A of channel 1 Filter capacitor input for terminal B of channel 1 Filter capacitor input for terminal A of channel 2 Filter capacitor input for terminal B of channel 2 Chip 0V supply ARINC 429 input terminal A of channel 1 ARINC 429 input terminal B of channel 1 ARINC 429 input terminal A of channel 2 ARINC 429 input terminal B of channel 2 TTL output terminal A of channel 1 TTL output terminal B of channel 1 TTL output terminal A of channel 2 TTL output terminal B of channel 2 Test input terminal A Test input terminal B +5 Volts +/- 10% +15 Volts +/- 10% -15 Volts +/- 10% BLOCK DIAGRAM +VS +VL Bit Detection and Level Shifting Hysteresis IN1A IN1B Output Driver OUT1A OUT1B CAP1A CAP1B TESTA TESTB Channel Test Circuitry Voltage Reference Threshold Generator CAP2A CAP2B Bit Detection and Level Shifting Hysteresis IN2A IN2B -VS Output Driver GND FIGURE 1 - HI-8483 BLOCK DIAGRAM HOLT INTEGRATED CIRCUITS 2 OUT2A OUT2B HI-8483 FUNCTIONAL DESCRIPTION The HI-8483 contains two independent ARINC 429 receive channels, which take differently encoded ARINC level data and convert it to serial TTL level data. The HI-8483 provides two complete analog line receivers and no external components are required. ARINC LEVELS The ARINC 429 specification requires the following detection levels: STATE ONE NULL ZERO Input level-shifting resistor networks allow ARINC input voltage transients up to +/- 200V without damage to the HI8483. DIFFERENTIAL VOLTAGE +6.5V to +13V +2.5V to -2.5V -6.5V to -13V Each channel is identical, featuring symmetrical delays for better high-speed performance. Input common mode rejection is excellent and threshold voltage is stable, independent of supply voltage. Data outputs are TTL and CMOS compatible. The HI-8483 guarantees recognition of these levels with a common mode voltage with respect to GND less than ±13V for the worst case condition. Two TTL compatible test inputs (TESTA and TESTB) used to simultaneously test both ARINC channels are available. They can be used to override the ARINC input data and set the channel outputs to a known state. The input hysteresis is set to reject voltage level transitions in the undefined region between the maximum ZERO level and the minimum NULL level and the undefined region between the maximum NULL level and the minimum ONE level. Therefore, once a valid input differential voltage threshold is detected, the outputs will remain at a valid logic state until a new valid input voltage is detected. The HI-8483 contains two discrete ARINC 429 receiver channels. Each channel contains three main sections: a resistor input network, a window comparator, and a logic output buffer stage. The first stage provides over-voltage protection and biases the signal using voltage dividers, providing excellent input common mode rejection. The TESTA and TESTB inputs are provided to set the outputs to a predetermined state for built-in channel test capability. If the test inputs are not used they should be grounded. The window comparator section detects data from the input resistor network. An ARINC “high” state generates a logic “1” at OUTA and an ARINC “low” state generates a logic “1” at OUTB. An ARINC “null” state at the inputs forces both outputs to logic “0”. Threshold and hysteresis voltages are generated by an on-chip voltage reference to maintain stable switching characteristics over temperature and supply voltage variations. The output stage generates a TTL compatible logic output capable of driving 3 mA of load. NOISE The noise filter capacitors are optional and are added to provide extra noise immunity by limiting the bandwidth of the input signal before it reaches the window comparator stage. Two capacitors are required for each channel and they must be of the same value. The suggested capacitor value for 100KHz operation is 39 pF. For lower data rates, larger values of capacitance may be used to yield better noise performance. To get optimum performance, the following equation can be used to calculate capacitor value for a specific data rate: CFILTER = 3.95 x 10 F0 6 Where: CFILTER is the capacitor value in pF F0 is the input frequency 10 KHz <= F0 <= 150 KHz HOLT INTEGRATED CIRCUITS 3 HI-8483 TYPICAL APPLICATIONS APPLICATIONS The HI-8483 can be used with HI-8570 or HI-8585 Line Drivers to provide a complete analog ARINC 429 interface solution. A simple application, which can be used in systems requiring a repeater type circuit for long transmissions or for test interfaces, is given in Figure 3. More HI-8570 or HI-8585 drivers may be added to test multiple ARINC channels, as shown. The standard connections for the HI-8483 are shown in Figure 2. Decoupling of the supply should be done near the IC to avoid propagation of noise spikes due to switching transients. The ground (GND) connection should be sturdy and isolated from large switching currents to provide a quiet ground reference. +5V +15V HI-8483 ARINC CHANNEL 1 IN1A OUT1A A IN1B OUT1B B OUT2A A OUT2B B CHANNEL 1 DATA OUT TO LOGIC 39 pF CAP1A 39 pF CAP1B IN2A ARINC CHANNEL 2 IN2B 39 pF 39 pF CHANNEL 2 DATA OUT TO LOGIC CAP2A CAP2B TESTA LOGIC TEST INPUTS N/C TESTB N/C -15V FIGURE 2 - ARINC RECEIVER STANDARD CONNECTIONS ARINC INPUT CHANNEL IN1A OUT1A DATA (A) AOUT IN1B OUT1B DATA (B) BOUT 1/2 HI-8483 A B ARINC OUTPUT CHANNEL 1 HI-8570 or HI-8585 DATA (A) AOUT DATA (B) BOUT HI-8570 or HI-8585 TO ADDITIONAL CHANNELS FIGURE 3 - ARINC REPEATER CIRCUIT HOLT INTEGRATED CIRCUITS 4 A B ARINC OUTPUT CHANNEL 2 HI-8483 TIMING DIAGRAMS +10V ARINC DIFFERENTIAL INPUT 0V -10V tPLH tr 90% 50% OUTA tf 10% tPHL tPHL tPLH 50% OUTB FIGURE 4 +5V TESTA 0V +5V TESTB 0V tPTLH tr 90% 50% OUTA (test) tf 10% tPTHL tPTHL tPTLH 50% OUTB (test) FIGURE 5 HOLT INTEGRATED CIRCUITS 5 HI-8483 ABSOLUTE MAXIMUM RATINGS (Voltages referenced to Gnd = 0V) Supply Voltage, +VS: .....................................................................+20 VDC -VS: .......................................................................-20 VDC +VS to -VS: ...........................................................+36 VDC +VL: .......................................................................+7 VDC Voltage at ARINC Inputs: ...................................................-200V to +200V Operating Temperature Range: (Industrial) .........................-40°C to +85°C (Hi-Temp) ........................-55°C to +125°C (Military) ..........................-55°C to +125°C Storage Temperature Range: .........................................-65°C to +150°C Internal Power Dissipation: ..............................................................900mW Voltage at Any Other Input:.............................................-0.3V to VL + 0.3V Output Short Circuit Protected: .............................................Not Protected Soldering Temperature: (Ceramic).................................60 sec. at +300°C (Plastic - leads)........................10 sec. at +280°C (Plastic - body) ................................+260°C Max. NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS ±13.5V < VS < ±16.5V, +4.5V < VL < +5.5V, Operating temperature range (unless otherwise noted) LIMITS PARAMETER SYMBOL CONDITIONS ICC +/-VS = +/- 16.5V, VL = 5.0V Test Inputs = 0V Test Inputs = 5V 6.0 6.0 mA mA +/-VS = +/- 16.5V, VL = 5.0V Test Inputs = 0V Test Inputs = 5V 12.0 18.5 mA mA +/-VS = +/- 16.5V, VL = 5.0V Test Inputs = 0V Test Inputs = 5V 9.0 17.5 mA mA MIN TYP MAX UNIT Power Supplies +VS (+15V) Supply Current -VS (-15V) Supply Current IEE +VL (+5V) Supply Current IL ARINC 429 Inputs Null - to - One Transition V(INA) - V(INB) VHH +/-VS = +/- 15.0V, VL = 5.0V Test inputs = 0V, V(INB) = -2.50V TA = 25°C 5.70 6.30 V One - to - Null Transition V(INA) - V(INB) VHL +/-VS = +/- 15.0V, VL = 5.0V Test inputs = 0V, V(INB) = -2.50V 4.50 5.50 V VHHYS VHH - VHL TA = 25°C 0.8 1.2 V Null - to - Zero Transition V(INA) - V(INB) VLL +/-VS = +/- 15.0V, VL = 5.0V Test inputs = 0V, V(INB) = +2.50V TA = 25°C -6.30 -5.70 V Zero - to - Null Transition V(INA) - V(INB) VLH +/-VS = +/- 15.0V, VL = 5.0V Test inputs = 0V, V(INB) = +2.50V -5.50 -4.50 V Zero - to - Null Transition Hysteresis VLHYS VLL - VLH TA = 25°C -1.2 -0.8 V Input Common-Mode Voltage Range VCM -13 +13 V 11.5 KW One - to - Null Transition Hysteresis Input Resistor Value: Input Resistance: Input Current: Input Capacitance: (Guaranteed but not tested) Unpowered RIN INA to CAPA, INB to CAPB 8.5 10 Differential (Unpowered) To GND (Unpowered) RI RG INA to INB, INA to GND, INB to GND 30 20 50 30 Input Sink Input Source IIH IIL Differential To GND To VDD CI CG CH KW KW 200 µA µA 10 10 10 pF pF pF -450 INA to INB HOLT INTEGRATED CIRCUITS 6 HI-8483 ELECTRICAL CHARACTERISTICS (Cont.) ±13.5V < VS < ±16.5V, +4.5V < VL < +5.5V, Operating temperature range (unless otherwise noted) LIMITS PARAMETER SYMBOL CONDITIONS Input Voltage HI Input Voltage LO VIH VIL VS = +/-15V, VL=4.5V Input Sink Input Source IIH IIL VIH = 5V, VS = +/-15V, VL=5V VIL = 0.8V, VS = +/-15V, VL=5V -40 µA µA VOH VS = +/-15V, VL=5V IOH = -100 µA (TA = 25°C) IOH = -2.8 mA 4.0 3.5 V V MIN TYP MAX UNIT Logic Inputs (TESTA, TESTB) Input Voltage: Input Current: 2.0 0.9 300 V V Logic Outputs (OUTA, OUTB) Output Voltage: Input Voltage HI Input Voltage LO VOL VS = +/-15V, VL=5V IOL = 100 µA (TA = 25°C) IOL = 2.0 mA 0.1 0.8 V V Timing Parameters Output Rise Time tr CL - 60 pF 10 70 ns Output Fall Time tf CL - 60 pF 10 70 ns INA/B to OUTA/B rising edge tPLH CAPA, CAPB, CL = 60 pF 700 ns INA/B to OUTA/B falling edge tPHL CAPA, CAPB, CL = 60 pF 700 ns Matching of TPLH and TPHL tDTP | TPLH - TPHL | TESTA/B to OUTA/B rising edge tPTLH CL = 60 pF, VIN = 0.8V/2.0V 700 ns TESTA/B to OUTA/B falling edge tPTHL CL = 60 pF, VIN = 0.8V/2.0V 700 ns Propagation Delay 500 ORDERING INFORMATION & THERMAL CHARACTERISTICS HI - 8483PS x x (Plastic Wide Body SOIC) PART NUMBER Blank F PART NUMBER LEAD FINISH Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free, RoHS compliant) TEMPERATURE RANGE FLOW BURN IN I -40°C TO +85°C I NO T -55°C TO +125°C T NO M -55°C TO +125°C M YES PART NUMBER PS PACKAGE DESCRIPTION THERMAL RES. QJC 20 PIN PLASTIC SOIC WIDE BODY PACKAGE (20HW) 17°C/W HOLT INTEGRATED CIRCUITS 7 QJA 90°C/W ns HI-8483 ORDERING INFORMATION & THERMAL CHARACTERISTICS (Cont.) HI - 8483CR x (20-pin CerDIP) PART NUMBER TEMPERATURE RANGE FLOW BURN IN LEAD FINISH I -40°C TO +85°C I NO Tin / Lead (Sn / Pb) Solder T -55°C TO +125°C T NO Tin / Lead (Sn / Pb) Solder M -55°C TO +125°C M YES Tin / Lead (Sn / Pb) Solder PART NUMBER CR THERMAL RES. QJC QJA PACKAGE DESCRIPTION 20 PIN CERDIP (20D) 28°C/W 90°C/W HI - 8483CL x (20-pin Ceramic LCC) PART NUMBER TEMPERATURE RANGE FLOW BURN IN I -40°C TO +85°C I NO Gold T -55°C TO +125°C T NO Gold M -55°C TO +125°C M YES PART NUMBER CL PACKAGE DESCRIPTION CAP2B TESTA -VS TESTB CAP1A 3 2 1 20 19 4 5 6 7 8 HI-8483CLI HI-8483CLT HI-8483CLM 18 17 16 15 14 - IN1A CAP1B IN1B OUT1A GND +VL N/C +VS OUT1B N/C - 9 10 11 12 13 - Tin / Lead (Sn / Pb) Solder THERMAL RES. QJC 20 PIN CERAMIC LEADLESS CHIP CARRIER (20S) 25°C/W ADDITIONAL HI-8483 PIN CONFIGURATION IN2B OUT2B IN2A CAP2A OUT2A LEAD FINISH 20 - Pin Ceramic Leadless Chip Carrier (LCC) (See first page of data sheet for additional pin configurations) HOLT INTEGRATED CIRCUITS 8 QJA 85°C/W HI-8483 REVISION HISTORY Dwg. No. Rev. Date Description of Change DS8483 03/22/10 02/29/12 Initial Release Correct typo in part numbers on Ordering Information, page 8. Change soldering temperature (Plastic - body) in Absolute Maximum Ratings from 220C to 260C. NEW A HOLT INTEGRATED CIRCUITS 9 HI-8483 PACKAGE DIMENSIONS inches (millimeters) 20-PIN PLASTIC SMALL OUTLINE (SOIC) - WB (Wide Body) Package Type: 20HW .5035 ± .0075 (12.789 ± .191) .0105 ± .0015 (.2667 ± .0381) .4065 ± .0125 (10.325 ± .318) .295 ± .002 (7.493 ± .051) See Detail A .018 typ (.457) .090 ± .010 (2.286 ± .254) 0° to 8° .050 BSC (1.27) .0075 ± .0035 (.191 ± .089) .033 ± .017 (.838 ± .432) Detail A BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) inches (millimeters) 20-PIN CERDIP 1.060 max (26.924 max) .005 min (.127 min) Package Type: 20D .070 max (1.778 max) .288 ±.005 (7.315 ± .127) .060 typ (1.524 typ) .100 BSC (2.54) .310 ± .010 (7.874 ± .254) .170 max (4.318 max) .200 max (5.080 max) .015 min (.381 min) .125 min (3.175 min) .018 ±.003 (.457 ±.760) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HOLT INTEGRATED CIRCUITS 10 0° to 15° .010 ±.002 (.254 ±.051) HI-8483 PACKAGE DIMENSIONS inches (millimeters) 20-PIN CERAMIC LEADLESS CHIP CARRIER Package Type: 20S .040 x 45° 3 PLCS (1.016 x 45°) .020 INDEX (.508) PIN 1 .175 ±.004 (4.445 ±.101) .080 ±.020 (2.032 ±.508) .075 ± .004 (1.905 ±.101) .009R .006 (.229R ±.152) PIN 1 .050 ±.005 (1.270 ±.127) .350 ±.008 (8.890 ±.203) SQ. .025 ±.003 (.635 ±.076) .050 BSC (1.270) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HOLT INTEGRATED CIRCUITS 11