240pin DDR3L SDRAM VLP Registered DIMM DDR3L SDRAM VLP Registered DIMM Based on 4Gb M-die HMT451V7MFR8A HMT41GV7MFR4A HMT41GV7MFR8A HMT82GV7MMR4A HMT82GV7MMR8A *SK hynix reserves the right to change products or specifications without notice. Rev. 1.0 / Aug. 2012 1 Revision History Revision No. History Draft Date 0.1 Initial Release Dec.2011 1.0 Latest JEDEC Spec Updated Aug.2012 Rev. 1.0 / Aug. 2012 Remark 2 Description SK hynix VLP (Very Low Profile) registered DDR3L SDRAM DIMMs (Registered Double Data Rate Synchronous DRAM Dual In-Line Memory Modules) are low power, high-speed operation memory modules that use DDR3L SDRAM devices. These Registered SDRAM DIMMs are intended for use as main memory when installed in systems such as servers and workstations. Features • • • • • • • • • • • • • Power Supply: VDD=1.35V (1.283V to 1.45V) VDDQ = 1.35V (1.283V to 1.45V) VDDSPD=3.0V to 3.6V Functionality and operations comply with the DDR3L SDRAM datasheet 8 internal banks Data transfer rates: PC3-10600, PC3-8500 Bi-Directional Differential Data Strobe 8 bit pre-fetch Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop) Supports ECC error correction and detection On-Die Termination (ODT) Temperature sensor with integrated SPD This product is in compliance with the RoHS directive. Ordering Information Density Organization Component Composition # of ranks FDHS HMT451V7MFR8A-G7/H9 4GB 512Mx72 512Mx8(H5TC4G83MFR)*9 1 X HMT41GV7MFR4A-G7/H9 8GB 1Gx72 1Gx4(H5TC4G43MFR)*18 1 X HMT41GV7MFR8A-G7/H9 8GB 1Gx72 512Mx8(H5TC4G83MFR)*18 2 X HMT82GV7MMR4A-G7/H9 16GB 2Gx72 DDP 2Gx4(H5TC8G43MMR)*36 2 O HMT82GV7MMR8A-G7/H9 16GB 2Gx72 DDP 1Gx8(H5TC8G83MMR)*36 4 O Part Number * In order to uninstall FDHS, please contact sales administrator Rev. 1.0 / Aug. 2012 3 Key Parameters MT/s Grade tCK (ns) CAS Latency (tCK) tRCD (ns) tRP (ns) tRAS (ns) tRC (ns) CL-tRCD-tRP DDR3L-1066 -G7 1.875 7 13.125 13.125 37.5 50.625 7-7-7 DDR3L-1333 -H9 1.5 9 36 49.5 (49.125)* 9-9-9 13.5 13.5 (13.125)* (13.125)* *SK hynix DRAM devices support optional downbinning to CL7. SPD setting is programmed to match. Speed Grade Frequency [MHz] Grade Remark CL6 CL7 CL8 -G7 800 1066 1066 -H9 800 1066 1066 CL9 CL10 1333 1333 Address Table 4GB(1Rx8) 8GB(1Rx4) 8GB(2Rx8) 16GB(2Rx4) 16GB(4Rx8) Refresh Method 8K/64ms 8K/64ms 8K/64ms 8K/64ms 8K/64ms Row Address A0-A15 A0-A15 A0-A15 A0-A15 A0-A15 Column Address A0-A9 A0-A9, A11 A0-A9 A0-A9, A11 A0-A9 Bank Address BA0-BA2 BA0-BA2 BA0-BA2 BA0-BA2 BA0-BA2 Page Size 1KB 1KB 1KB 1KB 1KB Rev. 1.0 / Aug. 2012 4 Pin Descriptions Pin Name Description Num ber Pin Name Description Num ber CK0 Clock Input, positive line 1 ODT[1:0] On Die Termination Inputs 2 CK0 Clock Input, negative line 1 DQ[63:0] Data Input/Output 64 CK1 Clock Input, positive line 1 CB[7:0] CK1 Clock Input, negative line 1 DQS[8:0] Clock Enables 2 DQS[8:0] RAS Row Address Strobe 1 DM[8:0]/ DQS[17:9], TDQS[17:9] CAS Column Address Strobe 1 DQS[17:9], TDQS[17:9] WE Write Enable 1 EVENT S[3:0] Chip Selects 4 TEST Memory bus test tool (Not Connected and Not Usable on DIMMs) 1 Address Inputs 14 RESET Register and SDRAM control pin 1 A10/AP Address Input/Autoprecharge 1 VDD Power Supply 22 A12/BC Address Input/Burst chop 1 VSS Ground 59 BA[2:0] SDRAM Bank Addresses 3 VREFDQ Reference Voltage for DQ 1 Reference Voltage for CA 1 Termination Voltage 4 SPD Power 1 CKE[1:0] A[9:0],A11, A[15:13] SCL Serial Presence Detect (SPD) Clock Input 1 VREFCA SDA SPD Data Input/Output 1 VTT SA[2:0] SPD Address Inputs 3 VDDSPD Par_In Parity bit for the Address and Control bus 1 Err_Out Parity error found on the Address and Control bus 1 Rev. 1.0 / Aug. 2012 Data check bits Input/Output Data strobes Data strobes, negative line Data Masks / Data strobes, Termination data strobes Data strobes, negative line, Termination data strobes Reserved for optional hardware temperature sensing 8 9 9 9 9 1 5 Input/Output Functional Descriptions Symbol Type Polarity CK0 IN Positive Line Positive line of the differential pair of system clock inputs that drives input to the onDIMM Clock Driver. CK0 IN Negative Line Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM Clock Driver. CK1 IN Positive Line Terminated but not used on RDIMMs. CK1 IN Negative Line Terminated but not used on RDIMMs. IN Active High CKE[1:0] Function CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank) Enables the command decoders for the associated rank of SDRAM when low and disables decoders when high. When decoders are disabled, new commands are ignored and previous operations continue. Other combinations of these input signals perform unique functions, including disabling all outputs (except CKE and ODT) of the register(s) on the DIMM or accessing internal control words in the register device(s). For modules with two registers, S[3:2] operate similarly to S[1:0] for the second set of register outputs or register control words. S[3:0] IN Active Low ODT[1:0] IN Active High On-Die Termination control signals RAS, CAS, WE IN Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM. VREFDQ Supply Reference voltage for DQ0-DQ63 and CB0-CB7. VREFCA Supply Reference voltage for A0-A15, BA0-BA2, RAS, CAS, WE, S0, S1, CKE0, CKE1, Par_In, ODT0 and ODT1. BA[2:0] IN — Selects which SDRAM bank of eight is activated. BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines mode register is to be accessed during an MRS cycle. A[15:13, 12/BC,11, 10/AP,[9:0] IN — Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write commands to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is also utilized for BL 4/8 identification for ‘’BL on the fly’’ during CAS command. The address inputs also provide the op-code during Mode Register Set commands. DQ[63:0], CB[7:0] I/O — Data and Check Bit Input/Output pins DM[8:0] IN Active High VDD, VSS Supply Power and ground for the DDR SDRAM input buffers and core logic. VTT Supply Termination Voltage for Address/Command/Control/Clock nets. Rev. 1.0 / Aug. 2012 Masks write data when high, issued concurrently with input data. 6 Symbol Type Polarity Function DQS[17:0] I/O Positive Edge Positive line of the differential data strobe for input and output data. DQS[17:0] I/O Negative Edge Negative line of the differential data strobe for input and output data. TDQS/TDQS is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in MR1,DRAM will enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When disabled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. X4 DRAMs must disable the TDQS function via mode register A11=0 in MR1 TDQS[17:9] TDQS[17:9] OUT SA[2:0] IN — These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range. SDA I/O — This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to VDDSPD on the system planar to act as a pullup. SCL IN — This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to VDDSPD on the system planar to act as a pullup. EVENT OUT (open drain) VDDSPD Supply Serial EEPROM positive power supply wired to a separate power pin at the connector which supports from 3.0 Volt to 3.6 Volt (nominal 3.3V) operation. RESET IN The RESET pin is connected to the RESET pin on the register and to the RESET pin on the DRAM. Par_In IN Parity bit for the Address and Control bus. (“1 “: Odd, “0 “: Even) Err_Out OUT (open drain) TEST Rev. 1.0 / Aug. 2012 This signal indicates that a thermal event has been detected in the thermal sensing device.The system should guarantee the electrical level requirement is met for the Active Low EVENT pin on TS/SPD part. No pull-up resister is provided on DIMM. Parity error detected on the Address and Control bus. A resistor may be connected from Err_Out bus line to VDD on the system planar to act as a pull up. Used by memory bus analysis tools (unused (NC) on memory DIMMs) 7 Pin Assignments Pin # Front Side (left 1–60) Pin # Back Side (right 121–180) Pin # Front Side (left 61–120) Pin # Back Side (right 181–240) 1 VREFDQ 121 VSS 61 A2 181 A1 2 VSS 122 DQ4 62 VDD 182 VDD 3 DQ0 123 DQ5 63 NC, CK1 183 VDD 4 DQ1 124 VSS 64 NC, CK1 184 CK0 5 VSS 125 DM0,DQS9, TDQS9 65 VDD 185 CK0 6 DQS0 126 NC,DQS9, TDQS9 66 VDD 186 VDD 7 DQS0 127 VSS 67 VREFCA 187 EVENT, NC 8 VSS 128 DQ6 68 Par_In, NC 188 A0 9 DQ2 129 DQ7 69 VDD 189 VDD 10 DQ3 130 VSS 70 A10 / AP 190 BA1 11 VSS 131 DQ12 71 BA0 191 VDD 12 DQ8 132 DQ13 72 VDD 192 RAS 13 DQ9 133 VSS 73 WE 193 S0 14 VSS 134 DM1,DQS10, TDQS10 74 CAS 194 VDD 15 DQS1 135 NC,DQS10, TDQS10 75 VDD 195 ODT0 16 DQS1 136 VSS 76 S1, NC 196 A13 17 VSS 137 DQ14 77 ODT1, NC 197 VDD 18 DQ10 138 DQ15 78 VDD 198 S3, NC 19 DQ11 139 VSS 79 S2, NC 199 VSS 20 VSS 140 DQ20 80 VSS 200 DQ36 21 DQ16 141 DQ21 81 DQ32 201 DQ37 22 DQ17 142 VSS 82 DQ33 202 VSS 83 VSS 203 DM4,DQS13, TDQS13 23 VSS 143 DM2,DQS11, TDQS11 24 DQS2 144 NC,DQS11, TDQS11 84 DQS4 204 NC,DQS13, TDQS13 25 DQS2 145 VSS 85 DQS4 205 VSS 26 VSS 146 DQ22 86 VSS 206 DQ38 27 DQ18 147 DQ23 87 DQ34 207 DQ39 28 DQ19 148 VSS 88 DQ35 208 VSS 29 VSS 149 DQ28 89 VSS 209 DQ44 30 DQ24 150 DQ29 90 DQ40 210 DQ45 31 DQ25 151 VSS 91 DQ41 211 VSS NC = No Connect; RFU = Reserved Future Use Rev. 1.0 / Aug. 2012 8 Pin # Front Side (left 1–60) Pin # Back Side (right 121–180) Pin # Front Side (left 61–120) Pin # Back Side (right 181–240) 32 VSS 152 DM3,DQS12, TDQS12 92 VSS 212 DM5,DQS14, TDQS14 33 DQS3 153 NC,DQS12, TDQS12 93 DQS5 213 NC,DQS14, TDQS14 34 DQS3 154 VSS 94 DQS5 214 VSS 35 VSS 155 DQ30 95 VSS 215 DQ46 36 DQ26 156 DQ31 96 DQ42 216 DQ47 37 DQ27 157 VSS 97 DQ43 217 VSS 38 VSS 158 CB4, NC 98 VSS 218 DQ52 39 CB0, NC 159 CB5, NC 99 DQ48 219 DQ53 40 CB1, NC 160 VSS 100 DQ49 220 VSS 41 VSS 161 NC,DM8,DQS17, TDQS17 101 VSS 221 DM6,DQS15, TDQS15 42 DQS8 162 NC,DQS17, TDQS17 102 DQS6 222 NC,DQS15, TDQS15 43 DQS8 163 VSS 103 DQS6 223 VSS 44 VSS 164 CB6, NC 104 VSS 224 DQ54 45 CB2, NC 165 CB7, NC 105 DQ50 225 DQ55 46 CB3, NC 166 VSS 106 DQ51 226 VSS 47 VSS 167 NC(TEST) 107 VSS 227 DQ60 VTT, NC 168 RESET 108 DQ56 228 DQ61 109 DQ57 229 VSS 48 KEY KEY 49 VTT, NC 169 CKE1, NC 110 VSS 230 DM7,DQS16, TDQS16 50 CKE0 170 VDD 111 DQS7 231 NC,DQS16, TDQS16 51 VDD 171 A15 112 DQS7 232 VSS 52 BA2 172 A14 113 VSS 233 DQ62 53 Err_Out, NC 173 VDD 114 DQ58 234 DQ63 54 VDD 174 A12 / BC 115 DQ59 235 VSS 55 A11 175 A9 116 VSS 236 VDDSPD 56 A7 176 VDD 117 SA0 237 SA1 57 VDD 177 A8 118 SCL 238 SDA 58 A5 178 A6 119 SA2 239 VSS 59 A4 179 VDD 120 VTT 240 VTT 60 VDD 180 A3 NC = No Connect; RFU = Reserved Future Use Rev. 1.0 / Aug. 2012 9 Registering Clock Driver Specifications Capacitance Values Symbol Parameter Conditions Min Typ Max Unit 1.5 - 2.5 pF Input capacitance, CK, CK, FBIN, FBIN 2 - 3 pF Input capacitance, CK, CK, FBIN, FBIN (DDR3-1600) 1.5 - 2.5 pF - - 3 pF Input capacitance, Data inputs CI CIR Input capacitance, RESET, MIRROR, QCSEN VI = VDD or GND; VDD = 1.5v Input & Output Timing Requirements Symbol Parameter DDR3-800 1066/1333 Conditions Unit Min Max fclock Input clock frequency Application frequency 300 670 Mhz fTEST Input clock frequency Test frequency 70 300 Mhz tSU Setup time Input valid before CK/CK 100 - ps tH Hold time Input to remain valid after CK/CK 175 - ps tPDM Propagation delay, single-bit switching CK/CK to output 0.65 1.0 ns tDIS Output disable time (1/2-Clock prelaunch) Yn/Yn to output float 0.5 + tQSK1(min) - ps tEN Output enable time (1/2-Clock prelaunch) Output driving to Yn/Yn 0.5 - tQSK1(max) - ps Rev. 1.0 / Aug. 2012 10 On DIMM Thermal Sensor The DDR3 SDRAM DIMM temperature is monitored by integrated thermal sensor. The integrated thermal sensor comply with JEDEC “TSE2002av, Serial Presence Detect with Temperature Sensor”. Connection of Thermal Sensor EVENT SCL SDA SA0 SPD with SA1 Integrated SA2 TS EVENT SCL SA0 SDA SA1 SA2 Temperature-to-Digital Conversion Performance Parameter Temperature Sensor Accuracy (Grade B) Resolution Rev. 1.0 / Aug. 2012 Condition Min Typ Max Unit Active Range, 75°C < TA < 95°C - ± 0.5 ± 1.0 °C Monitor Range, 40°C < TA < 125°C - ± 1.0 ± 2.0 °C -20°C < TA < 125°C - ± 2.0 ± 3.0 °C 0.25 °C 11 Functional Block Diagram A[N:0] RAS_n CAS_n WE_n CKE0 ODT0 CK0_t CK0_c CK1_t CK1_c PAR_IN 120 Ω ±1% 1: 2 R E G I S T E R / P L L 120 Ω ±1% RESET_n OERR_n RST_n RS0A_n → CS0_n: SDRAMs D[3:0], D8 RS0BCK_n → CS0_n: SDRAMs D[7:4] RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D8 RBA[N:0]B → BA[N:0]: SDRAMs D[7:4] RA[N:0]A → A[N:0]: SDRAMs D[3:0], D8 RA[N:0]B → A[N:0]: SDRAMs D[7:4] RRASA_n → RAS_n: SDRAMs D[3:0], D8 RRASB_n → RAS_n: SDRAMs D[7:4] RCASA_n → CAS_n: SDRAMs D[3:0], D8 RCASB_n → CAS_n: SDRAMs D[7:4] RWEA_n → WE_n: SDRAMs D[3:0], D8 RWEB_n → WE_n: SDRAMs D[7:4] RCKE0A → CKE0: SDRAMs D[3:0], D8 RCKE0B → CKE0: SDRAMs D[7:4] RODT0A → ODT0: SDRAMs D[3:0], D8 RODT0B → ODT0: SDRAMs D[7:4] PCK0A_t → CK_t: SDRAMs D[3:0], D8 PCK0B_t → CK_t: SDRAMs D[7:4] PCK0A_c → CK_c: SDRAMs D[3:0], D8 PCK0B_c → CK_c: SDRAMs D[7:4] A[N:O]B /BA[N:O]B RODT0B PCK0B_c RCKE0B RWEB_n PCK0B_t A[O:N]/BA[O:N] ODT CK_n CKE CK_t CAS_n WE_n ODT CK_n CKE CK_t WE_n CAS_n D5 ODT CK_n CKE CK_t WE_n CAS_n D6 A[O:N]/BA[N:O] ZQ ODT CK_n CKE CK_t D7 A[N:O]/BA[N:O] ZQ WE_n RAS_n CS_n A[N:O]/BA[N:O] ODT CK_n CKE CK_t Vtt S0_n S1_n BA[N:0] ZQ A[O:N]/BA[N:O] DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ D0 RCASB_n DQS7_t DQS7_c DM7/DQS16_t DQS16_c DQ[63:56] RAS_n DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] CS_n DQS6_t DQS6_c DM6/DQS15-t DQS15_c DQ[55:48] D4 CAS_n ODT A[O:N]/BA[N:O] A[N:O]/BA[N:O] ODT DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] RAS_n ODT ODT CK_n CKE CK_n CKE CK_n CKE RS0B_n RRASB_n A[N:O]A /BA[N:O]A RODT0A PCK0A_c RCKE0A CK_n CKE CK_t CK_t D1 WE_n CAS_n RAS_n CK_t WE_n ZQ DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] CS_n CK_t CAS_n WE_n WE_n CAS_n CAS_n CAS_n D2 WE_n RAS_n CS_n CS_n RAS_n RAS_n ZQ DQS5_t DQS5_c DM5/DQS14_t DQS14_c DQ[47:40] CS_n DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] D3 DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] RAS_n DQS1_t DQS1_c DM1/DQS10_t DQS10_c DQ[15:8] ZQ ZQ DQS4_t DQS4_c DM4/DQS13_t DQS13_c DQ[39:32] CS_n DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] A[N:O]/BA[N:O] DQS2_t DQS2_c DM2/DQS11_t DQS11_c DQ[23:16] D8 A[O:N]/BA[N:O] DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] RAS_n DQS3_t DQS3_c DM3/DQS12_t DQS12_c DQ[31:24] CS_n DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] CS_n RWEA_n ZQ DQS8_t DQS8_c DM8/DQS17_t DQS17_c CB[7:0] DQS0_t DQS0_c DM0/DQS9_t DQS9_c DQ[7:0] PCK0A_t RS0A_n RRASA_n RCASA_n 4GB, 512Mx72 Module(1Rank of x8) Vtt VDDSPD SPD VDD D0–D8 VTT VREFCA D0–D8 VREFDQ D0–D8 VSS D0–D8 Note: 1.DQ-to-I/O wiring may be changed within byte. 2.ZQ resistors are 240 Ω ±1%.For all other resistor values refer to the appropriate wiring diagram. VDDSPD EVENT SCL SDA VDDSPD SA0 SA0 EVENT SPD with SA1 Integrated SA2 SCL TS SDA VSS SA1 SA2 VSS Plan to use SPD with Integrated TS of Class B and might be changed on customer’s requests. For more details of SPD and Thermal sensor, please contact local SK SK hynix sales representative Err_Out_n RST_n: SDRAMs D[8:0] S[3:2], CKE1, ODT1, are NC (Unused register inputs ODT1 and CKE1 have a 120...330 Ω resistor to ground Rev. 1.0 / Aug. 2012 12 ODT CK_c CKE CK_t VSS A[N:O]/BA[N:O] ODT CK_c CKE CK_t WE_n CAS_n VSS A[N:O]/BA[N:O] ODT CK_c CKE CK_t VSS A[N:O]/BA[N:O] ODT CK_t CK_c CKE D15 ODT CK_c CKE VSS D16 A[N:O]/BA[N:O] ZQ CK_t RAS_n CS_n CAS_n ZQ CAS_n RAS_n CS_n D14 CAS_n ODT A[N:O]/BA[N:O] A[N:O]/BA[N:O] ODT CK_c CKE D7 RAS_n DQS_t DQS_c DM DQ [3:0] ZQ WE_n DQS16_t DQS16_c VSS DQ[63:60] ZQ RAS_n A[N:O]/BA[N:O] ODT CK_c CKE CK_c CKE D6 D13 WE_n DQS_t DQS_c DM DQ [3:0] ZQ ZQ WE_n DQS15_t DQS15_c VSS DQ[55;52] CS_n VSS VSS A[N:O]/BA[N:O] DQS_t DQS_c DM DQ [3:0] VSS ODT VSS DQS14_t DQS14_c VSS DQ[47:44] CS_n RODT0B A[O:N]B /BA[O:N]B RWEB_n PCK0B_t RCASB_n PCK0B_c RCKE0B CK_c CKE CK_t WE_n CK_t WE_n CAS_n CAS_n CAS_n CAS_n RAS_n CS_n DQS_t DQS_c DM DQ [3:0] Vtt VSS D9 A[N:O]/BA[N:O] ZQ RAS_n CS_n CS_n A[N:O]/BA[N:O] ODT CK_c CKE CK_t WE_n CAS_n D10 D5 CK_t DQS_t DQS_c DM DQ [3:0] DQS13_t DQS13_c VSS DQ[39:36] ZQ WE_n DQS7_t DQS7_c VSS DQ[59:56] ZQ RAS_n A[N:O]/BA[N:O] A[N:O]/BA[N:O] ODT CK_c CKE CK_t WE_n CAS_n D11 D4 CK_t DQS_t DQS_c DM DQ [3:0] ZQ WE_n RS0B_n RRASB_n DQS6_t DQS6_c VSS DQ[51:48] ZQ RAS_n DQS_t DQS_c DM DQ [3:0] CS_n VSS A[N:O]/BA[N:O] VSS DQS5_t DQS5_c VSS DQ[43:40] VSS ODT DQS_t DQS_c DM DQ [3:0] VSS ODT CK_c CKE CK_t WE_n CAS_n D12 WE_n CS_n RAS_n RAS_n CS_n DQS4_t DQS4_c VSS DQ[35:32] ZQ CAS_n A[N:O]/BA[N:O] ODT CK_c CKE CK_t WE_n D0 CK_c CKE DQS_t DQS_c DM DQ [3:0] ZQ D17 CK_t DQS9_t DQS9_c VSS DQ[7:4] CS_n A[N:O]/BA[N:O] ODT CK_c CKE CK_t WE_n CAS_n D1 ZQ WE_n DQS_t DQS_c DM DQ [3:0] CAS_n DQS10_t DQS10_c VSS DQ[15:12] ZQ RAS_n A[N:O]/BA[N:O] ODT CK_c CKE CK_t WE_n CAS_n D2 RAS_n DQS_t DQS_c DM DQ [3:0] CS_n DQS11_t DQS11_c VSS DQ23:20] ZQ RAS_n A[N:O]/BA[N:O] ODT CK_c CKE CK_t WE_n CAS_n D3 CS_n PCK0A_c RCKE0A RODT0A RWEA_n PCK0A_t A[N:O]A /BA[N:O]A VSS CAS_n DQS_t DQS_c DM DQ [3:0] ZQ CAS_n CS_n RAS_n RAS_n CS_n CS_n RAS_n RAS_n CS_n A[N:O]/BA[N:O] DQS_t DQS_c DM DQ [3:0] VSS DQS0_t DQS0_c VSS DQ[3:0] DQS12_t DQS12_c VSS DQ[31:28] VSS DQS_t DQS_c DM DQ [3:0] DQS_t DQS_c DM DQ [3:0] VSS DQS1_t DQS1_c VSS DQ[11;8] DQS17_t DQS17_c VSS CB[7:4] VSS DQS_t DQS_c DM DQ [3:0] ODT DQS2_t DQS2_c VSS DQ[19:16] D8 CK_c CKE DQS_t DQS_c DM DQ [3:0] ZQ CK_t DQS3_t DQS3_c VSS DQ[27:24] RAS_n DQS_t DQS_c DM DQ [3:0] CS_n DQS8_t DQS8_c VSS CB[3:0] WE_n RS0A_n RRASA_n RCASA_n 8GB, 1Gx72 Module(1Rank of x4) - page1 Vtt VDDSPD EVENT SCL SDA VDDSPD SA0 SA0 EVENT SPD with SA1 Integrated SA2 SCL TS VSS SDA SA1 SA2 VSS Plan to use SPD with Integrated TS of Class B and might be changed on customer’s requests. For more details of SPD and Thermal sensor, please contact local SK SK hynix sales representative Note: 1. DQ-to-I/O wiring may be changed within a nibble. 2. Unless otherwise noted, resistor values are 15 5 %. 3. See the wiring diagrams for all resistors associated with the command, address and control bus. 4. ZQ resistors are 240 1 %. For all other resistor values refer to the appropriate wiring diagram. Rev. 1.0 / Aug. 2012 VDDSPD SPD VDD D0–D17 VTT VREFCA D0–D17 VREFDQ D0–D17 VSS D0–D17 13 8GB, 1Gx72 Module(1Rank of x4) - page2 S0_n 1:2 S1_n R E G I S T E R / P L L BA[2:0] A[15:0] RAS_n CAS_n WE_n CKE[1:0] ODT[1:0] RBA[2:0]A → BA[2:0]: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35 RBA[2:0]B → BA[2:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RA[15:0]A → A[15:0]: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35 RA[15:0]B → A[15:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RRASA_n → RAS_n: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35 RRASB_n → RAS_n: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RCASA_n → CAS_n: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35 RCASB_n → CAS_n: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RWEA_n → WE_n: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35 RWEB_n → WE_n: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RCKE0A → CKE[1:0]A_n: SDRAMs D[3:0], D8. D[12:9], D17 RCKE0B → CKE[1:0]B_n: SDRAMs D[21:18], D26, D[30:27], D35 RODT[1:0]A → ODT0: SDRAMs D[3:0], D8. D[12:9], D17 RODT[1:0]B → ODT0: SDRAMs D[21:18], D26, D[30:27], D35 CK0A_t_R0 → CK-t: SDRAMs D[3:0], D8, D[21:18], D26 CK0B_t_R0 → CK_t: SDRAMs D[7:4], D[25:22] CK0A_t_R1 → CK-t: SDRAMs D[12:9], D17, D[30:27], D35 CK0B_t_R1 → CK_t: SDRAMs D[16:13], D[34:31] CK0A_c_R0 → CK_c: SDRAMs D[3:0], D8, D[21:18], D26 CK0B_c_R0 → CK_c: SDRAMs D[7:4], D[25:22] CK0A_c_R1 → CK_c: SDRAMs D[12:9], D17, D[30:27], D35 CK0B_c_R1 → CK_c: SDRAMs D[16:13], D[34:31] CK0_t 120 Ω CK0_c CK1_t RS0A_n → CS0A_n: SDRAMs D[3:0], D8, D[12:9], D17 RS1A_n → CS1A_n: SDRAMs D[21:18], D26, D[30:27], D35 RS0B_n → CS0B_n: SDRAMs D[7:4], D[16:13] RS1B_n → CS1B_n: SDRAMs D[25:22], D[34:31] 120 Ω CK1_c PAR_IN Err_Out_n RESET_n * S[3:2]_n are NC Rev. 1.0 / Aug. 2012 RST_n RST_n: All SDRAMs (Note: Otherwise stated differently all resistors values on this base are 22+-5%) 14 PCK1B RODT1B A[N:O]/BA[N:O] ODT A[N:O]/BA[N:O] A[O:N]/BA[N:O] ODT ODT ODT CK_c CKE CK_c CKE CK_c CKE D16 CK_t A[N:O]/BA[N:O] CK_c CKE CK_t WE_n WE_n CK_t CK_t WE_n D15 WE_n RAS_n CS_n CAS_n CAS_n RAS_n CS_n D14 CAS_n RAS_n CS_n CS_n RAS_n DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ D13 CAS_n DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ PCK1B RCKE1B RS1B A[N:O]B /BA[N:O]B A[N:O]/BA[N:O] A[N:O]/BA[N:O] DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ A[N:O]/BA[N:O] CK_c CKE ODT ODT CK_c CKE CK_c CKE ODT ODT CK_c CKE DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ A[N:O]/BA[N:O] PCK0B RCKE0B RODT0B RWEB RCASB PCK0B CK_t WE_n WE_n CK_t CK_t RAS_n CS_n CS_n RAS_n RAS_n CS_n D7 ODT D9 A[N:O]/BA[N:O] Vtt VDDSPD EVENT_n SCL Vtt SDA Note: 1. DQ-to-I/O wiring may be changed within a byte. 2. Unless otherwise noted, resistor values are 15 Ω ±5%. 3. ZQ resistors are 240 Ω ±1%. For all other resistor values refer to the appropriate wiring diagram. 4. See the wiring diagrams for all resistors associated with the command, address and control bus. Rev. 1.0 / Aug. 2012 WE_n DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ D6 CK_t DQS7_t DQS7_c DM7/DQS16_t DQS16_c DQ[63:56] D5 WE_n RS0B RRASB DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ CAS_n DQS6_t DQS6_c DM6/DQS15_t DQS15_c DQ55:48] RAS_n DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ CS_n DQS5_t DQS5_c DM5/DQS14_t DQS14_ DQ[47:40] D4 CAS_n DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ CAS_n DQS4_t DQS4_c DM4/DQS13-t DQS13_c DQ[39:32] CAS_n RODT1A ODT A[N:O]/BA[N:O] A[N:O]/BA[N:O] ODT ODT A[N:O]/BA[N:O] ODT CK_c CKE CK_c CKE A[O:N]/BA[N:O] PCK1A_t CK_t WE_n CAS_n CK_c CKE CK_c CKE CK_t CAS_n WE_n WE_n CAS_n CK_t CK_t WE_n CAS_n D10 CK_c CKE RAS_n DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ D11 CK_t RAS_n CS_n DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ D12 WE_n RAS_n CS_n DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ D17 CAS_n RAS_n CS_n DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ PCK1A_c RCKE1A RS1A_c RAS_n CS_n DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ CS_n RODT0A A[N:O]A /BA[N:O]A A[N:O]/BA[N:O] ODT ODT A[N:O]/BA[N:O] A[N:O]/BA[N:O] ODT ODT ODT A[O:N]/BA[N:O] CK_c CKE CK_c CKE CK_c CKE CK_c CKE D0 A[N:O]/BA[N:O] RWEA_n PCK0A_t RCASA_n PCK0A_c RCKE0A CK_c CKE CK_t WE_n WE_n CK_t CK_t WE_n CS_n RAS_n RAS_n CS_n CS_n RAS_n RAS_n CS_n CK_t DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ D1 WE_n DQS0_t DQS0_c DM0/DQS9_t DQS9_c DQ[7:0] D2 CK_t DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ D3 WE_n DQS1_t DQS1_c DM1/DQS10_t DQS10_c DQ[15:8] CAS_n DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ RAS_n DQS2_t DQS2_c DM2/DQS11_t DQS11_c DQ[23:16] CS_n DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ CAS_n DQS3_t DQS3_c DM3/DQS12_t DQS12_c DQ[31:24] D8 CAS_n DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ CAS_n DQS8_t DQS8_c DM8/DQS17_t DQS17_c CB[7:0] CAS_n RS0A_n RRASA_n 8GB, 1Gx72 Module(2Rank of x8) - page1 VDDSPD SA0 SA0 EVENT SPD with SA1 Integrated SA2 SCL TS VSS SDA SA1 SA2 VSS Plan to use SPD with Integrated TS of Class B and might be changed on customer’s requests. For more details of SPD and Thermal sensor, please contact local SK SK hynix sales representative VDDSPD Serial PD VDD D0–D17 VTT VREFCA D0–D17 VREFDQ D0–D17 VSS D0–D17 D0–D17 15 8GB, 1Gx72 Module(2Rank of x8) - page2 S0_n 1:2 S1_n S[3:2] NC R E G I S T E R / P L L BA[N:0] A[N:0] RAS_n CAS_n WE_n CKE0 ODT0 RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D[12:8], D17 RBA[N:0]B → BA[N:0]: SDRAMs D[7:4], D[16:13] RA[N:0]A → A[N:0]: SDRAMs D[3:0], D[12:8], D17 RA[N:0]B → A[N:0]: SDRAMs D[7:4], D[16:13] RRASA_n → RAS_n: SDRAMs D[3:0], D[12:8], D17 RRASB_n → RAS_n: SDRAMs D[7:4], D[16:13] RCASA_n → CAS_n: SDRAMs D[3:0], D[12:8], D17 RCASB_n → CAS_n: SDRAMs D[7:4], D[16:13] RWEA_n → WE_n: SDRAMs D[3:0], D[12:8], D17 RWEB_n → WE_n: SDRAMs D[7:4], D[16:13] RCKE0A → CKE0: SDRAMs D[3:0], D8 RCKE0B → CKE0: SDRAMs D[7:4] RODT0A → ODT0: SDRAMs D[3:0], D8 RODT0B → ODT0: SDRAMs D[7:4] PCK0A_t → CK-t: SDRAMs D[3:0], D8 PCK0B_t → CK_t: SDRAMs D[7:4] CK0_t 120 Ω PCK0A_c → CK_c: SDRAMs D[3:0], D8 PCK0B_c → CK_c: SDRAMs D[7:4] CK0_c CK1_t RS0A_n → CS0_n: SDRAMs D[3:0], D8 RS0B_n → CS0_n: SDRAMs D[7:4] 120 Ω CK1_c PAR_IN Err_Out_n RESET_n Rev. 1.0 / Aug. 2012 RST_n RST_n: SDRAMs D[17:0] 16 16GB, 2Gx72 Module(2Rank of x4) - page1 VSS RS0_n RS1_n DM CS_n ZQ DQS0_t DQS0_c DQ[3:0] DQS_t DQS_c DQ [3:0] DQS1_t DQS1_c DQ[11:8] DQS_t DQS_c DQ [3:0] DQS2_t DQS2_c DQ[16:19] DQS_t DQS_c DQ [3:0] DQS3_t DQS3_c DQ[24:27] DQS_t DQS_c DQ [3:0] DQS4_t DQS4_c DQ[32:35] DQS_t DQS_c DQ [3:0] DQS5_t DQS5_c DQ[40:43] DQS_t DQS_c DQ [3:0] DQS6_t DQS6_c DQ[48:51] DQS_t DQS_c DQ [3:0] DQS7_t DQS7_c DQ[56:59] DQS_t DQS_c DQ [3:0] DQS8_t DQS8_c CB[3:0] DQS_t DQS_c DQ [3:0] VSS DM CS_n ZQ VSS VSS DM CS_n ZQ VSS DM CS_n ZQ VSS DM CS_n ZQ VSS DM CS_n ZQ VSS D6 DM CS_n ZQ VSS DM CS_n ZQ D8 VSS DQS12_t DQS12_c DQ[28:31] DQS_t DQS_c DQ [3:0] DQS13_t DQS13_c DQ[36:39] DQS_t DQS_c DQ [3:0] DQS14_t DQS14_c DQ[44:47] DQS_t DQS_c DQ [3:0] DQS15_t DQS15_c DQ[52:55] DQS_t DQS_c DQ [3:0] DQS16_t DQS16_c DQ[60:63] DQS_t DQS_c DQ [3:0] DQS17_t DQS17_c CB[7:4] DQS_t DQS_c DQ [3:0] DM CS_n ZQ DM CS_n ZQ DM CS_n ZQ EVENT SCL SDA VDDSPD VSS VSS DM CS_n ZQ VSS DM CS_n ZQ VSS D15 DM CS_n ZQ VSS DM CS_n ZQ D17 VSS SPD SA0 VDD D0–D17 EVENT SPD with SA1 Integrated SA2 SCL TS VSS SDA SA1 VTT VREFCA D0–D17 VREFDQ D0–D17 VSS D0–D17 VSS Plan to use SPD with Integrated TS of Class B and might be changed on customer’s requests. For more details of SPD and Thermal sensor, please contact local SK SK hynix sales representative VSS D35 SA0 SA2 VSS D34 DM CS_n ZQ DQS_t DQS_c DQ [3:0] VSS D33 DM CS_n ZQ DQS_t DQS_c DQ [3:0] D16 VSS D32 DM CS_n ZQ DQS_t DQS_c DQ [3:0] VSS D31 DM CS_n ZQ DQS_t DQS_c DQ [3:0] D14 VSS D30 DM CS_n ZQ DQS_t DQS_c DQ [3:0] VSS D29 DM CS_n ZQ DQS_t DQS_c DQ [3:0] VSS D28 DM CS_n ZQ DQS_t DQS_c DQ [3:0] D13 VDDSPD VDDSPD VSS VSS D27 DM CS_n ZQ DQS_t DQS_c DQ [3:0] D12 VSS D26 VSS D11 VSS D25 DM CS_n ZQ DQS_t DQS_c DQ [3:0] DQS_t DQS_c DQ [3:0] DM CS_n ZQ DQS_t DQS_c DQ [3:0] D10 VSS D24 DM CS_n ZQ DQS_t DQS_c DQ [3:0] D7 DQS11_t DQS11_c DQ[20:23] DM CS_n ZQ VSS D23 DM CS_n ZQ DQS_t DQS_c DQ [3:0] DQS_t DQS_c DQ [3:0] VSS D22 DM CS_n ZQ DQS_t DQS_c DQ [3:0] D5 DQS10_t DQS10_c DQ[12:15] VSS D9 VSS D21 DM CS_n ZQ DQS_t DQS_c DQ [3:0] D4 DQS_t DQS_c DQ [3:0] VSS D20 DM CS_n ZQ DQS_t DQS_c DQ [3:0] D3 DM CS_n ZQ DQS9_t DQS9_c DQ[7:4] VSS D19 DM CS_n ZQ DQS_t DQS_c DQ [3:0] D2 VSS D18 DM CS_n ZQ DQS_t DQS_c DQ [3:0] D1 DM CS_n ZQ DM CS_n ZQ DQS_t DQS_c DQ [3:0] D0 Note: 1. DQ-to-I/O wiring may be changed within a nibble. 2. ZQ pins of each SDRAM are connected to individual RZQ resistors (240+/-1%) ohms. Rev. 1.0 / Aug. 2012 17 16GB, 2Gx72 Module(2Rank of x4) - page2 S0_n S1_n S2_n S3_n BA[N:0] 1:2 R E G I S T E R / P L L A[N:0] RAS_n CAS_n WE_n CKE0 CKE1 ODT0 ODT1 CK0_t 120 Ω CK0_c CK1_t 120 Ω CK1_c PAR_IN RESET_n RS0_n → CS1_n: SDRAMs D[17:9] RS1_n → CS0_n: SDRAMs D[8:0] RS2_n → CS1_n: SDRAMs D[35:27] RS3_n → CS0_n: SDRAMs D[26:18] RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RBA[N:0]B → BA[N:0]: SDRAMs D[7:4], D[16:13], U[25:22], U[34:31] RA[N:0]A → A[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RA[N:0]B → A[N:0]: SDRAMs D[7:4], D[16:13], U[25:22], U[34:31] RRASA_n → RAS_n: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RRASB_n → RAS_n: SDRAMs D[7:4], D[16:13], U[25:22], U[34:31] RCASA_n → CAS_n: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RCASB_n → CAS_n: SDRAMs D[7:4], D[16:13], U[25:22], U[34:31] RWEA_n → WE_n: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RWEB_n → WE_n: SDRAMs D[7:4], D[16:13], U[25:22], U[34:31] RCKE0A → CKE1: SDRAMs D[12:9], D17, D[30:27], D35 RCKE0B → CKE1: SDRAMs D[16:13], D[34:31] RCKE1A → CKE0: SDRAMs D[3:0], D8, D[21:18], D26 RCKE1B → CKE0: SDRAMs D[7:4], D[25:22] RODT0A → ODT1: SDRAMs D[12:9], D17 RODT0B → ODT1: SDRAMs D[16:13] RODT1A → ODT1: SDRAMs D[30:27], D35 RODT1B → ODT1: SDRAMs D[34:31] PCK0A_t → CK_t: SDRAMs D[3:0], D[12:8], D17 PCK0B_t → CK_t: SDRAMs D[7:4], D[16:13] PCK1A_t → CK_t: SDRAMs D[21:18], D[30:26], D35 PCK1B_t → CK_t: SDRAMs D[25:22], D[34:31] PCK0A_c → CK_c: SDRAMs D[3:0], D[12:8], D17 PCK0B_c → CK_c: SDRAMs D[7:4], D[16:13] PCK1A_c → CK_c: SDRAMs D[21:18], D[30:26], D35 PCK1B_c → CK_c: SDRAMs D[25:22], D[34:31] Err_Out_n RST_n RESET_n: SDRAMs D[35:0] Rev. 1.0 / Aug. 2012 18 VSS DQS0_t DQS0_c DM0/TDQS9_t TDQS9_c DQ[7:0] ZQ DQS DQS TDQS TDQS DQ [7:0] Rev. 1.0 / Aug. 2012 D9 D0 ZQ DQS DQS TDQS TDQS DQ [7:0] D27 ZQ DQS DQS TDQS TDQS DQ [7:0] A[N:O]/BA[N:0] A[N:O]/BA[N:0] D18 ODT D19 ODT CKE ZQ DQS DQS TDQS TDQS DQ [7:0] CKE D21 D20 A[N:O]/BA[N:0] ODT CKE CK_c CK_t WE_n CAS_n A[N:O]/BA[N:0] ODT CKE CK_c CK_t WE_n CAS_n RAS_n CS_n D26 A[N:O]/BA[N:0] ODT CKE ZQ DQS DQS TDQS TDQS DQ [7:0] CK_c CK_t WE_n CAS_n ZQ DQS DQS TDQS TDQS DQ [7:0] CK_c CK_t WE_n CAS_n RAS_n CS_n A[N:O]/BA[N:0] ODT CKE ZQ DQS DQS TDQS TDQS DQ [7:0] CK_c CK_t WE_n VSS CAS_n VSS RAS_n CS_n VSS RAS_n CS_n VSS RAS_n D28 A[N:O]/BA[N:0] ODT CKE CK_c CK_t WE_n CAS_n VSS CS_n D29 A[N:O]/BA[N:0] ODT CKE D30 A[N:O]/BA[N:0] ODT CKE CK_c CK_t WE_n CAS_n RAS_n CS_n D35 A[N:O]/BA[N:0] ODT ZQ DQS DQS TDQS TDQS DQ [7:0] CKE ZQ DQS DQS TDQS TDQS DQ [7:0] CK_c CK_t WE_n CAS_n ZQ DQS DQS TDQS TDQS DQ [7:0] CK_c CK_t WE_n CAS_n RAS_n CS_n A[N:O]/BA[N:0] ODT CKE ZQ DQS DQS TDQS TDQS DQ [7:0] CK_c CK_t WE_n VSS CAS_n VSS RAS_n CS_n VSS RAS_n CS_n VSS RAS_n D1 A[N:O]/BA[N:0] ODT CK_c CK_t WE_n CAS_n VSS CS_n D2 A[N:O]/BA[N:0] ODT CKE D3 A[N:O]/BA[N:0] ODT CKE CK_c CK_t WE_n CAS_n RAS_n CS_n D8 A[N:O]/BA[N:0] ODT ZQ DQS DQS TDQS TDQS DQ [7:0] CKE ZQ DQS DQS TDQS TDQS DQ [7:0] CKE ZQ DQS DQS TDQS TDQS DQ [7:0] CK_c CK_t WE_n CAS_n ZQ DQS DQS TDQS TDQS DQ [7:0] CK_c CK_t WE_n CAS_n RAS_n CS_n A[N:O]/BA[N:0] ZQ DQS DQS TDQS TDQS DQ [7:0] CK_c CK_t WE_n VSS CAS_n VSS RAS_n CS_n VSS RAS_n CS_n VSS RAS_n D10 A[N:O]/BA[N:0] ODT CKE CK_c CK_t WE_n CAS_n VSS CS_n D11 A[N:O]/BA[N:0] ODT CKE CK_c CK_t WE_n CAS_n D12 A[N:O]/BA[N:0] ODT CKE CK_c CK_t WE_n CAS_n D17 A[N:O]/BA[N:0] ODT CKE CK_c CK_t WE_n CAS_n RAS_n ZQ DQS DQS TDQS TDQS DQ [7:0] ODT CS_n VSS DQS1_t DQS1_c DM1/TDQS10_t TDQS10_c DQ[15:8] RAS_n ZQ DQS DQS TDQS TDQS DQ [7:0] CKE CS_n VSS DQS2_t DQS2_c DM2/TDQS11_t TDQS11_c DQ[23:16] RAS_n ZQ DQS DQS TDQS TDQS DQ [7:0] CK_c CS_n VSS DQS3_t DQS3_c DM3/TDQS12_t TDQS12_c DQ[31:24] RAS_n ZQ DQS DQS TDQS TDQS DQ [7:0] CK_t CS_n VSS DQS8_t DQS8_c DM8/TDQS17_t TDQS17_c CB[7:0] WE_n CAS_n RAS_n CS_n VDD RS3_n RODT1A PCK1A_c PCK1A_t RS2_n VDD RCKE1A RS1_n /RBA[N:0]A RA[N:0]A RODT0A RCKE0A PCK0A_c PCK0A_t RWEA_n RCASA_n RRASA_n RS0_n 16GB, 2Gx72 Module(4Rank of x8) - page1 Vtt 19 A[N:O]/BA[N:0] ODT A[N:O]/BA[N:0] A[N:O]/BA[N:0] ODT ODT ODT CKE CKE CKE A[N:O]/BA[N:0] CKE CK_c WE_n CK_t CK_t D25 WE_n CAS_n CS_n ZQ DQS DQS TDQS TDQS DQ [7:0] CK_c CK_t D24 WE_n CAS_n CS_n ZQ DQS DQS TDQS TDQS DQ [7:0] CK_c CK_t WE_n CAS_n RAS_n CS_n D23 CK_c CAS_n RAS_n CS_n D22 ZQ DQS DQS TDQS TDQS DQ [7:0] RAS_n A[N:O]/BA[N:0] CKE ODT ODT CKE A[N:O]/BA[N:0] A[N:O]/BA[N:0] CKE ODT ODT CKE CK_t WE_n A[N:O]/BA[N:0] VSS D34 ZQ DQS DQS TDQS TDQS DQ [7:0] RAS_n ZQ DQS DQS TDQS TDQS DQ [7:0] CK_c CK_t D33 VDD RS3_n RODT1A PCK1A_t PCK1A_c CK_c CK_t VSS WE_n CAS_n CK_c CK_t D32 CK_c CAS_n WE_n VSS WE_n CAS_n RAS_n CS_n CS_n RAS_n RCKE1A RS2_n RAS_n CS_n D31 ZQ DQS DQS TDQS TDQS DQ [7:0] CAS_n ODT CKE CK_c CK_t WE_n D7 A[N:O]/BA[N:0] VSS VSS ZQ DQS DQS TDQS TDQS DQ [7:0] RAS_n ODT CKE CK_c CK_t A[N:O]/BA[N:0] VSS D6 ZQ DQS DQS TDQS TDQS DQ [7:0] CS_n ODT CKE CK_c CK_t WE_n A[N:O]/BA[N:0] A[N:O]/BA[N:0] ODT CKE CK_c CK_t WE_n D5 WE_n CAS_n CS_n VDD RS1_n RAS_n CS_n CAS_n CAS_n RAS_n CS_n VSS ZQ DQS DQS TDQS TDQS DQ [7:0] CS_n A[N:O]/BA[N:0] ODT CKE CK_c D16 D4 ZQ DQS DQS TDQS TDQS DQ [7:0] RAS_n A[N:O]/BA[N:0] A[N:O]/BA[N:0] ODT CKE CK_c VSS VSS ZQ DQS DQS TDQS TDQS DQ [7:0] CAS_n A[N:O]/BA[N:0] CKE CK_c ODT ODT CKE CK_c VSS D15 ZQ DQS DQS TDQS TDQS DQ [7:0] RAS_n RA[N:0]A /RBA[N:0]A PCK0A_c RCKE0A RODT0A RWEA_n PCK0A_t CK_t CK_t CAS_n CS_n RAS_n RAS_n CS_n CAS_n CAS_n RAS_n CS_n D14 CK_t ZQ DQS DQS TDQS TDQS DQ [7:0] VSS CK_t RCASA_n VSS DQS7_t DQS7_c DM7/TDQS16_t TDQS16_c DQ[63:56] WE_n ZQ DQS DQS TDQS TDQS DQ [7:0] D13 WE_n VSS DQS6_t DQS6_c DM6/TDQS15_t TDQS15_c DQ[55:48] VSS WE_n ZQ DQS DQS TDQS TDQS DQ [7:0] CAS_n VSS DQS5_t DQS5_c DM5/TDQS14_t TDQS14_c DQ[47:40] RAS_n ZQ DQS DQS TDQS TDQS DQ [7:0] CS_n VSS DQS4_t DQS4_c DM4/TDQS13_t TDQS13_c DQ[39:32] WE_n RRASA_n RS0_n 16GB, 2Gx72 Module(4Rank of x8) - page2 Vtt VDDSPD EVENT SCL SDA VDDSPD SA0 SA0 EVENT SPD with SA1 Integrated SA2 SCL TS VSS SDA SA1 SA2 VSS Plan to use SPD with Integrated TS of Class B and might be changed on customer’s requests. For more details of SPD and Thermal sensor, please contact local SK SK hynix sales representative VDDSPD Note: VDD 1. DQ-to-I/O wiring may be changed within a nibble. 2. Unless otherwise noted, resistor values are 15 5 %. 3. See the wiring diagrams for all resistors associated with the command, address and control bus. 4. ZQ resistors are 240 1 %. For all other resistor values refer to the appropriate wiring diagram. VTT Rev. 1.0 / Aug. 2012 Serial PD D0-D35 VREFCA D0-D35 VREFDQ D0-D35 VSS D0-D35 20 16GB, 2Gx72 Module(4Rank of x8) - page3 S0_n S1_n S2_n S3_n BA[N:0] 1:2 R E G I S T E R / P L L A[N:0] RAS_n CAS_n WE_n CKE0 CKE1 ODT0 ODT1 CK0_t 120 Ω CK0_c CK1_t 120 Ω CK1_c PAR_IN RESET_n RS0_n → CS1_n: SDRAMs D[17:9] RS1_n → CS0_n: SDRAMs D[8:0] RS2_n → CS1_n: SDRAMs D[35:27] RS3_n → CS0_n: SDRAMs D[26:18] RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RBA[N:0]B → BA[N:0]: SDRAMs D[7:4], D[16:13], U[25:22], U[34:31] RA[N:0]A → A[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RA[N:0]B → A[N:0]: SDRAMs D[7:4], D[16:13], U[25:22], U[34:31] RRASA_n → RAS_n: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RRASB_n → RAS_n: SDRAMs D[7:4], D[16:13], U[25:22], U[34:31] RCASA_n → CAS_n: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RCASB_n → CAS_n: SDRAMs D[7:4], D[16:13], U[25:22], U[34:31] RWEA_n → WE_n: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RWEB_n → WE_n: SDRAMs D[7:4], D[16:13], U[25:22], U[34:31] RCKE0A → CKE1: SDRAMs D[12:9], D17, D[30:27], D35 RCKE0B → CKE1: SDRAMs D[16:13], D[34:31] RCKE1A → CKE0: SDRAMs D[3:0], D8, D[21:18], D26 RCKE1B → CKE0: SDRAMs D[7:4], D[25:22] RODT0A → ODT1: SDRAMs D[12:9], D17 RODT0B → ODT1: SDRAMs D[16:13] RODT1A → ODT1: SDRAMs D[30:27], D35 RODT1B → ODT1: SDRAMs D[34:31] PCK0A_t → CK_t: SDRAMs D[3:0], D[12:8], D17 PCK0B_t → CK_t: SDRAMs D[7:4], D[16:13] PCK1A_t → CK_t: SDRAMs D[21:18], D[30:26], D35 PCK1B_t → CK_t: SDRAMs D[25:22], D[34:31] PCK0A_c → CK_c: SDRAMs D[3:0], D[12:8], D17 PCK0B_c → CK_c: SDRAMs D[7:4], D[16:13] PCK1A_c → CK_c: SDRAMs D[21:18], D[30:26], D35 PCK1B_c → CK_c: SDRAMs D[25:22], D[34:31] Err_Out_n RST_n RESET_n: SDRAMs D[35:0] Rev. 1.0 / Aug. 2012 21 Absolute Maximum Ratings Absolute Maximum DC Ratings Absolute Maximum DC Ratings Symbol VDD VDDQ Parameter Rating Units Notes Voltage on VDD pin relative to Vss - 0.4 V ~ 1.80 V V 1,3 Voltage on VDDQ pin relative to Vss - 0.4 V ~ 1.80 V V 1,3 - 0.4 V ~ 1.80 V V 1 C 1, 2 VIN, VOUT Voltage on any pin relative to Vss TSTG -55 to +100 Storage Temperature o Notes: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than 0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV. DRAM Component Operating Temperature Range Temperature Range Symbol TOPER Parameter Rating Units Notes Normal Operating Temperature Range 0 to 85 oC 1,2 Extended Temperature Range 85 to 95 oC 1,3 Notes: 1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions. 3. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It is also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range. Please refer to the DIMM SPD for option availability b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b). DDR3 SDRAMs support Auto Self-Refresh and in Extended Temperature Range and please refer to component datasheet and/or the DIMM SPD for tREFI requirements in the Extended Temperature Range Rev. 1.0 / Aug. 2012 22 AC & DC Operating Conditions Recommended DC Operating Conditions Recommended DC Operating Conditions - DDR3L (1.35V) operation Symbol VDD VDDQ Parameter Rating Units Notes 1.45 V 1,2,3,4 1.45 V 1,2,3,4 Min. Typ. Max. Supply Voltage 1.283 1.35 Supply Voltage for Output 1.283 1.35 Notes: 1. Maximum DC value may not be greater than 1.425V. The DC value is the linear average of VDD/VDDQ (t) over a very long period of time (e.g., 1 sec). 2. If maximum limit is exceeded, input levels shall be governed by DDR3 specifications. 3. Under these supply voltages, the device operates to this DDR3L specification. 4. Once initialized for DDR3L operation, DDR3 operation may only be used if the device is in reset while VDD and VDDQ are changed for DDR3 operation (see Figure 0). Recommended DC Operating Conditions - - DDR3 (1.5V) operation Symbol VDD VDDQ Parameter Rating Units Notes 1.575 V 1,2,3 1.575 V 1,2,3 Min. Typ. Max. Supply Voltage 1.425 1.5 Supply Voltage for Output 1.425 1.5 Notes: 1. If minimum limit is exceeded, input levels shall be governed by DDR3L specifications. 2. Under 1.5V operation, this DDR3L device operates to the DDR3 specifications under the same speed timings as defined for this device. 3. Once initialized for DDR3 operation, DDR3L operation may only be used if the device is in reset while VDD and VDDQ are changed for DDR3L operation (see Figure 0). Rev. 1.0 / Aug. 2012 23 Ta Tb Tc Td Te Tf Tg Th Ti Tj Tk CK,CK# VDD, VDDQ (DDR3) tCKSRX Tmin = 10ns VDD, VDDQ (DDR3L) Tmin = 10ns Tmin = 200us T = 500us RESET# Tmin = 10ns CKE VALID tDLLK tIS COMMAND READ BA READ 1) tXPR tMRD tMRD tMRD tMOD MRS MRS MRS MRS MR2 MR3 MR1 MR0 tZQinit ZQCL 1) VALID VALID tIS ODT READ tIS Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW VALID RTT NOTE 1: From time point “Td” until “Tk” NOP or DES commands must be applied between MRS and ZQCL commands. TIME BREAK DON’T CARE Figure 0 - VDD/VDDQ Voltage Switch Between DDR3L and DDR3 Rev. 1.0 / Aug. 2012 24 AC & DC Input Measurement Levels AC and DC Logic Input Levels for Single-Ended Signals AC and DC Input Levels for Single-Ended Command and Address Signals Single Ended AC and DC Input Levels for Command and Address DDR3L-800/1066 Symbol VIH.CA(DC90) VIL.CA(DC90) VIH.CA(AC160) VIL.CA(AC160) VIH.CA(AC135) VIL.CA(AC135) VIH.CA(AC125) VIL.CA(AC125) VRefCA(DC) DDR3L-1333 Parameter DC input logic high DC input logic low AC input logic high AC input logic low AC Input logic high AC input logic low AC Input logic high AC input logic low Reference Voltage for ADD, CMD inputs Unit Notes Min Max Min Max Vref + 0.09 VSS Vref + 0.160 Note2 Vref + 0.135 Note2 - VDD Vref - 0.09 Note2 Vref - 0.160 Note2 Vref - 0.135 - Vref + 0.09 VSS Vref + 0.160 Note2 Vref + 0.135 Note2 - VDD Vref - 0.09 Note2 Vref - 0.160 Note2 Vref - 0.135 - V V V V V V V V 1 1 1,2,5 1,2,5 1,2,5 1,2,5 1,2,5 1,2,5 0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD V 3,4 Notes: 1. For input only pins except RESET, Vref = VrefCA (DC). 2. Refer to "Overshoot and Undershoot Specifications" on page 38. 3. The ac peak noise on VRef may not allow VRef to deviate from VRefCA(DC) by more than +/-1% VDD (for reference: approx. +/- 13.5 mV). 4. For reference: approx. VDD/2 +/- 13.5 mV 5. These levels apply for 1.35 volt (see table above) operation only. If the device is operated at 1.5V (table "Single Ended AC and DC Input Levels for DQ and DM" on page 26), the respective levels in JESD79-3 (VIH/L.CA(DC100), VIH/L.CA(AC175), VIH/L.CA(AC150), VIH/L.CA(AC135), VIH/L.CA(AC125) etc.) apply. The 1.5V levels (VIH/L.CA(DC100), VIH/L.CA(AC175), VIH/L.CA(AC150), VIH/L.CA(AC135), VIH/ L.CA(AC125) etc.) do not apply when the device is operated in the 1.35 voltage range. Rev. 1.0 / Aug. 2012 25 AC and DC Input Levels for Single-Ended Signals DDR3 SDRAM will support two Vih/Vil AC levels for DDR3-800 and DDR3-1066s specified in table below. DDR3 SDRAM will also support corresponding tDS values (Table 43 and Table 51 in “DDR3L Device Operation”) as well as derating tables Table 46 in “Device Operation” depending on Vih/Vil AC levels. Single Ended AC and DC Input Levels for DQ and DM DDR3L-800/1066 Symbol VIH.DQ(DC90) VIL.DQ(DC90) VIH.DQ(AC160) VIL.DQ(AC160) VIH.DQ(AC135) VIL.DQ(AC135) VIH.DQ(AC130) VIL.DQ(AC130) VRefDQ(DC) DDR3L-1333 Parameter DC input logic high DC input logic low AC input logic high AC input logic low AC Input logic high AC input logic low AC Input logic high AC input logic low Reference Voltage for DQ, DM inputs Unit Notes Min Max Min Max Vref + 0.09 VSS Vref + 0.160 Note2 Vref + 0.135 Note2 - VDD Vref - 0.09 Note2 Vref - 0.160 Note2 Vref - 0.135 - Vref + 0.09 VSS Vref + 0.135 Note2 - VDD Vref - 0.09 Note2 Vref - 0.135 - V V V V V V V V 1 1 1, 2, 5 1, 2, 5 1, 2, 5 1, 2, 5 1, 2, 5 1, 2, 5 0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD V 3, 4 Notes: 1. Vref = VrefDQ (DC). 2. Refer to "Overshoot and Undershoot Specifications" on page 38. 3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 13.5 mV). 4. For reference: approx. VDD/2 +/- 13.5 mV 4. For reference: approx. VDD/2 +/- 13.5 mV 5. These levels apply for 1.35 volt (table "Single Ended AC and DC Input Levels for Command and Address" on page 25) operation only. If the device is operated at 1.5V (table above), the respective levels in JESD79-3 (VIH/L.DQ(DC100), VIH/L.DQ(AC175), VIH/L.DQ(AC150), VIH/L.DQ(AC135) etc.) apply. The 1.5V levels (VIH/L.DQ(DC100), VIH/L.DQ(AC175), VIH/L.DQ(AC150), VIH/L.DQ(AC135) etc.) do not apply when the device is operated in the 1.35 voltage range. Rev. 1.0 / Aug. 2012 26 Vref Tolerances The dc-tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in figure below. It shows a valid reference voltage VRef (t) as a function of time. (VRef stands for VRefCA and VRefDQ likewise). VRef (DC) is the linear average of VRef (t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements in the table "Differential Input Slew Rate Definition" on page 33. Furthermore VRef (t) may temporarily deviate from VRef (DC) by no more than +/- 1% VDD. voltage VDD VRef ac-noise VRef(DC) VRef(t) VRef(DC)max VDD/2 VRef(DC)min VSS time Illustration of VRef(DC) tolerance and VRef ac-noise limits The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC), and VIL(DC) are dependent on VRef. “VRef ” shall be understood as VRef(DC), as defined in figure above. This clarifies that dc-variations of VRef affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for VRef(DC) deviations from the optimum position within the data-eye of the input signals. This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VRefac-noise. Timing and voltage effects due to ac-noise on VRef up to the specified limit (+/- 1% of VDD) are included in DRAM timings and their associated deratings. Rev. 1.0 / Aug. 2012 27 AC and DC Logic Input Levels for Differential Signals Differential signal definition tDVAC Differential Input Voltage(i.e.DQS - DQS#, CK - CK#) VIL.DIFF.AC.MIN VIL.DIFF.MIN 0 half cycle VIL.DIFF.MAX VIL.DIFF.AC.MAX tDVAC time Definition of differential ac-swing and “time above ac-level” tDVAC Rev. 1.0 / Aug. 2012 28 Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS) Differential AC and DC Input Levels DDR3L-800, 1066, 1333 Symbol Parameter VIHdiff VILdiff VIHdiff (ac) VILdiff (ac) Unit Notes Differential input high Differential input logic low Differential input high ac Differential input low ac Min Max + 0.180 Note 3 2 x (VIH (ac) - Vref) Note 3 Note 3 - 0.180 Note 3 2 x (VIL (ac) - Vref) V V V V 1 1 2 2 Notes: 1. Used to define a differential signal slew-rate. 2. For CK - CK use VIH/VIL (ac) of AADD/CMD and VREFCA; for DQS - DQS, DQSL, DQSL, DQSU, DQSU use VIH/VIL (ac) of DQs and VREFDQ; if a reduced ac-high or ac-low levels is used for a signal group, then the reduced level applies also here. 3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limitations for overshoot and undershoot.Refer to "Overshoot and Undershoot Specifications" on page 38. Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS DDR3L-800/1066/1333 Slew Rate [V/ns] tDVAC [ps] @ |VIH/Ldiff (ac)| = 320mV min max tDVAC [ps] @ |VIH/Ldiff (ac)| = 270mV min max > 4.0 189 - 201 - 4.0 189 - 201 - 3.0 162 - 179 - 2.0 109 - 134 1.8 91 - 119 - 1.6 69 - 100 - 1.4 40 - 76 - 1.2 note - 44 - 1.0 note - note - < 1.0 note - note - note : Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall become equal to or less than VIL(ac) level. Rev. 1.0 / Aug. 2012 29 Single-ended requirements for differential signals Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, of DQSU) has also to comply with certain requirements for single-ended signals. CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH (ac) / VIL (ac)) for ADD/CMD signals) in every half-cycle. DQS, DQSL, DQSU, DQS, DQSL have to reach VSEHmin / VSELmax (approximately the ac-levels (VIH (ac) / VIL (ac)) for DQ signals) in every half-cycle preceding and following a valid transition. Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g., if VIH.CA(AC150)/VIL.CA(AC150) is used for ADD/CMD signals, then these ac-levels apply also for the singleended signals CK and CK. VDD or VDDQ VSEHmin VSEH VDD/2 or VDDQ/2 CK or DQS VSELmax VSS or VSSQ VSEL time Single-ended requirements for differential signals. Note that, while ADD/CMD and DQ signal requirements are with respect to Vref, the single-ended components of differential signals have a requirement with respect to VDD / 2; this is nominally the same. the transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common mode characteristics of these signals. Rev. 1.0 / Aug. 2012 30 Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU DDR3L-800, 1066, 1333 Symbol VSEH VSEL Parameter Single-ended high level for strobes Single-ended high level for Ck, CK Single-ended low level for strobes Single-ended low level for CK, CK Unit Notes Min Max (VDD / 2) + 0.175 (VDD /2) + 0.175 Note 3 Note 3 Note 3 Note 3 (VDD / 2) = 0.175 (VDD / 2) = 0.175 V V V V 1,2 1,2 1,2 1,2 Notes: 1. For CK, CK use VIH/VIL (ac) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL (ac) of DQs. 2. VIH (ac)/VIL (ac) for DQs is based on VREFDQ; VIH (ac)/VIL (ac) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here. 3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot Specifications" on page 38. Rev. 1.0 / Aug. 2012 31 Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements in table below. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signals to the midlevel between of VDD and VSS Vix Definition Cross point voltage for differential input signals (CK, DQS) DDR3L-800, 1066, 1333 Symbol Parameter Unit Notes Min Max VIX(CK) Differential Input Cross Point Voltage relative to VDD/2 for CK, CK -150 -175 150 175 mV mV 2 1 VIX(DQS) Differential Input Cross Point Voltage relative to VDD/2 for DQS, DQS -150 150 mV 2 Notes: 1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CK and CK are monotonic with a single-ended swing VSEL / VSEH of at least VDD/2 +/-250 mV, and when the differential slew rate of CK - CK is larger than 3 V/ns. 2. The relation between Vix Min/Max and VSEL/VSEH should satisfy following. (VDD/2) + Vix (Min) - VSEL 25mV VSEH - ((VDD/2) + Vix (Max)) 25mV Rev. 1.0 / Aug. 2012 32 Slew Rate Definitions for Single-Ended Input Signals See 7.5 “Address / Command Setup, Hold and Derating” on “DDR3L Device Operation” for single-ended slew rate definitions for address and command signals. See 7.6 “Data Setup, Hold and Slew Rate Derating” on “DDR3L Device Operation” for single-ended slew rate definition for data signals. Slew Rate Definitions for Differential Input Signals Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in table and figure below. Differential Input Slew Rate Definition Measured Description Differential input slew rate for rising edge (CK-CK and DQS-DQS) Differential input slew rate for falling edge (CK-CK and DQS-DQS) Defined by Min Max VILdiffmax VIHdiffmin [VIHdiffmin-VILdiffmax] / DeltaTRdiff VIHdiffmin VILdiffmax [VIHdiffmin-VILdiffmax] / DeltaTFdiff Notes: Differential Input Voltage (i.e. DQS-DQS; CK-CK) The differential signal (i.e. CK-CK and DQS-DQS) must be linear between these thresholds. Delta TRdiff VIHdiffmin 0 VILdiffmax Delta TFdiff Differential Input Slew Rate Definition for DQS, DQS and CK, CK Rev. 1.0 / Aug. 2012 33 AC & DC Output Measurement Levels Single Ended AC and DC Output Levels Table below shows the output levels used for measurements of single ended signals. Single-ended AC and DC Output Levels Symbol Parameter VOH(DC) DC output high measurement level (for IV curve linearity) VOM(DC) DC output mid measurement level (for IV curve linearity) VOL(DC) VOH(AC) DDR3L-800, 1066, 1333 0.8 x VDDQ Unit Notes V V DC output low measurement level (for IV curve linearity) 0.5 x VDDQ 0.2 x VDDQ AC output high measurement level (for output SR) VTT + 0.1 x VDDQ V 1 AC output low measurement level (for output SR) VTT - 0.1 x VDDQ V 1 VOL(AC) V Notes: 1. The swing of ±0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 Ω and an effective test load of 25 Ω to VTT = VDDQ / 2. Differential AC and DC Output Levels Table below shows the output levels used for measurements of single ended signals. Differential AC and DC Output Levels DDR3L-800, 1066, Symbol Parameter VOHdiff (AC) AC differential output high measurement level (for output SR) 1333 + 0.2 x VDDQ VOLdiff (AC) AC differential output low measurement level (for output SR) - 0.2 x VDDQ Unit Notes V 1 V 1 Notes: 1. The swing of ±0.2 x VDDQ is based on approximately 50% of the static differential output high or low swing with a driver impedance of 40 Ω and an effective test load of 25 Ω to VTT = VDDQ/2 at each of the differential outputs. Rev. 1.0 / Aug. 2012 34 Single Ended Output Slew Rate When the Reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single ended signals are shown in table and figure below. Single-ended Output slew Rate Definition Measured Description Defined by From To Single-ended output slew rate for rising edge VOL(AC) VOH(AC) [VOH(AC)-VOL(AC)] / DeltaTRse Single-ended output slew rate for falling edge VOH(AC) VOL(AC) [VOH(AC)-VOL(AC)] / DeltaTFse Notes: 1. Output slew rate is verified by design and characterisation, and may not be subject to production test. Single Ended Output Voltage(l.e.DQ) Delta TRse vOH(AC) V∏ vOl(AC) Delta TFse Single Ended Output Slew Rate Definition Single Ended Output slew Rate Definition Output Slew Rate (single-ended) DDR3L-800 DDR3L-1066 DDR3L-1333 Parameter Symbol Min Max Min Max Min Max Single-ended Output Slew Rate SRQse 1.75 51) 1.75 51) 1.75 51) Units V/ns Description: SR; Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) se: Single-ended Signals For Ron = RZQ/7 setting Note 1): In two cases, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane. Case 1 is a defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining DQ signals in the same byte lane are static (i.e. they stay at either high or low). Case 2 is a defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining DQ signals in the same byte lane switching into the opposite direction (i.e. from low to high of high to low respectively). For the remaining DQ signal switching in to the opposite direction, the regular maximum limite of 5 V/ns applies. Rev. 1.0 / Aug. 2012 35 Differential Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff (AC) and VOHdiff (AC) for differential signals as shown in table and figure below. Differential Output Slew Rate Definition Measured Description Defined by From To Differential output slew rate for rising edge VOLdiff (AC) VOHdiff (AC) [VOHdiff (AC)-VOLdiff (AC)] / DeltaTRdiff Differential output slew rate for falling edge VOHdiff (AC) VOLdiff (AC) [VOHdiff (AC)-VOLdiff (AC)] / DeltaTFdiff Notes: 1. Output slew rate is verified by design and characterization, and may not be subject to production test. Differential Output Voltage(i.e. DQS-DQS) Delta TRdiff VOHdiff(AC) O VOLdiff(AC) Delta TFdiff Differential Output slew Rate Definition Differential Output Slew Rate DDR3L-800 DDR3L-1066 DDR3L-1333 Parameter Symbol Min Max Min Max Min Max Differential Output Slew Rate SRQdiff 3.5 12 3.5 12 3.5 12 Units V/ns Description: SR; Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) se: Single-ended Signals For Ron = RZQ/7 setting Rev. 1.0 / Aug. 2012 36 Reference Load for AC Timing and Output Slew Rate Figure below represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements. It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics. VDDQ CK, CK DUT DQ DQS DQS 25 Ohm VTT = VDDQ/2 Reference Load for AC Timing and Output Slew Rate Rev. 1.0 / Aug. 2012 37 Overshoot and Undershoot Specifications Address and Control Overshoot and Undershoot Specifications AC Overshoot/Undershoot Specification for Address and Control Pins Parameter Maximum peak amplitude allowed for overshoot area. (See Figure below) Maximum peak amplitude allowed for undershoot area. (See Figure below) Maximum overshoot area above VDD (See Figure below) Maximum undershoot area below VSS (See Figure below) DDR3L- DDR3L- DDR3L- 800 1066 1333 0.4 0.4 0.67 0.67 0.4 0.4 0.5 0.5 0.4 0.4 0.4 0.4 Units V V V-ns V-ns (A0-A15, BA0-BA3, CS, RAS, CAS, WE, CKE, ODT) See figure below for each parameter definition Maximum Amplitude Overshoot Area Volts (V) VDD VSS Undershoot Area Maximum Amplitude Time (ns) Address and Control Overshoot and Undershoot Definition Rev. 1.0 / Aug. 2012 38 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask Parameter Maximum peak amplitude allowed for overshoot area. (See Figure below) Maximum peak amplitude allowed for undershoot area. (See Figure below) Maximum overshoot area above VDD (See Figure below) Maximum undershoot area below VSS (See Figure below) DDR3L- DDR3L- DDR3L- 800 1066 1333 0.4 0.4 0.25 0.25 0.4 0.4 0.19 0.19 0.4 0.4 0.15 0.15 Units V V V-ns V-ns (CK, CK, DQ, DQS, DQS, DM) See figure below for each parameter definition Maximum Amplitude Overshoot Area Volts (V) VDDQ VSSQ Undershoot Area Maximum Amplitude Time (ns) Clock, Data, Strobe and Mask Overshoot and Undershoot Definition Rev. 1.0 / Aug. 2012 39 Refresh parameters by device density Refresh parameters by device density Parameter REF command ACT or REF command time Average periodic refresh interval Rev. 1.0 / Aug. 2012 RTT_Nom Setting 512Mb 1Gb 2Gb 4Gb 8Gb tRFC 90 110 160 260 350 ns 7.8 7.8 7.8 7.8 7.8 us 3.9 3.9 3.9 3.9 3.9 us tREFI 0 C TCASE 85 C 85 C TCASE 95 C Units Notes 1 40 Standard Speed Bins DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin. DDR3L-800 Speed Bins For specific Notes See "Speed Bin Table Notes" on page 44. Speed Bin DDR3L-800E CL - nRCD - nRP 6-6-6 Unit Parameter Symbol min max Internal read command to first data tAA 15 20 ns ACT to internal read or write delay time tRCD 15 — ns PRE command period tRP 15 — ns ACT to ACT or REF command period tRC 52.5 — ns ACT to PRE command period tRAS 37.5 9 * tREFI ns CL = 5 CL = 6 CWL = 5 tCK(AVG) CWL = 5 tCK(AVG) Reserved 2.5 3.3 ns 1, 2, 3, 4 ns 1, 2, 3 Supported CL Settings 6 nCK Supported CWL Settings 5 nCK Rev. 1.0 / Aug. 2012 Notes 41 DDR3L-1066 Speed Bins For specific Notes See "Speed Bin Table Notes" on page 44. Speed Bin DDR3L-1066F CL - nRCD - nRP Parameter Symbol Unit 7-7-7 min max Internal read command to first data tAA 13.125 20 ns ACT to internal read or write delay time tRCD 13.125 — ns PRE command period tRP 13.125 — ns ACT to ACT or REF command period tRC 50.625 — ns ACT to PRE command period tRAS 37.5 9 * tREFI ns CL = 5 CL = 6 CL = 7 CL = 8 Note CWL = 5 tCK(AVG) Reserved ns 1, 2, 3, 4, 6 CWL = 6 tCK(AVG) Reserved ns 4 CWL = 5 tCK(AVG) ns 1, 2, 3, 6 CWL = 6 tCK(AVG) Reserved ns 1, 2, 3, 4 CWL = 5 tCK(AVG) Reserved ns 4 CWL = 6 tCK(AVG) ns 1, 2, 3, 4 CWL = 5 tCK(AVG) ns 4 CWL = 6 tCK(AVG) ns 1, 2, 3 2.5 3.3 1.875 < 2.5 Reserved 1.875 < 2.5 Supported CL Settings 6, 7, 8 nCK Supported CWL Settings 5, 6 nCK Rev. 1.0 / Aug. 2012 42 DDR3L-1333 Speed Bins For specific Notes See "Speed Bin Table Notes" on page 44. Speed Bin DDR3L-1333H CL - nRCD - nRP Parameter Symbol Unit 9-9-9 min max Internal read command to first data tAA 13.75 (13.125)5,8 20 ns ACT to internal read or write delay time tRCD 13.75 (13.125)5,8 — ns PRE command period tRP 13.75 (13.125)5,8 — ns ACT to ACT or REF command period tRC 48.75 (48.125)5,8 — ns ACT to PRE command period tRAS 36 9 * tREFI ns CL = 5 CL = 6 CL = 7 CL = 8 CL = 9 Note CWL = 5 tCK(AVG) Reserved ns 1,2, 3,4, 7 CWL = 6, 7 tCK(AVG) Reserved ns 4 CWL = 5 tCK(AVG) ns 1, 2, 3, 7 CWL = 6 tCK(AVG) Reserved ns 1, 2, 3, 4, 7 CWL = 7 tCK(AVG) Reserved ns 4 CWL = 5 tCK(AVG) Reserved ns 4 CWL = 6 tCK(AVG) ns 1, 2, 3, 4, 7 CWL = 7 tCK(AVG) Reserved ns 1, 2, 3, 4 CWL = 5 tCK(AVG) Reserved ns 4 CWL = 6 tCK(AVG) ns 1, 2, 3, 7 CWL = 7 tCK(AVG) Reserved ns 1, 2, 3, 4 CWL = 5, 6 tCK(AVG) Reserved ns 4 CWL = 7 tCK(AVG) ns 1, 2, 3, 4 CWL = 5, 6 tCK(AVG) 2.5 3.3 1.875 < 2.5 (Optional)5,9 1.875 < 2.5 1.5 <1.875 ns 4 (Optional) ns ns 1, 2, 3 5 Supported CL Settings 6, (7), 8, 9, (10) nCK Supported CWL Settings 5, 6, 7 nCK CL = 10 CWL = 7 Rev. 1.0 / Aug. 2012 tCK(AVG) Reserved 1.5 <1.875 43 Speed Bin Table Notes Absolute Specification (TOPER; VDDQ = VDD = 1.35V +1.000/- 0.067 V); Notes: 1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting. 2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC standard tCK(AVG) value (3.0, 2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next ‘Supported CL’, where tCK(AVG) = 3.0 ns should only be used for CL = 5 calculation. 3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX corresponding to CL SELECTED. 4. ‘Reserved’ settings are not allowed. User must program a different value. 5. ‘Optional’ settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. Refer to DIMM data sheet and/or the DIMM SPD information if and how this setting is supported. 6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. 7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. 8. DDR3 SDRAM devices supporting optional down binning to CL=7 and CL=9, and tAA/tRCD/tRP must be 13.125 ns or lower. SPD settings must be programmed to match. For example, DDR3-1333H devices supporting down binning to DDR3-1066F should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600K devices supporting down binning to DDR3-1333H or DDR3-1600F should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be programmed accordingly. For example, 49.125ns (tRASmin + tRPmin = 36 ns + 13.125 ns) for DDR3-1333H and 48.125ns (tRASmin + tRPmin = 35 ns + 13.125 ns) for DDR3-1600K. Rev. 1.0 / Aug. 2012 44 Environmental Parameters Symbol Parameter Rating TOPR Operating temperature See Note HOPR Operating humidity (relative) 10 to 90 TSTG Storage temperature HSTG Storage humidity (without condensation) PBAR Barometric Pressure (operating & storage) Units Notes 3 % 1 o C 1 5 to 95 % 1 105 to 69 K Pascal 1, 2 -50 to +100 Note: 1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating conditions for extended periods may affect reliablility. 2. Up to 9850 ft. 3. The designer must meet the case temperature specifications for individual module components. Rev. 1.0 / Aug. 2012 45 IDD and IDDQ Specification Parameters and Test Conditions IDD and IDDQ Measurement Conditions In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure 1. shows the setup and test load for IDD and IDDQ measurements. • IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5B, IDD6, IDD6ET and IDD7) are measured as time-averaged currents with all VDD balls of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD currents. • IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ currents. Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one merged-power layer in Module PCB. For IDD and IDDQ measurements, the following definitions apply: • ”0” and “LOW” is defined as VIN <= VILAC(max). • ”1” and “HIGH” is defined as VIN >= VIHAC(max). • “MID_LEVEL” is defined as inputs are VREF = VDD/2. • Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1. • Basic IDD and IDDQ Measurement Conditions are described in Table 2. • Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 10. • IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting RON = RZQ/7 (34 Ohm in MR1); Qoff = 0B (Output Buffer enabled in MR1); RTT_Nom = RZQ/6 (40 Ohm in MR1); RTT_Wr = RZQ/2 (120 Ohm in MR2); TDQS Feature disabled in MR1 • Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started. • Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW} • Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH} Rev. 1.0 / Aug. 2012 46 IDDQ (optional) IDD VDD VDDQ RESET CK/CK DDR3L SDRAM CKE CS RAS, CAS, WE DQS, DQS DQ, DM, TDQS, TDQS A, BA ODT ZQ VSS RTT = 25 Ohm VDDQ/2 VSSQ Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements [Note: DIMM level Output test load condition may be different from above Application specific memory channel environment IDDQ Test Load Channel IO Power Simulation IDDQ Simulation IDDQ Simulation Correction Channel IO Power Number Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement Rev. 1.0 / Aug. 2012 47 Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns Symbol tCK DDR3L-1066 DDR3L-1333 7-7-7 9-9-9 1.875 1.5 Unit ns CL 7 9 nCK nRCD 7 9 nCK nRC 27 33 nCK nRAS 20 24 nCK nRP 7 9 nCK 1KB page size 20 20 nCK 2KB page size 27 30 nCK 1KB page size 4 4 nCK nFAW nRRD 6 5 nCK nRFC -512Mb 2KB page size 48 60 nCK nRFC-1 Gb 59 74 nCK nRFC- 2 Gb 86 107 nCK nRFC- 4 Gb 139 174 nCK nRFC- 8 Gb 187 234 nCK Table 2 -Basic IDD and IDDQ Measurement Conditions Symbol Description Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT and IDD0 PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO: MID-LEVEL; DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 3. Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT, IDD1 RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to Table 4; DM: stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 4. Rev. 1.0 / Aug. 2012 48 Symbol Description Precharge Standby Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank IDD2N Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 5. Precharge Standby ODT Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank IDD2NT Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: toggling according to Table 6; Pattern Details: see Table 6. Precharge Power-Down Current Slow Exit IDD2P0 CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exitc) Precharge Power-Down Current Fast Exit IDD2P1 CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exitc) Precharge Quiet Standby Current IDD2Q CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0 Active Standby Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank IDD3N Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 5. Active Power-Down Current IDD3P CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0 Rev. 1.0 / Aug. 2012 49 Symbol Description Operating Burst Read Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between RD; Command, Address, IDD4R Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst with different data between one burst and the next one according to Table 7; DM: stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 7. Operating Burst Write Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between WR; Command, Address, IDD4W Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless read data burst with different data between one burst and the next one according to Table 8; DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at HIGH; Pattern Details: see Table 8. Burst Refresh Current CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8a); AL: 0; CS: High between REF; Command, IDD5B Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: REF command every nREF (see Table 9); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 9. Self-Refresh Current: Normal Temperature Range TCASE: 0 - 85 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Normale); CKE: IDD6 Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL Self-Refresh Current: Extended Temperature Range (optional) TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Extendede); IDD6ET CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL Rev. 1.0 / Aug. 2012 50 Symbol Description Operating Bank Interleave Read Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8a),f); AL: CL-1; CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling according to Table IDD7 10; Data IO: read data burst with different data between one burst and the next one according to Table 10; DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1,...7) with different addressing, wee Table 10; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 10. a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature range f) Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B Rev. 1.0 / Aug. 2012 51 Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 ACT 0 0 1 1 0 0 00 0 0 0 0 - 1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 - D, D 1 1 1 1 0 0 00 0 0 0 0 - 0 0 0 - Cycle Number Datab) Sub-Loop CKE CK, CK Table 3 - IDD0 Measurement-Loop Patterna) 0 3,4 ... nRAS Static High toggling ... repeat pattern 1...4 until nRAS - 1, truncate if necessary PRE 0 0 1 0 0 0 00 0 repeat pattern 1...4 until nRC - 1, truncate if necessary 1*nRC+0 ACT 0 0 1 1 0 0 00 0 0 F 0 - 1*nRC+1, 2 D, D 1 0 0 0 0 0 00 0 0 F 0 - D, D 1 1 1 1 0 0 00 0 0 F 0 - 0 - 1*nRC+3, 4 ... 1*nRC+nRAS repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary PRE 0 0 1 0 0 0 00 0 0 ... repeat pattern 1...4 until 2*nRC - 1, truncate if necessary 1 2*nRC repeat Sub-Loop 0, use BA[2:0] = 1 instead 2 4*nRC repeat Sub-Loop 0, use BA[2:0] = 2 instead 3 6*nRC repeat Sub-Loop 0, use BA[2:0] = 3 instead 4 8*nRC repeat Sub-Loop 0, use BA[2:0] = 4 instead 5 10*nRC repeat Sub-Loop 0, use BA[2:0] = 5 instead 6 12*nRC repeat Sub-Loop 0, use BA[2:0] = 6 instead 7 14*nRC repeat Sub-Loop 0, use BA[2:0] = 7 instead F a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. b) DQ signals are MID-LEVEL. Rev. 1.0 / Aug. 2012 52 Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 ACT 0 0 1 1 0 0 00 0 0 0 0 - 1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 - D, D 1 1 1 1 0 0 00 0 0 0 0 - 0 0 00000000 0 0 0 - Cycle Number Datab) Sub-Loop CKE CK, CK Table 4 - IDD1 Measurement-Loop Patterna) 0 3,4 ... nRCD ... nRAS Static High toggling ... repeat pattern 1...4 until nRCD - 1, truncate if necessary RD 0 1 0 1 0 0 00 0 0 repeat pattern 1...4 until nRAS - 1, truncate if necessary PRE 0 0 1 0 0 0 00 0 repeat pattern 1...4 until nRC - 1, truncate if necessary 1*nRC+0 ACT 0 0 1 1 0 0 00 0 0 F 0 - 1*nRC+1,2 D, D 1 0 0 0 0 0 00 0 0 F 0 - D, D 1 1 1 1 0 0 00 0 0 F 0 - 1*nRC+3,4 ... 1*nRC+nRCD ... 1*nRC+nRAS repeat pattern nRC + 1,...4 until nRC + nRCE - 1, truncate if necessary RD 0 1 0 1 0 0 00 0 0 F 0 00110011 repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary PRE 0 0 1 0 0 0 00 0 0 F ... repeat pattern nRC + 1,...4 until *2 nRC - 1, truncate if necessary 1 2*nRC repeat Sub-Loop 0, use BA[2:0] = 1 instead 2 4*nRC repeat Sub-Loop 0, use BA[2:0] = 2 instead 3 6*nRC repeat Sub-Loop 0, use BA[2:0] = 3 instead 4 8*nRC repeat Sub-Loop 0, use BA[2:0] = 4 instead 5 10*nRC repeat Sub-Loop 0, use BA[2:0] = 5 instead 6 12*nRC repeat Sub-Loop 0, use BA[2:0] = 6 instead 7 14*nRC repeat Sub-Loop 0, use BA[2:0] = 7 instead 0 - a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MIDLEVEL. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID_LEVEL. Rev. 1.0 / Aug. 2012 53 Static High CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 D 1 0 0 0 0 0 0 0 0 0 0 - 1 D 1 0 0 0 0 0 0 0 0 0 0 - 2 D 1 1 1 1 0 0 0 0 0 F 0 - 3 D 1 1 1 1 0 0 0 0 0 F 0 - Cycle Number Command 0 toggling Datab) Sub-Loop CKE CK, CK Table 5 - IDD2N and IDD3N Measurement-Loop Patterna) 1 4-7 repeat Sub-Loop 0, use BA[2:0] = 1 instead 2 8-11 repeat Sub-Loop 0, use BA[2:0] = 2 instead 3 12-15 repeat Sub-Loop 0, use BA[2:0] = 3 instead 4 16-19 repeat Sub-Loop 0, use BA[2:0] = 4 instead 5 20-23 repeat Sub-Loop 0, use BA[2:0] = 5 instead 6 24-17 repeat Sub-Loop 0, use BA[2:0] = 6 instead 7 28-31 repeat Sub-Loop 0, use BA[2:0] = 7 instead a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. b) DQ signals are MID-LEVEL. Static High CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 D 1 0 0 0 0 0 0 0 0 0 0 - 1 D 1 0 0 0 0 0 0 0 0 0 0 - 2 D 1 1 1 1 0 0 0 0 0 F 0 - 3 D 1 1 1 1 0 0 0 0 0 F 0 - Cycle Number Command 0 toggling Datab) Sub-Loop CKE CK, CK Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Patterna) 1 4-7 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1 2 8-11 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2 3 12-15 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3 4 16-19 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4 5 20-23 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5 6 24-17 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6 7 28-31 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7 a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. b) DQ signals are MID-LEVEL. Rev. 1.0 / Aug. 2012 54 CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 RD 0 1 0 1 0 0 00 0 0 0 0 00000000 1 D 1 0 0 0 0 0 00 0 0 0 0 - 2,3 D,D 1 1 1 1 0 0 00 0 0 0 0 - 4 RD 0 1 0 1 0 0 00 0 0 F 0 00110011 5 D 1 0 0 0 0 0 00 0 0 F 0 - D,D 1 1 1 1 0 0 00 0 0 F 0 - Cycle Number Command Static High 0 toggling Datab) Sub-Loop CKE CK, CK Table 7 - IDD4R and IDDQ4R Measurement-Loop Patterna) 6,7 1 8-15 repeat Sub-Loop 0, but BA[2:0] = 1 2 16-23 repeat Sub-Loop 0, but BA[2:0] = 2 3 24-31 repeat Sub-Loop 0, but BA[2:0] = 3 4 32-39 repeat Sub-Loop 0, but BA[2:0] = 4 5 40-47 repeat Sub-Loop 0, but BA[2:0] = 5 6 48-55 repeat Sub-Loop 0, but BA[2:0] = 6 7 56-63 repeat Sub-Loop 0, but BA[2:0] = 7 a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL. A[2:0] 1 1 1 1 1 1 = = = = = = = A[6:3] ODT WE CAS RAS CS 0 1 0 0 1 0 0 0 1 1 1 1 0 1 0 0 1 0 0 0 1 1 1 1 Sub-Loop 0, but BA[2:0] Sub-Loop 0, but BA[2:0] Sub-Loop 0, but BA[2:0] Sub-Loop 0, but BA[2:0] Sub-Loop 0, but BA[2:0] Sub-Loop 0, but BA[2:0] Sub-Loop 0, but BA[2:0] A[9:7] WR D D,D WR D D,D repeat repeat repeat repeat repeat repeat repeat A[10] 1 2 3 4 5 6 7 1 2,3 4 5 6,7 8-15 16-23 24-31 32-39 40-47 48-55 56-63 A[15:11] 0 BA[2:0] 0 Command Cycle Number Sub-Loop CKE Static High toggling CK, CK Table 8 - IDD4W Measurement-Loop Patterna) Datab) 0 0 0 0 0 0 00 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F F F 0 0 0 0 0 0 00000000 00110011 - 1 2 3 4 5 6 7 a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL. b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL. Rev. 1.0 / Aug. 2012 55 Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 0 REF 0 0 0 1 0 0 0 0 0 0 0 - 1 1.2 D, D 1 0 0 0 0 0 00 0 0 0 0 - D, D 1 1 1 1 0 0 00 0 0 F 0 - Cycle Number Datab) Sub-Loop CKE CK, CK Table 9 - IDD5B Measurement-Loop Patterna) Static High toggling 3,4 2 5...8 repeat cycles 1...4, but BA[2:0] = 1 9...12 repeat cycles 1...4, but BA[2:0] = 2 13...16 repeat cycles 1...4, but BA[2:0] = 3 17...20 repeat cycles 1...4, but BA[2:0] = 4 21...24 repeat cycles 1...4, but BA[2:0] = 5 25...28 repeat cycles 1...4, but BA[2:0] = 6 29...32 repeat cycles 1...4, but BA[2:0] = 7 33...nRFC-1 repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary. a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. b) DQ signals are MID-LEVEL. Rev. 1.0 / Aug. 2012 56 Table 10 - IDD7 Measurement-Loop Patterna) 2 3 4 Static High 5 6 7 8 9 10 4*nRRD nFAW nFAW+nRRD nFAW+2*nRRD nFAW+3*nRRD nFAW+4*nRRD 2*nFAW+0 2*nFAW+1 2&nFAW+2 11 2*nFAW+nRRD 2*nFAW+nRRD+1 2&nFAW+nRRD+2 12 13 2*nFAW+2*nRRD 2*nFAW+3*nRRD 14 2*nFAW+4*nRRD 15 16 17 18 3*nFAW 3*nFAW+nRRD 3*nFAW+2*nRRD 3*nFAW+3*nRRD 19 3*nFAW+4*nRRD 00110011 - 0 - 0 - 0 0 0 00110011 - 0 0 0 00000000 - 0 - 0 - A[10] 0 0 0 ODT 00000000 - WE 0 0 0 CAS ACT 0 0 1 1 0 0 00 0 0 0 RDA 0 1 0 1 0 0 00 1 0 0 D 1 0 0 0 0 0 00 0 0 0 repeat above D Command until nRRD - 1 ACT 0 0 1 1 0 1 00 0 0 F RDA 0 1 0 1 0 1 00 1 0 F D 1 0 0 0 0 1 00 0 0 F repeat above D Command until 2* nRRD - 1 repeat Sub-Loop 0, but BA[2:0] = 2 repeat Sub-Loop 1, but BA[2:0] = 3 D 1 0 0 0 0 3 00 0 0 F Assert and repeat above D Command until nFAW - 1, if necessary repeat Sub-Loop 0, but BA[2:0] = 4 repeat Sub-Loop 1, but BA[2:0] = 5 repeat Sub-Loop 0, but BA[2:0] = 6 repeat Sub-Loop 1, but BA[2:0] = 7 D 1 0 0 0 0 7 00 0 0 F Assert and repeat above D Command until 2* nFAW - 1, if necessary ACT 0 0 1 1 0 0 00 0 0 F RDA 0 1 0 1 0 0 00 1 0 F D 1 0 0 0 0 0 00 0 0 F Repeat above D Command until 2* nFAW + nRRD - 1 ACT 0 0 1 1 0 1 00 0 0 0 RDA 0 1 0 1 0 1 00 1 0 0 D 1 0 0 0 0 1 00 0 0 0 Repeat above D Command until 2* nFAW + 2* nRRD - 1 repeat Sub-Loop 10, but BA[2:0] = 2 repeat Sub-Loop 11, but BA[2:0] = 3 D 1 0 0 0 0 3 00 0 0 0 Assert and repeat above D Command until 3* nFAW - 1, if necessary repeat Sub-Loop 10, but BA[2:0] = 4 repeat Sub-Loop 11, but BA[2:0] = 5 repeat Sub-Loop 10, but BA[2:0] = 6 repeat Sub-Loop 11, but BA[2:0] = 7 D 1 0 0 0 0 7 00 0 0 0 Assert and repeat above D Command until 4* nFAW - 1, if necessary RAS Datab) CS A[9:7] A[15:11] BA[2:0] Command A[2:0] 1 0 1 2 ... nRRD nRRD+1 nRRD+2 ... 2*nRRD 3*nRRD A[6:3] 0 toggling Cycle Number Sub-Loop CKE CK, CK ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9 a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL. Rev. 1.0 / Aug. 2012 57 IDD Specifications (Tcase: 0 to 95oC) * Module IDD values in the datasheet are only a calculation based on the component IDD spec and register power. The actual measurements may vary according to DQ loading cap. 4GB, 512M x 72 R-DIMM: HMT451V7MFR8A Symbol IDD0 IDD1 IDD2N IDD2NT IDD2P0 DDR3L 1066 1169 1259 989 1034 408 DDR3L 1333 1169 1259 989 1034 408 Unit mA mA mA mA mA IDD2P1 IDD2Q IDD3N IDD3P 426 989 1034 408 1574 1574 2024 408 426 2069 426 1034 1079 453 1709 1709 2069 408 426 2249 mA mA mA mA mA mA mA mA mA mA IDD4R IDD4W IDD5B IDD6 IDD6ET IDD7 note 8GB, 1G x 72 R-DIMM: HMT41GV7MFR4A Symbol IDD0 IDD1 IDD2N IDD2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R DDR3L 1066 1574 1754 1214 1304 588 624 1214 1304 588 2204 DDR3L 1333 1574 1754 1214 1304 588 624 1304 1394 678 2474 Unit mA mA mA mA mA mA mA mA mA mA IDD4W IDD5B IDD6 IDD6ET IDD7 2204 3284 588 624 3284 2384 3374 588 624 3644 mA mA mA mA mA Rev. 1.0 / Aug. 2012 note 58 8GB, 1G x 72 R-DIMM: HMT41GV7MFR8A Symbol IDD0 IDD1 IDD2N IDD2NT IDD2P0 IDD2P1 DDR3L 1066 1394 1484 1214 1304 588 624 DDR3L 1333 1394 1484 1214 1304 588 624 Unit mA mA mA mA mA mA IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 1214 1304 588 1799 1799 2249 588 624 2294 1304 1394 678 1934 1934 2294 588 624 2474 mA mA mA mA mA mA mA mA mA DDR3L 1333 2024 2204 1664 1844 948 1020 1844 2024 1128 2924 2834 3824 948 1020 4094 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA IDD6ET IDD7 note 16GB, 2G x 72 R-DIMM: HMT82GV7MMR4A Symbol IDD0 IDD1 IDD2N IDD2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDD6ET IDD7 Rev. 1.0 / Aug. 2012 DDR3L 1066 2024 2204 1664 1844 948 1020 1664 1844 948 2654 2654 3734 948 1020 3734 note 59 16GB, 2G x 72 R-DIMM: HMT82GV7MMR8A Symbol IDD0 IDD1 IDD2N IDD2NT IDD2P0 IDD2P1 DDR3L 1066 1844 1934 1664 1844 948 1020 DDR3L 1333 1844 1934 1664 1844 948 1020 Unit mA mA mA mA mA mA IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 1664 1844 948 2249 2249 2699 948 1020 2744 1844 2024 1128 2384 2384 2744 948 1020 2924 mA mA mA mA mA mA mA mA mA IDD6ET IDD7 Rev. 1.0 / Aug. 2012 note 60 Module Dimensions 512Mx72 - HMT451V7MFR8A Front 14.90 2.10±0.15 Detail C 13.60 18.75±0.15 Registering Clock Driver 3±0.1 3±0.1 15.80±0.1 1 8.00±0.1 120 2X3.0±0.10 47.00 5.175 71.00 Detail B Detail A 128.95 133.35 SPD/TS Back 240 121 2x R0.75 Max Side Detail of Contacts B Detail of Contacts A 0.80± 0.05 Detail of Contacts C 2.50 3.65mm max 14.90 2.50±0.20 0.3 ±0.15 3.80 0.35 0.05 2.50±0.20 0.4 13.60 0.3~0.1 1.00 1.50 ±0.10 5.00 1.27±010mm max Note: 1. 0.13 tolerance on all dimensions unless otherwise stated. Units: millimeters Rev. 1.0 / Aug. 2012 61 1Gx72 - HMT41GV7MFR4A Front 14.90 2.10±0.15 Detail C 13.60 18.75±0.15 Registering Clock Driver 3±0.1 3±0.1 15.80±0.1 1 8.00±0.1 120 2X3.0±0.10 47.00 5.175 71.00 Detail B Detail A 128.95 133.35 SPD/TS Back 240 121 2x R0.75 Max Side Detail of Contacts B Detail of Contacts A Detail of Contacts C 3.65mm max 0.80± 0.05 2.50 14.90 2.50±0.20 0.3 ±0.15 3.80 0.35 0.05 2.50±0.20 0.4 13.60 0.3~0.1 1.00 1.50 ±0.10 5.00 1.27±010mm max Note: 1. 0.13 tolerance on all dimensions unless otherwise stated. Units: millimeters Rev. 1.0 / Aug. 2012 62 1Gx72 - HMT41GV7MFR8A Front 14.90 2.10±0.15 Detail C 13.60 18.75±0.15 Registering Clock Driver 3±0.1 3±0.1 15.80±0.1 1 8.00±0.1 120 2X3.0±0.10 47.00 5.175 71.00 Detail B Detail A 128.95 133.35 SPD/TS Back 240 121 2x R0.75 Max Side Detail of Contacts B Detail of Contacts A Detail of Contacts C 3.65mm max 0.80± 0.05 2.50 14.90 2.50±0.20 0.3 ±0.15 3.80 0.35 0.05 2.50±0.20 0.4 13.60 0.3~0.1 1.00 1.50 ±0.10 5.00 1.27±010mm max Note: 1. 0.13 tolerance on all dimensions unless otherwise stated. Units: millimeters Rev. 1.0 / Aug. 2012 63 2Gx72 - HMT82GV7MMR4A Front 14.90 2.10±0.15 Detail C 13.60 18.75±0.15 15.80±0.1 DDP DDP DDP DDP Registering Clock Driver DDP DDP 3±0.1 DDP DDP DDP 3±0.1 1 8.00±0.1 120 2X3.0±0.10 47.00 5.175 71.00 Detail B Detail A 128.95 133.35 240 DDP DDP DDP DDP DDP SPD/TS DDP DDP DDP DDP Back 121 2x R0.75 Max Side Detail of Contacts B Detail of Contacts A Detail of Contacts C 3.65mm max 0.80± 0.05 2.50 14.90 2.50±0.20 0.3 ±0.15 3.80 0.35 0.05 2.50±0.20 0.4 13.60 0.3~0.1 1.00 1.50 ±0.10 5.00 1.27±010mm max Note: 1. 0.13 tolerance on all dimensions unless otherwise stated. Units: millimeters Rev. 1.0 / Aug. 2012 64 2Gx72 - HMT82GV7MMR4A - Heat Spreader Front 29 29 18.75±0.15 DDP DDP DDP DDP SPD/TS DDP DDP DDP DDP DDP 12.3 13.3 1 120 127 DDP DDP DDP DDP DDP SPD/TS DDP DDP DDP DDP Back 240 121 Detail of Contacts A Detail of Contacts B Side Detail of Contacts C 0.80± 0.05 7.55mm max 2.50 9.8 2.50±0.20 0.3 ±0.15 3.80 0.35 0.05 2.50±0.20 0.4 8.5 0.3~1.0 1.00 1.50 ±0.10 5.00 Note: 1. 0.13 tolerance on all dimensions unless otherwise stated. 2.In order to uninstall FDHS, please contact sales administrator. Rev. 1.0 / Aug. 2012 6.2mm 1.27±010mm max Units: millimeters 65 2Gx72 - HMT82GV7MMR8A Front 14.90 2.10±0.15 Detail C 13.60 18.75±0.15 15.80±0.1 DDP DDP DDP DDP Registering Clock Driver DDP DDP 3±0.1 DDP DDP DDP 3±0.1 1 8.00±0.1 120 2X3.0±0.10 47.00 5.175 71.00 Detail B Detail A 128.95 133.35 240 DDP DDP DDP DDP DDP SPD/TS DDP DDP DDP DDP Back 121 2x R0.75 Max Side Detail of Contacts B Detail of Contacts A Detail of Contacts C 3.65mm max 0.80± 0.05 2.50 14.90 2.50±0.20 0.3 ±0.15 3.80 0.35 0.05 2.50±0.20 0.4 13.60 0.3~0.1 1.00 1.50 ±0.10 5.00 1.27±010mm max Note: 1. 0.13 tolerance on all dimensions unless otherwise stated. Units: millimeters Rev. 1.0 / Aug. 2012 66 2Gx72 - HMT82GV7MMR8A - Heat Spreader Front 29 29 18.75±0.15 DDP DDP DDP DDP SPD/TS DDP DDP DDP DDP DDP 12.3 13.3 1 120 127 DDP DDP DDP DDP DDP SPD/TS DDP DDP DDP DDP Back 240 121 Detail of Contacts A Detail of Contacts B Side Detail of Contacts C 0.80± 0.05 7.55mm max 2.50 9.8 2.50±0.20 0.3 ±0.15 3.80 0.35 0.05 2.50±0.20 0.4 8.5 0.3~1.0 1.00 1.50 ±0.10 5.00 Note: 1. 0.13 tolerance on all dimensions unless otherwise stated. 2.In order to uninstall FDHS, please contact sales administrator. Rev. 1.0 / Aug. 2012 6.2mm 1.27±010mm max Units: millimeters 67