IS31FL3726 16-BIT COLOR LED DRIVER WITH PWM CONTROL January 2012 GENERAL DESCRIPTION The IS31FL3726 is comprised of constant-current drivers designed for color LEDs. The output current value can be set using an external resistor. The output current value can be adjusted from 5mA to 60mA through the external resistor. As a result, all outputs will have virtually the same current levels. This driver incorporates 16-bit constant t-current outputs, a 16-bit shift register, a 16-bit latch and a 16-bit AND-gate circuit. These drivers have been designed using the CMOS process. Output voltage ≥0.4V APPLICATIONAS FEATURES Output current capability and number of outputs: 60mA × 16 outputs Constant current range: 5mA to 60mA Application output voltage: ≥0.4V For anode-common LEDs Power supply voltage range, VDD = 3.3V to 5.5V Serial and parallel data transfer rate: 20MHz (Max. cascade connection) Operating temperature range, TA = −40°C ~ +85°C Package: QFN-24 Current accuracy (All output on) Current Accuracy Between Bits Between ICs ±4% ±12% Output Current 5 to 60 mA Cellular phones MP3/MP4/CD/minidiskplayers Toys BLOCK DIAGRAM Figure 1 Integrated Silicon Solution, Inc. — www.issi.com Rev.A, 12/19/2011 Block Diagram 1 IS31FL3726 TYPICAL APPLICATION CIRCUIT LDO 3.3V Vbat VDD 0.1uF O1 O2 MICROCONTROLLER O3 . .. .. . SERIAL-IN ENABLE LATCH O14 O15 GND REXT CLOCK O16 R1=2kohm(tpy.) Figure 2 Integrated Silicon Solution, Inc. — www.issi.com Rev.A, 12/19/2011 Typical Application Figure 2 IS31FL3726 PIN CONFIGURATION 19 OUT11 20 OUT12 21 OUT13 22 OUT14 23 OUT15 Pin Configuration (Top View) 24 ENABLE Package SERIAL-OUT 1 18 OUT10 R-EXT 2 17 OUT9 VDD 3 16 OUT8 GND 4 15 OUT7 SERIAL-IN 5 14 OUT6 CLOCK 6 13 OUT5 OUT4 12 9 OUT1 OUT3 11 8 OUT0 OUT2 10 7 LATCH QFN-24 PIN DESCRIPTION No Pin Description 1 SERIAL-OUT Output terminal for serial data input on SERIAL-IN terminal. 2 R-EXT Input terminal used to connect an external resistor. This regulated the output current. 3 VDD Supply voltage terminal. 4 GND GND terminal for control logic. 5 SERIAL-IN Input terminal for serial data for data shift register. 6 CLOCK Input terminal for clock for data shift on rising edge. 7 ———————— 8 ~ 23 —————— 24 ————————— ———————— LATCH ——————— OUT0 ~OUT15 Input terminal for data strobe When the L A T C H input is driven High, data is not latched. When it is pulled Low ， data is latched. Constant-current output terminals. Input terminal for output enable. —————— ENABLE Thermal Pad ——————— All outputs (OUT0 to OUT15) are turned off, when the ————————— ENABLE terminal is driven High .And are turned on, when the terminal is driven Low. Connect to GND. Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com Rev.A, 12/19/2011 3 IS31FL3726 ORDERING INFORMATION Industrial Range: -40°C to +85°C Order Part No. Package QTY/Reel IS31FL3726-QFLS2-TR QFN-24, Lead-free 2500 Integrated Silicon Solution, Inc. — www.issi.com Rev.A, 12/19/2011 4 IS31FL3726 n=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 H CLOCK L H SERIAL-IN L H L LATCH H ENABLE L ON OUT0 OFF ON OFF OUT1 ON OUT2 OFF ON OFF OUT15 H SERIAL-OUT L Timing Dagram Figure 3 Warning: Latch circuit is leveled-latch circuit. Be careful because it is not triggered-latch circuit. ———————— ———————— Note : The latches circuit holds data by pulling the L A T C H terminal Low. And, when L A T C H terminal is a High level, latch circuit ————————— —————— ——————— doesn’t hold data, and it passes from the input to the output. When E N A B L E terminal is a Low level, output terminal O U T 0 to O U T 1 5 ————————— respond to the data, and on and off does. And, when E N A B L E terminal is a High level, it offs with the output terminal regardless of the data. Truth Table CLOCK ————— ———————— ————————— ENABLE SERIAL-IN H L L —————— —————— ——————— OUT0 …OUT7 … OUT15 SERIAL-OUT Dn Dn …Dn-7 …Dn-15 Dn-15 L Dn+1 No change Dn-14 H L Dn+2 Dn+2 …Dn-5 …Dn-13 Dn-13 X L Dn+3 Dn+2 …Dn-5 …Dn-13 Dn-13 X H Dn+3 OFF Dn-13 LATCH ————— ————— ————— Note : OUT0 to OUT15 =On when Dn = H; OUT0 to OUT15 =Off when Dn = L. In order to ensure that the level of the power supply voltage is correct, an external resistor must be connected between R-EXT and GND. ____________ __________ Warning: When VDD < 2.5V or the start up time is less than 1ms, the following conditions, ENABLE=0, LATCH=1, SERIAL-IN=1, cannot be configured at the same time, or SN3726 will be abnormal. Integrated Silicon Solution, Inc. — www.issi.com Rev.A, 12/19/2011 5 IS31FL3726 ABSOLUTE MAXIMUM RATINGS Supply voltage, VDD Voltage at any input pin Maximum junction temperature, TJMAX Storage temperature range, TSTG Operating temperature range, TA ESD (HBM) -0.3V ~ +6.0V -0.3V ~ VDD+0.2V 150°C -65°C ~ +150°C −40°C ~ +85°C 3kV Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITION TA = 25°C, unless otherwise specified. Characteristic Symbol Supply voltage VDD Output voltage VOUT Output current Condition 0.7 Set-up time for L A T C H terminal V 60 mA/ch IOL SERIAL-OUT 1 5 1.4 0.4 fCLK twCLK ———————— 4 -1 CLOCK pulse width Hold time for CLOCK terminal V SERIAL-OUT twLAT Set-up time for CLOCK terminal 5.5 IOH L A T C H pulse width ENABLE pulse width (note ) Unit Each DC 1 circuit ———————— ————————— Max. IOUT VIL Clock frequency Typ. 3.3 VIH Input voltage Min. twENA Cascade connected 20 mA V MHz 50 ns 25 ns Upper IOUT = 20mA 2000 Lower IOUT = 20mA 3000 ns tSETUP1 10 ns tHOLD 10 ns tSETUP2 50 ns ————————— Note : When the pulse of the Low level is input to the E N A B L E terminal held in the High level. Integrated Silicon Solution, Inc. — www.issi.com Rev.A, 12/19/2011 6 IS31FL3726 ELECTRICAL CHARACTERISTICS TA = 25°C, VDD = 3.3V ~ 5.5V, unless otherwise specified. Characteristic Supply voltage Symbol 5.5 V VOUT = 0.4V VDD = 3.3V 15 18.7 22 IOUT2 VOUT = 0.4V VDD = 5V 15 18.9 22 ±3 ±4 % 1 uA IOZ VOUT≥0.4V, All outputs on REXT = 1kΩ mA REXT = 1kΩ VOUT = 5.0V VIH 1.4 VIL VOL SOUT terminal voltage VOH %/VDD R(Up) R(Down) IDD(OFF)1 Supply current Unit IOUT1 Output leakage current input voltage Pull-down resistor Max. 3.3 △IOUT1 Pull-up resistor Typ. Normal operation Output current error between bits Output current supply voltage regulation Min. VDD Output current Input voltage Condition 0.4 IOL = 1.0mA, VDD = 3.3V 0.3 IOL = 1.0mA, VDD = 5V 0.3 IOH = -1.0mA, VDD = 3.3V IOH = -1.0mA, VDD = 5V 3 V V 4.7 When VDD is changed 3.3V to 5.5V -1 % ————————— ENABLE terminal ———————— L A T C H terminal VOUT = 5V REXT = OPEN 250 500 kΩ 1 IDD(OFF)2 VOUT = 5V All outputs off REXT = 1kΩ 4.5 IDD(ON)1 VOUT = 0.7V All outputs on REXT = 1kΩ 5 Integrated Silicon Solution, Inc. — www.issi.com Rev.A, 12/19/2011 750 mA 7 IS31FL3726 SWITCHING CHARACTERISTICS TA = 25°C, unless otherwise specified. Characteristic Symbol Condition —————— tpLH1 Propagation delay Max. 80 200 ————————— 80 200 ———————— 130 250 CLK-OUTn , L A T C H = “H” ENABLE = “L” ———————— tpLH3 ————————— —————— —————— L A T C H –OUTn , ENABLE = “L” ENABLE -OUTn , L A T C H = “H” CLK-SERIAL OUT —————— tpHL1 Typ. ————————— tpLH2 tpLH Min. 3 5 ns ———————— CLK-OUTn , L A T C H = “H” ————————— ENABLE = “L” 160 250 tpHL2 ———————— —————— L A T C H -OUTn , ENABLE = “L” ————————— 160 250 tpHL3 ————————— —————— ———————— 200 350 tpLH Unit ———————— ENABLE -OUTn , L A T C H = “H” CLK-SERIAL OUT 4 6 Output rise time tor 10%~90% of voltage waveform 30 150 200 ns Output fall time tof 90%~10% of voltage waveform 150 200 250 ns Maximum CLOCK rise time tr 5 us Maximum CLOCK fall time tf 5 us When not on PCB （Note ) Conditions: (Refer to test circuit.) Topr = 25°C, VDD=VIH =3.3 V and 5 V, VOUT = 0.7 V, VIL =0 V, REXT =1000Ω,VL =3.0 V, RL=60Ω, CL=10.5 pF Note: 1. If the device is connected in a cascade and tr/tf for the waveform is large, it may not be possible to achieve the timing required for data transfer. Please consider the timings carefully. 2. Delay between outputs. The IS31FL3726 has graduated delay circuits between outputs. The fixed delay time is 5ns (typical), OUT1 has 5ns delay, OUT2 has 10 ns delay, etc. This delay prevents large inrush currents, which reduce power supply bypass capacitor requirements when ——————— the outputs turn on. The delay works during switch on and switch off of each output channel. LEDs that have not turned on before ENABLE is ——————— low will still turn on and off at the determined delayed time regardless of the state of ENABLE. Therefore, every LED will be illuminated for the ——————— amount of time ENABLE is pulled high. Figure 4 Integrated Silicon Solution, Inc. — www.issi.com Rev.A, 12/19/2011 Test Diagram 8 IS31FL3726 TIMING WAVEFORM 1．CLOCK, SERIAL-IN,SERIAL-OUT ———————— —————————— —————— 2. CLOCK, SERIAL-IN, L A T C H , E N A B L E , OUTn —————— 3. OUTn Integrated Silicon Solution, Inc. — www.issi.com Rev.A, 12/19/2011 9 IS31FL3726 TYPICAL OPERATING CHARACTERISTICS ADJUSTING OUTPUT CURRENT The output current of each channel is set by an external resistor Rext, the relationship between Iout and Rext is: Iout = (VR-ext/Rext)×52 the VR-ext is 0.36V in the IS31FL3726,so we can count the Iout as : Iout = 0.36×52/Rext. As show in the figure below: 50 -40°C 45 25°C 85°C LED current(mA) 40 35 30 25 20 15 10 400 600 800 1000 1200 1400 1600 Rset(Ω) Integrated Silicon Solution, Inc. — www.issi.com Rev.A, 12/19/2011 10 IS31FL3726 CLASSIFICATION REFLOW PROFILES Profile Feature Pb-Free Assembly Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) 150°C 200°C 60-120 seconds Average ramp-up rate (Tsmax to Tp) 3°C/second max. Liquidous temperature (TL) Time at liquidous (tL) 217°C 60-150 seconds Peak package body temperature (Tp)* Max 260°C Time (tp)** within 5°C of the specified classification temperature (Tc) Max 30 seconds Average ramp-down rate (Tp to Tsmax) 6°C/second max. Time 25°C to peak temperature 8 minutes max. Figure 5 Classification Profile Integrated Silicon Solution, Inc. — www.issi.com Rev.A, 12/19/2011 11 IS31FL3726 TAPE AND REEL INFORMATION Integrated Silicon Solution, Inc. — www.issi.com Rev.A, 12/19/2011 12 IS31FL3726 PACKAGE INFORMATION QFN-24 Note: All dimensions in millimeters unless otherwise stated. Integrated Silicon Solution, Inc. — www.issi.com Rev.A, 12/19/2011 13