TOSHIBA TB62726AFNA 16-bit constant current LED driver with operating supply of 3.3V to 5V TB62726AFNA Data Sheet Version No. Date Note Inspect 001 2002-4-26 Target spec by AFNA 002 2002-5-15 The setup of the tentative Spec of Iout 003 2002-5-21 Evaluation set of Iout Spec. 004 2002-5-28 The reflection of the test Spec. 005 2002-6-1 Some of proofreading 006 2002-6-22 Some of proofreading 007 2002-10-1 A format is changed. 008 2002-10-11 IOUT Spec. reexamination 009 2002-11-6 Final Spec. We agree this specification. Company Date Signature TB62726AFNA(Ver.9) 2002,Nov.6th page00/11 TOSHIBA TB62726AFNA TOSHIBA Bi-CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC TB62726AFNA 16-bit constant current LED driver with operation supply of 3.3V to 5V The TB62726AFNA is comprised of constant-current drivers designed for LEDs and LED displays. The output current value can be set using an external resistor. As a result, all outputs will have virtually the same current levels. This driver incorporates a 16-bit constant-current output, a 16-bit shift register, a 16-bit latch and a gate circuit. These drivers have been designed using the Bi-CMOS process. TB62726AFNA Feature *Output current capability and the number of output: 90 mA x 16 outputs *Constant current range : 2 to 90 mA *Application output voltage : 0.7V (output current 2 to 80mA) 0.4V (output current 2 to 40mA) *For anode common LED *Input signal voltage level : 3.3V-5.0V CMOS level (schmitt trigger input) *Power supply voltage range VDD=3.0 to 5.5V *Muximum output terminal voltage 17V *Serial and parallel data transfer rate 20 MHz (min., Cascade Connection) *Operation temperature range topr = -40 to 85 degrees *Package : P-SSOP24-150-0.635 *Current accuracy (not used dot-current correction.) Output voltage >= 0.4V >= 0.7V Current accuracy P-SSOP24-150-0.635 Output between bits between ICs current +/- 4 % +/- 12 % 2 to 40 mA 2 to 90 mA TB62726AFNA (Ver.9) 2002, Nov. 5th page 1/11 TOSHIBA TB62726AFNA Package and pin layout ( Top view ) OUT14 OUT15 ENABLE SERIAL-OUT R-EXT VDD GND SERIAL-IN CLOCK LATCH OUT0 OUT1 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 Warnings : Short-circuiting an output terminal to GND or to the power supply terminal may broken the device. Please take care when wiring the output terminals, the power supply terminal and the GND terminals. Block Diagram OUT0 R-EXT OUT1 OUT15 I-REG ENABLE Q Q Q ST D ST D ST D LATCH SERIAL-IN D Q D Q D Q CK CK CK SERIAL-OUT CLOCK Truth Table CLOCK LATCH ENABLE SERIAL-IN OUT0 --- OUT7 --- OUT15 SERIAL-OUT Positive edge H L Dn Dn --- Dn-7 --- Dn-15 Dn-15 Positive edge L L Dn+1 No Change Dn-14 Positive edge H L Dn+2 Dn+2 --- Dn-5 --- Dn-13 Dn-13 Negative edge X L Dn+3 Dn+2 --- Dn-5 --- Dn-13 Dn-13 Negative edge X H Dn+3 Off Dn-13 Note 1: OUT0~OUT15=ON when Dn=H ; OUT0~OUT15=OFF when Dn=L In order to ensure that the level of the power supply voltage is correct, an external resistor have to connected between R-EXT and GND. TB62726AFNA (Ver.09) 2002, Nov. 6th page 2/11 TOSHIBA TB62726AFNA Timing diagram n=01 2 3 4 5 6 7 8 9 101112131415 CLOCK 5V 0V SERIAL-IN 5V 0V LATCH 5V 0V ENABLE 5V 0V OUT0 On Off OUT1 On Off OUT3 On Off OUT15 On Off SERIAL-OUT 5V 0V Warning : Latch circuit is leveled-latch circuit. Be careful because it is not triggered-latch circuit. Note 2 : The latches circuit holds data by pulling the LATCH terminal Low. And, when LATCH terminal is a High-level, latch circuit doesn’t hold data, and it passes from theInput to the output. When ENABLE terminal is Low-level, output terminal OUT0~OUT15 respond to the data, and on & off does. And, when ENABLE terminal is a High-level, it offs with the output terminal regardless of the data. TB62726AFNA (Ver.09) 2002, Nov. 6th page 3/11 TOSHIBA TB62726AFNA Terminal description Pin No. 7 8 9 Pin Name GND SERIAL-IN CLOCK 10 LATCH 1 to 2, 11 to 24 OUT 0 to 7 Function GND terminal for control logic Input terminal for serial data for data shift register Input terminal for clock for data shift on rising edge Input terminal for data strobe When the LATCH=High-level, data is no latched. When ithe LATCH=Low-level, data is latched. Constant-current output terminals Input terminal for output enable. All outputs (OUT0 ~ OUT15 ) are turned off, when the ENABLE=High-level. And are turned on, when the ENABLE=Low-level. SERIAL-OUT Output terminal for serial data input on SERIAL-IN terminal R-EXT Input terminal used to connect an external resistor. This regulated the output current. VDD 3.3V - 5V supply voltage terminal. 3 ENABLE 4 5 6 Equivalent circuit of inputs and output VDD 2. LATCH Terminal R(UP) VDD 200k 1. ENABLE Terminal LATCH GND GND 3. CLOCK,SERIAL-IN Terminal 4. SERIAL-OUT Terminal VDD VDD CLOCK, SERIAL - IN Internal data GND GND 250k ENABLE R(DOWN) SERIAL - OUT 5. OUT0 to 15 Terminal OUT 0 to 15 Parasitic Diode GND TB62726AFNA (Ver.09) 2002, Nov. 6th page 4/11 TOSHIBA TB62726AFNA Absolute maximum ratings Characteristics Supply Voltage Symbol VDD Rating +6 Unit Input Voltage Output Current Output Voltage Power Dissipation Thermal Resistance Operating Temperature VIN IOUT VOUT Pd1 Rth(j-a) Topr -0.2 to VDD+0.2 +90 -0.2 to 17 0.89 140 (Free Air) -40 to 85 Storage Temperature Tstg -55 to 150 V mA/ch V W degree/W degree Note 3 : Subtract 7.10mW/degree every time an ambient temperature exceeds 25 times once. Recommended operating condition ( VDD=4.5~5.5V, Topr = -40~85 degree, unless otherwise noted. ) Characteristics Supply Voltage Output Voltage Symbol VDD VOUT(On) IOUT Output Current IOH IOL Input Voltage VIH VIL Clock Frequency fCLK LATCH Pulse Width tw LATCH CLOCK Pulse Width tw CLOCK ENABLE Pulse Width When the pulse of the Low level is inputted to the ENABLE terminal held in the H level. Setup Time for CLOCK Terminal Hold Time for CLOCK Terminal Setup Time for /LATCH Terminal Condition Each DC 1 Circuit Min 3 2 Typ 0.7 - Max 5.5 4 80 - - -1 - - 1 0.7xVDD - VDD+0.15 -0.15 - 0.3xVDD - - 20 Cascade Connected 50 25 - - Upper IOUT=20mA 2000 - - Lower IOUT=20 mA 3000 - - 10 10 - - 50 - - SERIAL-OUT - Unit V V mA/ch mA V MHz tw ENABLE t SETUP1 t HOLD ns - t SETUP2 TB62726AFNA (Ver.09) 2002, Nov. 6th page 5/11 TOSHIBA TB62726AFNA Electrical characteristics ( VDD=3V to 5.5V, Topr=25degree unless otherwise noted.) Characteristics Supply voltage Output current Output current error between bits Symbol VDD IOUT1 IOUT2 IOUT3 IOUT4 dIOUT1 dIOUT2 Output leakage Current Input voltage IOZ Input voltage VIN SOUT terminal Voltage Output current supply voltage regulation Pull up resistor Pull down resistor Supply current VOL VOH %/VDD R(UP) R(DOWN) IDD(OFF)1 IDD(OFF)2 IDD(OFF)3 IDD(ON)1 IDD(ON)2 Condition Normal operation VOUT=0.4V,VDD=3.3V REXT= VOUT=0.4V,VDD=5V 490 ohm VOUT=0.7V,VDD=3.3V REXT= VOUT=0.7V,VDD=5V 250 ohm VOUT=0.4V, REXT=490 ohm All output ON VOUT=0.4V, REXT=250 ohm Min 3.0 31.96 31.59 63.63 62.75 Typ 36.20 35.90 72.30 71.30 Max 5.5 40.54 40.20 80.97 79.95 Unit V - +/-1 +/-4 % VOUT=15V - - 1 uA IOL=+1 mA, Vdd=3.3V IOL=+1 mA, Vdd=5V IOH=-1 mA, Vdd=3.3V IOH=+1 mA,Vdd=5V 0.7VDD GND . 3 4.7 - VDD 0.3VDD 0.3 0.3 - When VDD is changed 3V to 5.5V - -1 -5 . 115 230 460 . 1 . 4 0.1 3.5 6 0.5 5 9 - 9 15 - - 20 - 18 25 - - 40 ENABLE terminal LATCH terminal REXT=Open, VOUT=15V REXT=490ohm All output OFF, VOUT=15V REXT=250ohm All output ON, REXT=490ohm VOUT=0.7V Ta= -40degree, Same as the avobe. All output ON, REXT=250ohm VOUT=0.7V Ta= -40 degree, Same as the avobe. mA V V %/V Ohm TB62726AFNA (Ver.09) 2002, Nov. 6th page 6/11 TOSHIBA TB62726AFNA Switching characterictics (Topr=25degree, unless otherwise noted ) Characteristics Propagation delay Symbol tpLH1 Condition CLK-OUTn, LATCH=”H”, ENABLE=”L” Min - Typ 150 Max 300 tpLH2 LATCH-OUTn, ENABLE=”L” - 140 300 tpLH3 ENABLE-OUTn, LATCH=”H” - 140 300 tpLH CLK-SERIALOUT 3 6 - tpHL1 CLK-OUTn, LATCH=”H”, ENABLE=”L” - 170 340 tpHL2 LATCH-OUTn, ENABLE=”L” - 170 340 tpHL3 ENABLE-OUTn, LATCH=”H” - 170 340 tpLH CLK-SERIAL-OUT 4 7 - tor Voltage waveform 10%~90% 40 85 150 Output rise time Unit ns tof Output fall time Voltage waveform 90%~10% 40 70 150 Maximum CLK 5 tr rise time us When not on PCB Maximum CLK 5 tf fall time Condition : (Refer to test circuit) Topr=25 degree, VDD=VIH=3.3V and 5V, VOUT=0.7V, VIL=0V,REXT=490ohms, VL=3.0V, RL=60ohms,CL=10.5pF Note 4 : If the device is connected in a cascade and tr/tf for the waveform is large, it may not be possible to achieve the timing required for data transfer. Please consider the timings carefully. Test circuit IDD V ,V IH IL VDD ENABLE RL OUT0 CLOCK Function Generator C LATCH SERIAL-IN R-EXT Logic input waveform Iref L OUT15 IOL SERIAL-OUT GND CL VL VDD=VIH=3.3V VIL=0V t = t = 10ns r f (10% to 90%) TB62726AFNA (Ver.09) 2002, Nov. 6th page 7/11 TOSHIBA TB62726AFNA Timing Waveform 1. CLOCK ,SERIAL-IN, SERIAL-OUT CLOCK SERIAL-IN twCLK 50% 50% 50% t SETUP1 50% t HOLD SERIAL-OUT 50% tpLH / tpHL 2. CLOCK, SERIAL-IN , LATCH, ENABLE, OUTn CLOCK 50% SERIAL-IN LATCH ENABLE t SETUP2 50% 50% tw LAT tSETUP3 50% tw ENA OUTn 50% 50% tpLH1 / tpHL1 tpLH2 / tpHL2 3. OUTn 90% tpLH3 / tpHL3 90% OUTn 10% tOf 10% tOr TB62726AFNA (Ver.09) 2002, Nov. 6th page 8/11 TOSHIBA TB62726AFNA Output current vs duty (LEDs turn on rate) DUTY(%)-IOUT(mA) On PCB Topr= 55 degree VDD=5.0V, Vce=1.0(V), Tj=120(degC max) 100 100 80 80 IOUT(mA) IOUT(mA) DUTY(%)-IOUT(mA) On PCB Topr= 25 degree VDD=5.0V, Vce=1.0(V), Tj=120(degC max) 60 40 20 60 40 20 TB62726AFNA 0 0 20 40 60 80 TB62726AFNA 0 100 0 DUTY - Turn On Rate (%) 40 60 80 100 DUTY(%)-IOUT(mA) On PCB Topr= 85 degree VDD=5.0V, Vce=1.0(V), Tj=120(degC max) REXT-IOUT (Topr) VDD=3.3(V), VCE=0.7(V) 100 70 50 30 20 100 80 IOUT(mA) IOUT(mA) 20 DUTY - Turn On Rate (%) 10 7 5 60 40 20 TB62726AFNA 1 100 1000 10000 REXT(Ohms) 0 0 20 40 60 80 100 DUTY - Turn On Rate (%) Ta(degree) - Pd(w) 1.2 Power dissipation PD (W/IC) AFNA (On PCB) 1 0.8 0.6 0.4 0.2 0 0 10 20 30 40 50 60 70 80 90 Ambient Temperature Ta (degree) TB62726AFNA (Ver.09) 2002, Nov. 6th page 9/11 TOSHIBA TB62726AFNA Package dimmension P-SSOP24-150-0.635 13 1 12 0.150 ~ 0.157 24 0.0325 REF 0.229 ~ 0.244 TENTATIVE UNIT : Inch 0.008 ~ 0.012 0.025 0.007 ~ 0.009 0.053 ~ 0.068 0.004 ~ 0.010 0.337 ~0.344 0.016 ~ 0.0 34 TB62726AFNA (Ver.09) 2002, Nov. 6th page 10/11 TOSHIBA TB62726AFNA The information contained herein is subject to change without notice. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patens or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within spacified operating ranges as set forth in the most recent products spacifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. The products described in the document may include products subject to foreign exchange and foreign trade control laws. (C) 2000-2002 TOSHIBA CORPORATION ALL RIGHT Reserved TB62726AFNA (Ver.09) 2002, Nov. 6th page 11/11