IS66WV51216DALL IS66/67WV51216DBLL 8Mb LOW VOLTAGE, ULTRA LOW POWER PSEUDO CMOS STATIC RAM FEATURES DESCRIPTION • High-speed access time: – 70ns (IS66WV51216DALL, IS66/67WV51216DBLL) – 55ns (IS66/67WV51216DBLL) • • • • • • CMOS low power operation Single power supply – Vdd = 1.7V-1.95V (IS66WV51216DALL) – Vdd = 2.5V-3.6V (IS66/67WV51216DBLL) Three state outputs Data control for upper and lower bytes Industrial temperature available Lead-free available JULY 2011 The ISSI IS66WV51216DALL and IS66/67WV51216DBLL are high-speed, 8M bit static RAMs organized as 512K words by 16 bits. It is fabricated using ISSI's highperformance CMOS technology.This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CS1 is HIGH (deselected) or when CS2 is low (deselected) or when CS1 is low, CS2 is high and both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS66WV51216DALL and IS66/67WV51216DBLL are packaged in the JEDEC standard 48-ball mini BGA (6mm x 8mm) and 44-Pin TSOP (TYPE II). The device is aslo available for die sales. FUNCTIONAL BLOCK DIAGRAM A0-A18 DECODER 512K x 16 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte CS2 CS1 OE WE UB LB CONTROL CIRCUIT Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com Rev. A 06/28/2011 1 IS66WV51216DALL IS66/67WV51216DBLL PIN CONFIGURATIONS: 48-Ball mini BGA (6mm x 8mm) 1 A LB 2 OE 3 4 5 44-Pin TSOP (Type II) 6 A0 A1 A2 CS2 CS1 I/O0 B I/O8 UB A3 A4 C I/O9 I/O10 A5 A6 I/O1 I/O2 D GND I/O11 A17 A7 I/O3 VDD` E VDD I/O12 NC A16 I/O4 GND F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H A18 A9 A10 A11 NC A8 A4 A3 A2 A1 A0 CS1 I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 A18 A8 A9 A10 A11 A17 PIN DESCRIPTIONS A0-A18 I/O0-I/O15 CS1, CS2 OE WE LB UB NC Vdd GND 2 Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground Integrated Silicon Solution, Inc. — www.issi.com Rev. A 06/28/2011 IS66WV51216DALL IS66/67WV51216DBLL TRUTH TABLE I/O PIN Mode WE CS1 CS2 OE LB UB I/O0-I/O7 I/O8-I/O15 Not Selected X H X X X X High-Z High-Z X X L X X X High-Z High-Z X X X X H H High-Z High-Z Output Disabled H L H H L X High-Z High-Z H L H H X L High-Z High-Z Read H L H L L H Dout High-Z H L H L H L High-Z Dout H L H L L LDoutDout Write L L H X L H Din High-Z L L H X H L High-Z Din L L H X L LDinDin Vdd Current Isb1, Isb2 Isb1, Isb2 Isb1, Isb2 Icc Icc Icc Icc Note: CS2 input signal pin is only available for 48-ball mini BGA package parts. CS2 input is internally enabled for 44-pin TSOP-II package parts. OPERATING RANGE (Vdd) Range Ambient Temperature IS66WV51216DALL (70ns) IS66WV51216DBLL (55ns, 70ns) IS67WV51216DBLL (55ns, 70ns) 1.7V - 1.95V 2.5V - 3.6V – Automotive, A1 –40°C to +85°C – – 2.5V - 3.6V Automotive, A2 –40°C to +105°C – – 2.5V - 3.6V Industrial –40°C to +85°C Power-Up Initialization IS66WV512616DALL/DBLL and IS67WV512616DBLL include an on-chip voltage sensor used to launch the power-up initialization process. When VDD reaches a stable level at or above the VDD (min) , the device will require 50μs to complete its self-initialization process. During the initialization period, CS should remain HIGH. When initialization is complete, the device is ready for normal operation. ≥ 50us VDD (min) 0V VDD Device Initialization Integrated Silicon Solution, Inc. — www.issi.com Rev. A 06/28/2011 Device for Normal Operation 3 IS66WV51216DALL IS66/67WV51216DBLL ABSOLUTE MAXIMUM RATINGS(1) Symbol Vterm Tbias Vdd Tstg Pt Parameter Terminal Voltage with Respect to GND Temperature Under Bias Vdd Related to GND Storage Temperature Power Dissipation Value –0.2 to Vdd+0.3 –40 to +85 –0.2 to +3.8 –65 to +150 1.0 Unit V °C V °C W Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 2.5V-3.6V Symbol Voh Vol Vih Vil Ili Ilo Parameter Test Conditions Vdd Output HIGH Voltage Ioh = -1 mA 2.5-3.6V Output LOW Voltage Iol = 2.1 mA 2.5-3.6V Input HIGH Voltage(1) 2.5-3.6V (1) Input LOW Voltage 2.5-3.6V Input Leakage GND ≤ Vin ≤ Vdd Output Leakage GND ≤ Vout ≤ Vdd, Outputs Disabled Min. 2.2 — 2.2 –0.2 –1 –1 Max. Unit — V 0.4 V Vdd + 0.3 V 0.6 V 1µA 1µA Min. 1.4 — 1.4 –0.2 –1 –1 Max. Unit — V 0.2 V Vdd + 0.2 V 0.4 V 1µA 1µA Notes: 1. Vill (min.) = –2.0V AC (pulse width < 10ns). Not 100% tested. Vihh (max.) = Vdd + 2.0V AC (pulse width < 10ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 1.7V-1.95V Symbol Voh Vol Vih Vil Ili Ilo Parameter Test Conditions Vdd Output HIGH Voltage Ioh = -0.1 mA 1.7-1.95V Output LOW Voltage Iol = 0.1 mA 1.7-1.95V (1) Input HIGH Voltage 1.7-1.95V (1) Input LOW Voltage 1.7-1.95V Input Leakage GND ≤ Vin ≤ Vdd Output Leakage GND ≤ Vout ≤ Vdd, Outputs Disabled Notes: 1. Vill (min.) = –1.0V AC (pulse width < 10ns). Not 100% tested. Vihh (max.) = Vdd + 1.0V AC (pulse width < 10ns). Not 100% tested. 4 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 06/28/2011 IS66WV51216DALL IS66/67WV51216DBLL CAPACITANCE(1) Symbol Cin Cout Parameter Input Capacitance Input/Output Capacitance Conditions Vin = 0V Vout = 0V Max. 8 10 Unit pF pF Note: 1. Tested initially and after any design or process changes that may affect these parameters. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load R1(Ω) R2(Ω) Vref Vtm 1.7V-1.95V (Unit) 0.4V to Vdd-0.2 5 ns 1.7V - 1.95V 3070 3150 0.9V 1.8V 2.5V-3.6V (Unit) 0.4V to Vdd-0.3V 5ns Vref Vref See Figures 1 and 2 See Figures 1 and 2 2.5V - 3.6V 1029 1728 1.4V 2.8V AC TEST LOADS R1 R1 VTM VTM OUTPUT OUTPUT 30 pF Including jig and scope R2 Figure 1 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 06/28/2011 5 pF Including jig and scope R2 Figure 2 5 IS66WV51216DALL IS66/67WV51216DBLL 1.7V-1.95V POWER SUPPLY CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Icc Vdd Dynamic Operating Vdd = Max., Com. Supply Current Iout = 0 mA, f = fmax Ind. All Inputs 0.4V Auto. or Vdd – 0.2V Icc1 Operating Supply Vdd = Max., CS1 = 0.2V Com. Current WE = Vdd – 0.2V Ind. CS2 = Vdd – 0.2V, f = 1mhz Auto. Isb1 TTL Standby Current Vdd = Max., Com. (TTL Inputs) Vin = Vih or Vil Ind. CS1 = Vih , CS2 = Vil, Auto. f = 1 MHz 4 4 10 0.6 0.6 1 mA 100 120 150 µA mA OR ULB Control Isb2 CMOS Standby Current (CMOS Inputs) Max. Unit 70ns 20 mA 25 30 Vdd = Max., Vin = Vih or Vil CS1 = Vil, f = 0, UB = Vih, LB = Vih Vdd = Max., Com. CS1 ≥ Vdd – 0.2V, Ind. CS2 ≤ 0.2V, Auto. Vin ≥ Vdd – 0.2V, or Vin ≤ 0.2V, f = 0 OR ULB Control Vdd = Max., CS1 = Vil, CS2=Vih Vin ≥ Vdd – 0.2V, or Vin ≤ 0.2V, f = 0; UB / LB = Vdd – 0.2V Note:. 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 6 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 06/28/2011 IS66WV51216DALL IS66/67WV51216DBLL 2.5V-3.6V POWER SUPPLY CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Icc Vdd Dynamic Operating Vdd = Max., Com. Supply Current Iout = 0 mA, f = fmax Ind. All Inputs 0.4V Auto. or Vdd – 0.3V typ.(2) Icc1 Operating Supply Vdd = Max., CS1 = 0.2V Com. Current WE = Vdd – 0.2V Ind. CS2 = Vdd – 0.2V, f = 1mhzAuto. Isb1 TTL Standby Current Vdd = Max., Com. (TTL Inputs) Vin = Vih or Vil Ind. CS1 = Vih , CS2 = Vil, Auto. f = 1 MHz OR ULB Control Isb2 CMOS Standby Current (CMOS Inputs) Max. Unit 55ns 25 mA 28 35 15 5 mA 5 10 0.6 mA 0.6 1 Vdd = Max., Vin = Vih or Vil CS1 = Vil, f = 0, UB = Vih, LB = Vih Vdd = Max., Com. CS1 ≥ Vdd – 0.2V, Ind. CS2 ≤ 0.2V, Auto. Vin ≥ Vdd – 0.2V, or typ.(2) Vin ≤ 0.2V, f = 0 100 130 150 75 µA OR ULB Control Vdd = Max., CS1 = Vil, CS2=Vih Vin ≥ Vdd – 0.2V, or Vin ≤ 0.2V, f = 0; UB / LB = Vdd – 0.2V Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 06/28/2011 7 IS66WV51216DALL IS66/67WV51216DBLL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) 55 ns 70 ns Symbol Parameter Min. Max. Min. Max. trc Read Cycle Time 55 — 70 — taa Address Access Time — 55 — 70 toha Output Hold Time 10 — 10 — tacs1/tacs2 CS1/CS2 Access Time — 55 — 70 tdoe OE Access Time — 25 — 35 (2) thzoe OE to High-Z Output — 20 — 25 (2) tlzoe OE to Low-Z Output 5 — 5 — thzcs1/thzcs2(2) CS1/CS2 to High-Z Output 0 20 0 25 tlzcs1/tlzcs2(2) CS1/CS2 to Low-Z Output 10 — 10 — tba LB, UB Access Time — 55 — 70 thzb LB, UB to High-Z Output 0 20 0 25 tlzb LB, UB to Low-Z Output 0 — 0 — Unit ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to Vdd-0.2V/0.4V to Vdd-0.3V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±100 mV from steady-state voltage. Not 100% tested. AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = Vil, CS2 = WE = Vih, UB or LB = Vil) tRC ADDRESS tAA tOHA DQ0-D15 8 PREVIOUS DATA VALID tOHA DATA VALID Integrated Silicon Solution, Inc. — www.issi.com Rev. A 06/28/2011 IS66WV51216DALL IS66/67WV51216DBLL AC WAVEFORMS READ CYCLE NO. 2(1,3) (CS1, CS2, OE, AND UB/LB Controlled) tRC ADDRESS tAA tOHA OE tDOE CS1 tHZOE tLZOE tACE1/tACE2 CS2 tLZCE1/ tLZCE2 tHZCS1/ tHZCS1 LB, UB tLZB DOUT tBA HIGH-Z tHZB DATA VALID Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CS1, UB, or LB = Vil. CS2=WE=Vih. 3. Address is valid prior to or coincident with CS1 LOW transition. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 06/28/2011 9 IS66WV51216DALL IS66/67WV51216DBLL WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) 55 ns 70 ns Symbol Parameter Min. Max. Min. Max. twc Write Cycle Time Unit 55 — 70 — ns tscs1/tscs2 CS1/CS2 to Write End 45 — 60 — ns taw Address Setup Time to Write End 45 — 60 — ns tha Address Hold from Write End 0 — 0 — ns tsa Address Setup Time 0 — 0 — ns tpwb LB, UB Valid to End of Write 45 — 60 — tpwe WE Pulse Width 45 15,000 tsd Data Setup to Write End 25 (4) thd ns 60 15,000 ns — 30 ns 0 — 0 —ns (5) (5) — Data Hold from Write End (3) thzwe WE LOW to High-Z Output — 20 — 30 ns tlzwe(3) WE HIGH to Low-Z Output 5 — 5 — ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to Vdd-0.2V/0.4V to Vdd-0.3V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. Tested with the load in Figure 2. Transition is measured ±100 mV from steady-state voltage. Not 100% tested. 4. tpwe > thzwe + tsd when OE is LOW. 5. Refer to Avoidable Timing and Recommendations for clear definition. AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CS1 Controlled, OE = HIGH or LOW) tWC ADDRESS tHA tSCS1 CS1 tSCS2 CS2 tAW tPWE WE tPWB LB, UB tSA DOUT DATA UNDEFINED tHZWE tLZWE HIGH-Z tSD DIN tHD DATA-IN VALID Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS1 , CS2 and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CS1) [ (LB) = (UB) ] (WE). 10 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 06/28/2011 IS66WV51216DALL IS66/67WV51216DBLL WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle) tWC ADDRESS OE tHA tSCS1 CS1 tSCS2 CS2 tAW t PWE WE LB, UB tSA DOUT tHZWE tLZWE HIGH-Z DATA UNDEFINED tSD DIN tHD DATA-IN VALID WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) tWC ADDRESS OE tHA tSCS1 CS1 tSCS2 CS2 tAW t PWE WE LB, UB tSA DOUT DATA UNDEFINED tHZWE tLZWE HIGH-Z tSD DIN Integrated Silicon Solution, Inc. — www.issi.com Rev. A 06/28/2011 tHD DATA-IN VALID 11 IS66WV51216DALL IS66/67WV51216DBLL WRITE CYCLE NO. 4 (UB/LB Controlled) t WC ADDRESS t WC ADDRESS 1 ADDRESS 2 OE t SA CS1 LOW CS2 HIGH t HA t SA WE UB, LB t HA t PWB t PWB WORD 1 WORD 2 t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t HD t SD DIN DATAIN VALID t HD t SD DATAIN VALID UB_CSWR4.eps 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 06/28/2011 IS66WV51216DALL IS66/67WV51216DBLL avoidable timing and recommendations Avoidable Timing Figure 2a Figure 2b Figure 2c Figure 3a Integrated Silicon Solution, Inc. — www.issi.com Rev. A 06/28/2011 13 IS66WV51216DALL IS66/67WV51216DBLL avoidable timing and recommendations Figure 3b ≥ 15us WE CS or UB & LB Address Figure 4 Notes: 1. PSRAM uses DRAM cell which needs a REFRESH action periodically to retain the information. This REFRESH action is performed internally as part of a READ cycle or when the device is not selected. A hidden REFRESH action has to be executed by the device at least once every 15ms. 2. Figure 2a shows a timing example in which consecutive READ cycles occurs in intervals less than the tRC spec while the device is selected for a period of 15ms. This timing should be avoided because output data from these READ cycles are not guaranteed to be valid due to violation of the tRC spec. This timing also prohibits the device from performing a hidden REFRESH action properly. Examples on how to avoid the timing in Figure 2a are shown in Figure 2b and 2c. 3. Figure 3a shows a timing example in which a single WRITE operation is maintained for a period greater than 15ms. Since a REFRESH action cannot be performed during a WRITE operation, information stored in the device will not be retained if this timing occurs. A WRITE operation is initiated when active LOW signals WE, CS, UB and LB are enabled (logic LOW) but any one of these signals can be disabled (logic HIGH) to complete the WRITE operation. Figure 3b is a timing example of using signal CS being disabled to complete the WRITE operation. 4. Since a REFRESH action cannot be performed during a WRITE operation, consecutive WRITE cycles occurring for a total period greater than 15ms are not permitted. However, executing consecutive WRITE cycles greater than 15ms is acceptable if either WE, CS, or both UB and LB, are disabled (logic HIGH) for a period of at least 5ns or higher and can be done once or multiple times. An example using CS signal is shown in Figure 4 14 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 06/28/2011 IS66WV51216DALL IS66/67WV51216DBLL IS66WV51216DALL Industrial Range: -40°C to +85°C Voltage Range: 1.7V to 1.95V Speed (ns) 70 Order Part No. IS66WV51216DALL-70TLI IS66WV51216DALL-70BLI Package TSOP-II, Lead-free mini BGA (6mm x 8mm), Lead-free IS66WV51216DBLL Industrial Range: -40°C to +85°C Voltage Range: 2.5V to 3.6V Speed (ns) 55 70 Order Part No. IS66WV51216DBLL-55TLI IS66WV51216DBLL-55BLI IS66WV51216DBLL-70TLI IS66WV51216DBLL-70BLI Package TSOP-II, Lead-free mini BGA (6mm x 8mm), Lead-free TSOP-II, Lead-free mini BGA (6mm x 8mm), Lead-free IS67WV51216DBLL Automotive (A1) Range: -40°C to +85°C Voltage Range: 2.5V to 3.6V Speed (ns) 55 70 Order Part No. IS67WV51216DBLL-55TLA1 IS67WV51216DBLL-55BLA1 IS67WV51216DBLL-70TLA1 IS67WV51216DBLL-70BLA1 Package TSOP-II, Lead-free mini BGA (6mm x 8mm), Lead-free TSOP-II, Lead-free mini BGA (6mm x 8mm), Lead-free Integrated Silicon Solution, Inc. — www.issi.com Rev. A 06/28/2011 15 16 Θ Package Outline 06/04/2008 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. 2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION. 1. CONTROLLING DIMENSION : MM NOTE : Θ IS66WV51216DALL IS66/67WV51216DBLL Integrated Silicon Solution, Inc. — www.issi.com Rev. A 06/28/2011 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 06/28/2011 08/12/2008 Package Outline 1. CONTROLLING DIMENSION : MM . 2. Reference document : JEDEC MO-207 NOTE : IS66WV51216DALL IS66/67WV51216DBLL 17