IS62C51216AL IS65C51216AL

IS62C51216AL
IS65C51216AL
512K x 16 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM DECEMBER 2010
FEATURES
DESCRIPTION
The ISSI IS62C51216AL and IS65C51216AL are high-
• High-speed access time: 45ns, 55ns
speed, 8M bit static RAMs organized as 512K words by 16
bits. It is fabricated using ISSI's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields high-performance
and low power consumption devices.
• CMOS low power operation
– 36 mW (typical) operating
– 12 µW (typical) CMOS standby
• TTL compatible interface levels
When CS1 is HIGH (deselected) or when CS2 is low
(deselected) or when CS1 is low, CS2 is high and both
LB and UB are HIGH, the device assumes a standby mode
at which the power dissipation can be reduced down with
CMOS input levels.
• Single power supply – 4.5V--5.5V Vdd
• Fully static operation: no clock or refresh
required
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs.The active LOW Write Enable (WE)
controls both writing and reading of the memory. A data byte
allows Upper Byte (UB) and Lower Byte (LB) access.
• Three state outputs
• Data control for upper and lower bytes
The IS62C51216AL and IS65C51216AL are packaged in
the JEDEC standard 48-pin mini BGA (9mm x 11mm) and
44-Pin TSOP (TYPE II).
• Automotive temperature (-40oC to +125oC)
• Lead-free available
FUNCTIONAL BLOCK DIAGRAM
A0-A18
DECODER
512K x 16
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VDD
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
CS2
CS1
OE
WE
UB
LB
CONTROL
CIRCUIT
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B
11/23/2010
1
IS62C51216AL, IS65C51216AL
PIN CONFIGURATIONS
PIN DESCRIPTIONS
48-Pin mini BGA (9mmx11mm)
1
2
3
4
5
6
A
LB
OE
A0
A1
A2
CS2
B
I/O8
UB
A3
A4
CS1
I/O0
C
I/O9
I/O10
A5
A6
I/O1
I/O2
D
GND
I/O11
A17
A7
I/O3
VDD`
E
VDD
I/O12
NC
A16
I/O4
GND
F
I/O14
I/O13
A14
A15
I/O5
I/O6
G
I/O15
NC
A12
A13
WE
I/O7
H
A18
A9
A10
A11
NC
A8
A0-A18 I/O0-I/O15
CS1, CS2 OE WE LB
UB
NC
Vdd
GND
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
Lower-byte Control (I/O0-I/O7)
Upper-byte Control (I/O8-I/O15)
No Connection
Power
Ground
44-Pin TSOP (Type II)
A4
A3
A2
A1
A0
CS1
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
I/O8
A18
A8
A9
A10
A11
A17
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
11/23/2010
IS62C51216AL, IS65C51216AL
TRUTH TABLE
I/O PIN
Mode
WE CS1 CS2 OE
LB
UB
I/O0-I/O7
I/O8-I/O15
Not Selected
X
H
X
X
X
X
High-Z
High-Z
X
X
L
X
X
X
High-Z
High-Z
X
X
X
X
H
H
High-Z
High-Z
Output Disabled
H
L
H
H
L
X
High-Z
High-Z
H
L
H
H
X
L
High-Z
High-Z
Read
H
L
H
L
L
H
Dout
High-Z
H
L
H
L
H
L
High-Z
Dout
H
L
H
L
L
LDoutDout
Write
L
L
H
X
L
H
Din
High-Z
L
L
H
X
H
L
High-Z
Din
L
L
H
X
L
LDinDin
Vdd Current
Isb1, Isb2
Isb1, Isb2
Isb1, Isb2
Icc
Icc
Icc
Icc
OPERATING RANGE (Vdd)
Range
Ambient Temperature
VDD
Speed
0°C to +70°C
4.5V - 5.5V
45ns
Industrial
–40°C to +85°C
4.5V - 5.5V
55ns
Automotive
–40°C to +125°C
4.5V - 5.5V
55ns
Commercial
CAPACITANCE(1,2)
Symbol
Cin
Cout
Parameter
Input Capacitance
Output Capacitance
Conditions
Vin = 0V
Vout = 0V
Max.
5
7
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 5.0V.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B
11/23/2010
3
IS62C51216AL, IS65C51216AL
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vterm
Tstg
Pt
Iout
Parameter
Terminal Voltage with Respect to GND
Storage Temperature
Power Dissipation
DC Output Current (LOW)
Value
–0.5 to +7.0
–65 to +150
1.5
20
Unit
V
°C
W
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Voh
Output HIGH Voltage
Vol
Output LOW Voltage
Vih
Input HIGH Voltage
Vil
Input LOW Voltage(1)
Ili
Input Leakage
Ilo
Output Leakage
Test Conditions
Min.
Max.
Unit
Vdd = Min., Ioh = –1 mA
Vdd = Min., Iol = 2.1 mA
GND ≤ Vin ≤ Vdd
GND ≤ Vout ≤ Vdd
Outputs Disabled
2.4
—
2.2
–0.3
–1
–2
–5
–1
–2
–5
—
0.4
Vdd + 0.5
0.8
1
2
5
1
2
5
V
V
V
V
µA
Com.
Ind.
Auto.
Com.
Ind.
Auto.
µA
Note:
1. Vil (min) = -0.3V DC; Vil (min) = -2.0V AC (pulse width -2.0 ns). Not 100% tested.
Vih (max) = Vdd + 0.3V DC; Vih (max) = Vdd + 2.0V AC (pulse width -2.0 ns). Not 100% tested.
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
11/23/2010
IS62C51216AL, IS65C51216AL
AC TEST CONDITIONS Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
5 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
481 Ω
481 Ω
5V
5V
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
Figure 1
255 Ω
5 pF
Including
jig and
scope
255 Ω
Figure 2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B
11/23/2010
5
IS62C51216AL, IS65C51216AL
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-45 ns -55 ns
SymbolParameter
Test Conditions
Min. Max.
Min. Max.
Unit
Icc
Vdd Dynamic Operating Vdd = Max., CE = Vil
Com.
—
25
mA
Supply Current
Iout = 0 mA, f = fmax
Ind.
— 25
Vin = Vih or Vil
Auto.
— 40
typ.(2)
13 12
Icc1
Average operating
CE = Vil, Com.
—
10
mA
Current
Vin = Vih or Vil,
Ind.
— 10
I I/O= 0 mA
Auto.
— 20
Isb1
TTL Standby Current Vdd = Max., Com.
—
1
mA
(TTL Inputs)
Vin = Vih or Vil, CE ≥ Vih,
Ind.
— 1.5
f = 0
Auto.
—
2
CMOS Standby
Vdd = Max., Com.
—
40
µA
Isb2
Current (CMOS Inputs) CE ≥ Vdd – 0.2V,
Ind.
— 60
Vin ≥ Vdd – 0.2V,
Auto.
— 180
or Vin ≤ Vss + 0.2V, f = 0
typ.(2)
15
Note:
1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical Values are measured at Vcc = 5V, Ta = 25oC and not 100% tested.
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
11/23/2010
IS62C51216AL, IS65C51216AL
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
trc
taa
toha3
tacs1/tacs2
tdoe
thzoe(2)
tlzoe(2)
thzcs1/thzcs2(2)
tlzcs1/tlzcs2(2)
tba
thzb
tlzb
Parameter
Read Cycle Time
Address Access Time
Output Hold Time
CS1/CS2 Access Time
OE Access Time
OE to High-Z Output
OE to Low-Z Output
CS1/CS2 to High-Z Output
CS1/CS2 to Low-Z Output
LB, UB Access Time
LB, UB to High-Z Output
LB, UB to Low-Z Output
45 ns
Min.
Max.
45
—
—
45
10
—
—
45
—
20
—
15
5
—
0
15
10
—
—
45
0
0
55 ns
Min.
Max.
55
—
—
55
10
—
—
55
—
25
—
20
5
—
0
20
10
—
—
55
15
—
0
0
70 ns
Min.
Max.
70
—
—
70
10
—
—
70
—
35
—
25
5
—
0
25
10
—
—
70
20
—
0
0
25
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. 10ns for CMOS Loading. 8ns @ AC Loading.
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = Vil, CS2 = WE = Vih, UB or LB = Vil)
tRC
ADDRESS
tAA
tOHA
DQ0-D15
PREVIOUS DATA VALID
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B
11/23/2010
tOHA
DATA VALID
7
IS62C51216AL, IS65C51216AL
AC WAVEFORMS
READ CYCLE NO. 2(1,3) (CS1, CS2, OE, AND UB/LB Controlled)
tRC
ADDRESS
tAA
tOHA
OE
tDOE
CS1s
tHZOE
tLZOE
tACE1/tACE2
CS2s
tLZCE1/
tLZCE2
tHZCS1/
tHZCS1
LBs, UBs
tLZB
DOUT
tBA
HIGH-Z
tHZB
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CS1, UB, or LB = Vil. CS2=WE=Vih.
3. Address is valid prior to or coincident with CS1 LOW transition.
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
11/23/2010
IS62C51216AL, IS65C51216AL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
45ns
55 ns
70 ns
Symbol
Parameter Min. Max. Min. Max. Min. Max.
twc
Write Cycle Time
45 —
55
—
70
—
tscs1/tscs2 CS1/CS2 to Write End
35
—
45
—
60
—
taw
Address Setup Time to Write End 35
—
45
—
60
—
tha
Address Hold from Write End
0
—
0
—
0
—
tsa
Address Setup Time
0
—
0
—
0
—
tpwb
LB, UB Valid to End of Write
35
—
45
—
60
—
(4)
tpwe WE Pulse Width
35
—
40
—
50
—
tsd
Data Setup to Write End
25
—
30
—
30
—
thd
Data Hold from Write End
0
—
0
—
0
—
(3)
thzwe WE LOW to High-Z Output
—
20
—
20
—
30
tlzwe(3)
WE HIGH to Low-Z Output
5
—
5
—
5
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
­ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the
write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
4. tpwe > thzwe + tsd when OE is LOW.
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CS1 Controlled, OE = HIGH or LOW)
tWC
ADDRESS
tHA
tSCS1
CS1
tSCS2
CS2
tAW
tPWE
WE
tPWB
LB, UB
tSA
DOUT
DATA UNDEFINED
tHZWE
tLZWE
HIGH-Z
tSD
DIN
tHD
DATA-IN VALID
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS1 , CS2 and WE inputs and at
least one of the LB and UB inputs being in the LOW state.
2. WRITE = (CS1) [ (LB) = (UB) ] (WE).
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B
11/23/2010
9
IS62C51216AL, IS65C51216AL
WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)
tWC
ADDRESS
OE
tHA
tSCS1
CS1
tSCS2
CS2
tAW
t PWE
WE
LB, UB
tSA
DOUT
tHZWE
tLZWE
HIGH-Z
DATA UNDEFINED
tSD
DIN
tHD
DATA-IN VALID
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
tWC
ADDRESS
OE
tHA
tSCS1
CS1
tSCS2
CS2
tAW
t PWE
WE
LB, UB
tSA
DOUT
tHZWE
DATA UNDEFINED
tLZWE
HIGH-Z
tSD
DIN
10
tHD
DATA-IN VALID
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
11/23/2010
IS62C51216AL, IS65C51216AL
WRITE CYCLE NO. 4 (UB/LB Controlled)
t WC
ADDRESS
t WC
ADDRESS 1
ADDRESS 2
OE
t SA
CS1
LOW
CS2
HIGH
t HA
t SA
WE
UB, LB
t HA
t PBW
t PBW
WORD 1
WORD 2
t HZWE
DOUT
t LZWE
HIGH-Z
DATA UNDEFINED
t HD
t SD
DIN
DATAIN
VALID
t HD
t SD
DATAIN
VALID
UB_CSWR4.eps
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B
11/23/2010
11
IS62C51216AL, IS65C51216AL
DATA RETENTION SWITCHING CHARACTERISTICS (4.5V - 5.5V) Symbol
Vdr
Idr
tsdr
trdr
Parameter
Vdd for Data Retention
Data Retention Current
Data Retention Setup Time
Recovery Time
Test Condition
See Data Retention Waveform
Vdd = 2.0V and
CS1 ≥ Vdd – 0.2V and
Com.
(a) CS2 ≥ Vdd – 0.2V or
Ind.
(b) CS2 ≤ GND + 0.2V
Auto.
See Data Retention Waveform
See Data Retention Waveform
Min.
2.0
—
—
—
—
0
trc
Typ.(1)
15
—
—
Max.
5.5
20
40
60
180
—
—
Unit
V
µA
ns
ns
Note:
1. Typical Values are measured at Vcc = 5V, Ta = 25oC and not 100% tested.
DATA RETENTION WAVEFORM (CS1 Controlled)
Data Retention Mode
tSDR
4.5V
2.2V
tRDR
VDD
VDR
CS1 ≥ VDD - 0.2V
CS1
GND
DATA RETENTION WAVEFORM (CS2 Controlled)
Data Retention Mode
4.5V
VDD
CS2
2.2V
tSDR
tRDR
VDR
0.4V
CS2 ≤ 0.2V
GND
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
11/23/2010
IS62C51216AL, IS65C51216AL
IS62c51216al (4.5V - 5.5V)
Industrial Range: –40°C to +85°C Speed (ns)
55
Order Part No.*
IS62C51216AL-55TLI
IS62C51216AL-55MLI
Package
TSOP-II, Lead-free
mini BGA, Lead-free (9mmx11mm)
*Devices will meet 45ns when used in 0oC to +70oC temperature range.
IS65c51216al (4.5V - 5.5V)
Automotive Range: –40°C to +125°C Speed (ns)
55
Order Part No.
IS65C51216AL-55CTLA3
IS65C51216AL-55MLA3
Package
TSOP-II, Lead-free, Copper Lead-frame
mini BGA, Lead-free (9mmx11mm)
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B
11/23/2010
13
14
Θ
Package Outline
06/04/2008
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION.
2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION.
1. CONTROLLING DIMENSION : MM
NOTE :
Θ
IS62C51216AL, IS65C51216AL
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
11/23/2010
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B
11/23/2010
1. CONTROLLING DIMENSION : MM .
2. Reference document : JEDEC MO-207
NOTE :
08/21/2008
IS62C51216AL, IS65C51216AL
15