LTC4303 Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery DESCRIPTIO U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LTC®4303 hot swappable 2-wire Bus Buffer allows I/O card insertion into a live backplane without corruption of the data and clock busses. When a connection is made, the LTC4303 provides bidirectional buffering, keeping the backplane and card capacitances isolated. If SDAOUT or SCLOUT is low for ≥ 30ms (typ), the LTC4303 automatically breaks the data and clock bus connection. At this time the LTC4303 automatically generates up to 16 clock pulses on SCLOUT in an attempt to free the bus. A connection will be enabled automatically when the bus becomes free. Automatic Disconnect of SDA/SCL Lines when Bus is Stuck Low for ≥ 30ms Recovers Stuck Busses with Automatic Clocking* Bidirectional Buffer* for SDA and SCL Lines Increases Fanout Prevents SDA and SCL Corruption During Live Board Insertion and Removal from Backplane Pin Compatible with LTC4300A-1 ±15kV Human Body Model ESD Protection Isolates Input SDA and SCL Lines from Output Compatible with I2CTM, I2C Fast-Mode and SMBus Standards (Up to 400kHz Operation) READY Open Drain Output 1V Precharge on All SDA and SCL Lines High Impedance SDA, SCL Pins for VCC = 0V ENABLE Gates Connection from Input to Output MSOP 8-Pin and DFN (3mm × 3mm) Packages Rise-time accelerator circuitry allows the use of larger pullup resistance while still meeting rise-time requirements. During insertion, the SDA and SCL lines are precharged to 1V to minimize bus disturbances. When driven high, ENABLE allows the LTC4303 to connect after a stop bit or bus idle occurs. Driving ENABLE low breaks the connection between SDAIN and SDAOUT, SCLIN and SCLOUT. READY is an open drain output that indicates when the backplane and card sides are connected together. U APPLICATIO S ■ ■ ■ ■ Hot Board Insertion Servers Capacitance Buffer/Bus Extender RAID Systems , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 6356140, 6650174, 7032051. U TYPICAL APPLICATIO 5V 3.3V Stuck Bus Resolved with Automatic Clocking 0.01mF 10k 10k 10k VCC 10k LTC4303 SCLIN CARD_SCL SDAOUT 5V/DIV CARD_SDA SDAIN 5V/DIV SCLOUT BACK_SCL STUCK LOW > 30ms RECOVERS DISCONNECT AT TIMEOUT SDAIN SDAOUT BACK_SDA AUTOMATIC CLOCKING 3.3V ENABLE GND 100k READY SCLOUT 5V/DIV 4303 TA01 200ms/DIV BACKPLANE CONNECTOR STAGGERED CONNECTOR 4303 TA01b CARD 4303fb 1 LTC4303 W W U W ABSOLUTE AXI U RATI GS (Notes 1, 2) VCC to GND .................................................. –0.3V to 7V SDAIN, SCLIN, SDAOUT, SCLOUT, READY, ENABLE ........................................... –0.3V to 7V Operating Temperature LTC4303C ................................................ 0°C to 70°C LTC4303I .............................................–40°C to 85°C SDAIN, SCLIN, SDAOUT, SCLOUT, READY (Note 3)..................................................................30mA Storage Temperature Range MSOP ................................................–65°C to 150°C DFN....................................................–65°C to 125°C Lead Temperature (Soldering, 10sec) MSOP ............................................................... 300°C U W U PACKAGE/ORDER I FOR ATIO TOP VIEW ENABLE 1 8 VCC SCLOUT 2 7 SDAOUT SCLIN 3 GND 4 9 6 SDAIN 5 READY TOP VIEW ENABLE SCLOUT SCLIN GND DD PART MARKING* LTC4303CDD LTC4303IDD VCC SDAOUT SDAIN READY MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 200°C/W DD PACKAGE 8-LEAD (3mm × 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 9) PCB CONNECTION OPTIONAL ORDER PART NUMBER 8 7 6 5 1 2 3 4 ORDER PART NUMBER LBPZ MS8 PART MARKING* LTC4303CMS8 LTC4303IMS8 LTBPY Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, unless otherwise noted. SYMBOL Power Supply VCC ICC Startup Circuitry VPRE TIDLE VOL_READY VTHR_ENABLE IENABLE VTHR PARAMETER CONDITIONS Positive Supply Voltage Supply Current Supply Current, ENABLE = GND VCC = 5.5V, VSDAIN = VSDAOUT = 0V (Note 7) VCC = 5.5V ● SDA, SCL Floating, VCC = 5.5V ● Precharge Voltage Bus Idle Time READY Output Low Voltage MIN ● ● IPULLUP = 3mA IPULLUP = 6mA, VCC = 4.7V ENABLE Threshold ENABLE Input Current ENABLE from 0 to VCC SDA, SCL Logic Input Threshold Voltage Rising Edge TYP 2.7 6 1.5 5.5 8 V mA mA 1 95 1.2 175 0.4 0.4 V µs V V 0.8 1.4 0.1 1.8 2 ±1.5 2 V µA V ● ● UNITS 0.8 60 ● ● ● MAX 1.6 4303fb 2 LTC4303 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS VHYS SDA, SCL, Logic Input Threshold Voltage (Note 6) Hysteresis MIN tPHL_ENABLE Delay ENABLE High-Low to Disconnect VCC = 3.3V tPHL_READY Delay READY High-Low after Disconnect tPLH_ENABLE Delay ENABLE Low-High to Connect VCC = 3.3V tPLH_READY Delay READY Low-High after Connect IOFF_READY Ready Off Leakage Current Rise-Time Accelerators IPULLUPAC Transient Boosted Pull-Up Current Positive Transition on SDA, SCL, VCC = 2.7V, Slew Rate = 0.8V/µs (Note 5) Bus Stuck Low Timeout tTIMEOUT Bus Stuck Low Timer SDAOUT, SCLOUT = 0V Input-Output Connection VOS Input-Output Offset Voltage CIN Digital Input Capacitance SDAIN, SDAOUT, SCLIN, SCLOUT tSU, STO tHD, DATI tSU, DAT Stop Condition Set-Up Time Data Hold Time Input Data Set-Up Time 60 MAX UNITS 50 mV 300 10 95 10 ±10 ns ns µs ns µA ● 175 2 3.5 5.5 mA ● 25 30 35 ms ● ● 40 50 80 100 120 150 mV mV 10 pF 0.4 ±5 0.3 V µA V 1.3 kHz µs (Note 6) 100 ns (Note 6) (Note 6) (Note 6) (Note 6) 0 0 0 100 ns ns ns ns 10k to VCC on SDA, SCL, 2.7k to VCC on SDA, SCL VCC = 3.3V, VSDA/SCL = 0.2V (Note 4) (Note 6) ● VIL, MAX Input Logic Low Voltage ILEAK Input Leakage Current VOL Output Low Voltage, Input = 0 Timing Characteristics fI2C, MAX I2C Maximum Operating Frequency tBUF Bus Free Time Between Stop and Start Condition tHD, STA Hold Time After (Repeated) Start Condition tSU, STA Repeated Start Condition Set-Up Time ● TYP SDA, SCL, VCC = 5.5V SDA, SCL Pins, ISINK = 4mA, VCC = 2.7V (Note 6) (Note 6) Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into pins are positive; all voltages are referenced to GND unless otherwise specified. Note 3: Pulsed less than 5µs. ● ● 0 0.19 400 600 Note 4: The connection circuitry always regulates the output to a higher voltage than its input. The magnitude of this offset voltage as a function of the pull-up resistor and VCC voltage is shown in the Typical Performance Characteristics section. Note 5: IPULLUPAC varies with temperature and VCC voltage, as shown in the Typical Performance Characteristics section. Note 6: Guaranteed by design, not tested in production. Note 7: ICC test performed with connection circuitry active. 4303fb 3 LTC4303 U W TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C unless otherwise indicated. ICC vs Temperature Input-Output tPHL vs Temperature 140 6.2 VCC = 5.5V 6.0 120 IPULLUPAC vs Temperature 14 CIN = COUT = 100pF RPULLUPIN = RPULLUPOUT = 10k 12 100 10 5.4 80 60 8 VCC = 3.3V 6 40 4 20 2 VCC = 2.7V 5.2 5.0 –50 IPULLUPAC (mA) tPHL (ns) ICC (mA) 5.8 5.6 VCC = 5.5V –25 VCC = 2.7V 0 25 50 TEMPERATURE (°C) 75 100 0 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 0 –50 –25 0 25 50 TEMPERATURE (°C) 4303 G02 4303 G01 75 100 4303 G03 Input-Output tPHL vs COUT Connection Circuitry VOUT - VIN 180 250 CIN = 50pF 160 RPULLUPIN = RPULLUPOUT = 10k 200 140 150 100 tPHL (ns) VOUT-VIN (mV) VCC = 5.5V 120 100 80 VCC = 2.7V 60 50 40 0 1000 20 3000 7000 5000 RPULLUP (Ω) 9000 4303 G04 0 500 1000 COUT (pF) 1500 2000 4303 G05 4303fb 4 LTC4303 U U U PI FU CTIO S ENABLE (Pin 1): Connection Enable. This is a digital threshold input pin. For normal operation ENABLE is high. Driving ENABLE below 0.8V isolates SDAIN from SDAOUT, SCLIN from SCLOUT, asserts READY low and disables automatic clocking. A rising edge on ENABLE after a fault has occurred unconditionally forces a connection between SDAIN, SDAOUT and SCLIN, SCLOUT. READY (Pin 5): Connection Status Flag. READY provides a digital flag which indicates the status of the connection circuitry described in the “Connection Circuitry” section. Connect a resistor of 10k to VCC to provide the pull-up. SDAIN (Pin 6): Serial Data Input. Connect this pin to the SDA bus on the backplane. SDAOUT (Pin 7): Serial Data Output. Connect this pin to the SDA bus on the card. SCLOUT (Pin 2): Serial Clock Output. Connect this pin to the SCL bus on the card. VCC (Pin 8): Supply Voltage Input. Place a bypass capacitor of at least 0.01µF close to VCC for best results. SCLIN (Pin 3): Serial Clock Input. Connect this pin to SCL on the bus backplane. Exposed Pad (Pin 9, DFN Only): Exposed pad may be left open or connected to the ground plane. GND (Pin 4): Device Ground. Connect this pin to a ground plane for best results. W BLOCK DIAGRA LTC4303 2-Wire Bus Buffer with Stuck Bus Protection 3.5mA SLEW RATE DETECTOR 8 VCC 3.5mA SLEW RATE DETECTOR CONNECT SDAIN SDAOUT 6 200k PC_CONNECT 7 200k PC_CONNECT PRECHARGE 3.5mA SLEW RATE DETECTOR 200k 3 3.5mA SLEW RATE DETECTOR CONNECT SCLOUT SCLIN – UVLO 30ms TIMER – AUTOMATIC CLOCKING + – 1.8V LOGIC PC_CONNECT – + CONNECT ENABLE 2 + + 1 200k 1.8V READY 5 + 1.4V – UVLO 95ms DELAY CONNECT GND 4 4301 BD 4303fb 5 LTC4303 U OPERATIO Start-Up When the LTC4303 first receives power on its VCC pin, either during power up or live insertion, it starts in an under voltage lockout (UVLO) state, ignoring any activity on the SDA or SCL pins until VCC rises above 2.5V (typical). During this time, the precharge circuitry is active and forces 1V through 200k nominal resistors to the SDA and SCL pins. Because the I/O card is being plugged into a live backplane, the voltage on the backplane SDA and SCL busses may be anywhere between 0V and VCC. Precharging the SCL and SDA pins to 1V minimizes the worst-case voltage differential these pins will see at the moment of connection, therefore minimizing the amount of disturbance caused by the I/O card. Once the LTC4303 comes out of UVLO, it assumes that SDAIN and SCLIN have been inserted into a live system and that SDAOUT and SCLOUT are being powered up at the same time as itself. Therefore, it looks for either a stop bit or bus idle condition on the input side to indicate the completion of a data transaction. When either one occurs, the part also verifies that both the SDAOUT and SCLOUT voltages are high. When all of these conditions are met, the input-to-output connection circuitry is activated, joining the SDA and SCL busses on the I/O card with those on the backplane and READY goes high. Connection Circuitry Once the connection circuitry is activated, the functionality of the SDAIN and SDAOUT pins is identical. A low forced on either pin at any time results in both pin voltages being low. For proper operation, logic low input voltages should be no higher than 0.4V with respect to the ground pin voltage of the LTC4303. SDAIN and SDAOUT enter a logic high state only when all devices on both SDAIN and SDAOUT release high. The same is true for SCLIN and SCLOUT. This important feature ensures that clock stretching, clock synchronization, arbitration and the acknowledge protocol always work, regardless of how the devices in the system are tied to the LTC4303. Another key feature of the connection circuitry is that it provides bidirectional buffering, keeping the backplane and card capacitances isolated. Because of this isolation, the waveforms on the backplane busses look slightly different than the corresponding card bus waveforms, as described here. Input to Output Offset Voltage When a logic low voltage, VLOW1, is driven on any of the LTC4303’s data or clock pins, the LTC4303 regulates the voltage on the opposite side of the part (call it VLOW2) to a slightly higher voltage, as directed by the following equation: VLOW2 = VLOW1 + 75mV + (VCC/R) • 20Ω (typical) where R is the bus pull-up resistance in ohms. For example, if a device is forcing SDAOUT to 10mV where VCC = 3.3V and the pull-up resistor R on SDAIN is 10k, then the voltage on SDAIN = 10mV + 75mV + (3.3/10000) • 20 = 91.6mV (typical). See the Typical Performance Characteristics section for curves showing the offset voltage as a function of VCC and R. Bus Stuck Low Time-Out When SDAOUT or SCLOUT is low, an internal timer starts. The timer is only reset when SDAOUT and SCLOUT are both high. If they do not go high within 30ms (typical), the connection between SDAIN and SDAOUT, and SCLIN and SCLOUT is broken. After a delay of at least 40µs the LTC4303 automatically generates up to 16 clock pulses at 8.5kHz (typical) on SCLOUT in an attempt to unstick the bus. When SDAOUT and SCLOUT go high, reconnection occurs when the conditions described in the “Start-Up” section above are satisfied. When powering up into a bus stuck low condition, the connection circuitry joining the SDA and SCL busses on the I/O card with those on the backplane is not activated. 30ms after UVLO, automatic clocking takes place as described above. Propagation Delays During a rising edge, the rise-time on each side is determined by the bus pull-up resistor and the equivalent capacitance on the line. If the pull-up resistors are the same, a difference in rise-time occurs which is directly proportional to the difference in capacitance between 4303fb 6 LTC4303 U OPERATIO OUTPUT SIDE 50pF 0.5V/DIV INPUT SIDE 150pF 0.5V/DIV 200ns/DIV INPUT SIDE 50pF 0.5V/DIV OUTPUT SIDE 150pF 0.5V/DIV 4303 F01 20ns/DIV Figure 1. Input-Output Connection tPLH the two sides. This effect is displayed in Figure 1 for a VCC = 3.3V and a 10k pull-up resistor on each side (50pF on one side and 150pF on the other). Since the output side has less capacitance than the input, it rises faster and the effective tPLH is negative. There is a propagation delay, tPHL, through the connection circuitry for falling waveforms. Figure 2 shows the falling edge waveforms. An external driver pulls down the voltage on the side with 50pF capacitance; LTC4303 pulls down the voltage on the opposite side with a delay of 80ns. This delay is always positive and is a function of supply voltage, temperature and the pull-up resistors and equivalent bus capacitances on both sides of the bus. The Typical Performance Characteristics section shows tPHL as a function of temperature and voltage for 10k pull-up resistors and 100pF equivalent capacitance on both sides of the part. Larger output capacitances translate to longer delays. Users must quantify the difference in propagation times for a rising edge versus a falling edge in their systems and adjust setup and hold times accordingly. READY Digital Output The READY pin provides a digital flag which indicates the status of the connection circuitry described previously in the “Connection Circuitry” section. READY is high when the connection circuitry is active, and pulls low when there is not a valid connection. The pin is driven by an open drain pull-down capable of sinking 3mA while holding 0.4V on the pin. Connect a resistor of 10k to VCC to provide the pull-up. 4303 F02 Figure 2. Input-Output Connection tPHL ENABLE When the ENABLE pin is driven below 0.8V with respect to the LTC4303’s ground, the backplane side is disconnected from the card side, and the READY pin is internally pulled low. When the pin is driven above 2V, the part waits for data transactions on the IN side to be complete and for the OUT side to be high (as described in the Start-Up section) before connecting the two sides. At this time the internal pull-down on READY releases. When ENABLE is low, automatic clocking is disabled. A rising edge on ENABLE after a stuck bus condition has occurred forces a connection between SDAIN, SDAOUT and SCLIN, SCLOUT even if bus idle conditions are not met. At this time the internal 30ms timer is reset but not disabled. Rise Time Accelerators Once connection has been established, rise time accelerator circuits on all four SDA and SCL pins are activated. These allow the use of larger pull-up resistors, reducing power consumption, or bus capacitance beyond that specified in I2C, while still meeting system rise time requirements. During positive bus transitions, the LTC4303 switches in 3.5mA (typical) of current to quickly slew the SDA and SCL lines once their DC voltages exceed 0.8V. Choose a pull-up resistor so that the bus will rise on its own at a rate of at least 0.8V/µs to guarantee activation of the accelerators. Rise time accelerators turn off when SDA and SCL lines are approximately 1V below VCC.The rise time accelerators are automatically disabled during automatic clocking. 4303fb 7 LTC4303 U W U U APPLICATIO S I FOR ATIO Resistor Pull-Up Selection The system pull-up resistors must be strong enough to provide a positive slew rate of 0.8V/µs on the SDA and SCL pins, in order to activate the rise time accelerators during rising edges. Choose maximum resistor value RPULL-UP(MAX) using the formula: where VBUSMIN is the minimum operating pull-up supply voltage, and CBUS the total capacitance on respective bus line. VBUS(MIN) – 0.8 V • 1250[ns/V] RPULLUP(MAX)[kΩ] = CBUS [pF] ( ) For example, assume VBUS = VCC = 3.3V, and assuming ±10% supply tolerance, VBUSMIN = 2.97V. With CBUS = 100pF, RPULL-UP, MAX = 27.1k. Therefore a smaller pull-up resistor than 27.1k must be used, so 10k works fine. Live Insertion and Capacitance Buffering Application Figures 3 through 6 illustrate applications of the LTC4303 that take advantage of both its Hot SwapTM controlling and capacitance buffering features. In all of these applications, note that if the I/O cards were plugged directly into the backplane without the LTC4303 buffer, all of the backplane and card capacitances would add directly together, making rise- and fall-time requirements difficult to meet. Placing a LTC4303 on the edge of each card, however, isolates the card capacitance from the backplane. For a given I/O card, the LTC4303 drives the capacitance on the card side and the backplane must drive only the digital input capacitance of the LTC4303, which is less than 10pF. In most applications the LTC4303 will be used with a staggered connector where VCC and GND will be long pins. SDA and SCL are medium length pins to ensure that the VCC and GND pins make contact first. This will allow the precharge circuitry to be activated on SDA and SCL before they make contact. ENABLE is a short pin that is pulled down when not connected. This is to ensure that the connection between the backplane and the cards data and clock busses is not enabled until the transients associated with live insertion have settled. Figure 3 shows the LTC4303 in a CompactPCITM configuration. Connect VCC and ENABLE to the output of one of the CompactPCI power supply Hot Swap circuits. Use a pull-up resistor to ENABLE for a card side enable/disable. VCC is monitored by a filtered UVLO circuit. With the VCC voltage powering up after all the other pins have established connection, the UVLO circuit ensures that the backplane and the card data and clock busses are not connected until the transients associated with live insertion have settled. Owing to their small capacitance, the SDAIN and SCLIN pins cause minimal disturbance on the backplane busses when they make contact with the connector. Figure 4 shows the LTC4303 in a PCI application where all of the pins have the same length. In this case, a RC filter circuit on the I/O card with a product of 10ms provides a filter to prevent the LTC4303 from becoming activated until the transients associated with live insertion have settled. Connect the capacitor between ENABLE and GND, and the resistor from VCC to ENABLE. Hot Swap is a trademark of Linear Technology Corporation. 4303fb 8 LTC4303 U W U U APPLICATIO S I FOR ATIO BACKPLANE VCC R1 10k BACKPLANE CONNECTOR STAGGERED CONNECTOR POWER SUPPLY HOT SWAP R2 10k I/O PERIPHERAL CARD 1 R3 10k BD_SEL CARD ENABLE/DISABLE ENABLE SDA SDAIN SCL SCLIN VCC LTC4303 C1 0.01µF R4 10k R5 10k R6 10k SDAOUT CARD1_SDA SCLOUT CARD1_SCL READY GND POWER SUPPLY HOT SWAP I/O PERIPHERAL CARD 2 R7 10k CARD ENABLE/DISABLE ENABLE SDAIN SCLIN VCC LTC4303 C3 0.01µF R8 10k R9 10k R10 10k SDAOUT CARD2_SDA SCLOUT CARD2_SCL READY GND • • • POWER SUPPLY HOT SWAP I/O PERIPHERAL CARD N C5 0.01µF R11 10k CARD R12 10k R13 10k R14 10k ENABLE/DISABLE ENABLE SDAIN SCLIN VCC LTC4303 SDAOUT CARDN_SDA SCLOUT CARDN_SCL READY GND 4303 F03 Figure 3. Inserting Multiple I/O Cards into a Live Backplane Using the LTC4303 in a CompactPCI System 4303fb 9 LTC4303 U U W U APPLICATIO S I FOR ATIO BACKPLANE CONNECTOR BACKPLANE I/O PERIPHERAL CARD 1 VCC R1 10k C1 0.01mF R3 100k R2 10k ENABLE SDAIN SDA SCL SCLIN C2 0.1mF R4 10k R5 10k R6 10k VCC SDAOUT CARD1_SDA LTC4303 SCLOUT CARD1_SCL READY GND I/O PERIPHERAL CARD 2 C3 0.01mF R7 100k ENABLE SDAIN SCLIN C4 0.1mF R8 10k R9 10k R10 10k VCC SDAOUT CARD2_SDA LTC4303 SCLOUT CARD2_SCL READY GND • • • 4303 F04 Figure 4. Inserting Multiple I/O Cards into a Live Backplane Using the LTC4303 in a PCI System VCC SHELF MANAGER R1 10k VCC ShMC 0.01µF R2 10k ENABLE R3 2.7k ATCA BOARD 0.01µF R4 2.7k VCC SDAIN SDAOUT LTC4303 SCLIN SCLOUT R6 10k VCC ENABLE VCC SDAOUT LTC4303 SCLOUT SCLIN IPMC SDAIN IPM BUS (1 OF 2) R5 10k 4303 F05 Figure 5. Simplified ATCA IPMB Application 4303fb 10 LTC4303 U PACKAGE DESCRIPTIO DD Package 8-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1698) R = 0.115 TYP 5 0.38 ± 0.10 8 0.675 ±0.05 3.5 ±0.05 1.65 ±0.05 2.15 ±0.05 (2 SIDES) 3.00 ±0.10 (4 SIDES) PACKAGE OUTLINE 1.65 ± 0.10 (2 SIDES) PIN 1 TOP MARK (NOTE 6) (DD8) DFN 1203 0.25 ± 0.05 4 0.25 ± 0.05 0.75 ±0.05 0.200 REF 0.50 BSC 2.38 ±0.05 (2 SIDES) 1 0.50 BSC 2.38 ±0.10 (2 SIDES) 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 0.42 ± 0.038 (.0165 ± .0015) TYP 3.20 – 3.45 (.126 – .136) 0.65 (.0256) BSC 0.254 (.010) 8 7 6 5 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 4.90 ± 0.152 (.193 ± .006) DETAIL “A” 0.52 (.0205) REF 0° – 6° TYP GAUGE PLANE 1 0.53 ± 0.152 (.021 ± .006) RECOMMENDED SOLDER PAD LAYOUT DETAIL “A” 1.10 (.043) MAX 2 3 4 0.86 (.034) REF 0.18 (.007) NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX SEATING PLANE 0.22 – 0.38 (.009 – .015) TYP 0.65 (.0256) BSC 0.127 ± 0.076 (.005 ± .003) MSOP (MS8) 0204 4303fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 11 LTC4303 U TYPICAL APPLICATIO 3.3V C1 0.01mF 5V R3 10k VCC R1 10k R2 10k R4 10k LTC4303 SCLIN SCLOUT CARD_SCL BACK_SCL SDAIN SDAOUT BACK_SDA CARD_SDA FROM MICROPROCESSOR ENABLE R5 100k BACKPLANE CONNECTOR STAGGERED CONNECTOR GND READY 4303 F06 CARD Figure 6. System with Active Connection Control RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1380/LTC1393 Single-Ended 8-Channel/Differential 4-Channel Analog Mux with SMBus Interface Micropower, 10-Bit Current Output DAC with SMBus Interface Dual High Side Switch Controller with SMBus Interface SMBus Interface 10-Bit Rail-to-Rail Micropower DAC SMBus Accelerator Low RON: 35Ω Single-Ended/70Ω Differential, Expandable to 32 Single or 16 Differential Channels Precision 50µA ± 2.5% Tolerance Over Temperature, 4 Selectable SMBus Addresses, DAC Powers up at Zero or Midscale 8 Selectable Addresses/16-Channel Capability DNL < 0.75LSB Max, 5-Lead SOT-23 Package Improved SMBus/I2C Rise-Time, Ensures Data Integrity with Multiple SMBus/I2C Devices 1.25A, 200kHz, Floating or Grounded Lamp Configurations 0.75Ω PMOS 180mA Regulator, 6-Bit DAC Two 100µA 8-Bit DACs, Two Tach Inputs, Four GPI0 Isolates Backplane and Card Capacitances Provides Level Shifting and Enable Functions Supply Independent Allows Bus Pull-Up Voltages as Low as 1V on SDAIN and SCLIN LTC1427-50 LTC1623 LTC1663 LTC1694/LTC1694-1 LT1786F LTC1695 LTC1840 LTC4300A-1/LTC4300A-2 LTC4300A-3 LTC4301 LTC4301L SMBus Controlled CCFL Switching Regulator SMBus/I2C Fan Speed Controller in ThinSOTTM Dual I2C Fan Speed Controller Hot Swappable 2-Wire Bus Buffer Hot Swappable 2-Wire Bus Buffer Supply Independent Hot Swappable 2-Wire Bus Buffer Hot Swappable 2-Wire Bus Buffer with Low Voltage Level Translation LTC4302-1/LTC4302-2 Addressable 2-Wire Bus Buffer LTC4304 Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery ThinSOT is a trademark of Linear Technology Corporation. Address Expansion, GPIO, Software Controlled Provides Automatic Clocking to Free Stuck I2C Busses; Fault Flag for Stuck Bus, Level Shifting Functions 4303fb 12 Linear Technology Corporation LT/LWI 0806 REV B • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2005